1 /* 2 * PCI bus driver for Bosch C_CAN/D_CAN controller 3 * 4 * Copyright (C) 2012 Federico Vaga <federico.vaga@gmail.com> 5 * 6 * Borrowed from c_can_platform.c 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/pci.h> 17 18 #include <linux/can/dev.h> 19 20 #include "c_can.h" 21 22 #define PCI_DEVICE_ID_PCH_CAN 0x8818 23 #define PCH_PCI_SOFT_RESET 0x01fc 24 25 enum c_can_pci_reg_align { 26 C_CAN_REG_ALIGN_16, 27 C_CAN_REG_ALIGN_32, 28 C_CAN_REG_32, 29 }; 30 31 struct c_can_pci_data { 32 /* Specify if is C_CAN or D_CAN */ 33 enum c_can_dev_id type; 34 /* Set the register alignment in the memory */ 35 enum c_can_pci_reg_align reg_align; 36 /* Set the frequency */ 37 unsigned int freq; 38 /* PCI bar number */ 39 int bar; 40 /* Callback for reset */ 41 void (*init)(const struct c_can_priv *priv, bool enable); 42 }; 43 44 /* 16-bit c_can registers can be arranged differently in the memory 45 * architecture of different implementations. For example: 16-bit 46 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. 47 * Handle the same by providing a common read/write interface. 48 */ 49 static u16 c_can_pci_read_reg_aligned_to_16bit(const struct c_can_priv *priv, 50 enum reg index) 51 { 52 return readw(priv->base + priv->regs[index]); 53 } 54 55 static void c_can_pci_write_reg_aligned_to_16bit(const struct c_can_priv *priv, 56 enum reg index, u16 val) 57 { 58 writew(val, priv->base + priv->regs[index]); 59 } 60 61 static u16 c_can_pci_read_reg_aligned_to_32bit(const struct c_can_priv *priv, 62 enum reg index) 63 { 64 return readw(priv->base + 2 * priv->regs[index]); 65 } 66 67 static void c_can_pci_write_reg_aligned_to_32bit(const struct c_can_priv *priv, 68 enum reg index, u16 val) 69 { 70 writew(val, priv->base + 2 * priv->regs[index]); 71 } 72 73 static u16 c_can_pci_read_reg_32bit(const struct c_can_priv *priv, 74 enum reg index) 75 { 76 return (u16)ioread32(priv->base + 2 * priv->regs[index]); 77 } 78 79 static void c_can_pci_write_reg_32bit(const struct c_can_priv *priv, 80 enum reg index, u16 val) 81 { 82 iowrite32((u32)val, priv->base + 2 * priv->regs[index]); 83 } 84 85 static u32 c_can_pci_read_reg32(const struct c_can_priv *priv, enum reg index) 86 { 87 u32 val; 88 89 val = priv->read_reg(priv, index); 90 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 91 92 return val; 93 } 94 95 static void c_can_pci_write_reg32(const struct c_can_priv *priv, enum reg index, 96 u32 val) 97 { 98 priv->write_reg(priv, index + 1, val >> 16); 99 priv->write_reg(priv, index, val); 100 } 101 102 static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable) 103 { 104 if (enable) { 105 u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET; 106 107 /* write to sw reset register */ 108 iowrite32(1, addr); 109 iowrite32(0, addr); 110 } 111 } 112 113 static int c_can_pci_probe(struct pci_dev *pdev, 114 const struct pci_device_id *ent) 115 { 116 struct c_can_pci_data *c_can_pci_data = (void *)ent->driver_data; 117 struct c_can_priv *priv; 118 struct net_device *dev; 119 void __iomem *addr; 120 int ret; 121 122 ret = pci_enable_device(pdev); 123 if (ret) { 124 dev_err(&pdev->dev, "pci_enable_device FAILED\n"); 125 goto out; 126 } 127 128 ret = pci_request_regions(pdev, KBUILD_MODNAME); 129 if (ret) { 130 dev_err(&pdev->dev, "pci_request_regions FAILED\n"); 131 goto out_disable_device; 132 } 133 134 ret = pci_enable_msi(pdev); 135 if (!ret) { 136 dev_info(&pdev->dev, "MSI enabled\n"); 137 pci_set_master(pdev); 138 } 139 140 addr = pci_iomap(pdev, c_can_pci_data->bar, 141 pci_resource_len(pdev, c_can_pci_data->bar)); 142 if (!addr) { 143 dev_err(&pdev->dev, 144 "device has no PCI memory resources, " 145 "failing adapter\n"); 146 ret = -ENOMEM; 147 goto out_release_regions; 148 } 149 150 /* allocate the c_can device */ 151 dev = alloc_c_can_dev(); 152 if (!dev) { 153 ret = -ENOMEM; 154 goto out_iounmap; 155 } 156 157 priv = netdev_priv(dev); 158 pci_set_drvdata(pdev, dev); 159 SET_NETDEV_DEV(dev, &pdev->dev); 160 161 dev->irq = pdev->irq; 162 priv->base = addr; 163 priv->device = &pdev->dev; 164 165 if (!c_can_pci_data->freq) { 166 dev_err(&pdev->dev, "no clock frequency defined\n"); 167 ret = -ENODEV; 168 goto out_free_c_can; 169 } else { 170 priv->can.clock.freq = c_can_pci_data->freq; 171 } 172 173 /* Configure CAN type */ 174 switch (c_can_pci_data->type) { 175 case BOSCH_C_CAN: 176 priv->regs = reg_map_c_can; 177 break; 178 case BOSCH_D_CAN: 179 priv->regs = reg_map_d_can; 180 break; 181 default: 182 ret = -EINVAL; 183 goto out_free_c_can; 184 } 185 186 priv->type = c_can_pci_data->type; 187 188 /* Configure access to registers */ 189 switch (c_can_pci_data->reg_align) { 190 case C_CAN_REG_ALIGN_32: 191 priv->read_reg = c_can_pci_read_reg_aligned_to_32bit; 192 priv->write_reg = c_can_pci_write_reg_aligned_to_32bit; 193 break; 194 case C_CAN_REG_ALIGN_16: 195 priv->read_reg = c_can_pci_read_reg_aligned_to_16bit; 196 priv->write_reg = c_can_pci_write_reg_aligned_to_16bit; 197 break; 198 case C_CAN_REG_32: 199 priv->read_reg = c_can_pci_read_reg_32bit; 200 priv->write_reg = c_can_pci_write_reg_32bit; 201 break; 202 default: 203 ret = -EINVAL; 204 goto out_free_c_can; 205 } 206 priv->read_reg32 = c_can_pci_read_reg32; 207 priv->write_reg32 = c_can_pci_write_reg32; 208 209 priv->raminit = c_can_pci_data->init; 210 211 ret = register_c_can_dev(dev); 212 if (ret) { 213 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 214 KBUILD_MODNAME, ret); 215 goto out_free_c_can; 216 } 217 218 dev_dbg(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", 219 KBUILD_MODNAME, priv->regs, dev->irq); 220 221 return 0; 222 223 out_free_c_can: 224 free_c_can_dev(dev); 225 out_iounmap: 226 pci_iounmap(pdev, addr); 227 out_release_regions: 228 pci_disable_msi(pdev); 229 pci_clear_master(pdev); 230 pci_release_regions(pdev); 231 out_disable_device: 232 pci_disable_device(pdev); 233 out: 234 return ret; 235 } 236 237 static void c_can_pci_remove(struct pci_dev *pdev) 238 { 239 struct net_device *dev = pci_get_drvdata(pdev); 240 struct c_can_priv *priv = netdev_priv(dev); 241 void __iomem *addr = priv->base; 242 243 unregister_c_can_dev(dev); 244 245 free_c_can_dev(dev); 246 247 pci_iounmap(pdev, addr); 248 pci_disable_msi(pdev); 249 pci_clear_master(pdev); 250 pci_release_regions(pdev); 251 pci_disable_device(pdev); 252 } 253 254 static const struct c_can_pci_data c_can_sta2x11= { 255 .type = BOSCH_C_CAN, 256 .reg_align = C_CAN_REG_ALIGN_32, 257 .freq = 52000000, /* 52 Mhz */ 258 .bar = 0, 259 }; 260 261 static const struct c_can_pci_data c_can_pch = { 262 .type = BOSCH_C_CAN, 263 .reg_align = C_CAN_REG_32, 264 .freq = 50000000, /* 50 MHz */ 265 .init = c_can_pci_reset_pch, 266 .bar = 1, 267 }; 268 269 #define C_CAN_ID(_vend, _dev, _driverdata) { \ 270 PCI_DEVICE(_vend, _dev), \ 271 .driver_data = (unsigned long)&_driverdata, \ 272 } 273 274 static const struct pci_device_id c_can_pci_tbl[] = { 275 C_CAN_ID(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_CAN, 276 c_can_sta2x11), 277 C_CAN_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_CAN, 278 c_can_pch), 279 {}, 280 }; 281 282 static struct pci_driver c_can_pci_driver = { 283 .name = KBUILD_MODNAME, 284 .id_table = c_can_pci_tbl, 285 .probe = c_can_pci_probe, 286 .remove = c_can_pci_remove, 287 }; 288 289 module_pci_driver(c_can_pci_driver); 290 291 MODULE_AUTHOR("Federico Vaga <federico.vaga@gmail.com>"); 292 MODULE_LICENSE("GPL v2"); 293 MODULE_DESCRIPTION("PCI CAN bus driver for Bosch C_CAN/D_CAN controller"); 294 MODULE_DEVICE_TABLE(pci, c_can_pci_tbl); 295