1 /* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/interrupt.h> 31 #include <linux/delay.h> 32 #include <linux/netdevice.h> 33 #include <linux/if_arp.h> 34 #include <linux/if_ether.h> 35 #include <linux/list.h> 36 #include <linux/io.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/pinctrl/consumer.h> 39 40 #include <linux/can.h> 41 #include <linux/can/dev.h> 42 #include <linux/can/error.h> 43 #include <linux/can/led.h> 44 45 #include "c_can.h" 46 47 /* Number of interface registers */ 48 #define IF_ENUM_REG_LEN 11 49 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 50 51 /* control extension register D_CAN specific */ 52 #define CONTROL_EX_PDR BIT(8) 53 54 /* control register */ 55 #define CONTROL_SWR BIT(15) 56 #define CONTROL_TEST BIT(7) 57 #define CONTROL_CCE BIT(6) 58 #define CONTROL_DISABLE_AR BIT(5) 59 #define CONTROL_ENABLE_AR (0 << 5) 60 #define CONTROL_EIE BIT(3) 61 #define CONTROL_SIE BIT(2) 62 #define CONTROL_IE BIT(1) 63 #define CONTROL_INIT BIT(0) 64 65 #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 66 67 /* test register */ 68 #define TEST_RX BIT(7) 69 #define TEST_TX1 BIT(6) 70 #define TEST_TX2 BIT(5) 71 #define TEST_LBACK BIT(4) 72 #define TEST_SILENT BIT(3) 73 #define TEST_BASIC BIT(2) 74 75 /* status register */ 76 #define STATUS_PDA BIT(10) 77 #define STATUS_BOFF BIT(7) 78 #define STATUS_EWARN BIT(6) 79 #define STATUS_EPASS BIT(5) 80 #define STATUS_RXOK BIT(4) 81 #define STATUS_TXOK BIT(3) 82 83 /* error counter register */ 84 #define ERR_CNT_TEC_MASK 0xff 85 #define ERR_CNT_TEC_SHIFT 0 86 #define ERR_CNT_REC_SHIFT 8 87 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 88 #define ERR_CNT_RP_SHIFT 15 89 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 90 91 /* bit-timing register */ 92 #define BTR_BRP_MASK 0x3f 93 #define BTR_BRP_SHIFT 0 94 #define BTR_SJW_SHIFT 6 95 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 96 #define BTR_TSEG1_SHIFT 8 97 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 98 #define BTR_TSEG2_SHIFT 12 99 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 100 101 /* interrupt register */ 102 #define INT_STS_PENDING 0x8000 103 104 /* brp extension register */ 105 #define BRP_EXT_BRPE_MASK 0x0f 106 #define BRP_EXT_BRPE_SHIFT 0 107 108 /* IFx command request */ 109 #define IF_COMR_BUSY BIT(15) 110 111 /* IFx command mask */ 112 #define IF_COMM_WR BIT(7) 113 #define IF_COMM_MASK BIT(6) 114 #define IF_COMM_ARB BIT(5) 115 #define IF_COMM_CONTROL BIT(4) 116 #define IF_COMM_CLR_INT_PND BIT(3) 117 #define IF_COMM_TXRQST BIT(2) 118 #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 119 #define IF_COMM_DATAA BIT(1) 120 #define IF_COMM_DATAB BIT(0) 121 122 /* TX buffer setup */ 123 #define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 124 IF_COMM_TXRQST | \ 125 IF_COMM_DATAA | IF_COMM_DATAB) 126 127 /* For the low buffers we clear the interrupt bit, but keep newdat */ 128 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 129 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 130 IF_COMM_DATAA | IF_COMM_DATAB) 131 132 /* For the high buffers we clear the interrupt bit and newdat */ 133 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 134 135 /* Receive setup of message objects */ 136 #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 137 138 /* Invalidation of message objects */ 139 #define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 140 141 /* IFx arbitration */ 142 #define IF_ARB_MSGVAL BIT(31) 143 #define IF_ARB_MSGXTD BIT(30) 144 #define IF_ARB_TRANSMIT BIT(29) 145 146 /* IFx message control */ 147 #define IF_MCONT_NEWDAT BIT(15) 148 #define IF_MCONT_MSGLST BIT(14) 149 #define IF_MCONT_INTPND BIT(13) 150 #define IF_MCONT_UMASK BIT(12) 151 #define IF_MCONT_TXIE BIT(11) 152 #define IF_MCONT_RXIE BIT(10) 153 #define IF_MCONT_RMTEN BIT(9) 154 #define IF_MCONT_TXRQST BIT(8) 155 #define IF_MCONT_EOB BIT(7) 156 #define IF_MCONT_DLC_MASK 0xf 157 158 #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 159 #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 160 161 #define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 162 163 /* Use IF1 in NAPI path and IF2 in TX path */ 164 #define IF_NAPI 0 165 #define IF_TX 1 166 167 /* minimum timeout for checking BUSY status */ 168 #define MIN_TIMEOUT_VALUE 6 169 170 /* Wait for ~1 sec for INIT bit */ 171 #define INIT_WAIT_MS 1000 172 173 /* c_can lec values */ 174 enum c_can_lec_type { 175 LEC_NO_ERROR = 0, 176 LEC_STUFF_ERROR, 177 LEC_FORM_ERROR, 178 LEC_ACK_ERROR, 179 LEC_BIT1_ERROR, 180 LEC_BIT0_ERROR, 181 LEC_CRC_ERROR, 182 LEC_UNUSED, 183 LEC_MASK = LEC_UNUSED, 184 }; 185 186 /* c_can error types: 187 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 188 */ 189 enum c_can_bus_error_types { 190 C_CAN_NO_ERROR = 0, 191 C_CAN_BUS_OFF, 192 C_CAN_ERROR_WARNING, 193 C_CAN_ERROR_PASSIVE, 194 }; 195 196 static const struct can_bittiming_const c_can_bittiming_const = { 197 .name = KBUILD_MODNAME, 198 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 199 .tseg1_max = 16, 200 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 201 .tseg2_max = 8, 202 .sjw_max = 4, 203 .brp_min = 1, 204 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 205 .brp_inc = 1, 206 }; 207 208 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 209 { 210 if (priv->device) 211 pm_runtime_get_sync(priv->device); 212 } 213 214 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 215 { 216 if (priv->device) 217 pm_runtime_put_sync(priv->device); 218 } 219 220 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 221 { 222 if (priv->raminit) 223 priv->raminit(priv, enable); 224 } 225 226 static void c_can_irq_control(struct c_can_priv *priv, bool enable) 227 { 228 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 229 230 if (enable) 231 ctrl |= CONTROL_IRQMSK; 232 233 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 234 } 235 236 static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 237 { 238 struct c_can_priv *priv = netdev_priv(dev); 239 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 240 241 priv->write_reg32(priv, reg, (cmd << 16) | obj); 242 243 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 244 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 245 return; 246 udelay(1); 247 } 248 netdev_err(dev, "Updating object timed out\n"); 249 } 250 251 static inline void c_can_object_get(struct net_device *dev, int iface, 252 u32 obj, u32 cmd) 253 { 254 c_can_obj_update(dev, iface, cmd, obj); 255 } 256 257 static inline void c_can_object_put(struct net_device *dev, int iface, 258 u32 obj, u32 cmd) 259 { 260 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 261 } 262 263 /* Note: According to documentation clearing TXIE while MSGVAL is set 264 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O 265 * load significantly. 266 */ 267 static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) 268 { 269 struct c_can_priv *priv = netdev_priv(dev); 270 271 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 272 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 273 } 274 275 static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 276 { 277 struct c_can_priv *priv = netdev_priv(dev); 278 279 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 280 c_can_inval_tx_object(dev, iface, obj); 281 } 282 283 static void c_can_setup_tx_object(struct net_device *dev, int iface, 284 struct can_frame *frame, int idx) 285 { 286 struct c_can_priv *priv = netdev_priv(dev); 287 u16 ctrl = IF_MCONT_TX | frame->len; 288 bool rtr = frame->can_id & CAN_RTR_FLAG; 289 u32 arb = IF_ARB_MSGVAL; 290 int i; 291 292 if (frame->can_id & CAN_EFF_FLAG) { 293 arb |= frame->can_id & CAN_EFF_MASK; 294 arb |= IF_ARB_MSGXTD; 295 } else { 296 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 297 } 298 299 if (!rtr) 300 arb |= IF_ARB_TRANSMIT; 301 302 /* If we change the DIR bit, we need to invalidate the buffer 303 * first, i.e. clear the MSGVAL flag in the arbiter. 304 */ 305 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { 306 u32 obj = idx + priv->msg_obj_tx_first; 307 308 c_can_inval_msg_object(dev, iface, obj); 309 change_bit(idx, &priv->tx_dir); 310 } 311 312 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 313 314 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 315 316 if (priv->type == BOSCH_D_CAN) { 317 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface); 318 319 for (i = 0; i < frame->len; i += 4, dreg += 2) { 320 data = (u32)frame->data[i]; 321 data |= (u32)frame->data[i + 1] << 8; 322 data |= (u32)frame->data[i + 2] << 16; 323 data |= (u32)frame->data[i + 3] << 24; 324 priv->write_reg32(priv, dreg, data); 325 } 326 } else { 327 for (i = 0; i < frame->len; i += 2) { 328 priv->write_reg(priv, 329 C_CAN_IFACE(DATA1_REG, iface) + i / 2, 330 frame->data[i] | 331 (frame->data[i + 1] << 8)); 332 } 333 } 334 } 335 336 static int c_can_handle_lost_msg_obj(struct net_device *dev, 337 int iface, int objno, u32 ctrl) 338 { 339 struct net_device_stats *stats = &dev->stats; 340 struct c_can_priv *priv = netdev_priv(dev); 341 struct can_frame *frame; 342 struct sk_buff *skb; 343 344 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 345 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 346 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 347 348 stats->rx_errors++; 349 stats->rx_over_errors++; 350 351 /* create an error msg */ 352 skb = alloc_can_err_skb(dev, &frame); 353 if (unlikely(!skb)) 354 return 0; 355 356 frame->can_id |= CAN_ERR_CRTL; 357 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 358 359 netif_receive_skb(skb); 360 return 1; 361 } 362 363 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 364 { 365 struct net_device_stats *stats = &dev->stats; 366 struct c_can_priv *priv = netdev_priv(dev); 367 struct can_frame *frame; 368 struct sk_buff *skb; 369 u32 arb, data; 370 371 skb = alloc_can_skb(dev, &frame); 372 if (!skb) { 373 stats->rx_dropped++; 374 return -ENOMEM; 375 } 376 377 frame->len = can_cc_dlc2len(ctrl & 0x0F); 378 379 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); 380 381 if (arb & IF_ARB_MSGXTD) 382 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 383 else 384 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 385 386 if (arb & IF_ARB_TRANSMIT) { 387 frame->can_id |= CAN_RTR_FLAG; 388 } else { 389 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 390 391 if (priv->type == BOSCH_D_CAN) { 392 for (i = 0; i < frame->len; i += 4, dreg += 2) { 393 data = priv->read_reg32(priv, dreg); 394 frame->data[i] = data; 395 frame->data[i + 1] = data >> 8; 396 frame->data[i + 2] = data >> 16; 397 frame->data[i + 3] = data >> 24; 398 } 399 } else { 400 for (i = 0; i < frame->len; i += 2, dreg++) { 401 data = priv->read_reg(priv, dreg); 402 frame->data[i] = data; 403 frame->data[i + 1] = data >> 8; 404 } 405 } 406 407 stats->rx_bytes += frame->len; 408 } 409 stats->rx_packets++; 410 411 netif_receive_skb(skb); 412 return 0; 413 } 414 415 static void c_can_setup_receive_object(struct net_device *dev, int iface, 416 u32 obj, u32 mask, u32 id, u32 mcont) 417 { 418 struct c_can_priv *priv = netdev_priv(dev); 419 420 mask |= BIT(29); 421 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 422 423 id |= IF_ARB_MSGVAL; 424 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); 425 426 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 427 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 428 } 429 430 static bool c_can_tx_busy(const struct c_can_priv *priv, 431 const struct c_can_tx_ring *tx_ring) 432 { 433 if (c_can_get_tx_free(tx_ring) > 0) 434 return false; 435 436 netif_stop_queue(priv->dev); 437 438 /* Memory barrier before checking tx_free (head and tail) */ 439 smp_mb(); 440 441 if (c_can_get_tx_free(tx_ring) == 0) { 442 netdev_dbg(priv->dev, 443 "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n", 444 tx_ring->head, tx_ring->tail, 445 tx_ring->head - tx_ring->tail); 446 return true; 447 } 448 449 netif_start_queue(priv->dev); 450 return false; 451 } 452 453 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 454 struct net_device *dev) 455 { 456 struct can_frame *frame = (struct can_frame *)skb->data; 457 struct c_can_priv *priv = netdev_priv(dev); 458 struct c_can_tx_ring *tx_ring = &priv->tx; 459 u32 idx, obj, cmd = IF_COMM_TX; 460 461 if (can_dropped_invalid_skb(dev, skb)) 462 return NETDEV_TX_OK; 463 464 if (c_can_tx_busy(priv, tx_ring)) 465 return NETDEV_TX_BUSY; 466 467 idx = c_can_get_tx_head(tx_ring); 468 tx_ring->head++; 469 if (c_can_get_tx_free(tx_ring) == 0) 470 netif_stop_queue(dev); 471 472 if (idx < c_can_get_tx_tail(tx_ring)) 473 cmd &= ~IF_COMM_TXRQST; /* Cache the message */ 474 475 /* Store the message in the interface so we can call 476 * can_put_echo_skb(). We must do this before we enable 477 * transmit as we might race against do_tx(). 478 */ 479 c_can_setup_tx_object(dev, IF_TX, frame, idx); 480 can_put_echo_skb(skb, dev, idx, 0); 481 obj = idx + priv->msg_obj_tx_first; 482 c_can_object_put(dev, IF_TX, obj, cmd); 483 484 return NETDEV_TX_OK; 485 } 486 487 static int c_can_wait_for_ctrl_init(struct net_device *dev, 488 struct c_can_priv *priv, u32 init) 489 { 490 int retry = 0; 491 492 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 493 udelay(10); 494 if (retry++ > 1000) { 495 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 496 return -EIO; 497 } 498 } 499 return 0; 500 } 501 502 static int c_can_set_bittiming(struct net_device *dev) 503 { 504 unsigned int reg_btr, reg_brpe, ctrl_save; 505 u8 brp, brpe, sjw, tseg1, tseg2; 506 u32 ten_bit_brp; 507 struct c_can_priv *priv = netdev_priv(dev); 508 const struct can_bittiming *bt = &priv->can.bittiming; 509 int res; 510 511 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 512 ten_bit_brp = bt->brp - 1; 513 brp = ten_bit_brp & BTR_BRP_MASK; 514 brpe = ten_bit_brp >> 6; 515 516 sjw = bt->sjw - 1; 517 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 518 tseg2 = bt->phase_seg2 - 1; 519 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 520 (tseg2 << BTR_TSEG2_SHIFT); 521 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 522 523 netdev_info(dev, 524 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 525 526 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 527 ctrl_save &= ~CONTROL_INIT; 528 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 529 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 530 if (res) 531 return res; 532 533 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 534 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 535 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 536 537 return c_can_wait_for_ctrl_init(dev, priv, 0); 538 } 539 540 /* Configure C_CAN message objects for Tx and Rx purposes: 541 * C_CAN provides a total of 32 message objects that can be configured 542 * either for Tx or Rx purposes. Here the first 16 message objects are used as 543 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 544 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 545 * See user guide document for further details on configuring message 546 * objects. 547 */ 548 static void c_can_configure_msg_objects(struct net_device *dev) 549 { 550 struct c_can_priv *priv = netdev_priv(dev); 551 int i; 552 553 /* first invalidate all message objects */ 554 for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++) 555 c_can_inval_msg_object(dev, IF_NAPI, i); 556 557 /* setup receive message objects */ 558 for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++) 559 c_can_setup_receive_object(dev, IF_NAPI, i, 0, 0, IF_MCONT_RCV); 560 561 c_can_setup_receive_object(dev, IF_NAPI, priv->msg_obj_rx_last, 0, 0, 562 IF_MCONT_RCV_EOB); 563 } 564 565 static int c_can_software_reset(struct net_device *dev) 566 { 567 struct c_can_priv *priv = netdev_priv(dev); 568 int retry = 0; 569 570 if (priv->type != BOSCH_D_CAN) 571 return 0; 572 573 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT); 574 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) { 575 msleep(20); 576 if (retry++ > 100) { 577 netdev_err(dev, "CCTRL: software reset failed\n"); 578 return -EIO; 579 } 580 } 581 582 return 0; 583 } 584 585 /* Configure C_CAN chip: 586 * - enable/disable auto-retransmission 587 * - set operating mode 588 * - configure message objects 589 */ 590 static int c_can_chip_config(struct net_device *dev) 591 { 592 struct c_can_priv *priv = netdev_priv(dev); 593 struct c_can_tx_ring *tx_ring = &priv->tx; 594 int err; 595 596 err = c_can_software_reset(dev); 597 if (err) 598 return err; 599 600 /* enable automatic retransmission */ 601 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 602 603 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 604 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 605 /* loopback + silent mode : useful for hot self-test */ 606 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 607 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 608 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 609 /* loopback mode : useful for self-test function */ 610 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 611 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 612 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 613 /* silent mode : bus-monitoring mode */ 614 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 615 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 616 } 617 618 /* configure message objects */ 619 c_can_configure_msg_objects(dev); 620 621 /* set a `lec` value so that we can check for updates later */ 622 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 623 624 /* Clear all internal status */ 625 tx_ring->head = 0; 626 tx_ring->tail = 0; 627 priv->tx_dir = 0; 628 629 /* set bittiming params */ 630 return c_can_set_bittiming(dev); 631 } 632 633 static int c_can_start(struct net_device *dev) 634 { 635 struct c_can_priv *priv = netdev_priv(dev); 636 int err; 637 struct pinctrl *p; 638 639 /* basic c_can configuration */ 640 err = c_can_chip_config(dev); 641 if (err) 642 return err; 643 644 /* Setup the command for new messages */ 645 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 646 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 647 648 priv->can.state = CAN_STATE_ERROR_ACTIVE; 649 650 /* Attempt to use "active" if available else use "default" */ 651 p = pinctrl_get_select(priv->device, "active"); 652 if (!IS_ERR(p)) 653 pinctrl_put(p); 654 else 655 pinctrl_pm_select_default_state(priv->device); 656 657 return 0; 658 } 659 660 static void c_can_stop(struct net_device *dev) 661 { 662 struct c_can_priv *priv = netdev_priv(dev); 663 664 c_can_irq_control(priv, false); 665 666 /* put ctrl to init on stop to end ongoing transmission */ 667 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); 668 669 /* deactivate pins */ 670 pinctrl_pm_select_sleep_state(dev->dev.parent); 671 priv->can.state = CAN_STATE_STOPPED; 672 } 673 674 static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 675 { 676 struct c_can_priv *priv = netdev_priv(dev); 677 int err; 678 679 switch (mode) { 680 case CAN_MODE_START: 681 err = c_can_start(dev); 682 if (err) 683 return err; 684 netif_wake_queue(dev); 685 c_can_irq_control(priv, true); 686 break; 687 default: 688 return -EOPNOTSUPP; 689 } 690 691 return 0; 692 } 693 694 static int __c_can_get_berr_counter(const struct net_device *dev, 695 struct can_berr_counter *bec) 696 { 697 unsigned int reg_err_counter; 698 struct c_can_priv *priv = netdev_priv(dev); 699 700 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 701 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 702 ERR_CNT_REC_SHIFT; 703 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 704 705 return 0; 706 } 707 708 static int c_can_get_berr_counter(const struct net_device *dev, 709 struct can_berr_counter *bec) 710 { 711 struct c_can_priv *priv = netdev_priv(dev); 712 int err; 713 714 c_can_pm_runtime_get_sync(priv); 715 err = __c_can_get_berr_counter(dev, bec); 716 c_can_pm_runtime_put_sync(priv); 717 718 return err; 719 } 720 721 static void c_can_do_tx(struct net_device *dev) 722 { 723 struct c_can_priv *priv = netdev_priv(dev); 724 struct c_can_tx_ring *tx_ring = &priv->tx; 725 struct net_device_stats *stats = &dev->stats; 726 u32 idx, obj, pkts = 0, bytes = 0, pend; 727 u8 tail; 728 729 if (priv->msg_obj_tx_last > 32) 730 pend = priv->read_reg32(priv, C_CAN_INTPND3_REG); 731 else 732 pend = priv->read_reg(priv, C_CAN_INTPND2_REG); 733 734 while ((idx = ffs(pend))) { 735 idx--; 736 pend &= ~BIT(idx); 737 obj = idx + priv->msg_obj_tx_first; 738 739 /* We use IF_NAPI interface instead of IF_TX because we 740 * are called from c_can_poll(), which runs inside 741 * NAPI. We are not transmitting. 742 */ 743 c_can_inval_tx_object(dev, IF_NAPI, obj); 744 bytes += can_get_echo_skb(dev, idx, NULL); 745 pkts++; 746 } 747 748 if (!pkts) 749 return; 750 751 tx_ring->tail += pkts; 752 if (c_can_get_tx_free(tx_ring)) { 753 /* Make sure that anybody stopping the queue after 754 * this sees the new tx_ring->tail. 755 */ 756 smp_mb(); 757 netif_wake_queue(priv->dev); 758 } 759 760 stats->tx_bytes += bytes; 761 stats->tx_packets += pkts; 762 can_led_event(dev, CAN_LED_EVENT_TX); 763 764 tail = c_can_get_tx_tail(tx_ring); 765 766 if (tail == 0) { 767 u8 head = c_can_get_tx_head(tx_ring); 768 769 /* Start transmission for all cached messages */ 770 for (idx = tail; idx < head; idx++) { 771 obj = idx + priv->msg_obj_tx_first; 772 c_can_object_put(dev, IF_NAPI, obj, IF_COMM_TXRQST); 773 } 774 } 775 } 776 777 /* If we have a gap in the pending bits, that means we either 778 * raced with the hardware or failed to readout all upper 779 * objects in the last run due to quota limit. 780 */ 781 static u32 c_can_adjust_pending(u32 pend, u32 rx_mask) 782 { 783 u32 weight, lasts; 784 785 if (pend == rx_mask) 786 return pend; 787 788 /* If the last set bit is larger than the number of pending 789 * bits we have a gap. 790 */ 791 weight = hweight32(pend); 792 lasts = fls(pend); 793 794 /* If the bits are linear, nothing to do */ 795 if (lasts == weight) 796 return pend; 797 798 /* Find the first set bit after the gap. We walk backwards 799 * from the last set bit. 800 */ 801 for (lasts--; pend & BIT(lasts - 1); lasts--) 802 ; 803 804 return pend & ~GENMASK(lasts - 1, 0); 805 } 806 807 static inline void c_can_rx_object_get(struct net_device *dev, 808 struct c_can_priv *priv, u32 obj) 809 { 810 c_can_object_get(dev, IF_NAPI, obj, priv->comm_rcv_high); 811 } 812 813 static inline void c_can_rx_finalize(struct net_device *dev, 814 struct c_can_priv *priv, u32 obj) 815 { 816 if (priv->type != BOSCH_D_CAN) 817 c_can_object_get(dev, IF_NAPI, obj, IF_COMM_CLR_NEWDAT); 818 } 819 820 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 821 u32 pend, int quota) 822 { 823 u32 pkts = 0, ctrl, obj; 824 825 while ((obj = ffs(pend)) && quota > 0) { 826 pend &= ~BIT(obj - 1); 827 828 c_can_rx_object_get(dev, priv, obj); 829 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_NAPI)); 830 831 if (ctrl & IF_MCONT_MSGLST) { 832 int n; 833 834 n = c_can_handle_lost_msg_obj(dev, IF_NAPI, obj, ctrl); 835 836 pkts += n; 837 quota -= n; 838 continue; 839 } 840 841 /* This really should not happen, but this covers some 842 * odd HW behaviour. Do not remove that unless you 843 * want to brick your machine. 844 */ 845 if (!(ctrl & IF_MCONT_NEWDAT)) 846 continue; 847 848 /* read the data from the message object */ 849 c_can_read_msg_object(dev, IF_NAPI, ctrl); 850 851 c_can_rx_finalize(dev, priv, obj); 852 853 pkts++; 854 quota--; 855 } 856 857 return pkts; 858 } 859 860 static inline u32 c_can_get_pending(struct c_can_priv *priv) 861 { 862 u32 pend; 863 864 if (priv->msg_obj_rx_last > 16) 865 pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG); 866 else 867 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 868 869 return pend; 870 } 871 872 /* theory of operation: 873 * 874 * c_can core saves a received CAN message into the first free message 875 * object it finds free (starting with the lowest). Bits NEWDAT and 876 * INTPND are set for this message object indicating that a new message 877 * has arrived. 878 * 879 * We clear the newdat bit right away. 880 * 881 * This can result in packet reordering when the readout is slow. 882 */ 883 static int c_can_do_rx_poll(struct net_device *dev, int quota) 884 { 885 struct c_can_priv *priv = netdev_priv(dev); 886 u32 pkts = 0, pend = 0, toread, n; 887 888 while (quota > 0) { 889 if (!pend) { 890 pend = c_can_get_pending(priv); 891 if (!pend) 892 break; 893 /* If the pending field has a gap, handle the 894 * bits above the gap first. 895 */ 896 toread = c_can_adjust_pending(pend, 897 priv->msg_obj_rx_mask); 898 } else { 899 toread = pend; 900 } 901 /* Remove the bits from pend */ 902 pend &= ~toread; 903 /* Read the objects */ 904 n = c_can_read_objects(dev, priv, toread, quota); 905 pkts += n; 906 quota -= n; 907 } 908 909 if (pkts) 910 can_led_event(dev, CAN_LED_EVENT_RX); 911 912 return pkts; 913 } 914 915 static int c_can_handle_state_change(struct net_device *dev, 916 enum c_can_bus_error_types error_type) 917 { 918 unsigned int reg_err_counter; 919 unsigned int rx_err_passive; 920 struct c_can_priv *priv = netdev_priv(dev); 921 struct can_frame *cf; 922 struct sk_buff *skb; 923 struct can_berr_counter bec; 924 925 switch (error_type) { 926 case C_CAN_NO_ERROR: 927 priv->can.state = CAN_STATE_ERROR_ACTIVE; 928 break; 929 case C_CAN_ERROR_WARNING: 930 /* error warning state */ 931 priv->can.can_stats.error_warning++; 932 priv->can.state = CAN_STATE_ERROR_WARNING; 933 break; 934 case C_CAN_ERROR_PASSIVE: 935 /* error passive state */ 936 priv->can.can_stats.error_passive++; 937 priv->can.state = CAN_STATE_ERROR_PASSIVE; 938 break; 939 case C_CAN_BUS_OFF: 940 /* bus-off state */ 941 priv->can.state = CAN_STATE_BUS_OFF; 942 priv->can.can_stats.bus_off++; 943 break; 944 default: 945 break; 946 } 947 948 /* propagate the error condition to the CAN stack */ 949 skb = alloc_can_err_skb(dev, &cf); 950 if (unlikely(!skb)) 951 return 0; 952 953 __c_can_get_berr_counter(dev, &bec); 954 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 955 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 956 ERR_CNT_RP_SHIFT; 957 958 switch (error_type) { 959 case C_CAN_NO_ERROR: 960 /* error warning state */ 961 cf->can_id |= CAN_ERR_CRTL; 962 cf->data[1] = CAN_ERR_CRTL_ACTIVE; 963 cf->data[6] = bec.txerr; 964 cf->data[7] = bec.rxerr; 965 break; 966 case C_CAN_ERROR_WARNING: 967 /* error warning state */ 968 cf->can_id |= CAN_ERR_CRTL; 969 cf->data[1] = (bec.txerr > bec.rxerr) ? 970 CAN_ERR_CRTL_TX_WARNING : 971 CAN_ERR_CRTL_RX_WARNING; 972 cf->data[6] = bec.txerr; 973 cf->data[7] = bec.rxerr; 974 975 break; 976 case C_CAN_ERROR_PASSIVE: 977 /* error passive state */ 978 cf->can_id |= CAN_ERR_CRTL; 979 if (rx_err_passive) 980 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 981 if (bec.txerr > 127) 982 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 983 984 cf->data[6] = bec.txerr; 985 cf->data[7] = bec.rxerr; 986 break; 987 case C_CAN_BUS_OFF: 988 /* bus-off state */ 989 cf->can_id |= CAN_ERR_BUSOFF; 990 can_bus_off(dev); 991 break; 992 default: 993 break; 994 } 995 996 netif_receive_skb(skb); 997 998 return 1; 999 } 1000 1001 static int c_can_handle_bus_err(struct net_device *dev, 1002 enum c_can_lec_type lec_type) 1003 { 1004 struct c_can_priv *priv = netdev_priv(dev); 1005 struct net_device_stats *stats = &dev->stats; 1006 struct can_frame *cf; 1007 struct sk_buff *skb; 1008 1009 /* early exit if no lec update or no error. 1010 * no lec update means that no CAN bus event has been detected 1011 * since CPU wrote 0x7 value to status reg. 1012 */ 1013 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 1014 return 0; 1015 1016 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1017 return 0; 1018 1019 /* common for all type of bus errors */ 1020 priv->can.can_stats.bus_error++; 1021 stats->rx_errors++; 1022 1023 /* propagate the error condition to the CAN stack */ 1024 skb = alloc_can_err_skb(dev, &cf); 1025 if (unlikely(!skb)) 1026 return 0; 1027 1028 /* check for 'last error code' which tells us the 1029 * type of the last error to occur on the CAN bus 1030 */ 1031 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1032 1033 switch (lec_type) { 1034 case LEC_STUFF_ERROR: 1035 netdev_dbg(dev, "stuff error\n"); 1036 cf->data[2] |= CAN_ERR_PROT_STUFF; 1037 break; 1038 case LEC_FORM_ERROR: 1039 netdev_dbg(dev, "form error\n"); 1040 cf->data[2] |= CAN_ERR_PROT_FORM; 1041 break; 1042 case LEC_ACK_ERROR: 1043 netdev_dbg(dev, "ack error\n"); 1044 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 1045 break; 1046 case LEC_BIT1_ERROR: 1047 netdev_dbg(dev, "bit1 error\n"); 1048 cf->data[2] |= CAN_ERR_PROT_BIT1; 1049 break; 1050 case LEC_BIT0_ERROR: 1051 netdev_dbg(dev, "bit0 error\n"); 1052 cf->data[2] |= CAN_ERR_PROT_BIT0; 1053 break; 1054 case LEC_CRC_ERROR: 1055 netdev_dbg(dev, "CRC error\n"); 1056 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 1057 break; 1058 default: 1059 break; 1060 } 1061 1062 netif_receive_skb(skb); 1063 return 1; 1064 } 1065 1066 static int c_can_poll(struct napi_struct *napi, int quota) 1067 { 1068 struct net_device *dev = napi->dev; 1069 struct c_can_priv *priv = netdev_priv(dev); 1070 u16 curr, last = priv->last_status; 1071 int work_done = 0; 1072 1073 /* Only read the status register if a status interrupt was pending */ 1074 if (atomic_xchg(&priv->sie_pending, 0)) { 1075 priv->last_status = priv->read_reg(priv, C_CAN_STS_REG); 1076 curr = priv->last_status; 1077 /* Ack status on C_CAN. D_CAN is self clearing */ 1078 if (priv->type != BOSCH_D_CAN) 1079 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1080 } else { 1081 /* no change detected ... */ 1082 curr = last; 1083 } 1084 1085 /* handle state changes */ 1086 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1087 netdev_dbg(dev, "entered error warning state\n"); 1088 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1089 } 1090 1091 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1092 netdev_dbg(dev, "entered error passive state\n"); 1093 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1094 } 1095 1096 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1097 netdev_dbg(dev, "entered bus off state\n"); 1098 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1099 goto end; 1100 } 1101 1102 /* handle bus recovery events */ 1103 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1104 netdev_dbg(dev, "left bus off state\n"); 1105 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1106 } 1107 1108 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1109 netdev_dbg(dev, "left error passive state\n"); 1110 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1111 } 1112 1113 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) { 1114 netdev_dbg(dev, "left error warning state\n"); 1115 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR); 1116 } 1117 1118 /* handle lec errors on the bus */ 1119 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1120 1121 /* Handle Tx/Rx events. We do this unconditionally */ 1122 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1123 c_can_do_tx(dev); 1124 1125 end: 1126 if (work_done < quota) { 1127 napi_complete_done(napi, work_done); 1128 /* enable all IRQs if we are not in bus off state */ 1129 if (priv->can.state != CAN_STATE_BUS_OFF) 1130 c_can_irq_control(priv, true); 1131 } 1132 1133 return work_done; 1134 } 1135 1136 static irqreturn_t c_can_isr(int irq, void *dev_id) 1137 { 1138 struct net_device *dev = (struct net_device *)dev_id; 1139 struct c_can_priv *priv = netdev_priv(dev); 1140 int reg_int; 1141 1142 reg_int = priv->read_reg(priv, C_CAN_INT_REG); 1143 if (!reg_int) 1144 return IRQ_NONE; 1145 1146 /* save for later use */ 1147 if (reg_int & INT_STS_PENDING) 1148 atomic_set(&priv->sie_pending, 1); 1149 1150 /* disable all interrupts and schedule the NAPI */ 1151 c_can_irq_control(priv, false); 1152 napi_schedule(&priv->napi); 1153 1154 return IRQ_HANDLED; 1155 } 1156 1157 static int c_can_open(struct net_device *dev) 1158 { 1159 int err; 1160 struct c_can_priv *priv = netdev_priv(dev); 1161 1162 c_can_pm_runtime_get_sync(priv); 1163 c_can_reset_ram(priv, true); 1164 1165 /* open the can device */ 1166 err = open_candev(dev); 1167 if (err) { 1168 netdev_err(dev, "failed to open can device\n"); 1169 goto exit_open_fail; 1170 } 1171 1172 /* register interrupt handler */ 1173 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1174 dev); 1175 if (err < 0) { 1176 netdev_err(dev, "failed to request interrupt\n"); 1177 goto exit_irq_fail; 1178 } 1179 1180 /* start the c_can controller */ 1181 err = c_can_start(dev); 1182 if (err) 1183 goto exit_start_fail; 1184 1185 can_led_event(dev, CAN_LED_EVENT_OPEN); 1186 1187 napi_enable(&priv->napi); 1188 /* enable status change, error and module interrupts */ 1189 c_can_irq_control(priv, true); 1190 netif_start_queue(dev); 1191 1192 return 0; 1193 1194 exit_start_fail: 1195 free_irq(dev->irq, dev); 1196 exit_irq_fail: 1197 close_candev(dev); 1198 exit_open_fail: 1199 c_can_reset_ram(priv, false); 1200 c_can_pm_runtime_put_sync(priv); 1201 return err; 1202 } 1203 1204 static int c_can_close(struct net_device *dev) 1205 { 1206 struct c_can_priv *priv = netdev_priv(dev); 1207 1208 netif_stop_queue(dev); 1209 napi_disable(&priv->napi); 1210 c_can_stop(dev); 1211 free_irq(dev->irq, dev); 1212 close_candev(dev); 1213 1214 c_can_reset_ram(priv, false); 1215 c_can_pm_runtime_put_sync(priv); 1216 1217 can_led_event(dev, CAN_LED_EVENT_STOP); 1218 1219 return 0; 1220 } 1221 1222 struct net_device *alloc_c_can_dev(int msg_obj_num) 1223 { 1224 struct net_device *dev; 1225 struct c_can_priv *priv; 1226 int msg_obj_tx_num = msg_obj_num / 2; 1227 1228 dev = alloc_candev(sizeof(*priv), msg_obj_tx_num); 1229 if (!dev) 1230 return NULL; 1231 1232 priv = netdev_priv(dev); 1233 priv->msg_obj_num = msg_obj_num; 1234 priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num; 1235 priv->msg_obj_rx_first = 1; 1236 priv->msg_obj_rx_last = 1237 priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1; 1238 priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0); 1239 1240 priv->msg_obj_tx_num = msg_obj_tx_num; 1241 priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1; 1242 priv->msg_obj_tx_last = 1243 priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1; 1244 1245 priv->tx.head = 0; 1246 priv->tx.tail = 0; 1247 priv->tx.obj_num = msg_obj_tx_num; 1248 1249 netif_napi_add(dev, &priv->napi, c_can_poll, priv->msg_obj_rx_num); 1250 1251 priv->dev = dev; 1252 priv->can.bittiming_const = &c_can_bittiming_const; 1253 priv->can.do_set_mode = c_can_set_mode; 1254 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1255 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1256 CAN_CTRLMODE_LISTENONLY | 1257 CAN_CTRLMODE_BERR_REPORTING; 1258 1259 return dev; 1260 } 1261 EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1262 1263 #ifdef CONFIG_PM 1264 int c_can_power_down(struct net_device *dev) 1265 { 1266 u32 val; 1267 unsigned long time_out; 1268 struct c_can_priv *priv = netdev_priv(dev); 1269 1270 if (!(dev->flags & IFF_UP)) 1271 return 0; 1272 1273 WARN_ON(priv->type != BOSCH_D_CAN); 1274 1275 /* set PDR value so the device goes to power down mode */ 1276 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1277 val |= CONTROL_EX_PDR; 1278 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1279 1280 /* Wait for the PDA bit to get set */ 1281 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1282 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1283 time_after(time_out, jiffies)) 1284 cpu_relax(); 1285 1286 if (time_after(jiffies, time_out)) 1287 return -ETIMEDOUT; 1288 1289 c_can_stop(dev); 1290 1291 c_can_reset_ram(priv, false); 1292 c_can_pm_runtime_put_sync(priv); 1293 1294 return 0; 1295 } 1296 EXPORT_SYMBOL_GPL(c_can_power_down); 1297 1298 int c_can_power_up(struct net_device *dev) 1299 { 1300 u32 val; 1301 unsigned long time_out; 1302 struct c_can_priv *priv = netdev_priv(dev); 1303 int ret; 1304 1305 if (!(dev->flags & IFF_UP)) 1306 return 0; 1307 1308 WARN_ON(priv->type != BOSCH_D_CAN); 1309 1310 c_can_pm_runtime_get_sync(priv); 1311 c_can_reset_ram(priv, true); 1312 1313 /* Clear PDR and INIT bits */ 1314 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1315 val &= ~CONTROL_EX_PDR; 1316 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1317 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1318 val &= ~CONTROL_INIT; 1319 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1320 1321 /* Wait for the PDA bit to get clear */ 1322 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1323 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1324 time_after(time_out, jiffies)) 1325 cpu_relax(); 1326 1327 if (time_after(jiffies, time_out)) { 1328 ret = -ETIMEDOUT; 1329 goto err_out; 1330 } 1331 1332 ret = c_can_start(dev); 1333 if (ret) 1334 goto err_out; 1335 1336 c_can_irq_control(priv, true); 1337 1338 return 0; 1339 1340 err_out: 1341 c_can_reset_ram(priv, false); 1342 c_can_pm_runtime_put_sync(priv); 1343 1344 return ret; 1345 } 1346 EXPORT_SYMBOL_GPL(c_can_power_up); 1347 #endif 1348 1349 void free_c_can_dev(struct net_device *dev) 1350 { 1351 struct c_can_priv *priv = netdev_priv(dev); 1352 1353 netif_napi_del(&priv->napi); 1354 free_candev(dev); 1355 } 1356 EXPORT_SYMBOL_GPL(free_c_can_dev); 1357 1358 static const struct net_device_ops c_can_netdev_ops = { 1359 .ndo_open = c_can_open, 1360 .ndo_stop = c_can_close, 1361 .ndo_start_xmit = c_can_start_xmit, 1362 .ndo_change_mtu = can_change_mtu, 1363 }; 1364 1365 int register_c_can_dev(struct net_device *dev) 1366 { 1367 int err; 1368 1369 /* Deactivate pins to prevent DRA7 DCAN IP from being 1370 * stuck in transition when module is disabled. 1371 * Pins are activated in c_can_start() and deactivated 1372 * in c_can_stop() 1373 */ 1374 pinctrl_pm_select_sleep_state(dev->dev.parent); 1375 1376 dev->flags |= IFF_ECHO; /* we support local echo */ 1377 dev->netdev_ops = &c_can_netdev_ops; 1378 c_can_set_ethtool_ops(dev); 1379 1380 err = register_candev(dev); 1381 if (!err) 1382 devm_can_led_init(dev); 1383 return err; 1384 } 1385 EXPORT_SYMBOL_GPL(register_c_can_dev); 1386 1387 void unregister_c_can_dev(struct net_device *dev) 1388 { 1389 unregister_candev(dev); 1390 } 1391 EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1392 1393 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1394 MODULE_LICENSE("GPL v2"); 1395 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1396