1 /* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/interrupt.h> 31 #include <linux/delay.h> 32 #include <linux/netdevice.h> 33 #include <linux/if_arp.h> 34 #include <linux/if_ether.h> 35 #include <linux/list.h> 36 #include <linux/io.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/pinctrl/consumer.h> 39 40 #include <linux/can.h> 41 #include <linux/can/dev.h> 42 #include <linux/can/error.h> 43 #include <linux/can/led.h> 44 45 #include "c_can.h" 46 47 /* Number of interface registers */ 48 #define IF_ENUM_REG_LEN 11 49 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 50 51 /* control extension register D_CAN specific */ 52 #define CONTROL_EX_PDR BIT(8) 53 54 /* control register */ 55 #define CONTROL_SWR BIT(15) 56 #define CONTROL_TEST BIT(7) 57 #define CONTROL_CCE BIT(6) 58 #define CONTROL_DISABLE_AR BIT(5) 59 #define CONTROL_ENABLE_AR (0 << 5) 60 #define CONTROL_EIE BIT(3) 61 #define CONTROL_SIE BIT(2) 62 #define CONTROL_IE BIT(1) 63 #define CONTROL_INIT BIT(0) 64 65 #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 66 67 /* test register */ 68 #define TEST_RX BIT(7) 69 #define TEST_TX1 BIT(6) 70 #define TEST_TX2 BIT(5) 71 #define TEST_LBACK BIT(4) 72 #define TEST_SILENT BIT(3) 73 #define TEST_BASIC BIT(2) 74 75 /* status register */ 76 #define STATUS_PDA BIT(10) 77 #define STATUS_BOFF BIT(7) 78 #define STATUS_EWARN BIT(6) 79 #define STATUS_EPASS BIT(5) 80 #define STATUS_RXOK BIT(4) 81 #define STATUS_TXOK BIT(3) 82 83 /* error counter register */ 84 #define ERR_CNT_TEC_MASK 0xff 85 #define ERR_CNT_TEC_SHIFT 0 86 #define ERR_CNT_REC_SHIFT 8 87 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 88 #define ERR_CNT_RP_SHIFT 15 89 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 90 91 /* bit-timing register */ 92 #define BTR_BRP_MASK 0x3f 93 #define BTR_BRP_SHIFT 0 94 #define BTR_SJW_SHIFT 6 95 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 96 #define BTR_TSEG1_SHIFT 8 97 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 98 #define BTR_TSEG2_SHIFT 12 99 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 100 101 /* interrupt register */ 102 #define INT_STS_PENDING 0x8000 103 104 /* brp extension register */ 105 #define BRP_EXT_BRPE_MASK 0x0f 106 #define BRP_EXT_BRPE_SHIFT 0 107 108 /* IFx command request */ 109 #define IF_COMR_BUSY BIT(15) 110 111 /* IFx command mask */ 112 #define IF_COMM_WR BIT(7) 113 #define IF_COMM_MASK BIT(6) 114 #define IF_COMM_ARB BIT(5) 115 #define IF_COMM_CONTROL BIT(4) 116 #define IF_COMM_CLR_INT_PND BIT(3) 117 #define IF_COMM_TXRQST BIT(2) 118 #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 119 #define IF_COMM_DATAA BIT(1) 120 #define IF_COMM_DATAB BIT(0) 121 122 /* TX buffer setup */ 123 #define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 124 IF_COMM_TXRQST | \ 125 IF_COMM_DATAA | IF_COMM_DATAB) 126 127 /* For the low buffers we clear the interrupt bit, but keep newdat */ 128 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 129 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 130 IF_COMM_DATAA | IF_COMM_DATAB) 131 132 /* For the high buffers we clear the interrupt bit and newdat */ 133 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 134 135 /* Receive setup of message objects */ 136 #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 137 138 /* Invalidation of message objects */ 139 #define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 140 141 /* IFx arbitration */ 142 #define IF_ARB_MSGVAL BIT(31) 143 #define IF_ARB_MSGXTD BIT(30) 144 #define IF_ARB_TRANSMIT BIT(29) 145 146 /* IFx message control */ 147 #define IF_MCONT_NEWDAT BIT(15) 148 #define IF_MCONT_MSGLST BIT(14) 149 #define IF_MCONT_INTPND BIT(13) 150 #define IF_MCONT_UMASK BIT(12) 151 #define IF_MCONT_TXIE BIT(11) 152 #define IF_MCONT_RXIE BIT(10) 153 #define IF_MCONT_RMTEN BIT(9) 154 #define IF_MCONT_TXRQST BIT(8) 155 #define IF_MCONT_EOB BIT(7) 156 #define IF_MCONT_DLC_MASK 0xf 157 158 #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 159 #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 160 161 #define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 162 163 /* Use IF1 for RX and IF2 for TX */ 164 #define IF_RX 0 165 #define IF_TX 1 166 167 /* minimum timeout for checking BUSY status */ 168 #define MIN_TIMEOUT_VALUE 6 169 170 /* Wait for ~1 sec for INIT bit */ 171 #define INIT_WAIT_MS 1000 172 173 /* c_can lec values */ 174 enum c_can_lec_type { 175 LEC_NO_ERROR = 0, 176 LEC_STUFF_ERROR, 177 LEC_FORM_ERROR, 178 LEC_ACK_ERROR, 179 LEC_BIT1_ERROR, 180 LEC_BIT0_ERROR, 181 LEC_CRC_ERROR, 182 LEC_UNUSED, 183 LEC_MASK = LEC_UNUSED, 184 }; 185 186 /* c_can error types: 187 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 188 */ 189 enum c_can_bus_error_types { 190 C_CAN_NO_ERROR = 0, 191 C_CAN_BUS_OFF, 192 C_CAN_ERROR_WARNING, 193 C_CAN_ERROR_PASSIVE, 194 }; 195 196 static const struct can_bittiming_const c_can_bittiming_const = { 197 .name = KBUILD_MODNAME, 198 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 199 .tseg1_max = 16, 200 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 201 .tseg2_max = 8, 202 .sjw_max = 4, 203 .brp_min = 1, 204 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 205 .brp_inc = 1, 206 }; 207 208 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 209 { 210 if (priv->device) 211 pm_runtime_get_sync(priv->device); 212 } 213 214 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 215 { 216 if (priv->device) 217 pm_runtime_put_sync(priv->device); 218 } 219 220 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 221 { 222 if (priv->raminit) 223 priv->raminit(priv, enable); 224 } 225 226 static void c_can_irq_control(struct c_can_priv *priv, bool enable) 227 { 228 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 229 230 if (enable) 231 ctrl |= CONTROL_IRQMSK; 232 233 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 234 } 235 236 static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 237 { 238 struct c_can_priv *priv = netdev_priv(dev); 239 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 240 241 priv->write_reg32(priv, reg, (cmd << 16) | obj); 242 243 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 244 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 245 return; 246 udelay(1); 247 } 248 netdev_err(dev, "Updating object timed out\n"); 249 } 250 251 static inline void c_can_object_get(struct net_device *dev, int iface, 252 u32 obj, u32 cmd) 253 { 254 c_can_obj_update(dev, iface, cmd, obj); 255 } 256 257 static inline void c_can_object_put(struct net_device *dev, int iface, 258 u32 obj, u32 cmd) 259 { 260 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 261 } 262 263 /* Note: According to documentation clearing TXIE while MSGVAL is set 264 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O 265 * load significantly. 266 */ 267 static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) 268 { 269 struct c_can_priv *priv = netdev_priv(dev); 270 271 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 272 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 273 } 274 275 static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 276 { 277 struct c_can_priv *priv = netdev_priv(dev); 278 279 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 280 c_can_inval_tx_object(dev, iface, obj); 281 } 282 283 static void c_can_setup_tx_object(struct net_device *dev, int iface, 284 struct can_frame *frame, int idx) 285 { 286 struct c_can_priv *priv = netdev_priv(dev); 287 u16 ctrl = IF_MCONT_TX | frame->len; 288 bool rtr = frame->can_id & CAN_RTR_FLAG; 289 u32 arb = IF_ARB_MSGVAL; 290 int i; 291 292 if (frame->can_id & CAN_EFF_FLAG) { 293 arb |= frame->can_id & CAN_EFF_MASK; 294 arb |= IF_ARB_MSGXTD; 295 } else { 296 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 297 } 298 299 if (!rtr) 300 arb |= IF_ARB_TRANSMIT; 301 302 /* If we change the DIR bit, we need to invalidate the buffer 303 * first, i.e. clear the MSGVAL flag in the arbiter. 304 */ 305 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { 306 u32 obj = idx + priv->msg_obj_tx_first; 307 308 c_can_inval_msg_object(dev, iface, obj); 309 change_bit(idx, &priv->tx_dir); 310 } 311 312 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 313 314 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 315 316 if (priv->type == BOSCH_D_CAN) { 317 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface); 318 319 for (i = 0; i < frame->len; i += 4, dreg += 2) { 320 data = (u32)frame->data[i]; 321 data |= (u32)frame->data[i + 1] << 8; 322 data |= (u32)frame->data[i + 2] << 16; 323 data |= (u32)frame->data[i + 3] << 24; 324 priv->write_reg32(priv, dreg, data); 325 } 326 } else { 327 for (i = 0; i < frame->len; i += 2) { 328 priv->write_reg(priv, 329 C_CAN_IFACE(DATA1_REG, iface) + i / 2, 330 frame->data[i] | 331 (frame->data[i + 1] << 8)); 332 } 333 } 334 } 335 336 static int c_can_handle_lost_msg_obj(struct net_device *dev, 337 int iface, int objno, u32 ctrl) 338 { 339 struct net_device_stats *stats = &dev->stats; 340 struct c_can_priv *priv = netdev_priv(dev); 341 struct can_frame *frame; 342 struct sk_buff *skb; 343 344 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 345 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 346 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 347 348 stats->rx_errors++; 349 stats->rx_over_errors++; 350 351 /* create an error msg */ 352 skb = alloc_can_err_skb(dev, &frame); 353 if (unlikely(!skb)) 354 return 0; 355 356 frame->can_id |= CAN_ERR_CRTL; 357 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 358 359 netif_receive_skb(skb); 360 return 1; 361 } 362 363 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 364 { 365 struct net_device_stats *stats = &dev->stats; 366 struct c_can_priv *priv = netdev_priv(dev); 367 struct can_frame *frame; 368 struct sk_buff *skb; 369 u32 arb, data; 370 371 skb = alloc_can_skb(dev, &frame); 372 if (!skb) { 373 stats->rx_dropped++; 374 return -ENOMEM; 375 } 376 377 frame->len = can_cc_dlc2len(ctrl & 0x0F); 378 379 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); 380 381 if (arb & IF_ARB_MSGXTD) 382 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 383 else 384 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 385 386 if (arb & IF_ARB_TRANSMIT) { 387 frame->can_id |= CAN_RTR_FLAG; 388 } else { 389 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 390 391 if (priv->type == BOSCH_D_CAN) { 392 for (i = 0; i < frame->len; i += 4, dreg += 2) { 393 data = priv->read_reg32(priv, dreg); 394 frame->data[i] = data; 395 frame->data[i + 1] = data >> 8; 396 frame->data[i + 2] = data >> 16; 397 frame->data[i + 3] = data >> 24; 398 } 399 } else { 400 for (i = 0; i < frame->len; i += 2, dreg++) { 401 data = priv->read_reg(priv, dreg); 402 frame->data[i] = data; 403 frame->data[i + 1] = data >> 8; 404 } 405 } 406 } 407 408 stats->rx_packets++; 409 stats->rx_bytes += frame->len; 410 411 netif_receive_skb(skb); 412 return 0; 413 } 414 415 static void c_can_setup_receive_object(struct net_device *dev, int iface, 416 u32 obj, u32 mask, u32 id, u32 mcont) 417 { 418 struct c_can_priv *priv = netdev_priv(dev); 419 420 mask |= BIT(29); 421 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 422 423 id |= IF_ARB_MSGVAL; 424 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); 425 426 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 427 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 428 } 429 430 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 431 struct net_device *dev) 432 { 433 struct can_frame *frame = (struct can_frame *)skb->data; 434 struct c_can_priv *priv = netdev_priv(dev); 435 u32 idx, obj; 436 437 if (can_dropped_invalid_skb(dev, skb)) 438 return NETDEV_TX_OK; 439 /* This is not a FIFO. C/D_CAN sends out the buffers 440 * prioritized. The lowest buffer number wins. 441 */ 442 idx = fls(atomic_read(&priv->tx_active)); 443 obj = idx + priv->msg_obj_tx_first; 444 445 /* If this is the last buffer, stop the xmit queue */ 446 if (idx == priv->msg_obj_tx_num - 1) 447 netif_stop_queue(dev); 448 /* Store the message in the interface so we can call 449 * can_put_echo_skb(). We must do this before we enable 450 * transmit as we might race against do_tx(). 451 */ 452 c_can_setup_tx_object(dev, IF_TX, frame, idx); 453 priv->dlc[idx] = frame->len; 454 can_put_echo_skb(skb, dev, idx, 0); 455 456 /* Update the active bits */ 457 atomic_add(BIT(idx), &priv->tx_active); 458 /* Start transmission */ 459 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); 460 461 return NETDEV_TX_OK; 462 } 463 464 static int c_can_wait_for_ctrl_init(struct net_device *dev, 465 struct c_can_priv *priv, u32 init) 466 { 467 int retry = 0; 468 469 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 470 udelay(10); 471 if (retry++ > 1000) { 472 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 473 return -EIO; 474 } 475 } 476 return 0; 477 } 478 479 static int c_can_set_bittiming(struct net_device *dev) 480 { 481 unsigned int reg_btr, reg_brpe, ctrl_save; 482 u8 brp, brpe, sjw, tseg1, tseg2; 483 u32 ten_bit_brp; 484 struct c_can_priv *priv = netdev_priv(dev); 485 const struct can_bittiming *bt = &priv->can.bittiming; 486 int res; 487 488 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 489 ten_bit_brp = bt->brp - 1; 490 brp = ten_bit_brp & BTR_BRP_MASK; 491 brpe = ten_bit_brp >> 6; 492 493 sjw = bt->sjw - 1; 494 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 495 tseg2 = bt->phase_seg2 - 1; 496 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 497 (tseg2 << BTR_TSEG2_SHIFT); 498 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 499 500 netdev_info(dev, 501 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 502 503 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 504 ctrl_save &= ~CONTROL_INIT; 505 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 506 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 507 if (res) 508 return res; 509 510 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 511 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 512 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 513 514 return c_can_wait_for_ctrl_init(dev, priv, 0); 515 } 516 517 /* Configure C_CAN message objects for Tx and Rx purposes: 518 * C_CAN provides a total of 32 message objects that can be configured 519 * either for Tx or Rx purposes. Here the first 16 message objects are used as 520 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 521 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 522 * See user guide document for further details on configuring message 523 * objects. 524 */ 525 static void c_can_configure_msg_objects(struct net_device *dev) 526 { 527 struct c_can_priv *priv = netdev_priv(dev); 528 int i; 529 530 /* first invalidate all message objects */ 531 for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++) 532 c_can_inval_msg_object(dev, IF_RX, i); 533 534 /* setup receive message objects */ 535 for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++) 536 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); 537 538 c_can_setup_receive_object(dev, IF_RX, priv->msg_obj_rx_last, 0, 0, 539 IF_MCONT_RCV_EOB); 540 } 541 542 static int c_can_software_reset(struct net_device *dev) 543 { 544 struct c_can_priv *priv = netdev_priv(dev); 545 int retry = 0; 546 547 if (priv->type != BOSCH_D_CAN) 548 return 0; 549 550 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT); 551 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) { 552 msleep(20); 553 if (retry++ > 100) { 554 netdev_err(dev, "CCTRL: software reset failed\n"); 555 return -EIO; 556 } 557 } 558 559 return 0; 560 } 561 562 /* Configure C_CAN chip: 563 * - enable/disable auto-retransmission 564 * - set operating mode 565 * - configure message objects 566 */ 567 static int c_can_chip_config(struct net_device *dev) 568 { 569 struct c_can_priv *priv = netdev_priv(dev); 570 int err; 571 572 err = c_can_software_reset(dev); 573 if (err) 574 return err; 575 576 /* enable automatic retransmission */ 577 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 578 579 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 580 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 581 /* loopback + silent mode : useful for hot self-test */ 582 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 583 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 584 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 585 /* loopback mode : useful for self-test function */ 586 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 587 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 588 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 589 /* silent mode : bus-monitoring mode */ 590 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 591 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 592 } 593 594 /* configure message objects */ 595 c_can_configure_msg_objects(dev); 596 597 /* set a `lec` value so that we can check for updates later */ 598 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 599 600 /* Clear all internal status */ 601 atomic_set(&priv->tx_active, 0); 602 priv->tx_dir = 0; 603 604 /* set bittiming params */ 605 return c_can_set_bittiming(dev); 606 } 607 608 static int c_can_start(struct net_device *dev) 609 { 610 struct c_can_priv *priv = netdev_priv(dev); 611 int err; 612 struct pinctrl *p; 613 614 /* basic c_can configuration */ 615 err = c_can_chip_config(dev); 616 if (err) 617 return err; 618 619 /* Setup the command for new messages */ 620 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 621 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 622 623 priv->can.state = CAN_STATE_ERROR_ACTIVE; 624 625 /* Attempt to use "active" if available else use "default" */ 626 p = pinctrl_get_select(priv->device, "active"); 627 if (!IS_ERR(p)) 628 pinctrl_put(p); 629 else 630 pinctrl_pm_select_default_state(priv->device); 631 632 return 0; 633 } 634 635 static void c_can_stop(struct net_device *dev) 636 { 637 struct c_can_priv *priv = netdev_priv(dev); 638 639 c_can_irq_control(priv, false); 640 641 /* put ctrl to init on stop to end ongoing transmission */ 642 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); 643 644 /* deactivate pins */ 645 pinctrl_pm_select_sleep_state(dev->dev.parent); 646 priv->can.state = CAN_STATE_STOPPED; 647 } 648 649 static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 650 { 651 struct c_can_priv *priv = netdev_priv(dev); 652 int err; 653 654 switch (mode) { 655 case CAN_MODE_START: 656 err = c_can_start(dev); 657 if (err) 658 return err; 659 netif_wake_queue(dev); 660 c_can_irq_control(priv, true); 661 break; 662 default: 663 return -EOPNOTSUPP; 664 } 665 666 return 0; 667 } 668 669 static int __c_can_get_berr_counter(const struct net_device *dev, 670 struct can_berr_counter *bec) 671 { 672 unsigned int reg_err_counter; 673 struct c_can_priv *priv = netdev_priv(dev); 674 675 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 676 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 677 ERR_CNT_REC_SHIFT; 678 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 679 680 return 0; 681 } 682 683 static int c_can_get_berr_counter(const struct net_device *dev, 684 struct can_berr_counter *bec) 685 { 686 struct c_can_priv *priv = netdev_priv(dev); 687 int err; 688 689 c_can_pm_runtime_get_sync(priv); 690 err = __c_can_get_berr_counter(dev, bec); 691 c_can_pm_runtime_put_sync(priv); 692 693 return err; 694 } 695 696 static void c_can_do_tx(struct net_device *dev) 697 { 698 struct c_can_priv *priv = netdev_priv(dev); 699 struct net_device_stats *stats = &dev->stats; 700 u32 idx, obj, pkts = 0, bytes = 0, pend, clr; 701 702 if (priv->msg_obj_tx_last > 32) 703 pend = priv->read_reg32(priv, C_CAN_INTPND3_REG); 704 else 705 pend = priv->read_reg(priv, C_CAN_INTPND2_REG); 706 clr = pend; 707 708 while ((idx = ffs(pend))) { 709 idx--; 710 pend &= ~BIT(idx); 711 obj = idx + priv->msg_obj_tx_first; 712 713 /* We use IF_RX interface instead of IF_TX because we 714 * are called from c_can_poll(), which runs inside 715 * NAPI. We are not trasmitting. 716 */ 717 c_can_inval_tx_object(dev, IF_RX, obj); 718 can_get_echo_skb(dev, idx, NULL); 719 bytes += priv->dlc[idx]; 720 pkts++; 721 } 722 723 /* Clear the bits in the tx_active mask */ 724 atomic_sub(clr, &priv->tx_active); 725 726 if (clr & BIT(priv->msg_obj_tx_num - 1)) 727 netif_wake_queue(dev); 728 729 if (pkts) { 730 stats->tx_bytes += bytes; 731 stats->tx_packets += pkts; 732 can_led_event(dev, CAN_LED_EVENT_TX); 733 } 734 } 735 736 /* If we have a gap in the pending bits, that means we either 737 * raced with the hardware or failed to readout all upper 738 * objects in the last run due to quota limit. 739 */ 740 static u32 c_can_adjust_pending(u32 pend, u32 rx_mask) 741 { 742 u32 weight, lasts; 743 744 if (pend == rx_mask) 745 return pend; 746 747 /* If the last set bit is larger than the number of pending 748 * bits we have a gap. 749 */ 750 weight = hweight32(pend); 751 lasts = fls(pend); 752 753 /* If the bits are linear, nothing to do */ 754 if (lasts == weight) 755 return pend; 756 757 /* Find the first set bit after the gap. We walk backwards 758 * from the last set bit. 759 */ 760 for (lasts--; pend & BIT(lasts - 1); lasts--) 761 ; 762 763 return pend & ~GENMASK(lasts - 1, 0); 764 } 765 766 static inline void c_can_rx_object_get(struct net_device *dev, 767 struct c_can_priv *priv, u32 obj) 768 { 769 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); 770 } 771 772 static inline void c_can_rx_finalize(struct net_device *dev, 773 struct c_can_priv *priv, u32 obj) 774 { 775 if (priv->type != BOSCH_D_CAN) 776 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); 777 } 778 779 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 780 u32 pend, int quota) 781 { 782 u32 pkts = 0, ctrl, obj; 783 784 while ((obj = ffs(pend)) && quota > 0) { 785 pend &= ~BIT(obj - 1); 786 787 c_can_rx_object_get(dev, priv, obj); 788 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 789 790 if (ctrl & IF_MCONT_MSGLST) { 791 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 792 793 pkts += n; 794 quota -= n; 795 continue; 796 } 797 798 /* This really should not happen, but this covers some 799 * odd HW behaviour. Do not remove that unless you 800 * want to brick your machine. 801 */ 802 if (!(ctrl & IF_MCONT_NEWDAT)) 803 continue; 804 805 /* read the data from the message object */ 806 c_can_read_msg_object(dev, IF_RX, ctrl); 807 808 c_can_rx_finalize(dev, priv, obj); 809 810 pkts++; 811 quota--; 812 } 813 814 return pkts; 815 } 816 817 static inline u32 c_can_get_pending(struct c_can_priv *priv) 818 { 819 u32 pend; 820 821 if (priv->msg_obj_rx_last > 16) 822 pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG); 823 else 824 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 825 826 return pend; 827 } 828 829 /* theory of operation: 830 * 831 * c_can core saves a received CAN message into the first free message 832 * object it finds free (starting with the lowest). Bits NEWDAT and 833 * INTPND are set for this message object indicating that a new message 834 * has arrived. 835 * 836 * We clear the newdat bit right away. 837 * 838 * This can result in packet reordering when the readout is slow. 839 */ 840 static int c_can_do_rx_poll(struct net_device *dev, int quota) 841 { 842 struct c_can_priv *priv = netdev_priv(dev); 843 u32 pkts = 0, pend = 0, toread, n; 844 845 while (quota > 0) { 846 if (!pend) { 847 pend = c_can_get_pending(priv); 848 if (!pend) 849 break; 850 /* If the pending field has a gap, handle the 851 * bits above the gap first. 852 */ 853 toread = c_can_adjust_pending(pend, 854 priv->msg_obj_rx_mask); 855 } else { 856 toread = pend; 857 } 858 /* Remove the bits from pend */ 859 pend &= ~toread; 860 /* Read the objects */ 861 n = c_can_read_objects(dev, priv, toread, quota); 862 pkts += n; 863 quota -= n; 864 } 865 866 if (pkts) 867 can_led_event(dev, CAN_LED_EVENT_RX); 868 869 return pkts; 870 } 871 872 static int c_can_handle_state_change(struct net_device *dev, 873 enum c_can_bus_error_types error_type) 874 { 875 unsigned int reg_err_counter; 876 unsigned int rx_err_passive; 877 struct c_can_priv *priv = netdev_priv(dev); 878 struct net_device_stats *stats = &dev->stats; 879 struct can_frame *cf; 880 struct sk_buff *skb; 881 struct can_berr_counter bec; 882 883 switch (error_type) { 884 case C_CAN_NO_ERROR: 885 priv->can.state = CAN_STATE_ERROR_ACTIVE; 886 break; 887 case C_CAN_ERROR_WARNING: 888 /* error warning state */ 889 priv->can.can_stats.error_warning++; 890 priv->can.state = CAN_STATE_ERROR_WARNING; 891 break; 892 case C_CAN_ERROR_PASSIVE: 893 /* error passive state */ 894 priv->can.can_stats.error_passive++; 895 priv->can.state = CAN_STATE_ERROR_PASSIVE; 896 break; 897 case C_CAN_BUS_OFF: 898 /* bus-off state */ 899 priv->can.state = CAN_STATE_BUS_OFF; 900 priv->can.can_stats.bus_off++; 901 break; 902 default: 903 break; 904 } 905 906 /* propagate the error condition to the CAN stack */ 907 skb = alloc_can_err_skb(dev, &cf); 908 if (unlikely(!skb)) 909 return 0; 910 911 __c_can_get_berr_counter(dev, &bec); 912 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 913 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 914 ERR_CNT_RP_SHIFT; 915 916 switch (error_type) { 917 case C_CAN_NO_ERROR: 918 /* error warning state */ 919 cf->can_id |= CAN_ERR_CRTL; 920 cf->data[1] = CAN_ERR_CRTL_ACTIVE; 921 cf->data[6] = bec.txerr; 922 cf->data[7] = bec.rxerr; 923 break; 924 case C_CAN_ERROR_WARNING: 925 /* error warning state */ 926 cf->can_id |= CAN_ERR_CRTL; 927 cf->data[1] = (bec.txerr > bec.rxerr) ? 928 CAN_ERR_CRTL_TX_WARNING : 929 CAN_ERR_CRTL_RX_WARNING; 930 cf->data[6] = bec.txerr; 931 cf->data[7] = bec.rxerr; 932 933 break; 934 case C_CAN_ERROR_PASSIVE: 935 /* error passive state */ 936 cf->can_id |= CAN_ERR_CRTL; 937 if (rx_err_passive) 938 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 939 if (bec.txerr > 127) 940 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 941 942 cf->data[6] = bec.txerr; 943 cf->data[7] = bec.rxerr; 944 break; 945 case C_CAN_BUS_OFF: 946 /* bus-off state */ 947 cf->can_id |= CAN_ERR_BUSOFF; 948 can_bus_off(dev); 949 break; 950 default: 951 break; 952 } 953 954 stats->rx_packets++; 955 stats->rx_bytes += cf->len; 956 netif_receive_skb(skb); 957 958 return 1; 959 } 960 961 static int c_can_handle_bus_err(struct net_device *dev, 962 enum c_can_lec_type lec_type) 963 { 964 struct c_can_priv *priv = netdev_priv(dev); 965 struct net_device_stats *stats = &dev->stats; 966 struct can_frame *cf; 967 struct sk_buff *skb; 968 969 /* early exit if no lec update or no error. 970 * no lec update means that no CAN bus event has been detected 971 * since CPU wrote 0x7 value to status reg. 972 */ 973 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 974 return 0; 975 976 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 977 return 0; 978 979 /* common for all type of bus errors */ 980 priv->can.can_stats.bus_error++; 981 stats->rx_errors++; 982 983 /* propagate the error condition to the CAN stack */ 984 skb = alloc_can_err_skb(dev, &cf); 985 if (unlikely(!skb)) 986 return 0; 987 988 /* check for 'last error code' which tells us the 989 * type of the last error to occur on the CAN bus 990 */ 991 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 992 993 switch (lec_type) { 994 case LEC_STUFF_ERROR: 995 netdev_dbg(dev, "stuff error\n"); 996 cf->data[2] |= CAN_ERR_PROT_STUFF; 997 break; 998 case LEC_FORM_ERROR: 999 netdev_dbg(dev, "form error\n"); 1000 cf->data[2] |= CAN_ERR_PROT_FORM; 1001 break; 1002 case LEC_ACK_ERROR: 1003 netdev_dbg(dev, "ack error\n"); 1004 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 1005 break; 1006 case LEC_BIT1_ERROR: 1007 netdev_dbg(dev, "bit1 error\n"); 1008 cf->data[2] |= CAN_ERR_PROT_BIT1; 1009 break; 1010 case LEC_BIT0_ERROR: 1011 netdev_dbg(dev, "bit0 error\n"); 1012 cf->data[2] |= CAN_ERR_PROT_BIT0; 1013 break; 1014 case LEC_CRC_ERROR: 1015 netdev_dbg(dev, "CRC error\n"); 1016 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 1017 break; 1018 default: 1019 break; 1020 } 1021 1022 stats->rx_packets++; 1023 stats->rx_bytes += cf->len; 1024 netif_receive_skb(skb); 1025 return 1; 1026 } 1027 1028 static int c_can_poll(struct napi_struct *napi, int quota) 1029 { 1030 struct net_device *dev = napi->dev; 1031 struct c_can_priv *priv = netdev_priv(dev); 1032 u16 curr, last = priv->last_status; 1033 int work_done = 0; 1034 1035 /* Only read the status register if a status interrupt was pending */ 1036 if (atomic_xchg(&priv->sie_pending, 0)) { 1037 priv->last_status = priv->read_reg(priv, C_CAN_STS_REG); 1038 curr = priv->last_status; 1039 /* Ack status on C_CAN. D_CAN is self clearing */ 1040 if (priv->type != BOSCH_D_CAN) 1041 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1042 } else { 1043 /* no change detected ... */ 1044 curr = last; 1045 } 1046 1047 /* handle state changes */ 1048 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1049 netdev_dbg(dev, "entered error warning state\n"); 1050 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1051 } 1052 1053 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1054 netdev_dbg(dev, "entered error passive state\n"); 1055 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1056 } 1057 1058 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1059 netdev_dbg(dev, "entered bus off state\n"); 1060 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1061 goto end; 1062 } 1063 1064 /* handle bus recovery events */ 1065 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1066 netdev_dbg(dev, "left bus off state\n"); 1067 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1068 } 1069 1070 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1071 netdev_dbg(dev, "left error passive state\n"); 1072 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1073 } 1074 1075 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) { 1076 netdev_dbg(dev, "left error warning state\n"); 1077 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR); 1078 } 1079 1080 /* handle lec errors on the bus */ 1081 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1082 1083 /* Handle Tx/Rx events. We do this unconditionally */ 1084 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1085 c_can_do_tx(dev); 1086 1087 end: 1088 if (work_done < quota) { 1089 napi_complete_done(napi, work_done); 1090 /* enable all IRQs if we are not in bus off state */ 1091 if (priv->can.state != CAN_STATE_BUS_OFF) 1092 c_can_irq_control(priv, true); 1093 } 1094 1095 return work_done; 1096 } 1097 1098 static irqreturn_t c_can_isr(int irq, void *dev_id) 1099 { 1100 struct net_device *dev = (struct net_device *)dev_id; 1101 struct c_can_priv *priv = netdev_priv(dev); 1102 int reg_int; 1103 1104 reg_int = priv->read_reg(priv, C_CAN_INT_REG); 1105 if (!reg_int) 1106 return IRQ_NONE; 1107 1108 /* save for later use */ 1109 if (reg_int & INT_STS_PENDING) 1110 atomic_set(&priv->sie_pending, 1); 1111 1112 /* disable all interrupts and schedule the NAPI */ 1113 c_can_irq_control(priv, false); 1114 napi_schedule(&priv->napi); 1115 1116 return IRQ_HANDLED; 1117 } 1118 1119 static int c_can_open(struct net_device *dev) 1120 { 1121 int err; 1122 struct c_can_priv *priv = netdev_priv(dev); 1123 1124 c_can_pm_runtime_get_sync(priv); 1125 c_can_reset_ram(priv, true); 1126 1127 /* open the can device */ 1128 err = open_candev(dev); 1129 if (err) { 1130 netdev_err(dev, "failed to open can device\n"); 1131 goto exit_open_fail; 1132 } 1133 1134 /* register interrupt handler */ 1135 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1136 dev); 1137 if (err < 0) { 1138 netdev_err(dev, "failed to request interrupt\n"); 1139 goto exit_irq_fail; 1140 } 1141 1142 /* start the c_can controller */ 1143 err = c_can_start(dev); 1144 if (err) 1145 goto exit_start_fail; 1146 1147 can_led_event(dev, CAN_LED_EVENT_OPEN); 1148 1149 napi_enable(&priv->napi); 1150 /* enable status change, error and module interrupts */ 1151 c_can_irq_control(priv, true); 1152 netif_start_queue(dev); 1153 1154 return 0; 1155 1156 exit_start_fail: 1157 free_irq(dev->irq, dev); 1158 exit_irq_fail: 1159 close_candev(dev); 1160 exit_open_fail: 1161 c_can_reset_ram(priv, false); 1162 c_can_pm_runtime_put_sync(priv); 1163 return err; 1164 } 1165 1166 static int c_can_close(struct net_device *dev) 1167 { 1168 struct c_can_priv *priv = netdev_priv(dev); 1169 1170 netif_stop_queue(dev); 1171 napi_disable(&priv->napi); 1172 c_can_stop(dev); 1173 free_irq(dev->irq, dev); 1174 close_candev(dev); 1175 1176 c_can_reset_ram(priv, false); 1177 c_can_pm_runtime_put_sync(priv); 1178 1179 can_led_event(dev, CAN_LED_EVENT_STOP); 1180 1181 return 0; 1182 } 1183 1184 struct net_device *alloc_c_can_dev(int msg_obj_num) 1185 { 1186 struct net_device *dev; 1187 struct c_can_priv *priv; 1188 int msg_obj_tx_num = msg_obj_num / 2; 1189 1190 dev = alloc_candev(struct_size(priv, dlc, msg_obj_tx_num), 1191 msg_obj_tx_num); 1192 if (!dev) 1193 return NULL; 1194 1195 priv = netdev_priv(dev); 1196 priv->msg_obj_num = msg_obj_num; 1197 priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num; 1198 priv->msg_obj_rx_first = 1; 1199 priv->msg_obj_rx_last = 1200 priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1; 1201 priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0); 1202 1203 priv->msg_obj_tx_num = msg_obj_tx_num; 1204 priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1; 1205 priv->msg_obj_tx_last = 1206 priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1; 1207 1208 netif_napi_add(dev, &priv->napi, c_can_poll, priv->msg_obj_rx_num); 1209 1210 priv->dev = dev; 1211 priv->can.bittiming_const = &c_can_bittiming_const; 1212 priv->can.do_set_mode = c_can_set_mode; 1213 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1214 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1215 CAN_CTRLMODE_LISTENONLY | 1216 CAN_CTRLMODE_BERR_REPORTING; 1217 1218 return dev; 1219 } 1220 EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1221 1222 #ifdef CONFIG_PM 1223 int c_can_power_down(struct net_device *dev) 1224 { 1225 u32 val; 1226 unsigned long time_out; 1227 struct c_can_priv *priv = netdev_priv(dev); 1228 1229 if (!(dev->flags & IFF_UP)) 1230 return 0; 1231 1232 WARN_ON(priv->type != BOSCH_D_CAN); 1233 1234 /* set PDR value so the device goes to power down mode */ 1235 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1236 val |= CONTROL_EX_PDR; 1237 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1238 1239 /* Wait for the PDA bit to get set */ 1240 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1241 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1242 time_after(time_out, jiffies)) 1243 cpu_relax(); 1244 1245 if (time_after(jiffies, time_out)) 1246 return -ETIMEDOUT; 1247 1248 c_can_stop(dev); 1249 1250 c_can_reset_ram(priv, false); 1251 c_can_pm_runtime_put_sync(priv); 1252 1253 return 0; 1254 } 1255 EXPORT_SYMBOL_GPL(c_can_power_down); 1256 1257 int c_can_power_up(struct net_device *dev) 1258 { 1259 u32 val; 1260 unsigned long time_out; 1261 struct c_can_priv *priv = netdev_priv(dev); 1262 int ret; 1263 1264 if (!(dev->flags & IFF_UP)) 1265 return 0; 1266 1267 WARN_ON(priv->type != BOSCH_D_CAN); 1268 1269 c_can_pm_runtime_get_sync(priv); 1270 c_can_reset_ram(priv, true); 1271 1272 /* Clear PDR and INIT bits */ 1273 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1274 val &= ~CONTROL_EX_PDR; 1275 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1276 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1277 val &= ~CONTROL_INIT; 1278 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1279 1280 /* Wait for the PDA bit to get clear */ 1281 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1282 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1283 time_after(time_out, jiffies)) 1284 cpu_relax(); 1285 1286 if (time_after(jiffies, time_out)) { 1287 ret = -ETIMEDOUT; 1288 goto err_out; 1289 } 1290 1291 ret = c_can_start(dev); 1292 if (ret) 1293 goto err_out; 1294 1295 c_can_irq_control(priv, true); 1296 1297 return 0; 1298 1299 err_out: 1300 c_can_reset_ram(priv, false); 1301 c_can_pm_runtime_put_sync(priv); 1302 1303 return ret; 1304 } 1305 EXPORT_SYMBOL_GPL(c_can_power_up); 1306 #endif 1307 1308 void free_c_can_dev(struct net_device *dev) 1309 { 1310 struct c_can_priv *priv = netdev_priv(dev); 1311 1312 netif_napi_del(&priv->napi); 1313 free_candev(dev); 1314 } 1315 EXPORT_SYMBOL_GPL(free_c_can_dev); 1316 1317 static const struct net_device_ops c_can_netdev_ops = { 1318 .ndo_open = c_can_open, 1319 .ndo_stop = c_can_close, 1320 .ndo_start_xmit = c_can_start_xmit, 1321 .ndo_change_mtu = can_change_mtu, 1322 }; 1323 1324 int register_c_can_dev(struct net_device *dev) 1325 { 1326 int err; 1327 1328 /* Deactivate pins to prevent DRA7 DCAN IP from being 1329 * stuck in transition when module is disabled. 1330 * Pins are activated in c_can_start() and deactivated 1331 * in c_can_stop() 1332 */ 1333 pinctrl_pm_select_sleep_state(dev->dev.parent); 1334 1335 dev->flags |= IFF_ECHO; /* we support local echo */ 1336 dev->netdev_ops = &c_can_netdev_ops; 1337 c_can_set_ethtool_ops(dev); 1338 1339 err = register_candev(dev); 1340 if (!err) 1341 devm_can_led_init(dev); 1342 return err; 1343 } 1344 EXPORT_SYMBOL_GPL(register_c_can_dev); 1345 1346 void unregister_c_can_dev(struct net_device *dev) 1347 { 1348 unregister_candev(dev); 1349 } 1350 EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1351 1352 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1353 MODULE_LICENSE("GPL v2"); 1354 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1355