1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * at91_can.c - CAN network driver for AT91 SoC CAN controller 4 * 5 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 6 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/errno.h> 11 #include <linux/if_arp.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/rtnetlink.h> 19 #include <linux/skbuff.h> 20 #include <linux/spinlock.h> 21 #include <linux/string.h> 22 #include <linux/types.h> 23 24 #include <linux/can/dev.h> 25 #include <linux/can/error.h> 26 #include <linux/can/led.h> 27 28 #define AT91_MB_MASK(i) ((1 << (i)) - 1) 29 30 /* Common registers */ 31 enum at91_reg { 32 AT91_MR = 0x000, 33 AT91_IER = 0x004, 34 AT91_IDR = 0x008, 35 AT91_IMR = 0x00C, 36 AT91_SR = 0x010, 37 AT91_BR = 0x014, 38 AT91_TIM = 0x018, 39 AT91_TIMESTP = 0x01C, 40 AT91_ECR = 0x020, 41 AT91_TCR = 0x024, 42 AT91_ACR = 0x028, 43 }; 44 45 /* Mailbox registers (0 <= i <= 15) */ 46 #define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20))) 47 #define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20))) 48 #define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20))) 49 #define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20))) 50 #define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20))) 51 #define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20))) 52 #define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20))) 53 #define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20))) 54 55 /* Register bits */ 56 #define AT91_MR_CANEN BIT(0) 57 #define AT91_MR_LPM BIT(1) 58 #define AT91_MR_ABM BIT(2) 59 #define AT91_MR_OVL BIT(3) 60 #define AT91_MR_TEOF BIT(4) 61 #define AT91_MR_TTM BIT(5) 62 #define AT91_MR_TIMFRZ BIT(6) 63 #define AT91_MR_DRPT BIT(7) 64 65 #define AT91_SR_RBSY BIT(29) 66 67 #define AT91_MMR_PRIO_SHIFT (16) 68 69 #define AT91_MID_MIDE BIT(29) 70 71 #define AT91_MSR_MRTR BIT(20) 72 #define AT91_MSR_MABT BIT(22) 73 #define AT91_MSR_MRDY BIT(23) 74 #define AT91_MSR_MMI BIT(24) 75 76 #define AT91_MCR_MRTR BIT(20) 77 #define AT91_MCR_MTCR BIT(23) 78 79 /* Mailbox Modes */ 80 enum at91_mb_mode { 81 AT91_MB_MODE_DISABLED = 0, 82 AT91_MB_MODE_RX = 1, 83 AT91_MB_MODE_RX_OVRWR = 2, 84 AT91_MB_MODE_TX = 3, 85 AT91_MB_MODE_CONSUMER = 4, 86 AT91_MB_MODE_PRODUCER = 5, 87 }; 88 89 /* Interrupt mask bits */ 90 #define AT91_IRQ_ERRA BIT(16) 91 #define AT91_IRQ_WARN BIT(17) 92 #define AT91_IRQ_ERRP BIT(18) 93 #define AT91_IRQ_BOFF BIT(19) 94 #define AT91_IRQ_SLEEP BIT(20) 95 #define AT91_IRQ_WAKEUP BIT(21) 96 #define AT91_IRQ_TOVF BIT(22) 97 #define AT91_IRQ_TSTP BIT(23) 98 #define AT91_IRQ_CERR BIT(24) 99 #define AT91_IRQ_SERR BIT(25) 100 #define AT91_IRQ_AERR BIT(26) 101 #define AT91_IRQ_FERR BIT(27) 102 #define AT91_IRQ_BERR BIT(28) 103 104 #define AT91_IRQ_ERR_ALL (0x1fff0000) 105 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 106 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 107 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 108 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 109 110 #define AT91_IRQ_ALL (0x1fffffff) 111 112 enum at91_devtype { 113 AT91_DEVTYPE_SAM9263, 114 AT91_DEVTYPE_SAM9X5, 115 }; 116 117 struct at91_devtype_data { 118 unsigned int rx_first; 119 unsigned int rx_split; 120 unsigned int rx_last; 121 unsigned int tx_shift; 122 enum at91_devtype type; 123 }; 124 125 struct at91_priv { 126 struct can_priv can; /* must be the first member! */ 127 struct napi_struct napi; 128 129 void __iomem *reg_base; 130 131 u32 reg_sr; 132 unsigned int tx_next; 133 unsigned int tx_echo; 134 unsigned int rx_next; 135 struct at91_devtype_data devtype_data; 136 137 struct clk *clk; 138 struct at91_can_data *pdata; 139 140 canid_t mb0_id; 141 }; 142 143 static const struct at91_devtype_data at91_at91sam9263_data = { 144 .rx_first = 1, 145 .rx_split = 8, 146 .rx_last = 11, 147 .tx_shift = 2, 148 .type = AT91_DEVTYPE_SAM9263, 149 }; 150 151 static const struct at91_devtype_data at91_at91sam9x5_data = { 152 .rx_first = 0, 153 .rx_split = 4, 154 .rx_last = 5, 155 .tx_shift = 1, 156 .type = AT91_DEVTYPE_SAM9X5, 157 }; 158 159 static const struct can_bittiming_const at91_bittiming_const = { 160 .name = KBUILD_MODNAME, 161 .tseg1_min = 4, 162 .tseg1_max = 16, 163 .tseg2_min = 2, 164 .tseg2_max = 8, 165 .sjw_max = 4, 166 .brp_min = 2, 167 .brp_max = 128, 168 .brp_inc = 1, 169 }; 170 171 #define AT91_IS(_model) \ 172 static inline int __maybe_unused at91_is_sam##_model(const struct at91_priv *priv) \ 173 { \ 174 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ 175 } 176 177 AT91_IS(9263); 178 AT91_IS(9X5); 179 180 static inline unsigned int get_mb_rx_first(const struct at91_priv *priv) 181 { 182 return priv->devtype_data.rx_first; 183 } 184 185 static inline unsigned int get_mb_rx_last(const struct at91_priv *priv) 186 { 187 return priv->devtype_data.rx_last; 188 } 189 190 static inline unsigned int get_mb_rx_split(const struct at91_priv *priv) 191 { 192 return priv->devtype_data.rx_split; 193 } 194 195 static inline unsigned int get_mb_rx_num(const struct at91_priv *priv) 196 { 197 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1; 198 } 199 200 static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 201 { 202 return get_mb_rx_split(priv) - 1; 203 } 204 205 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 206 { 207 return AT91_MB_MASK(get_mb_rx_split(priv)) & 208 ~AT91_MB_MASK(get_mb_rx_first(priv)); 209 } 210 211 static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv) 212 { 213 return priv->devtype_data.tx_shift; 214 } 215 216 static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 217 { 218 return 1 << get_mb_tx_shift(priv); 219 } 220 221 static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 222 { 223 return get_mb_rx_last(priv) + 1; 224 } 225 226 static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 227 { 228 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 229 } 230 231 static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 232 { 233 return get_mb_tx_shift(priv); 234 } 235 236 static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 237 { 238 return 0xf << get_mb_tx_shift(priv); 239 } 240 241 static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 242 { 243 return AT91_MB_MASK(get_mb_tx_shift(priv)); 244 } 245 246 static inline unsigned int get_next_mask(const struct at91_priv *priv) 247 { 248 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 249 } 250 251 static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 252 { 253 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) & 254 ~AT91_MB_MASK(get_mb_rx_first(priv)); 255 } 256 257 static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 258 { 259 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 260 ~AT91_MB_MASK(get_mb_tx_first(priv)); 261 } 262 263 static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 264 { 265 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 266 } 267 268 static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 269 { 270 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 271 } 272 273 static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 274 { 275 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 276 } 277 278 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 279 { 280 return readl_relaxed(priv->reg_base + reg); 281 } 282 283 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 284 u32 value) 285 { 286 writel_relaxed(value, priv->reg_base + reg); 287 } 288 289 static inline void set_mb_mode_prio(const struct at91_priv *priv, 290 unsigned int mb, enum at91_mb_mode mode, 291 int prio) 292 { 293 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 294 } 295 296 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 297 enum at91_mb_mode mode) 298 { 299 set_mb_mode_prio(priv, mb, mode, 0); 300 } 301 302 static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 303 { 304 u32 reg_mid; 305 306 if (can_id & CAN_EFF_FLAG) 307 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 308 else 309 reg_mid = (can_id & CAN_SFF_MASK) << 18; 310 311 return reg_mid; 312 } 313 314 static void at91_setup_mailboxes(struct net_device *dev) 315 { 316 struct at91_priv *priv = netdev_priv(dev); 317 unsigned int i; 318 u32 reg_mid; 319 320 /* Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 321 * mailbox is disabled. The next 11 mailboxes are used as a 322 * reception FIFO. The last mailbox is configured with 323 * overwrite option. The overwrite flag indicates a FIFO 324 * overflow. 325 */ 326 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 327 for (i = 0; i < get_mb_rx_first(priv); i++) { 328 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 329 at91_write(priv, AT91_MID(i), reg_mid); 330 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 331 } 332 333 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++) 334 set_mb_mode(priv, i, AT91_MB_MODE_RX); 335 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR); 336 337 /* reset acceptance mask and id register */ 338 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) { 339 at91_write(priv, AT91_MAM(i), 0x0); 340 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 341 } 342 343 /* The last 4 mailboxes are used for transmitting. */ 344 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 345 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 346 347 /* Reset tx and rx helper pointers */ 348 priv->tx_next = priv->tx_echo = 0; 349 priv->rx_next = get_mb_rx_first(priv); 350 } 351 352 static int at91_set_bittiming(struct net_device *dev) 353 { 354 const struct at91_priv *priv = netdev_priv(dev); 355 const struct can_bittiming *bt = &priv->can.bittiming; 356 u32 reg_br; 357 358 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 359 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 360 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 361 ((bt->phase_seg2 - 1) << 0); 362 363 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 364 365 at91_write(priv, AT91_BR, reg_br); 366 367 return 0; 368 } 369 370 static int at91_get_berr_counter(const struct net_device *dev, 371 struct can_berr_counter *bec) 372 { 373 const struct at91_priv *priv = netdev_priv(dev); 374 u32 reg_ecr = at91_read(priv, AT91_ECR); 375 376 bec->rxerr = reg_ecr & 0xff; 377 bec->txerr = reg_ecr >> 16; 378 379 return 0; 380 } 381 382 static void at91_chip_start(struct net_device *dev) 383 { 384 struct at91_priv *priv = netdev_priv(dev); 385 u32 reg_mr, reg_ier; 386 387 /* disable interrupts */ 388 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 389 390 /* disable chip */ 391 reg_mr = at91_read(priv, AT91_MR); 392 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 393 394 at91_set_bittiming(dev); 395 at91_setup_mailboxes(dev); 396 397 /* enable chip */ 398 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 399 reg_mr = AT91_MR_CANEN | AT91_MR_ABM; 400 else 401 reg_mr = AT91_MR_CANEN; 402 at91_write(priv, AT91_MR, reg_mr); 403 404 priv->can.state = CAN_STATE_ERROR_ACTIVE; 405 406 /* Enable interrupts */ 407 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 408 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 409 at91_write(priv, AT91_IER, reg_ier); 410 } 411 412 static void at91_chip_stop(struct net_device *dev, enum can_state state) 413 { 414 struct at91_priv *priv = netdev_priv(dev); 415 u32 reg_mr; 416 417 /* disable interrupts */ 418 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 419 420 reg_mr = at91_read(priv, AT91_MR); 421 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 422 423 priv->can.state = state; 424 } 425 426 /* theory of operation: 427 * 428 * According to the datasheet priority 0 is the highest priority, 15 429 * is the lowest. If two mailboxes have the same priority level the 430 * message of the mailbox with the lowest number is sent first. 431 * 432 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 433 * the next mailbox with prio 0, and so on, until all mailboxes are 434 * used. Then we start from the beginning with mailbox 435 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 436 * prio 1. When we reach the last mailbox with prio 15, we have to 437 * stop sending, waiting for all messages to be delivered, then start 438 * again with mailbox AT91_MB_TX_FIRST prio 0. 439 * 440 * We use the priv->tx_next as counter for the next transmission 441 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 442 * encode the mailbox number, the upper 4 bits the mailbox priority: 443 * 444 * priv->tx_next = (prio << get_next_prio_shift(priv)) | 445 * (mb - get_mb_tx_first(priv)); 446 * 447 */ 448 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 449 { 450 struct at91_priv *priv = netdev_priv(dev); 451 struct net_device_stats *stats = &dev->stats; 452 struct can_frame *cf = (struct can_frame *)skb->data; 453 unsigned int mb, prio; 454 u32 reg_mid, reg_mcr; 455 456 if (can_dropped_invalid_skb(dev, skb)) 457 return NETDEV_TX_OK; 458 459 mb = get_tx_next_mb(priv); 460 prio = get_tx_next_prio(priv); 461 462 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 463 netif_stop_queue(dev); 464 465 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 466 return NETDEV_TX_BUSY; 467 } 468 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 469 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 470 (cf->len << 16) | AT91_MCR_MTCR; 471 472 /* disable MB while writing ID (see datasheet) */ 473 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 474 at91_write(priv, AT91_MID(mb), reg_mid); 475 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 476 477 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 478 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 479 480 /* This triggers transmission */ 481 at91_write(priv, AT91_MCR(mb), reg_mcr); 482 483 stats->tx_bytes += cf->len; 484 485 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 486 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv), 0); 487 488 /* we have to stop the queue and deliver all messages in case 489 * of a prio+mb counter wrap around. This is the case if 490 * tx_next buffer prio and mailbox equals 0. 491 * 492 * also stop the queue if next buffer is still in use 493 * (== not ready) 494 */ 495 priv->tx_next++; 496 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 497 AT91_MSR_MRDY) || 498 (priv->tx_next & get_next_mask(priv)) == 0) 499 netif_stop_queue(dev); 500 501 /* Enable interrupt for this mailbox */ 502 at91_write(priv, AT91_IER, 1 << mb); 503 504 return NETDEV_TX_OK; 505 } 506 507 /** 508 * at91_activate_rx_low - activate lower rx mailboxes 509 * @priv: a91 context 510 * 511 * Reenables the lower mailboxes for reception of new CAN messages 512 */ 513 static inline void at91_activate_rx_low(const struct at91_priv *priv) 514 { 515 u32 mask = get_mb_rx_low_mask(priv); 516 517 at91_write(priv, AT91_TCR, mask); 518 } 519 520 /** 521 * at91_activate_rx_mb - reactive single rx mailbox 522 * @priv: a91 context 523 * @mb: mailbox to reactivate 524 * 525 * Reenables given mailbox for reception of new CAN messages 526 */ 527 static inline void at91_activate_rx_mb(const struct at91_priv *priv, 528 unsigned int mb) 529 { 530 u32 mask = 1 << mb; 531 532 at91_write(priv, AT91_TCR, mask); 533 } 534 535 /** 536 * at91_rx_overflow_err - send error frame due to rx overflow 537 * @dev: net device 538 */ 539 static void at91_rx_overflow_err(struct net_device *dev) 540 { 541 struct net_device_stats *stats = &dev->stats; 542 struct sk_buff *skb; 543 struct can_frame *cf; 544 545 netdev_dbg(dev, "RX buffer overflow\n"); 546 stats->rx_over_errors++; 547 stats->rx_errors++; 548 549 skb = alloc_can_err_skb(dev, &cf); 550 if (unlikely(!skb)) 551 return; 552 553 cf->can_id |= CAN_ERR_CRTL; 554 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 555 556 stats->rx_packets++; 557 stats->rx_bytes += cf->len; 558 netif_receive_skb(skb); 559 } 560 561 /** 562 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 563 * @dev: net device 564 * @mb: mailbox number to read from 565 * @cf: can frame where to store message 566 * 567 * Reads a CAN message from the given mailbox and stores data into 568 * given can frame. "mb" and "cf" must be valid. 569 */ 570 static void at91_read_mb(struct net_device *dev, unsigned int mb, 571 struct can_frame *cf) 572 { 573 const struct at91_priv *priv = netdev_priv(dev); 574 u32 reg_msr, reg_mid; 575 576 reg_mid = at91_read(priv, AT91_MID(mb)); 577 if (reg_mid & AT91_MID_MIDE) 578 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 579 else 580 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 581 582 reg_msr = at91_read(priv, AT91_MSR(mb)); 583 cf->len = can_cc_dlc2len((reg_msr >> 16) & 0xf); 584 585 if (reg_msr & AT91_MSR_MRTR) { 586 cf->can_id |= CAN_RTR_FLAG; 587 } else { 588 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 589 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 590 } 591 592 /* allow RX of extended frames */ 593 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 594 595 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI)) 596 at91_rx_overflow_err(dev); 597 } 598 599 /** 600 * at91_read_msg - read CAN message from mailbox 601 * @dev: net device 602 * @mb: mail box to read from 603 * 604 * Reads a CAN message from given mailbox, and put into linux network 605 * RX queue, does all housekeeping chores (stats, ...) 606 */ 607 static void at91_read_msg(struct net_device *dev, unsigned int mb) 608 { 609 struct net_device_stats *stats = &dev->stats; 610 struct can_frame *cf; 611 struct sk_buff *skb; 612 613 skb = alloc_can_skb(dev, &cf); 614 if (unlikely(!skb)) { 615 stats->rx_dropped++; 616 return; 617 } 618 619 at91_read_mb(dev, mb, cf); 620 621 stats->rx_packets++; 622 stats->rx_bytes += cf->len; 623 netif_receive_skb(skb); 624 625 can_led_event(dev, CAN_LED_EVENT_RX); 626 } 627 628 /** 629 * at91_poll_rx - read multiple CAN messages from mailboxes 630 * @dev: net device 631 * @quota: max number of pkgs we're allowed to receive 632 * 633 * Theory of Operation: 634 * 635 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last()) 636 * on the chip are reserved for RX. We split them into 2 groups. The 637 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last(). 638 * 639 * Like it or not, but the chip always saves a received CAN message 640 * into the first free mailbox it finds (starting with the 641 * lowest). This makes it very difficult to read the messages in the 642 * right order from the chip. This is how we work around that problem: 643 * 644 * The first message goes into mb nr. 1 and issues an interrupt. All 645 * rx ints are disabled in the interrupt handler and a napi poll is 646 * scheduled. We read the mailbox, but do _not_ re-enable the mb (to 647 * receive another message). 648 * 649 * lower mbxs upper 650 * ____^______ __^__ 651 * / \ / \ 652 * +-+-+-+-+-+-+-+-++-+-+-+-+ 653 * | |x|x|x|x|x|x|x|| | | | | 654 * +-+-+-+-+-+-+-+-++-+-+-+-+ 655 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 656 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 657 * ^ 658 * | 659 * \ 660 * unused, due to chip bug 661 * 662 * The variable priv->rx_next points to the next mailbox to read a 663 * message from. As long we're in the lower mailboxes we just read the 664 * mailbox but not re-enable it. 665 * 666 * With completion of the last of the lower mailboxes, we re-enable the 667 * whole first group, but continue to look for filled mailboxes in the 668 * upper mailboxes. Imagine the second group like overflow mailboxes, 669 * which takes CAN messages if the lower goup is full. While in the 670 * upper group we re-enable the mailbox right after reading it. Giving 671 * the chip more room to store messages. 672 * 673 * After finishing we look again in the lower group if we've still 674 * quota. 675 * 676 */ 677 static int at91_poll_rx(struct net_device *dev, int quota) 678 { 679 struct at91_priv *priv = netdev_priv(dev); 680 u32 reg_sr = at91_read(priv, AT91_SR); 681 const unsigned long *addr = (unsigned long *)®_sr; 682 unsigned int mb; 683 int received = 0; 684 685 if (priv->rx_next > get_mb_rx_low_last(priv) && 686 reg_sr & get_mb_rx_low_mask(priv)) 687 netdev_info(dev, 688 "order of incoming frames cannot be guaranteed\n"); 689 690 again: 691 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 692 mb < get_mb_tx_first(priv) && quota > 0; 693 reg_sr = at91_read(priv, AT91_SR), 694 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 695 at91_read_msg(dev, mb); 696 697 /* reactivate mailboxes */ 698 if (mb == get_mb_rx_low_last(priv)) 699 /* all lower mailboxed, if just finished it */ 700 at91_activate_rx_low(priv); 701 else if (mb > get_mb_rx_low_last(priv)) 702 /* only the mailbox we read */ 703 at91_activate_rx_mb(priv, mb); 704 705 received++; 706 quota--; 707 } 708 709 /* upper group completed, look again in lower */ 710 if (priv->rx_next > get_mb_rx_low_last(priv) && 711 mb > get_mb_rx_last(priv)) { 712 priv->rx_next = get_mb_rx_first(priv); 713 if (quota > 0) 714 goto again; 715 } 716 717 return received; 718 } 719 720 static void at91_poll_err_frame(struct net_device *dev, 721 struct can_frame *cf, u32 reg_sr) 722 { 723 struct at91_priv *priv = netdev_priv(dev); 724 725 /* CRC error */ 726 if (reg_sr & AT91_IRQ_CERR) { 727 netdev_dbg(dev, "CERR irq\n"); 728 dev->stats.rx_errors++; 729 priv->can.can_stats.bus_error++; 730 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 731 } 732 733 /* Stuffing Error */ 734 if (reg_sr & AT91_IRQ_SERR) { 735 netdev_dbg(dev, "SERR irq\n"); 736 dev->stats.rx_errors++; 737 priv->can.can_stats.bus_error++; 738 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 739 cf->data[2] |= CAN_ERR_PROT_STUFF; 740 } 741 742 /* Acknowledgement Error */ 743 if (reg_sr & AT91_IRQ_AERR) { 744 netdev_dbg(dev, "AERR irq\n"); 745 dev->stats.tx_errors++; 746 cf->can_id |= CAN_ERR_ACK; 747 } 748 749 /* Form error */ 750 if (reg_sr & AT91_IRQ_FERR) { 751 netdev_dbg(dev, "FERR irq\n"); 752 dev->stats.rx_errors++; 753 priv->can.can_stats.bus_error++; 754 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 755 cf->data[2] |= CAN_ERR_PROT_FORM; 756 } 757 758 /* Bit Error */ 759 if (reg_sr & AT91_IRQ_BERR) { 760 netdev_dbg(dev, "BERR irq\n"); 761 dev->stats.tx_errors++; 762 priv->can.can_stats.bus_error++; 763 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 764 cf->data[2] |= CAN_ERR_PROT_BIT; 765 } 766 } 767 768 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 769 { 770 struct sk_buff *skb; 771 struct can_frame *cf; 772 773 if (quota == 0) 774 return 0; 775 776 skb = alloc_can_err_skb(dev, &cf); 777 if (unlikely(!skb)) 778 return 0; 779 780 at91_poll_err_frame(dev, cf, reg_sr); 781 782 dev->stats.rx_packets++; 783 dev->stats.rx_bytes += cf->len; 784 netif_receive_skb(skb); 785 786 return 1; 787 } 788 789 static int at91_poll(struct napi_struct *napi, int quota) 790 { 791 struct net_device *dev = napi->dev; 792 const struct at91_priv *priv = netdev_priv(dev); 793 u32 reg_sr = at91_read(priv, AT91_SR); 794 int work_done = 0; 795 796 if (reg_sr & get_irq_mb_rx(priv)) 797 work_done += at91_poll_rx(dev, quota - work_done); 798 799 /* The error bits are clear on read, 800 * so use saved value from irq handler. 801 */ 802 reg_sr |= priv->reg_sr; 803 if (reg_sr & AT91_IRQ_ERR_FRAME) 804 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 805 806 if (work_done < quota) { 807 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 808 u32 reg_ier = AT91_IRQ_ERR_FRAME; 809 810 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 811 812 napi_complete_done(napi, work_done); 813 at91_write(priv, AT91_IER, reg_ier); 814 } 815 816 return work_done; 817 } 818 819 /* theory of operation: 820 * 821 * priv->tx_echo holds the number of the oldest can_frame put for 822 * transmission into the hardware, but not yet ACKed by the CAN tx 823 * complete IRQ. 824 * 825 * We iterate from priv->tx_echo to priv->tx_next and check if the 826 * packet has been transmitted, echo it back to the CAN framework. If 827 * we discover a not yet transmitted package, stop looking for more. 828 * 829 */ 830 static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 831 { 832 struct at91_priv *priv = netdev_priv(dev); 833 u32 reg_msr; 834 unsigned int mb; 835 836 /* masking of reg_sr not needed, already done by at91_irq */ 837 838 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 839 mb = get_tx_echo_mb(priv); 840 841 /* no event in mailbox? */ 842 if (!(reg_sr & (1 << mb))) 843 break; 844 845 /* Disable irq for this TX mailbox */ 846 at91_write(priv, AT91_IDR, 1 << mb); 847 848 /* only echo if mailbox signals us a transfer 849 * complete (MSR_MRDY). Otherwise it's a tansfer 850 * abort. "can_bus_off()" takes care about the skbs 851 * parked in the echo queue. 852 */ 853 reg_msr = at91_read(priv, AT91_MSR(mb)); 854 if (likely(reg_msr & AT91_MSR_MRDY && 855 ~reg_msr & AT91_MSR_MABT)) { 856 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 857 can_get_echo_skb(dev, mb - get_mb_tx_first(priv), NULL); 858 dev->stats.tx_packets++; 859 can_led_event(dev, CAN_LED_EVENT_TX); 860 } 861 } 862 863 /* restart queue if we don't have a wrap around but restart if 864 * we get a TX int for the last can frame directly before a 865 * wrap around. 866 */ 867 if ((priv->tx_next & get_next_mask(priv)) != 0 || 868 (priv->tx_echo & get_next_mask(priv)) == 0) 869 netif_wake_queue(dev); 870 } 871 872 static void at91_irq_err_state(struct net_device *dev, 873 struct can_frame *cf, enum can_state new_state) 874 { 875 struct at91_priv *priv = netdev_priv(dev); 876 u32 reg_idr = 0, reg_ier = 0; 877 struct can_berr_counter bec; 878 879 at91_get_berr_counter(dev, &bec); 880 881 switch (priv->can.state) { 882 case CAN_STATE_ERROR_ACTIVE: 883 /* from: ERROR_ACTIVE 884 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 885 * => : there was a warning int 886 */ 887 if (new_state >= CAN_STATE_ERROR_WARNING && 888 new_state <= CAN_STATE_BUS_OFF) { 889 netdev_dbg(dev, "Error Warning IRQ\n"); 890 priv->can.can_stats.error_warning++; 891 892 cf->can_id |= CAN_ERR_CRTL; 893 cf->data[1] = (bec.txerr > bec.rxerr) ? 894 CAN_ERR_CRTL_TX_WARNING : 895 CAN_ERR_CRTL_RX_WARNING; 896 } 897 fallthrough; 898 case CAN_STATE_ERROR_WARNING: 899 /* from: ERROR_ACTIVE, ERROR_WARNING 900 * to : ERROR_PASSIVE, BUS_OFF 901 * => : error passive int 902 */ 903 if (new_state >= CAN_STATE_ERROR_PASSIVE && 904 new_state <= CAN_STATE_BUS_OFF) { 905 netdev_dbg(dev, "Error Passive IRQ\n"); 906 priv->can.can_stats.error_passive++; 907 908 cf->can_id |= CAN_ERR_CRTL; 909 cf->data[1] = (bec.txerr > bec.rxerr) ? 910 CAN_ERR_CRTL_TX_PASSIVE : 911 CAN_ERR_CRTL_RX_PASSIVE; 912 } 913 break; 914 case CAN_STATE_BUS_OFF: 915 /* from: BUS_OFF 916 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 917 */ 918 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 919 cf->can_id |= CAN_ERR_RESTARTED; 920 921 netdev_dbg(dev, "restarted\n"); 922 priv->can.can_stats.restarts++; 923 924 netif_carrier_on(dev); 925 netif_wake_queue(dev); 926 } 927 break; 928 default: 929 break; 930 } 931 932 /* process state changes depending on the new state */ 933 switch (new_state) { 934 case CAN_STATE_ERROR_ACTIVE: 935 /* actually we want to enable AT91_IRQ_WARN here, but 936 * it screws up the system under certain 937 * circumstances. so just enable AT91_IRQ_ERRP, thus 938 * the "fallthrough" 939 */ 940 netdev_dbg(dev, "Error Active\n"); 941 cf->can_id |= CAN_ERR_PROT; 942 cf->data[2] = CAN_ERR_PROT_ACTIVE; 943 fallthrough; 944 case CAN_STATE_ERROR_WARNING: 945 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 946 reg_ier = AT91_IRQ_ERRP; 947 break; 948 case CAN_STATE_ERROR_PASSIVE: 949 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 950 reg_ier = AT91_IRQ_BOFF; 951 break; 952 case CAN_STATE_BUS_OFF: 953 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 954 AT91_IRQ_WARN | AT91_IRQ_BOFF; 955 reg_ier = 0; 956 957 cf->can_id |= CAN_ERR_BUSOFF; 958 959 netdev_dbg(dev, "bus-off\n"); 960 netif_carrier_off(dev); 961 priv->can.can_stats.bus_off++; 962 963 /* turn off chip, if restart is disabled */ 964 if (!priv->can.restart_ms) { 965 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 966 return; 967 } 968 break; 969 default: 970 break; 971 } 972 973 at91_write(priv, AT91_IDR, reg_idr); 974 at91_write(priv, AT91_IER, reg_ier); 975 } 976 977 static int at91_get_state_by_bec(const struct net_device *dev, 978 enum can_state *state) 979 { 980 struct can_berr_counter bec; 981 int err; 982 983 err = at91_get_berr_counter(dev, &bec); 984 if (err) 985 return err; 986 987 if (bec.txerr < 96 && bec.rxerr < 96) 988 *state = CAN_STATE_ERROR_ACTIVE; 989 else if (bec.txerr < 128 && bec.rxerr < 128) 990 *state = CAN_STATE_ERROR_WARNING; 991 else if (bec.txerr < 256 && bec.rxerr < 256) 992 *state = CAN_STATE_ERROR_PASSIVE; 993 else 994 *state = CAN_STATE_BUS_OFF; 995 996 return 0; 997 } 998 999 static void at91_irq_err(struct net_device *dev) 1000 { 1001 struct at91_priv *priv = netdev_priv(dev); 1002 struct sk_buff *skb; 1003 struct can_frame *cf; 1004 enum can_state new_state; 1005 u32 reg_sr; 1006 int err; 1007 1008 if (at91_is_sam9263(priv)) { 1009 reg_sr = at91_read(priv, AT91_SR); 1010 1011 /* we need to look at the unmasked reg_sr */ 1012 if (unlikely(reg_sr & AT91_IRQ_BOFF)) { 1013 new_state = CAN_STATE_BUS_OFF; 1014 } else if (unlikely(reg_sr & AT91_IRQ_ERRP)) { 1015 new_state = CAN_STATE_ERROR_PASSIVE; 1016 } else if (unlikely(reg_sr & AT91_IRQ_WARN)) { 1017 new_state = CAN_STATE_ERROR_WARNING; 1018 } else if (likely(reg_sr & AT91_IRQ_ERRA)) { 1019 new_state = CAN_STATE_ERROR_ACTIVE; 1020 } else { 1021 netdev_err(dev, "BUG! hardware in undefined state\n"); 1022 return; 1023 } 1024 } else { 1025 err = at91_get_state_by_bec(dev, &new_state); 1026 if (err) 1027 return; 1028 } 1029 1030 /* state hasn't changed */ 1031 if (likely(new_state == priv->can.state)) 1032 return; 1033 1034 skb = alloc_can_err_skb(dev, &cf); 1035 if (unlikely(!skb)) 1036 return; 1037 1038 at91_irq_err_state(dev, cf, new_state); 1039 1040 dev->stats.rx_packets++; 1041 dev->stats.rx_bytes += cf->len; 1042 netif_rx(skb); 1043 1044 priv->can.state = new_state; 1045 } 1046 1047 /* interrupt handler 1048 */ 1049 static irqreturn_t at91_irq(int irq, void *dev_id) 1050 { 1051 struct net_device *dev = dev_id; 1052 struct at91_priv *priv = netdev_priv(dev); 1053 irqreturn_t handled = IRQ_NONE; 1054 u32 reg_sr, reg_imr; 1055 1056 reg_sr = at91_read(priv, AT91_SR); 1057 reg_imr = at91_read(priv, AT91_IMR); 1058 1059 /* Ignore masked interrupts */ 1060 reg_sr &= reg_imr; 1061 if (!reg_sr) 1062 goto exit; 1063 1064 handled = IRQ_HANDLED; 1065 1066 /* Receive or error interrupt? -> napi */ 1067 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1068 /* The error bits are clear on read, 1069 * save for later use. 1070 */ 1071 priv->reg_sr = reg_sr; 1072 at91_write(priv, AT91_IDR, 1073 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1074 napi_schedule(&priv->napi); 1075 } 1076 1077 /* Transmission complete interrupt */ 1078 if (reg_sr & get_irq_mb_tx(priv)) 1079 at91_irq_tx(dev, reg_sr); 1080 1081 at91_irq_err(dev); 1082 1083 exit: 1084 return handled; 1085 } 1086 1087 static int at91_open(struct net_device *dev) 1088 { 1089 struct at91_priv *priv = netdev_priv(dev); 1090 int err; 1091 1092 err = clk_prepare_enable(priv->clk); 1093 if (err) 1094 return err; 1095 1096 /* check or determine and set bittime */ 1097 err = open_candev(dev); 1098 if (err) 1099 goto out; 1100 1101 /* register interrupt handler */ 1102 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1103 dev->name, dev)) { 1104 err = -EAGAIN; 1105 goto out_close; 1106 } 1107 1108 can_led_event(dev, CAN_LED_EVENT_OPEN); 1109 1110 /* start chip and queuing */ 1111 at91_chip_start(dev); 1112 napi_enable(&priv->napi); 1113 netif_start_queue(dev); 1114 1115 return 0; 1116 1117 out_close: 1118 close_candev(dev); 1119 out: 1120 clk_disable_unprepare(priv->clk); 1121 1122 return err; 1123 } 1124 1125 /* stop CAN bus activity 1126 */ 1127 static int at91_close(struct net_device *dev) 1128 { 1129 struct at91_priv *priv = netdev_priv(dev); 1130 1131 netif_stop_queue(dev); 1132 napi_disable(&priv->napi); 1133 at91_chip_stop(dev, CAN_STATE_STOPPED); 1134 1135 free_irq(dev->irq, dev); 1136 clk_disable_unprepare(priv->clk); 1137 1138 close_candev(dev); 1139 1140 can_led_event(dev, CAN_LED_EVENT_STOP); 1141 1142 return 0; 1143 } 1144 1145 static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1146 { 1147 switch (mode) { 1148 case CAN_MODE_START: 1149 at91_chip_start(dev); 1150 netif_wake_queue(dev); 1151 break; 1152 1153 default: 1154 return -EOPNOTSUPP; 1155 } 1156 1157 return 0; 1158 } 1159 1160 static const struct net_device_ops at91_netdev_ops = { 1161 .ndo_open = at91_open, 1162 .ndo_stop = at91_close, 1163 .ndo_start_xmit = at91_start_xmit, 1164 .ndo_change_mtu = can_change_mtu, 1165 }; 1166 1167 static ssize_t mb0_id_show(struct device *dev, 1168 struct device_attribute *attr, char *buf) 1169 { 1170 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1171 1172 if (priv->mb0_id & CAN_EFF_FLAG) 1173 return sysfs_emit(buf, "0x%08x\n", priv->mb0_id); 1174 else 1175 return sysfs_emit(buf, "0x%03x\n", priv->mb0_id); 1176 } 1177 1178 static ssize_t mb0_id_store(struct device *dev, 1179 struct device_attribute *attr, 1180 const char *buf, size_t count) 1181 { 1182 struct net_device *ndev = to_net_dev(dev); 1183 struct at91_priv *priv = netdev_priv(ndev); 1184 unsigned long can_id; 1185 ssize_t ret; 1186 int err; 1187 1188 rtnl_lock(); 1189 1190 if (ndev->flags & IFF_UP) { 1191 ret = -EBUSY; 1192 goto out; 1193 } 1194 1195 err = kstrtoul(buf, 0, &can_id); 1196 if (err) { 1197 ret = err; 1198 goto out; 1199 } 1200 1201 if (can_id & CAN_EFF_FLAG) 1202 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1203 else 1204 can_id &= CAN_SFF_MASK; 1205 1206 priv->mb0_id = can_id; 1207 ret = count; 1208 1209 out: 1210 rtnl_unlock(); 1211 return ret; 1212 } 1213 1214 static DEVICE_ATTR_RW(mb0_id); 1215 1216 static struct attribute *at91_sysfs_attrs[] = { 1217 &dev_attr_mb0_id.attr, 1218 NULL, 1219 }; 1220 1221 static const struct attribute_group at91_sysfs_attr_group = { 1222 .attrs = at91_sysfs_attrs, 1223 }; 1224 1225 #if defined(CONFIG_OF) 1226 static const struct of_device_id at91_can_dt_ids[] = { 1227 { 1228 .compatible = "atmel,at91sam9x5-can", 1229 .data = &at91_at91sam9x5_data, 1230 }, { 1231 .compatible = "atmel,at91sam9263-can", 1232 .data = &at91_at91sam9263_data, 1233 }, { 1234 /* sentinel */ 1235 } 1236 }; 1237 MODULE_DEVICE_TABLE(of, at91_can_dt_ids); 1238 #endif 1239 1240 static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev) 1241 { 1242 if (pdev->dev.of_node) { 1243 const struct of_device_id *match; 1244 1245 match = of_match_node(at91_can_dt_ids, pdev->dev.of_node); 1246 if (!match) { 1247 dev_err(&pdev->dev, "no matching node found in dtb\n"); 1248 return NULL; 1249 } 1250 return (const struct at91_devtype_data *)match->data; 1251 } 1252 return (const struct at91_devtype_data *) 1253 platform_get_device_id(pdev)->driver_data; 1254 } 1255 1256 static int at91_can_probe(struct platform_device *pdev) 1257 { 1258 const struct at91_devtype_data *devtype_data; 1259 struct net_device *dev; 1260 struct at91_priv *priv; 1261 struct resource *res; 1262 struct clk *clk; 1263 void __iomem *addr; 1264 int err, irq; 1265 1266 devtype_data = at91_can_get_driver_data(pdev); 1267 if (!devtype_data) { 1268 dev_err(&pdev->dev, "no driver data\n"); 1269 err = -ENODEV; 1270 goto exit; 1271 } 1272 1273 clk = clk_get(&pdev->dev, "can_clk"); 1274 if (IS_ERR(clk)) { 1275 dev_err(&pdev->dev, "no clock defined\n"); 1276 err = -ENODEV; 1277 goto exit; 1278 } 1279 1280 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1281 irq = platform_get_irq(pdev, 0); 1282 if (!res || irq <= 0) { 1283 err = -ENODEV; 1284 goto exit_put; 1285 } 1286 1287 if (!request_mem_region(res->start, 1288 resource_size(res), 1289 pdev->name)) { 1290 err = -EBUSY; 1291 goto exit_put; 1292 } 1293 1294 addr = ioremap(res->start, resource_size(res)); 1295 if (!addr) { 1296 err = -ENOMEM; 1297 goto exit_release; 1298 } 1299 1300 dev = alloc_candev(sizeof(struct at91_priv), 1301 1 << devtype_data->tx_shift); 1302 if (!dev) { 1303 err = -ENOMEM; 1304 goto exit_iounmap; 1305 } 1306 1307 dev->netdev_ops = &at91_netdev_ops; 1308 dev->irq = irq; 1309 dev->flags |= IFF_ECHO; 1310 1311 priv = netdev_priv(dev); 1312 priv->can.clock.freq = clk_get_rate(clk); 1313 priv->can.bittiming_const = &at91_bittiming_const; 1314 priv->can.do_set_mode = at91_set_mode; 1315 priv->can.do_get_berr_counter = at91_get_berr_counter; 1316 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1317 CAN_CTRLMODE_LISTENONLY; 1318 priv->reg_base = addr; 1319 priv->devtype_data = *devtype_data; 1320 priv->clk = clk; 1321 priv->pdata = dev_get_platdata(&pdev->dev); 1322 priv->mb0_id = 0x7ff; 1323 1324 netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv)); 1325 1326 if (at91_is_sam9263(priv)) 1327 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1328 1329 platform_set_drvdata(pdev, dev); 1330 SET_NETDEV_DEV(dev, &pdev->dev); 1331 1332 err = register_candev(dev); 1333 if (err) { 1334 dev_err(&pdev->dev, "registering netdev failed\n"); 1335 goto exit_free; 1336 } 1337 1338 devm_can_led_init(dev); 1339 1340 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1341 priv->reg_base, dev->irq); 1342 1343 return 0; 1344 1345 exit_free: 1346 free_candev(dev); 1347 exit_iounmap: 1348 iounmap(addr); 1349 exit_release: 1350 release_mem_region(res->start, resource_size(res)); 1351 exit_put: 1352 clk_put(clk); 1353 exit: 1354 return err; 1355 } 1356 1357 static int at91_can_remove(struct platform_device *pdev) 1358 { 1359 struct net_device *dev = platform_get_drvdata(pdev); 1360 struct at91_priv *priv = netdev_priv(dev); 1361 struct resource *res; 1362 1363 unregister_netdev(dev); 1364 1365 iounmap(priv->reg_base); 1366 1367 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1368 release_mem_region(res->start, resource_size(res)); 1369 1370 clk_put(priv->clk); 1371 1372 free_candev(dev); 1373 1374 return 0; 1375 } 1376 1377 static const struct platform_device_id at91_can_id_table[] = { 1378 { 1379 .name = "at91sam9x5_can", 1380 .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data, 1381 }, { 1382 .name = "at91_can", 1383 .driver_data = (kernel_ulong_t)&at91_at91sam9263_data, 1384 }, { 1385 /* sentinel */ 1386 } 1387 }; 1388 MODULE_DEVICE_TABLE(platform, at91_can_id_table); 1389 1390 static struct platform_driver at91_can_driver = { 1391 .probe = at91_can_probe, 1392 .remove = at91_can_remove, 1393 .driver = { 1394 .name = KBUILD_MODNAME, 1395 .of_match_table = of_match_ptr(at91_can_dt_ids), 1396 }, 1397 .id_table = at91_can_id_table, 1398 }; 1399 1400 module_platform_driver(at91_can_driver); 1401 1402 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1403 MODULE_LICENSE("GPL v2"); 1404 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1405