xref: /openbmc/linux/drivers/net/can/at91_can.c (revision b6dcefde)
1 /*
2  * at91_can.c - CAN network driver for AT91 SoC CAN controller
3  *
4  * (C) 2007 by Hans J. Koch <hjk@linutronix.de>
5  * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
6  *
7  * This software may be distributed under the terms of the GNU General
8  * Public License ("GPL") version 2 as distributed in the 'COPYING'
9  * file from the main directory of the linux kernel source.
10  *
11  * Send feedback to <socketcan-users@lists.berlios.de>
12  *
13  *
14  * Your platform definition file should specify something like:
15  *
16  * static struct at91_can_data ek_can_data = {
17  *	transceiver_switch = sam9263ek_transceiver_switch,
18  * };
19  *
20  * at91_add_device_can(&ek_can_data);
21  *
22  */
23 
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <linux/if_arp.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
35 #include <linux/string.h>
36 #include <linux/types.h>
37 
38 #include <linux/can.h>
39 #include <linux/can/dev.h>
40 #include <linux/can/error.h>
41 
42 #include <mach/board.h>
43 
44 #define DRV_NAME		"at91_can"
45 #define AT91_NAPI_WEIGHT	12
46 
47 /*
48  * RX/TX Mailbox split
49  * don't dare to touch
50  */
51 #define AT91_MB_RX_NUM		12
52 #define AT91_MB_TX_SHIFT	2
53 
54 #define AT91_MB_RX_FIRST	0
55 #define AT91_MB_RX_LAST		(AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
56 
57 #define AT91_MB_RX_MASK(i)	((1 << (i)) - 1)
58 #define AT91_MB_RX_SPLIT	8
59 #define AT91_MB_RX_LOW_LAST	(AT91_MB_RX_SPLIT - 1)
60 #define AT91_MB_RX_LOW_MASK	(AT91_MB_RX_MASK(AT91_MB_RX_SPLIT))
61 
62 #define AT91_MB_TX_NUM		(1 << AT91_MB_TX_SHIFT)
63 #define AT91_MB_TX_FIRST	(AT91_MB_RX_LAST + 1)
64 #define AT91_MB_TX_LAST		(AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
65 
66 #define AT91_NEXT_PRIO_SHIFT	(AT91_MB_TX_SHIFT)
67 #define AT91_NEXT_PRIO_MASK	(0xf << AT91_MB_TX_SHIFT)
68 #define AT91_NEXT_MB_MASK	(AT91_MB_TX_NUM - 1)
69 #define AT91_NEXT_MASK		((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
70 
71 /* Common registers */
72 enum at91_reg {
73 	AT91_MR		= 0x000,
74 	AT91_IER	= 0x004,
75 	AT91_IDR	= 0x008,
76 	AT91_IMR	= 0x00C,
77 	AT91_SR		= 0x010,
78 	AT91_BR		= 0x014,
79 	AT91_TIM	= 0x018,
80 	AT91_TIMESTP	= 0x01C,
81 	AT91_ECR	= 0x020,
82 	AT91_TCR	= 0x024,
83 	AT91_ACR	= 0x028,
84 };
85 
86 /* Mailbox registers (0 <= i <= 15) */
87 #define AT91_MMR(i)		(enum at91_reg)(0x200 + ((i) * 0x20))
88 #define AT91_MAM(i)		(enum at91_reg)(0x204 + ((i) * 0x20))
89 #define AT91_MID(i)		(enum at91_reg)(0x208 + ((i) * 0x20))
90 #define AT91_MFID(i)		(enum at91_reg)(0x20C + ((i) * 0x20))
91 #define AT91_MSR(i)		(enum at91_reg)(0x210 + ((i) * 0x20))
92 #define AT91_MDL(i)		(enum at91_reg)(0x214 + ((i) * 0x20))
93 #define AT91_MDH(i)		(enum at91_reg)(0x218 + ((i) * 0x20))
94 #define AT91_MCR(i)		(enum at91_reg)(0x21C + ((i) * 0x20))
95 
96 /* Register bits */
97 #define AT91_MR_CANEN		BIT(0)
98 #define AT91_MR_LPM		BIT(1)
99 #define AT91_MR_ABM		BIT(2)
100 #define AT91_MR_OVL		BIT(3)
101 #define AT91_MR_TEOF		BIT(4)
102 #define AT91_MR_TTM		BIT(5)
103 #define AT91_MR_TIMFRZ		BIT(6)
104 #define AT91_MR_DRPT		BIT(7)
105 
106 #define AT91_SR_RBSY		BIT(29)
107 
108 #define AT91_MMR_PRIO_SHIFT	(16)
109 
110 #define AT91_MID_MIDE		BIT(29)
111 
112 #define AT91_MSR_MRTR		BIT(20)
113 #define AT91_MSR_MABT		BIT(22)
114 #define AT91_MSR_MRDY		BIT(23)
115 #define AT91_MSR_MMI		BIT(24)
116 
117 #define AT91_MCR_MRTR		BIT(20)
118 #define AT91_MCR_MTCR		BIT(23)
119 
120 /* Mailbox Modes */
121 enum at91_mb_mode {
122 	AT91_MB_MODE_DISABLED	= 0,
123 	AT91_MB_MODE_RX		= 1,
124 	AT91_MB_MODE_RX_OVRWR	= 2,
125 	AT91_MB_MODE_TX		= 3,
126 	AT91_MB_MODE_CONSUMER	= 4,
127 	AT91_MB_MODE_PRODUCER	= 5,
128 };
129 
130 /* Interrupt mask bits */
131 #define AT91_IRQ_MB_RX		((1 << (AT91_MB_RX_LAST + 1)) \
132 				 - (1 << AT91_MB_RX_FIRST))
133 #define AT91_IRQ_MB_TX		((1 << (AT91_MB_TX_LAST + 1)) \
134 				 - (1 << AT91_MB_TX_FIRST))
135 #define AT91_IRQ_MB_ALL		(AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
136 
137 #define AT91_IRQ_ERRA		(1 << 16)
138 #define AT91_IRQ_WARN		(1 << 17)
139 #define AT91_IRQ_ERRP		(1 << 18)
140 #define AT91_IRQ_BOFF		(1 << 19)
141 #define AT91_IRQ_SLEEP		(1 << 20)
142 #define AT91_IRQ_WAKEUP		(1 << 21)
143 #define AT91_IRQ_TOVF		(1 << 22)
144 #define AT91_IRQ_TSTP		(1 << 23)
145 #define AT91_IRQ_CERR		(1 << 24)
146 #define AT91_IRQ_SERR		(1 << 25)
147 #define AT91_IRQ_AERR		(1 << 26)
148 #define AT91_IRQ_FERR		(1 << 27)
149 #define AT91_IRQ_BERR		(1 << 28)
150 
151 #define AT91_IRQ_ERR_ALL	(0x1fff0000)
152 #define AT91_IRQ_ERR_FRAME	(AT91_IRQ_CERR | AT91_IRQ_SERR | \
153 				 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
154 #define AT91_IRQ_ERR_LINE	(AT91_IRQ_ERRA | AT91_IRQ_WARN | \
155 				 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
156 
157 #define AT91_IRQ_ALL		(0x1fffffff)
158 
159 struct at91_priv {
160 	struct can_priv		can;	   /* must be the first member! */
161 	struct net_device	*dev;
162 	struct napi_struct	napi;
163 
164 	void __iomem		*reg_base;
165 
166 	u32			reg_sr;
167 	unsigned int		tx_next;
168 	unsigned int		tx_echo;
169 	unsigned int		rx_next;
170 
171 	struct clk		*clk;
172 	struct at91_can_data	*pdata;
173 };
174 
175 static struct can_bittiming_const at91_bittiming_const = {
176 	.tseg1_min	= 4,
177 	.tseg1_max	= 16,
178 	.tseg2_min	= 2,
179 	.tseg2_max	= 8,
180 	.sjw_max	= 4,
181 	.brp_min 	= 2,
182 	.brp_max	= 128,
183 	.brp_inc	= 1,
184 };
185 
186 static inline int get_tx_next_mb(const struct at91_priv *priv)
187 {
188 	return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
189 }
190 
191 static inline int get_tx_next_prio(const struct at91_priv *priv)
192 {
193 	return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
194 }
195 
196 static inline int get_tx_echo_mb(const struct at91_priv *priv)
197 {
198 	return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
199 }
200 
201 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
202 {
203 	return readl(priv->reg_base + reg);
204 }
205 
206 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
207 		u32 value)
208 {
209 	writel(value, priv->reg_base + reg);
210 }
211 
212 static inline void set_mb_mode_prio(const struct at91_priv *priv,
213 		unsigned int mb, enum at91_mb_mode mode, int prio)
214 {
215 	at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
216 }
217 
218 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
219 		enum at91_mb_mode mode)
220 {
221 	set_mb_mode_prio(priv, mb, mode, 0);
222 }
223 
224 /*
225  * Swtich transceiver on or off
226  */
227 static void at91_transceiver_switch(const struct at91_priv *priv, int on)
228 {
229 	if (priv->pdata && priv->pdata->transceiver_switch)
230 		priv->pdata->transceiver_switch(on);
231 }
232 
233 static void at91_setup_mailboxes(struct net_device *dev)
234 {
235 	struct at91_priv *priv = netdev_priv(dev);
236 	unsigned int i;
237 
238 	/*
239 	 * The first 12 mailboxes are used as a reception FIFO. The
240 	 * last mailbox is configured with overwrite option. The
241 	 * overwrite flag indicates a FIFO overflow.
242 	 */
243 	for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
244 		set_mb_mode(priv, i, AT91_MB_MODE_RX);
245 	set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
246 
247 	/* The last 4 mailboxes are used for transmitting. */
248 	for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++)
249 		set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
250 
251 	/* Reset tx and rx helper pointers */
252 	priv->tx_next = priv->tx_echo = priv->rx_next = 0;
253 }
254 
255 static int at91_set_bittiming(struct net_device *dev)
256 {
257 	const struct at91_priv *priv = netdev_priv(dev);
258 	const struct can_bittiming *bt = &priv->can.bittiming;
259 	u32 reg_br;
260 
261 	reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) << 24) |
262 		((bt->brp - 1) << 16) |	((bt->sjw - 1) << 12) |
263 		((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
264 		((bt->phase_seg2 - 1) << 0);
265 
266 	dev_info(dev->dev.parent, "writing AT91_BR: 0x%08x\n", reg_br);
267 
268 	at91_write(priv, AT91_BR, reg_br);
269 
270 	return 0;
271 }
272 
273 static void at91_chip_start(struct net_device *dev)
274 {
275 	struct at91_priv *priv = netdev_priv(dev);
276 	u32 reg_mr, reg_ier;
277 
278 	/* disable interrupts */
279 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
280 
281 	/* disable chip */
282 	reg_mr = at91_read(priv, AT91_MR);
283 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
284 
285 	at91_setup_mailboxes(dev);
286 	at91_transceiver_switch(priv, 1);
287 
288 	/* enable chip */
289 	at91_write(priv, AT91_MR, AT91_MR_CANEN);
290 
291 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
292 
293 	/* Enable interrupts */
294 	reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
295 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
296 	at91_write(priv, AT91_IER, reg_ier);
297 }
298 
299 static void at91_chip_stop(struct net_device *dev, enum can_state state)
300 {
301 	struct at91_priv *priv = netdev_priv(dev);
302 	u32 reg_mr;
303 
304 	/* disable interrupts */
305 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
306 
307 	reg_mr = at91_read(priv, AT91_MR);
308 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
309 
310 	at91_transceiver_switch(priv, 0);
311 	priv->can.state = state;
312 }
313 
314 /*
315  * theory of operation:
316  *
317  * According to the datasheet priority 0 is the highest priority, 15
318  * is the lowest. If two mailboxes have the same priority level the
319  * message of the mailbox with the lowest number is sent first.
320  *
321  * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
322  * the next mailbox with prio 0, and so on, until all mailboxes are
323  * used. Then we start from the beginning with mailbox
324  * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
325  * prio 1. When we reach the last mailbox with prio 15, we have to
326  * stop sending, waiting for all messages to be delivered, then start
327  * again with mailbox AT91_MB_TX_FIRST prio 0.
328  *
329  * We use the priv->tx_next as counter for the next transmission
330  * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
331  * encode the mailbox number, the upper 4 bits the mailbox priority:
332  *
333  * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
334  *                 (mb - AT91_MB_TX_FIRST);
335  *
336  */
337 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
338 {
339 	struct at91_priv *priv = netdev_priv(dev);
340 	struct net_device_stats *stats = &dev->stats;
341 	struct can_frame *cf = (struct can_frame *)skb->data;
342 	unsigned int mb, prio;
343 	u32 reg_mid, reg_mcr;
344 
345 	mb = get_tx_next_mb(priv);
346 	prio = get_tx_next_prio(priv);
347 
348 	if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
349 		netif_stop_queue(dev);
350 
351 		dev_err(dev->dev.parent,
352 			"BUG! TX buffer full when queue awake!\n");
353 		return NETDEV_TX_BUSY;
354 	}
355 
356 	if (cf->can_id & CAN_EFF_FLAG)
357 		reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
358 	else
359 		reg_mid = (cf->can_id & CAN_SFF_MASK) << 18;
360 
361 	reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
362 		(cf->can_dlc << 16) | AT91_MCR_MTCR;
363 
364 	/* disable MB while writing ID (see datasheet) */
365 	set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
366 	at91_write(priv, AT91_MID(mb), reg_mid);
367 	set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
368 
369 	at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
370 	at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
371 
372 	/* This triggers transmission */
373 	at91_write(priv, AT91_MCR(mb), reg_mcr);
374 
375 	stats->tx_bytes += cf->can_dlc;
376 	dev->trans_start = jiffies;
377 
378 	/* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
379 	can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST);
380 
381 	/*
382 	 * we have to stop the queue and deliver all messages in case
383 	 * of a prio+mb counter wrap around. This is the case if
384 	 * tx_next buffer prio and mailbox equals 0.
385 	 *
386 	 * also stop the queue if next buffer is still in use
387 	 * (== not ready)
388 	 */
389 	priv->tx_next++;
390 	if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
391 	      AT91_MSR_MRDY) ||
392 	    (priv->tx_next & AT91_NEXT_MASK) == 0)
393 		netif_stop_queue(dev);
394 
395 	/* Enable interrupt for this mailbox */
396 	at91_write(priv, AT91_IER, 1 << mb);
397 
398 	return NETDEV_TX_OK;
399 }
400 
401 /**
402  * at91_activate_rx_low - activate lower rx mailboxes
403  * @priv: a91 context
404  *
405  * Reenables the lower mailboxes for reception of new CAN messages
406  */
407 static inline void at91_activate_rx_low(const struct at91_priv *priv)
408 {
409 	u32 mask = AT91_MB_RX_LOW_MASK;
410 	at91_write(priv, AT91_TCR, mask);
411 }
412 
413 /**
414  * at91_activate_rx_mb - reactive single rx mailbox
415  * @priv: a91 context
416  * @mb: mailbox to reactivate
417  *
418  * Reenables given mailbox for reception of new CAN messages
419  */
420 static inline void at91_activate_rx_mb(const struct at91_priv *priv,
421 		unsigned int mb)
422 {
423 	u32 mask = 1 << mb;
424 	at91_write(priv, AT91_TCR, mask);
425 }
426 
427 /**
428  * at91_rx_overflow_err - send error frame due to rx overflow
429  * @dev: net device
430  */
431 static void at91_rx_overflow_err(struct net_device *dev)
432 {
433 	struct net_device_stats *stats = &dev->stats;
434 	struct sk_buff *skb;
435 	struct can_frame *cf;
436 
437 	dev_dbg(dev->dev.parent, "RX buffer overflow\n");
438 	stats->rx_over_errors++;
439 	stats->rx_errors++;
440 
441 	skb = alloc_can_err_skb(dev, &cf);
442 	if (unlikely(!skb))
443 		return;
444 
445 	cf->can_id |= CAN_ERR_CRTL;
446 	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
447 	netif_receive_skb(skb);
448 
449 	stats->rx_packets++;
450 	stats->rx_bytes += cf->can_dlc;
451 }
452 
453 /**
454  * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
455  * @dev: net device
456  * @mb: mailbox number to read from
457  * @cf: can frame where to store message
458  *
459  * Reads a CAN message from the given mailbox and stores data into
460  * given can frame. "mb" and "cf" must be valid.
461  */
462 static void at91_read_mb(struct net_device *dev, unsigned int mb,
463 		struct can_frame *cf)
464 {
465 	const struct at91_priv *priv = netdev_priv(dev);
466 	u32 reg_msr, reg_mid;
467 
468 	reg_mid = at91_read(priv, AT91_MID(mb));
469 	if (reg_mid & AT91_MID_MIDE)
470 		cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
471 	else
472 		cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
473 
474 	reg_msr = at91_read(priv, AT91_MSR(mb));
475 	if (reg_msr & AT91_MSR_MRTR)
476 		cf->can_id |= CAN_RTR_FLAG;
477 	cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
478 
479 	*(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
480 	*(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
481 
482 	if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI))
483 		at91_rx_overflow_err(dev);
484 }
485 
486 /**
487  * at91_read_msg - read CAN message from mailbox
488  * @dev: net device
489  * @mb: mail box to read from
490  *
491  * Reads a CAN message from given mailbox, and put into linux network
492  * RX queue, does all housekeeping chores (stats, ...)
493  */
494 static void at91_read_msg(struct net_device *dev, unsigned int mb)
495 {
496 	struct net_device_stats *stats = &dev->stats;
497 	struct can_frame *cf;
498 	struct sk_buff *skb;
499 
500 	skb = alloc_can_skb(dev, &cf);
501 	if (unlikely(!skb)) {
502 		stats->rx_dropped++;
503 		return;
504 	}
505 
506 	at91_read_mb(dev, mb, cf);
507 	netif_receive_skb(skb);
508 
509 	stats->rx_packets++;
510 	stats->rx_bytes += cf->can_dlc;
511 }
512 
513 /**
514  * at91_poll_rx - read multiple CAN messages from mailboxes
515  * @dev: net device
516  * @quota: max number of pkgs we're allowed to receive
517  *
518  * Theory of Operation:
519  *
520  * 12 of the 16 mailboxes on the chip are reserved for RX. we split
521  * them into 2 groups. The lower group holds 8 and upper 4 mailboxes.
522  *
523  * Like it or not, but the chip always saves a received CAN message
524  * into the first free mailbox it finds (starting with the
525  * lowest). This makes it very difficult to read the messages in the
526  * right order from the chip. This is how we work around that problem:
527  *
528  * The first message goes into mb nr. 0 and issues an interrupt. All
529  * rx ints are disabled in the interrupt handler and a napi poll is
530  * scheduled. We read the mailbox, but do _not_ reenable the mb (to
531  * receive another message).
532  *
533  *    lower mbxs      upper
534  *   ______^______    __^__
535  *  /             \  /     \
536  * +-+-+-+-+-+-+-+-++-+-+-+-+
537  * |x|x|x|x|x|x|x|x|| | | | |
538  * +-+-+-+-+-+-+-+-++-+-+-+-+
539  *  0 0 0 0 0 0  0 0 0 0 1 1  \ mail
540  *  0 1 2 3 4 5  6 7 8 9 0 1  / box
541  *
542  * The variable priv->rx_next points to the next mailbox to read a
543  * message from. As long we're in the lower mailboxes we just read the
544  * mailbox but not reenable it.
545  *
546  * With completion of the last of the lower mailboxes, we reenable the
547  * whole first group, but continue to look for filled mailboxes in the
548  * upper mailboxes. Imagine the second group like overflow mailboxes,
549  * which takes CAN messages if the lower goup is full. While in the
550  * upper group we reenable the mailbox right after reading it. Giving
551  * the chip more room to store messages.
552  *
553  * After finishing we look again in the lower group if we've still
554  * quota.
555  *
556  */
557 static int at91_poll_rx(struct net_device *dev, int quota)
558 {
559 	struct at91_priv *priv = netdev_priv(dev);
560 	u32 reg_sr = at91_read(priv, AT91_SR);
561 	const unsigned long *addr = (unsigned long *)&reg_sr;
562 	unsigned int mb;
563 	int received = 0;
564 
565 	if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
566 	    reg_sr & AT91_MB_RX_LOW_MASK)
567 		dev_info(dev->dev.parent,
568 			 "order of incoming frames cannot be guaranteed\n");
569 
570  again:
571 	for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next);
572 	     mb < AT91_MB_RX_NUM && quota > 0;
573 	     reg_sr = at91_read(priv, AT91_SR),
574 	     mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) {
575 		at91_read_msg(dev, mb);
576 
577 		/* reactivate mailboxes */
578 		if (mb == AT91_MB_RX_LOW_LAST)
579 			/* all lower mailboxed, if just finished it */
580 			at91_activate_rx_low(priv);
581 		else if (mb > AT91_MB_RX_LOW_LAST)
582 			/* only the mailbox we read */
583 			at91_activate_rx_mb(priv, mb);
584 
585 		received++;
586 		quota--;
587 	}
588 
589 	/* upper group completed, look again in lower */
590 	if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
591 	    quota > 0 && mb >= AT91_MB_RX_NUM) {
592 		priv->rx_next = 0;
593 		goto again;
594 	}
595 
596 	return received;
597 }
598 
599 static void at91_poll_err_frame(struct net_device *dev,
600 		struct can_frame *cf, u32 reg_sr)
601 {
602 	struct at91_priv *priv = netdev_priv(dev);
603 
604 	/* CRC error */
605 	if (reg_sr & AT91_IRQ_CERR) {
606 		dev_dbg(dev->dev.parent, "CERR irq\n");
607 		dev->stats.rx_errors++;
608 		priv->can.can_stats.bus_error++;
609 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
610 	}
611 
612 	/* Stuffing Error */
613 	if (reg_sr & AT91_IRQ_SERR) {
614 		dev_dbg(dev->dev.parent, "SERR irq\n");
615 		dev->stats.rx_errors++;
616 		priv->can.can_stats.bus_error++;
617 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
618 		cf->data[2] |= CAN_ERR_PROT_STUFF;
619 	}
620 
621 	/* Acknowledgement Error */
622 	if (reg_sr & AT91_IRQ_AERR) {
623 		dev_dbg(dev->dev.parent, "AERR irq\n");
624 		dev->stats.tx_errors++;
625 		cf->can_id |= CAN_ERR_ACK;
626 	}
627 
628 	/* Form error */
629 	if (reg_sr & AT91_IRQ_FERR) {
630 		dev_dbg(dev->dev.parent, "FERR irq\n");
631 		dev->stats.rx_errors++;
632 		priv->can.can_stats.bus_error++;
633 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
634 		cf->data[2] |= CAN_ERR_PROT_FORM;
635 	}
636 
637 	/* Bit Error */
638 	if (reg_sr & AT91_IRQ_BERR) {
639 		dev_dbg(dev->dev.parent, "BERR irq\n");
640 		dev->stats.tx_errors++;
641 		priv->can.can_stats.bus_error++;
642 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
643 		cf->data[2] |= CAN_ERR_PROT_BIT;
644 	}
645 }
646 
647 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
648 {
649 	struct sk_buff *skb;
650 	struct can_frame *cf;
651 
652 	if (quota == 0)
653 		return 0;
654 
655 	skb = alloc_can_err_skb(dev, &cf);
656 	if (unlikely(!skb))
657 		return 0;
658 
659 	at91_poll_err_frame(dev, cf, reg_sr);
660 	netif_receive_skb(skb);
661 
662 	dev->last_rx = jiffies;
663 	dev->stats.rx_packets++;
664 	dev->stats.rx_bytes += cf->can_dlc;
665 
666 	return 1;
667 }
668 
669 static int at91_poll(struct napi_struct *napi, int quota)
670 {
671 	struct net_device *dev = napi->dev;
672 	const struct at91_priv *priv = netdev_priv(dev);
673 	u32 reg_sr = at91_read(priv, AT91_SR);
674 	int work_done = 0;
675 
676 	if (reg_sr & AT91_IRQ_MB_RX)
677 		work_done += at91_poll_rx(dev, quota - work_done);
678 
679 	/*
680 	 * The error bits are clear on read,
681 	 * so use saved value from irq handler.
682 	 */
683 	reg_sr |= priv->reg_sr;
684 	if (reg_sr & AT91_IRQ_ERR_FRAME)
685 		work_done += at91_poll_err(dev, quota - work_done, reg_sr);
686 
687 	if (work_done < quota) {
688 		/* enable IRQs for frame errors and all mailboxes >= rx_next */
689 		u32 reg_ier = AT91_IRQ_ERR_FRAME;
690 		reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next);
691 
692 		napi_complete(napi);
693 		at91_write(priv, AT91_IER, reg_ier);
694 	}
695 
696 	return work_done;
697 }
698 
699 /*
700  * theory of operation:
701  *
702  * priv->tx_echo holds the number of the oldest can_frame put for
703  * transmission into the hardware, but not yet ACKed by the CAN tx
704  * complete IRQ.
705  *
706  * We iterate from priv->tx_echo to priv->tx_next and check if the
707  * packet has been transmitted, echo it back to the CAN framework. If
708  * we discover a not yet transmitted package, stop looking for more.
709  *
710  */
711 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
712 {
713 	struct at91_priv *priv = netdev_priv(dev);
714 	u32 reg_msr;
715 	unsigned int mb;
716 
717 	/* masking of reg_sr not needed, already done by at91_irq */
718 
719 	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
720 		mb = get_tx_echo_mb(priv);
721 
722 		/* no event in mailbox? */
723 		if (!(reg_sr & (1 << mb)))
724 			break;
725 
726 		/* Disable irq for this TX mailbox */
727 		at91_write(priv, AT91_IDR, 1 << mb);
728 
729 		/*
730 		 * only echo if mailbox signals us a transfer
731 		 * complete (MSR_MRDY). Otherwise it's a tansfer
732 		 * abort. "can_bus_off()" takes care about the skbs
733 		 * parked in the echo queue.
734 		 */
735 		reg_msr = at91_read(priv, AT91_MSR(mb));
736 		if (likely(reg_msr & AT91_MSR_MRDY &&
737 			   ~reg_msr & AT91_MSR_MABT)) {
738 			/* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
739 			can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST);
740 			dev->stats.tx_packets++;
741 		}
742 	}
743 
744 	/*
745 	 * restart queue if we don't have a wrap around but restart if
746 	 * we get a TX int for the last can frame directly before a
747 	 * wrap around.
748 	 */
749 	if ((priv->tx_next & AT91_NEXT_MASK) != 0 ||
750 	    (priv->tx_echo & AT91_NEXT_MASK) == 0)
751 		netif_wake_queue(dev);
752 }
753 
754 static void at91_irq_err_state(struct net_device *dev,
755 		struct can_frame *cf, enum can_state new_state)
756 {
757 	struct at91_priv *priv = netdev_priv(dev);
758 	u32 reg_idr, reg_ier, reg_ecr;
759 	u8 tec, rec;
760 
761 	reg_ecr = at91_read(priv, AT91_ECR);
762 	rec = reg_ecr & 0xff;
763 	tec = reg_ecr >> 16;
764 
765 	switch (priv->can.state) {
766 	case CAN_STATE_ERROR_ACTIVE:
767 		/*
768 		 * from: ERROR_ACTIVE
769 		 * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
770 		 * =>  : there was a warning int
771 		 */
772 		if (new_state >= CAN_STATE_ERROR_WARNING &&
773 		    new_state <= CAN_STATE_BUS_OFF) {
774 			dev_dbg(dev->dev.parent, "Error Warning IRQ\n");
775 			priv->can.can_stats.error_warning++;
776 
777 			cf->can_id |= CAN_ERR_CRTL;
778 			cf->data[1] = (tec > rec) ?
779 				CAN_ERR_CRTL_TX_WARNING :
780 				CAN_ERR_CRTL_RX_WARNING;
781 		}
782 	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
783 		/*
784 		 * from: ERROR_ACTIVE, ERROR_WARNING
785 		 * to  : ERROR_PASSIVE, BUS_OFF
786 		 * =>  : error passive int
787 		 */
788 		if (new_state >= CAN_STATE_ERROR_PASSIVE &&
789 		    new_state <= CAN_STATE_BUS_OFF) {
790 			dev_dbg(dev->dev.parent, "Error Passive IRQ\n");
791 			priv->can.can_stats.error_passive++;
792 
793 			cf->can_id |= CAN_ERR_CRTL;
794 			cf->data[1] = (tec > rec) ?
795 				CAN_ERR_CRTL_TX_PASSIVE :
796 				CAN_ERR_CRTL_RX_PASSIVE;
797 		}
798 		break;
799 	case CAN_STATE_BUS_OFF:
800 		/*
801 		 * from: BUS_OFF
802 		 * to  : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
803 		 */
804 		if (new_state <= CAN_STATE_ERROR_PASSIVE) {
805 			cf->can_id |= CAN_ERR_RESTARTED;
806 
807 			dev_dbg(dev->dev.parent, "restarted\n");
808 			priv->can.can_stats.restarts++;
809 
810 			netif_carrier_on(dev);
811 			netif_wake_queue(dev);
812 		}
813 		break;
814 	default:
815 		break;
816 	}
817 
818 
819 	/* process state changes depending on the new state */
820 	switch (new_state) {
821 	case CAN_STATE_ERROR_ACTIVE:
822 		/*
823 		 * actually we want to enable AT91_IRQ_WARN here, but
824 		 * it screws up the system under certain
825 		 * circumstances. so just enable AT91_IRQ_ERRP, thus
826 		 * the "fallthrough"
827 		 */
828 		dev_dbg(dev->dev.parent, "Error Active\n");
829 		cf->can_id |= CAN_ERR_PROT;
830 		cf->data[2] = CAN_ERR_PROT_ACTIVE;
831 	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
832 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
833 		reg_ier = AT91_IRQ_ERRP;
834 		break;
835 	case CAN_STATE_ERROR_PASSIVE:
836 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
837 		reg_ier = AT91_IRQ_BOFF;
838 		break;
839 	case CAN_STATE_BUS_OFF:
840 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
841 			AT91_IRQ_WARN | AT91_IRQ_BOFF;
842 		reg_ier = 0;
843 
844 		cf->can_id |= CAN_ERR_BUSOFF;
845 
846 		dev_dbg(dev->dev.parent, "bus-off\n");
847 		netif_carrier_off(dev);
848 		priv->can.can_stats.bus_off++;
849 
850 		/* turn off chip, if restart is disabled */
851 		if (!priv->can.restart_ms) {
852 			at91_chip_stop(dev, CAN_STATE_BUS_OFF);
853 			return;
854 		}
855 		break;
856 	default:
857 		break;
858 	}
859 
860 	at91_write(priv, AT91_IDR, reg_idr);
861 	at91_write(priv, AT91_IER, reg_ier);
862 }
863 
864 static void at91_irq_err(struct net_device *dev)
865 {
866 	struct at91_priv *priv = netdev_priv(dev);
867 	struct sk_buff *skb;
868 	struct can_frame *cf;
869 	enum can_state new_state;
870 	u32 reg_sr;
871 
872 	reg_sr = at91_read(priv, AT91_SR);
873 
874 	/* we need to look at the unmasked reg_sr */
875 	if (unlikely(reg_sr & AT91_IRQ_BOFF))
876 		new_state = CAN_STATE_BUS_OFF;
877 	else if (unlikely(reg_sr & AT91_IRQ_ERRP))
878 		new_state = CAN_STATE_ERROR_PASSIVE;
879 	else if (unlikely(reg_sr & AT91_IRQ_WARN))
880 		new_state = CAN_STATE_ERROR_WARNING;
881 	else if (likely(reg_sr & AT91_IRQ_ERRA))
882 		new_state = CAN_STATE_ERROR_ACTIVE;
883 	else {
884 		dev_err(dev->dev.parent, "BUG! hardware in undefined state\n");
885 		return;
886 	}
887 
888 	/* state hasn't changed */
889 	if (likely(new_state == priv->can.state))
890 		return;
891 
892 	skb = alloc_can_err_skb(dev, &cf);
893 	if (unlikely(!skb))
894 		return;
895 
896 	at91_irq_err_state(dev, cf, new_state);
897 	netif_rx(skb);
898 
899 	dev->last_rx = jiffies;
900 	dev->stats.rx_packets++;
901 	dev->stats.rx_bytes += cf->can_dlc;
902 
903 	priv->can.state = new_state;
904 }
905 
906 /*
907  * interrupt handler
908  */
909 static irqreturn_t at91_irq(int irq, void *dev_id)
910 {
911 	struct net_device *dev = dev_id;
912 	struct at91_priv *priv = netdev_priv(dev);
913 	irqreturn_t handled = IRQ_NONE;
914 	u32 reg_sr, reg_imr;
915 
916 	reg_sr = at91_read(priv, AT91_SR);
917 	reg_imr = at91_read(priv, AT91_IMR);
918 
919 	/* Ignore masked interrupts */
920 	reg_sr &= reg_imr;
921 	if (!reg_sr)
922 		goto exit;
923 
924 	handled = IRQ_HANDLED;
925 
926 	/* Receive or error interrupt? -> napi */
927 	if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) {
928 		/*
929 		 * The error bits are clear on read,
930 		 * save for later use.
931 		 */
932 		priv->reg_sr = reg_sr;
933 		at91_write(priv, AT91_IDR,
934 			   AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME);
935 		napi_schedule(&priv->napi);
936 	}
937 
938 	/* Transmission complete interrupt */
939 	if (reg_sr & AT91_IRQ_MB_TX)
940 		at91_irq_tx(dev, reg_sr);
941 
942 	at91_irq_err(dev);
943 
944  exit:
945 	return handled;
946 }
947 
948 static int at91_open(struct net_device *dev)
949 {
950 	struct at91_priv *priv = netdev_priv(dev);
951 	int err;
952 
953 	clk_enable(priv->clk);
954 
955 	/* check or determine and set bittime */
956 	err = open_candev(dev);
957 	if (err)
958 		goto out;
959 
960 	/* register interrupt handler */
961 	if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
962 			dev->name, dev)) {
963 		err = -EAGAIN;
964 		goto out_close;
965 	}
966 
967 	/* start chip and queuing */
968 	at91_chip_start(dev);
969 	napi_enable(&priv->napi);
970 	netif_start_queue(dev);
971 
972 	return 0;
973 
974  out_close:
975 	close_candev(dev);
976  out:
977 	clk_disable(priv->clk);
978 
979 	return err;
980 }
981 
982 /*
983  * stop CAN bus activity
984  */
985 static int at91_close(struct net_device *dev)
986 {
987 	struct at91_priv *priv = netdev_priv(dev);
988 
989 	netif_stop_queue(dev);
990 	napi_disable(&priv->napi);
991 	at91_chip_stop(dev, CAN_STATE_STOPPED);
992 
993 	free_irq(dev->irq, dev);
994 	clk_disable(priv->clk);
995 
996 	close_candev(dev);
997 
998 	return 0;
999 }
1000 
1001 static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1002 {
1003 	switch (mode) {
1004 	case CAN_MODE_START:
1005 		at91_chip_start(dev);
1006 		netif_wake_queue(dev);
1007 		break;
1008 
1009 	default:
1010 		return -EOPNOTSUPP;
1011 	}
1012 
1013 	return 0;
1014 }
1015 
1016 static const struct net_device_ops at91_netdev_ops = {
1017 	.ndo_open	= at91_open,
1018 	.ndo_stop	= at91_close,
1019 	.ndo_start_xmit	= at91_start_xmit,
1020 };
1021 
1022 static int __init at91_can_probe(struct platform_device *pdev)
1023 {
1024 	struct net_device *dev;
1025 	struct at91_priv *priv;
1026 	struct resource *res;
1027 	struct clk *clk;
1028 	void __iomem *addr;
1029 	int err, irq;
1030 
1031 	clk = clk_get(&pdev->dev, "can_clk");
1032 	if (IS_ERR(clk)) {
1033 		dev_err(&pdev->dev, "no clock defined\n");
1034 		err = -ENODEV;
1035 		goto exit;
1036 	}
1037 
1038 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1039 	irq = platform_get_irq(pdev, 0);
1040 	if (!res || irq <= 0) {
1041 		err = -ENODEV;
1042 		goto exit_put;
1043 	}
1044 
1045 	if (!request_mem_region(res->start,
1046 				resource_size(res),
1047 				pdev->name)) {
1048 		err = -EBUSY;
1049 		goto exit_put;
1050 	}
1051 
1052 	addr = ioremap_nocache(res->start, resource_size(res));
1053 	if (!addr) {
1054 		err = -ENOMEM;
1055 		goto exit_release;
1056 	}
1057 
1058 	dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM);
1059 	if (!dev) {
1060 		err = -ENOMEM;
1061 		goto exit_iounmap;
1062 	}
1063 
1064 	dev->netdev_ops	= &at91_netdev_ops;
1065 	dev->irq = irq;
1066 	dev->flags |= IFF_ECHO;
1067 
1068 	priv = netdev_priv(dev);
1069 	priv->can.clock.freq = clk_get_rate(clk);
1070 	priv->can.bittiming_const = &at91_bittiming_const;
1071 	priv->can.do_set_bittiming = at91_set_bittiming;
1072 	priv->can.do_set_mode = at91_set_mode;
1073 	priv->reg_base = addr;
1074 	priv->dev = dev;
1075 	priv->clk = clk;
1076 	priv->pdata = pdev->dev.platform_data;
1077 
1078 	netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT);
1079 
1080 	dev_set_drvdata(&pdev->dev, dev);
1081 	SET_NETDEV_DEV(dev, &pdev->dev);
1082 
1083 	err = register_candev(dev);
1084 	if (err) {
1085 		dev_err(&pdev->dev, "registering netdev failed\n");
1086 		goto exit_free;
1087 	}
1088 
1089 	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1090 		 priv->reg_base, dev->irq);
1091 
1092 	return 0;
1093 
1094  exit_free:
1095 	free_netdev(dev);
1096  exit_iounmap:
1097 	iounmap(addr);
1098  exit_release:
1099 	release_mem_region(res->start, resource_size(res));
1100  exit_put:
1101 	clk_put(clk);
1102  exit:
1103 	return err;
1104 }
1105 
1106 static int __devexit at91_can_remove(struct platform_device *pdev)
1107 {
1108 	struct net_device *dev = platform_get_drvdata(pdev);
1109 	struct at91_priv *priv = netdev_priv(dev);
1110 	struct resource *res;
1111 
1112 	unregister_netdev(dev);
1113 
1114 	platform_set_drvdata(pdev, NULL);
1115 
1116 	free_netdev(dev);
1117 
1118 	iounmap(priv->reg_base);
1119 
1120 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121 	release_mem_region(res->start, resource_size(res));
1122 
1123 	clk_put(priv->clk);
1124 
1125 	return 0;
1126 }
1127 
1128 static struct platform_driver at91_can_driver = {
1129 	.probe		= at91_can_probe,
1130 	.remove		= __devexit_p(at91_can_remove),
1131 	.driver		= {
1132 		.name	= DRV_NAME,
1133 		.owner	= THIS_MODULE,
1134 	},
1135 };
1136 
1137 static int __init at91_can_module_init(void)
1138 {
1139 	printk(KERN_INFO "%s netdevice driver\n", DRV_NAME);
1140 	return platform_driver_register(&at91_can_driver);
1141 }
1142 
1143 static void __exit at91_can_module_exit(void)
1144 {
1145 	platform_driver_unregister(&at91_can_driver);
1146 	printk(KERN_INFO "%s: driver removed\n", DRV_NAME);
1147 }
1148 
1149 module_init(at91_can_module_init);
1150 module_exit(at91_can_module_exit);
1151 
1152 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1153 MODULE_LICENSE("GPL v2");
1154 MODULE_DESCRIPTION(DRV_NAME " CAN netdevice driver");
1155