xref: /openbmc/linux/drivers/net/can/at91_can.c (revision 9d749629) 
1 /*
2  * at91_can.c - CAN network driver for AT91 SoC CAN controller
3  *
4  * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
5  * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
6  *
7  * This software may be distributed under the terms of the GNU General
8  * Public License ("GPL") version 2 as distributed in the 'COPYING'
9  * file from the main directory of the linux kernel source.
10  *
11  *
12  * Your platform definition file should specify something like:
13  *
14  * static struct at91_can_data ek_can_data = {
15  *	transceiver_switch = sam9263ek_transceiver_switch,
16  * };
17  *
18  * at91_add_device_can(&ek_can_data);
19  *
20  */
21 
22 #include <linux/clk.h>
23 #include <linux/errno.h>
24 #include <linux/if_arp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/platform_device.h>
31 #include <linux/rtnetlink.h>
32 #include <linux/skbuff.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/types.h>
36 #include <linux/platform_data/atmel.h>
37 
38 #include <linux/can/dev.h>
39 #include <linux/can/error.h>
40 #include <linux/can/led.h>
41 
42 #define AT91_MB_MASK(i)		((1 << (i)) - 1)
43 
44 /* Common registers */
45 enum at91_reg {
46 	AT91_MR		= 0x000,
47 	AT91_IER	= 0x004,
48 	AT91_IDR	= 0x008,
49 	AT91_IMR	= 0x00C,
50 	AT91_SR		= 0x010,
51 	AT91_BR		= 0x014,
52 	AT91_TIM	= 0x018,
53 	AT91_TIMESTP	= 0x01C,
54 	AT91_ECR	= 0x020,
55 	AT91_TCR	= 0x024,
56 	AT91_ACR	= 0x028,
57 };
58 
59 /* Mailbox registers (0 <= i <= 15) */
60 #define AT91_MMR(i)		(enum at91_reg)(0x200 + ((i) * 0x20))
61 #define AT91_MAM(i)		(enum at91_reg)(0x204 + ((i) * 0x20))
62 #define AT91_MID(i)		(enum at91_reg)(0x208 + ((i) * 0x20))
63 #define AT91_MFID(i)		(enum at91_reg)(0x20C + ((i) * 0x20))
64 #define AT91_MSR(i)		(enum at91_reg)(0x210 + ((i) * 0x20))
65 #define AT91_MDL(i)		(enum at91_reg)(0x214 + ((i) * 0x20))
66 #define AT91_MDH(i)		(enum at91_reg)(0x218 + ((i) * 0x20))
67 #define AT91_MCR(i)		(enum at91_reg)(0x21C + ((i) * 0x20))
68 
69 /* Register bits */
70 #define AT91_MR_CANEN		BIT(0)
71 #define AT91_MR_LPM		BIT(1)
72 #define AT91_MR_ABM		BIT(2)
73 #define AT91_MR_OVL		BIT(3)
74 #define AT91_MR_TEOF		BIT(4)
75 #define AT91_MR_TTM		BIT(5)
76 #define AT91_MR_TIMFRZ		BIT(6)
77 #define AT91_MR_DRPT		BIT(7)
78 
79 #define AT91_SR_RBSY		BIT(29)
80 
81 #define AT91_MMR_PRIO_SHIFT	(16)
82 
83 #define AT91_MID_MIDE		BIT(29)
84 
85 #define AT91_MSR_MRTR		BIT(20)
86 #define AT91_MSR_MABT		BIT(22)
87 #define AT91_MSR_MRDY		BIT(23)
88 #define AT91_MSR_MMI		BIT(24)
89 
90 #define AT91_MCR_MRTR		BIT(20)
91 #define AT91_MCR_MTCR		BIT(23)
92 
93 /* Mailbox Modes */
94 enum at91_mb_mode {
95 	AT91_MB_MODE_DISABLED	= 0,
96 	AT91_MB_MODE_RX		= 1,
97 	AT91_MB_MODE_RX_OVRWR	= 2,
98 	AT91_MB_MODE_TX		= 3,
99 	AT91_MB_MODE_CONSUMER	= 4,
100 	AT91_MB_MODE_PRODUCER	= 5,
101 };
102 
103 /* Interrupt mask bits */
104 #define AT91_IRQ_ERRA		(1 << 16)
105 #define AT91_IRQ_WARN		(1 << 17)
106 #define AT91_IRQ_ERRP		(1 << 18)
107 #define AT91_IRQ_BOFF		(1 << 19)
108 #define AT91_IRQ_SLEEP		(1 << 20)
109 #define AT91_IRQ_WAKEUP		(1 << 21)
110 #define AT91_IRQ_TOVF		(1 << 22)
111 #define AT91_IRQ_TSTP		(1 << 23)
112 #define AT91_IRQ_CERR		(1 << 24)
113 #define AT91_IRQ_SERR		(1 << 25)
114 #define AT91_IRQ_AERR		(1 << 26)
115 #define AT91_IRQ_FERR		(1 << 27)
116 #define AT91_IRQ_BERR		(1 << 28)
117 
118 #define AT91_IRQ_ERR_ALL	(0x1fff0000)
119 #define AT91_IRQ_ERR_FRAME	(AT91_IRQ_CERR | AT91_IRQ_SERR | \
120 				 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
121 #define AT91_IRQ_ERR_LINE	(AT91_IRQ_ERRA | AT91_IRQ_WARN | \
122 				 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
123 
124 #define AT91_IRQ_ALL		(0x1fffffff)
125 
126 enum at91_devtype {
127 	AT91_DEVTYPE_SAM9263,
128 	AT91_DEVTYPE_SAM9X5,
129 };
130 
131 struct at91_devtype_data {
132 	unsigned int rx_first;
133 	unsigned int rx_split;
134 	unsigned int rx_last;
135 	unsigned int tx_shift;
136 	enum at91_devtype type;
137 };
138 
139 struct at91_priv {
140 	struct can_priv can;		/* must be the first member! */
141 	struct net_device *dev;
142 	struct napi_struct napi;
143 
144 	void __iomem *reg_base;
145 
146 	u32 reg_sr;
147 	unsigned int tx_next;
148 	unsigned int tx_echo;
149 	unsigned int rx_next;
150 	struct at91_devtype_data devtype_data;
151 
152 	struct clk *clk;
153 	struct at91_can_data *pdata;
154 
155 	canid_t mb0_id;
156 };
157 
158 static const struct at91_devtype_data at91_devtype_data[] = {
159 	[AT91_DEVTYPE_SAM9263] = {
160 		.rx_first = 1,
161 		.rx_split = 8,
162 		.rx_last = 11,
163 		.tx_shift = 2,
164 	},
165 	[AT91_DEVTYPE_SAM9X5] = {
166 		.rx_first = 0,
167 		.rx_split = 4,
168 		.rx_last = 5,
169 		.tx_shift = 1,
170 	},
171 };
172 
173 static const struct can_bittiming_const at91_bittiming_const = {
174 	.name		= KBUILD_MODNAME,
175 	.tseg1_min	= 4,
176 	.tseg1_max	= 16,
177 	.tseg2_min	= 2,
178 	.tseg2_max	= 8,
179 	.sjw_max	= 4,
180 	.brp_min 	= 2,
181 	.brp_max	= 128,
182 	.brp_inc	= 1,
183 };
184 
185 #define AT91_IS(_model) \
186 static inline int at91_is_sam##_model(const struct at91_priv *priv) \
187 { \
188 	return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
189 }
190 
191 AT91_IS(9263);
192 AT91_IS(9X5);
193 
194 static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
195 {
196 	return priv->devtype_data.rx_first;
197 }
198 
199 static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
200 {
201 	return priv->devtype_data.rx_last;
202 }
203 
204 static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
205 {
206 	return priv->devtype_data.rx_split;
207 }
208 
209 static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
210 {
211 	return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
212 }
213 
214 static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
215 {
216 	return get_mb_rx_split(priv) - 1;
217 }
218 
219 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
220 {
221 	return AT91_MB_MASK(get_mb_rx_split(priv)) &
222 		~AT91_MB_MASK(get_mb_rx_first(priv));
223 }
224 
225 static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
226 {
227 	return priv->devtype_data.tx_shift;
228 }
229 
230 static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
231 {
232 	return 1 << get_mb_tx_shift(priv);
233 }
234 
235 static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
236 {
237 	return get_mb_rx_last(priv) + 1;
238 }
239 
240 static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
241 {
242 	return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
243 }
244 
245 static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
246 {
247 	return get_mb_tx_shift(priv);
248 }
249 
250 static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
251 {
252 	return 0xf << get_mb_tx_shift(priv);
253 }
254 
255 static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
256 {
257 	return AT91_MB_MASK(get_mb_tx_shift(priv));
258 }
259 
260 static inline unsigned int get_next_mask(const struct at91_priv *priv)
261 {
262 	return get_next_mb_mask(priv) | get_next_prio_mask(priv);
263 }
264 
265 static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
266 {
267 	return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
268 		~AT91_MB_MASK(get_mb_rx_first(priv));
269 }
270 
271 static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
272 {
273 	return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
274 		~AT91_MB_MASK(get_mb_tx_first(priv));
275 }
276 
277 static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
278 {
279 	return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
280 }
281 
282 static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
283 {
284 	return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
285 }
286 
287 static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
288 {
289 	return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
290 }
291 
292 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
293 {
294 	return __raw_readl(priv->reg_base + reg);
295 }
296 
297 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
298 		u32 value)
299 {
300 	__raw_writel(value, priv->reg_base + reg);
301 }
302 
303 static inline void set_mb_mode_prio(const struct at91_priv *priv,
304 		unsigned int mb, enum at91_mb_mode mode, int prio)
305 {
306 	at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
307 }
308 
309 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
310 		enum at91_mb_mode mode)
311 {
312 	set_mb_mode_prio(priv, mb, mode, 0);
313 }
314 
315 static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
316 {
317 	u32 reg_mid;
318 
319 	if (can_id & CAN_EFF_FLAG)
320 		reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
321 	else
322 		reg_mid = (can_id & CAN_SFF_MASK) << 18;
323 
324 	return reg_mid;
325 }
326 
327 /*
328  * Swtich transceiver on or off
329  */
330 static void at91_transceiver_switch(const struct at91_priv *priv, int on)
331 {
332 	if (priv->pdata && priv->pdata->transceiver_switch)
333 		priv->pdata->transceiver_switch(on);
334 }
335 
336 static void at91_setup_mailboxes(struct net_device *dev)
337 {
338 	struct at91_priv *priv = netdev_priv(dev);
339 	unsigned int i;
340 	u32 reg_mid;
341 
342 	/*
343 	 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
344 	 * mailbox is disabled. The next 11 mailboxes are used as a
345 	 * reception FIFO. The last mailbox is configured with
346 	 * overwrite option. The overwrite flag indicates a FIFO
347 	 * overflow.
348 	 */
349 	reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
350 	for (i = 0; i < get_mb_rx_first(priv); i++) {
351 		set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
352 		at91_write(priv, AT91_MID(i), reg_mid);
353 		at91_write(priv, AT91_MCR(i), 0x0);	/* clear dlc */
354 	}
355 
356 	for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
357 		set_mb_mode(priv, i, AT91_MB_MODE_RX);
358 	set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
359 
360 	/* reset acceptance mask and id register */
361 	for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
362 		at91_write(priv, AT91_MAM(i), 0x0);
363 		at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
364 	}
365 
366 	/* The last 4 mailboxes are used for transmitting. */
367 	for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
368 		set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
369 
370 	/* Reset tx and rx helper pointers */
371 	priv->tx_next = priv->tx_echo = 0;
372 	priv->rx_next = get_mb_rx_first(priv);
373 }
374 
375 static int at91_set_bittiming(struct net_device *dev)
376 {
377 	const struct at91_priv *priv = netdev_priv(dev);
378 	const struct can_bittiming *bt = &priv->can.bittiming;
379 	u32 reg_br;
380 
381 	reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
382 		((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
383 		((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
384 		((bt->phase_seg2 - 1) << 0);
385 
386 	netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
387 
388 	at91_write(priv, AT91_BR, reg_br);
389 
390 	return 0;
391 }
392 
393 static int at91_get_berr_counter(const struct net_device *dev,
394 		struct can_berr_counter *bec)
395 {
396 	const struct at91_priv *priv = netdev_priv(dev);
397 	u32 reg_ecr = at91_read(priv, AT91_ECR);
398 
399 	bec->rxerr = reg_ecr & 0xff;
400 	bec->txerr = reg_ecr >> 16;
401 
402 	return 0;
403 }
404 
405 static void at91_chip_start(struct net_device *dev)
406 {
407 	struct at91_priv *priv = netdev_priv(dev);
408 	u32 reg_mr, reg_ier;
409 
410 	/* disable interrupts */
411 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
412 
413 	/* disable chip */
414 	reg_mr = at91_read(priv, AT91_MR);
415 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
416 
417 	at91_set_bittiming(dev);
418 	at91_setup_mailboxes(dev);
419 	at91_transceiver_switch(priv, 1);
420 
421 	/* enable chip */
422 	at91_write(priv, AT91_MR, AT91_MR_CANEN);
423 
424 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
425 
426 	/* Enable interrupts */
427 	reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
428 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
429 	at91_write(priv, AT91_IER, reg_ier);
430 }
431 
432 static void at91_chip_stop(struct net_device *dev, enum can_state state)
433 {
434 	struct at91_priv *priv = netdev_priv(dev);
435 	u32 reg_mr;
436 
437 	/* disable interrupts */
438 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
439 
440 	reg_mr = at91_read(priv, AT91_MR);
441 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
442 
443 	at91_transceiver_switch(priv, 0);
444 	priv->can.state = state;
445 }
446 
447 /*
448  * theory of operation:
449  *
450  * According to the datasheet priority 0 is the highest priority, 15
451  * is the lowest. If two mailboxes have the same priority level the
452  * message of the mailbox with the lowest number is sent first.
453  *
454  * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
455  * the next mailbox with prio 0, and so on, until all mailboxes are
456  * used. Then we start from the beginning with mailbox
457  * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
458  * prio 1. When we reach the last mailbox with prio 15, we have to
459  * stop sending, waiting for all messages to be delivered, then start
460  * again with mailbox AT91_MB_TX_FIRST prio 0.
461  *
462  * We use the priv->tx_next as counter for the next transmission
463  * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
464  * encode the mailbox number, the upper 4 bits the mailbox priority:
465  *
466  * priv->tx_next = (prio << get_next_prio_shift(priv)) |
467  *                 (mb - get_mb_tx_first(priv));
468  *
469  */
470 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
471 {
472 	struct at91_priv *priv = netdev_priv(dev);
473 	struct net_device_stats *stats = &dev->stats;
474 	struct can_frame *cf = (struct can_frame *)skb->data;
475 	unsigned int mb, prio;
476 	u32 reg_mid, reg_mcr;
477 
478 	if (can_dropped_invalid_skb(dev, skb))
479 		return NETDEV_TX_OK;
480 
481 	mb = get_tx_next_mb(priv);
482 	prio = get_tx_next_prio(priv);
483 
484 	if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
485 		netif_stop_queue(dev);
486 
487 		netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
488 		return NETDEV_TX_BUSY;
489 	}
490 	reg_mid = at91_can_id_to_reg_mid(cf->can_id);
491 	reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
492 		(cf->can_dlc << 16) | AT91_MCR_MTCR;
493 
494 	/* disable MB while writing ID (see datasheet) */
495 	set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
496 	at91_write(priv, AT91_MID(mb), reg_mid);
497 	set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
498 
499 	at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
500 	at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
501 
502 	/* This triggers transmission */
503 	at91_write(priv, AT91_MCR(mb), reg_mcr);
504 
505 	stats->tx_bytes += cf->can_dlc;
506 
507 	/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
508 	can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv));
509 
510 	/*
511 	 * we have to stop the queue and deliver all messages in case
512 	 * of a prio+mb counter wrap around. This is the case if
513 	 * tx_next buffer prio and mailbox equals 0.
514 	 *
515 	 * also stop the queue if next buffer is still in use
516 	 * (== not ready)
517 	 */
518 	priv->tx_next++;
519 	if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
520 	      AT91_MSR_MRDY) ||
521 	    (priv->tx_next & get_next_mask(priv)) == 0)
522 		netif_stop_queue(dev);
523 
524 	/* Enable interrupt for this mailbox */
525 	at91_write(priv, AT91_IER, 1 << mb);
526 
527 	return NETDEV_TX_OK;
528 }
529 
530 /**
531  * at91_activate_rx_low - activate lower rx mailboxes
532  * @priv: a91 context
533  *
534  * Reenables the lower mailboxes for reception of new CAN messages
535  */
536 static inline void at91_activate_rx_low(const struct at91_priv *priv)
537 {
538 	u32 mask = get_mb_rx_low_mask(priv);
539 	at91_write(priv, AT91_TCR, mask);
540 }
541 
542 /**
543  * at91_activate_rx_mb - reactive single rx mailbox
544  * @priv: a91 context
545  * @mb: mailbox to reactivate
546  *
547  * Reenables given mailbox for reception of new CAN messages
548  */
549 static inline void at91_activate_rx_mb(const struct at91_priv *priv,
550 		unsigned int mb)
551 {
552 	u32 mask = 1 << mb;
553 	at91_write(priv, AT91_TCR, mask);
554 }
555 
556 /**
557  * at91_rx_overflow_err - send error frame due to rx overflow
558  * @dev: net device
559  */
560 static void at91_rx_overflow_err(struct net_device *dev)
561 {
562 	struct net_device_stats *stats = &dev->stats;
563 	struct sk_buff *skb;
564 	struct can_frame *cf;
565 
566 	netdev_dbg(dev, "RX buffer overflow\n");
567 	stats->rx_over_errors++;
568 	stats->rx_errors++;
569 
570 	skb = alloc_can_err_skb(dev, &cf);
571 	if (unlikely(!skb))
572 		return;
573 
574 	cf->can_id |= CAN_ERR_CRTL;
575 	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
576 	netif_receive_skb(skb);
577 
578 	stats->rx_packets++;
579 	stats->rx_bytes += cf->can_dlc;
580 }
581 
582 /**
583  * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
584  * @dev: net device
585  * @mb: mailbox number to read from
586  * @cf: can frame where to store message
587  *
588  * Reads a CAN message from the given mailbox and stores data into
589  * given can frame. "mb" and "cf" must be valid.
590  */
591 static void at91_read_mb(struct net_device *dev, unsigned int mb,
592 		struct can_frame *cf)
593 {
594 	const struct at91_priv *priv = netdev_priv(dev);
595 	u32 reg_msr, reg_mid;
596 
597 	reg_mid = at91_read(priv, AT91_MID(mb));
598 	if (reg_mid & AT91_MID_MIDE)
599 		cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
600 	else
601 		cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
602 
603 	reg_msr = at91_read(priv, AT91_MSR(mb));
604 	cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
605 
606 	if (reg_msr & AT91_MSR_MRTR)
607 		cf->can_id |= CAN_RTR_FLAG;
608 	else {
609 		*(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
610 		*(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
611 	}
612 
613 	/* allow RX of extended frames */
614 	at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
615 
616 	if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
617 		at91_rx_overflow_err(dev);
618 }
619 
620 /**
621  * at91_read_msg - read CAN message from mailbox
622  * @dev: net device
623  * @mb: mail box to read from
624  *
625  * Reads a CAN message from given mailbox, and put into linux network
626  * RX queue, does all housekeeping chores (stats, ...)
627  */
628 static void at91_read_msg(struct net_device *dev, unsigned int mb)
629 {
630 	struct net_device_stats *stats = &dev->stats;
631 	struct can_frame *cf;
632 	struct sk_buff *skb;
633 
634 	skb = alloc_can_skb(dev, &cf);
635 	if (unlikely(!skb)) {
636 		stats->rx_dropped++;
637 		return;
638 	}
639 
640 	at91_read_mb(dev, mb, cf);
641 	netif_receive_skb(skb);
642 
643 	stats->rx_packets++;
644 	stats->rx_bytes += cf->can_dlc;
645 
646 	can_led_event(dev, CAN_LED_EVENT_RX);
647 }
648 
649 /**
650  * at91_poll_rx - read multiple CAN messages from mailboxes
651  * @dev: net device
652  * @quota: max number of pkgs we're allowed to receive
653  *
654  * Theory of Operation:
655  *
656  * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
657  * on the chip are reserved for RX. We split them into 2 groups. The
658  * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
659  *
660  * Like it or not, but the chip always saves a received CAN message
661  * into the first free mailbox it finds (starting with the
662  * lowest). This makes it very difficult to read the messages in the
663  * right order from the chip. This is how we work around that problem:
664  *
665  * The first message goes into mb nr. 1 and issues an interrupt. All
666  * rx ints are disabled in the interrupt handler and a napi poll is
667  * scheduled. We read the mailbox, but do _not_ reenable the mb (to
668  * receive another message).
669  *
670  *    lower mbxs      upper
671  *     ____^______    __^__
672  *    /           \  /     \
673  * +-+-+-+-+-+-+-+-++-+-+-+-+
674  * | |x|x|x|x|x|x|x|| | | | |
675  * +-+-+-+-+-+-+-+-++-+-+-+-+
676  *  0 0 0 0 0 0  0 0 0 0 1 1  \ mail
677  *  0 1 2 3 4 5  6 7 8 9 0 1  / box
678  *  ^
679  *  |
680  *   \
681  *     unused, due to chip bug
682  *
683  * The variable priv->rx_next points to the next mailbox to read a
684  * message from. As long we're in the lower mailboxes we just read the
685  * mailbox but not reenable it.
686  *
687  * With completion of the last of the lower mailboxes, we reenable the
688  * whole first group, but continue to look for filled mailboxes in the
689  * upper mailboxes. Imagine the second group like overflow mailboxes,
690  * which takes CAN messages if the lower goup is full. While in the
691  * upper group we reenable the mailbox right after reading it. Giving
692  * the chip more room to store messages.
693  *
694  * After finishing we look again in the lower group if we've still
695  * quota.
696  *
697  */
698 static int at91_poll_rx(struct net_device *dev, int quota)
699 {
700 	struct at91_priv *priv = netdev_priv(dev);
701 	u32 reg_sr = at91_read(priv, AT91_SR);
702 	const unsigned long *addr = (unsigned long *)&reg_sr;
703 	unsigned int mb;
704 	int received = 0;
705 
706 	if (priv->rx_next > get_mb_rx_low_last(priv) &&
707 	    reg_sr & get_mb_rx_low_mask(priv))
708 		netdev_info(dev,
709 			"order of incoming frames cannot be guaranteed\n");
710 
711  again:
712 	for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
713 	     mb < get_mb_tx_first(priv) && quota > 0;
714 	     reg_sr = at91_read(priv, AT91_SR),
715 	     mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
716 		at91_read_msg(dev, mb);
717 
718 		/* reactivate mailboxes */
719 		if (mb == get_mb_rx_low_last(priv))
720 			/* all lower mailboxed, if just finished it */
721 			at91_activate_rx_low(priv);
722 		else if (mb > get_mb_rx_low_last(priv))
723 			/* only the mailbox we read */
724 			at91_activate_rx_mb(priv, mb);
725 
726 		received++;
727 		quota--;
728 	}
729 
730 	/* upper group completed, look again in lower */
731 	if (priv->rx_next > get_mb_rx_low_last(priv) &&
732 	    quota > 0 && mb > get_mb_rx_last(priv)) {
733 		priv->rx_next = get_mb_rx_first(priv);
734 		goto again;
735 	}
736 
737 	return received;
738 }
739 
740 static void at91_poll_err_frame(struct net_device *dev,
741 		struct can_frame *cf, u32 reg_sr)
742 {
743 	struct at91_priv *priv = netdev_priv(dev);
744 
745 	/* CRC error */
746 	if (reg_sr & AT91_IRQ_CERR) {
747 		netdev_dbg(dev, "CERR irq\n");
748 		dev->stats.rx_errors++;
749 		priv->can.can_stats.bus_error++;
750 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
751 	}
752 
753 	/* Stuffing Error */
754 	if (reg_sr & AT91_IRQ_SERR) {
755 		netdev_dbg(dev, "SERR irq\n");
756 		dev->stats.rx_errors++;
757 		priv->can.can_stats.bus_error++;
758 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
759 		cf->data[2] |= CAN_ERR_PROT_STUFF;
760 	}
761 
762 	/* Acknowledgement Error */
763 	if (reg_sr & AT91_IRQ_AERR) {
764 		netdev_dbg(dev, "AERR irq\n");
765 		dev->stats.tx_errors++;
766 		cf->can_id |= CAN_ERR_ACK;
767 	}
768 
769 	/* Form error */
770 	if (reg_sr & AT91_IRQ_FERR) {
771 		netdev_dbg(dev, "FERR irq\n");
772 		dev->stats.rx_errors++;
773 		priv->can.can_stats.bus_error++;
774 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
775 		cf->data[2] |= CAN_ERR_PROT_FORM;
776 	}
777 
778 	/* Bit Error */
779 	if (reg_sr & AT91_IRQ_BERR) {
780 		netdev_dbg(dev, "BERR irq\n");
781 		dev->stats.tx_errors++;
782 		priv->can.can_stats.bus_error++;
783 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
784 		cf->data[2] |= CAN_ERR_PROT_BIT;
785 	}
786 }
787 
788 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
789 {
790 	struct sk_buff *skb;
791 	struct can_frame *cf;
792 
793 	if (quota == 0)
794 		return 0;
795 
796 	skb = alloc_can_err_skb(dev, &cf);
797 	if (unlikely(!skb))
798 		return 0;
799 
800 	at91_poll_err_frame(dev, cf, reg_sr);
801 	netif_receive_skb(skb);
802 
803 	dev->stats.rx_packets++;
804 	dev->stats.rx_bytes += cf->can_dlc;
805 
806 	return 1;
807 }
808 
809 static int at91_poll(struct napi_struct *napi, int quota)
810 {
811 	struct net_device *dev = napi->dev;
812 	const struct at91_priv *priv = netdev_priv(dev);
813 	u32 reg_sr = at91_read(priv, AT91_SR);
814 	int work_done = 0;
815 
816 	if (reg_sr & get_irq_mb_rx(priv))
817 		work_done += at91_poll_rx(dev, quota - work_done);
818 
819 	/*
820 	 * The error bits are clear on read,
821 	 * so use saved value from irq handler.
822 	 */
823 	reg_sr |= priv->reg_sr;
824 	if (reg_sr & AT91_IRQ_ERR_FRAME)
825 		work_done += at91_poll_err(dev, quota - work_done, reg_sr);
826 
827 	if (work_done < quota) {
828 		/* enable IRQs for frame errors and all mailboxes >= rx_next */
829 		u32 reg_ier = AT91_IRQ_ERR_FRAME;
830 		reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
831 
832 		napi_complete(napi);
833 		at91_write(priv, AT91_IER, reg_ier);
834 	}
835 
836 	return work_done;
837 }
838 
839 /*
840  * theory of operation:
841  *
842  * priv->tx_echo holds the number of the oldest can_frame put for
843  * transmission into the hardware, but not yet ACKed by the CAN tx
844  * complete IRQ.
845  *
846  * We iterate from priv->tx_echo to priv->tx_next and check if the
847  * packet has been transmitted, echo it back to the CAN framework. If
848  * we discover a not yet transmitted package, stop looking for more.
849  *
850  */
851 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
852 {
853 	struct at91_priv *priv = netdev_priv(dev);
854 	u32 reg_msr;
855 	unsigned int mb;
856 
857 	/* masking of reg_sr not needed, already done by at91_irq */
858 
859 	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
860 		mb = get_tx_echo_mb(priv);
861 
862 		/* no event in mailbox? */
863 		if (!(reg_sr & (1 << mb)))
864 			break;
865 
866 		/* Disable irq for this TX mailbox */
867 		at91_write(priv, AT91_IDR, 1 << mb);
868 
869 		/*
870 		 * only echo if mailbox signals us a transfer
871 		 * complete (MSR_MRDY). Otherwise it's a tansfer
872 		 * abort. "can_bus_off()" takes care about the skbs
873 		 * parked in the echo queue.
874 		 */
875 		reg_msr = at91_read(priv, AT91_MSR(mb));
876 		if (likely(reg_msr & AT91_MSR_MRDY &&
877 			   ~reg_msr & AT91_MSR_MABT)) {
878 			/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
879 			can_get_echo_skb(dev, mb - get_mb_tx_first(priv));
880 			dev->stats.tx_packets++;
881 			can_led_event(dev, CAN_LED_EVENT_TX);
882 		}
883 	}
884 
885 	/*
886 	 * restart queue if we don't have a wrap around but restart if
887 	 * we get a TX int for the last can frame directly before a
888 	 * wrap around.
889 	 */
890 	if ((priv->tx_next & get_next_mask(priv)) != 0 ||
891 	    (priv->tx_echo & get_next_mask(priv)) == 0)
892 		netif_wake_queue(dev);
893 }
894 
895 static void at91_irq_err_state(struct net_device *dev,
896 		struct can_frame *cf, enum can_state new_state)
897 {
898 	struct at91_priv *priv = netdev_priv(dev);
899 	u32 reg_idr = 0, reg_ier = 0;
900 	struct can_berr_counter bec;
901 
902 	at91_get_berr_counter(dev, &bec);
903 
904 	switch (priv->can.state) {
905 	case CAN_STATE_ERROR_ACTIVE:
906 		/*
907 		 * from: ERROR_ACTIVE
908 		 * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
909 		 * =>  : there was a warning int
910 		 */
911 		if (new_state >= CAN_STATE_ERROR_WARNING &&
912 		    new_state <= CAN_STATE_BUS_OFF) {
913 			netdev_dbg(dev, "Error Warning IRQ\n");
914 			priv->can.can_stats.error_warning++;
915 
916 			cf->can_id |= CAN_ERR_CRTL;
917 			cf->data[1] = (bec.txerr > bec.rxerr) ?
918 				CAN_ERR_CRTL_TX_WARNING :
919 				CAN_ERR_CRTL_RX_WARNING;
920 		}
921 	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
922 		/*
923 		 * from: ERROR_ACTIVE, ERROR_WARNING
924 		 * to  : ERROR_PASSIVE, BUS_OFF
925 		 * =>  : error passive int
926 		 */
927 		if (new_state >= CAN_STATE_ERROR_PASSIVE &&
928 		    new_state <= CAN_STATE_BUS_OFF) {
929 			netdev_dbg(dev, "Error Passive IRQ\n");
930 			priv->can.can_stats.error_passive++;
931 
932 			cf->can_id |= CAN_ERR_CRTL;
933 			cf->data[1] = (bec.txerr > bec.rxerr) ?
934 				CAN_ERR_CRTL_TX_PASSIVE :
935 				CAN_ERR_CRTL_RX_PASSIVE;
936 		}
937 		break;
938 	case CAN_STATE_BUS_OFF:
939 		/*
940 		 * from: BUS_OFF
941 		 * to  : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
942 		 */
943 		if (new_state <= CAN_STATE_ERROR_PASSIVE) {
944 			cf->can_id |= CAN_ERR_RESTARTED;
945 
946 			netdev_dbg(dev, "restarted\n");
947 			priv->can.can_stats.restarts++;
948 
949 			netif_carrier_on(dev);
950 			netif_wake_queue(dev);
951 		}
952 		break;
953 	default:
954 		break;
955 	}
956 
957 
958 	/* process state changes depending on the new state */
959 	switch (new_state) {
960 	case CAN_STATE_ERROR_ACTIVE:
961 		/*
962 		 * actually we want to enable AT91_IRQ_WARN here, but
963 		 * it screws up the system under certain
964 		 * circumstances. so just enable AT91_IRQ_ERRP, thus
965 		 * the "fallthrough"
966 		 */
967 		netdev_dbg(dev, "Error Active\n");
968 		cf->can_id |= CAN_ERR_PROT;
969 		cf->data[2] = CAN_ERR_PROT_ACTIVE;
970 	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
971 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
972 		reg_ier = AT91_IRQ_ERRP;
973 		break;
974 	case CAN_STATE_ERROR_PASSIVE:
975 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
976 		reg_ier = AT91_IRQ_BOFF;
977 		break;
978 	case CAN_STATE_BUS_OFF:
979 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
980 			AT91_IRQ_WARN | AT91_IRQ_BOFF;
981 		reg_ier = 0;
982 
983 		cf->can_id |= CAN_ERR_BUSOFF;
984 
985 		netdev_dbg(dev, "bus-off\n");
986 		netif_carrier_off(dev);
987 		priv->can.can_stats.bus_off++;
988 
989 		/* turn off chip, if restart is disabled */
990 		if (!priv->can.restart_ms) {
991 			at91_chip_stop(dev, CAN_STATE_BUS_OFF);
992 			return;
993 		}
994 		break;
995 	default:
996 		break;
997 	}
998 
999 	at91_write(priv, AT91_IDR, reg_idr);
1000 	at91_write(priv, AT91_IER, reg_ier);
1001 }
1002 
1003 static int at91_get_state_by_bec(const struct net_device *dev,
1004 		enum can_state *state)
1005 {
1006 	struct can_berr_counter bec;
1007 	int err;
1008 
1009 	err = at91_get_berr_counter(dev, &bec);
1010 	if (err)
1011 		return err;
1012 
1013 	if (bec.txerr < 96 && bec.rxerr < 96)
1014 		*state = CAN_STATE_ERROR_ACTIVE;
1015 	else if (bec.txerr < 128 && bec.rxerr < 128)
1016 		*state = CAN_STATE_ERROR_WARNING;
1017 	else if (bec.txerr < 256 && bec.rxerr < 256)
1018 		*state = CAN_STATE_ERROR_PASSIVE;
1019 	else
1020 		*state = CAN_STATE_BUS_OFF;
1021 
1022 	return 0;
1023 }
1024 
1025 
1026 static void at91_irq_err(struct net_device *dev)
1027 {
1028 	struct at91_priv *priv = netdev_priv(dev);
1029 	struct sk_buff *skb;
1030 	struct can_frame *cf;
1031 	enum can_state new_state;
1032 	u32 reg_sr;
1033 	int err;
1034 
1035 	if (at91_is_sam9263(priv)) {
1036 		reg_sr = at91_read(priv, AT91_SR);
1037 
1038 		/* we need to look at the unmasked reg_sr */
1039 		if (unlikely(reg_sr & AT91_IRQ_BOFF))
1040 			new_state = CAN_STATE_BUS_OFF;
1041 		else if (unlikely(reg_sr & AT91_IRQ_ERRP))
1042 			new_state = CAN_STATE_ERROR_PASSIVE;
1043 		else if (unlikely(reg_sr & AT91_IRQ_WARN))
1044 			new_state = CAN_STATE_ERROR_WARNING;
1045 		else if (likely(reg_sr & AT91_IRQ_ERRA))
1046 			new_state = CAN_STATE_ERROR_ACTIVE;
1047 		else {
1048 			netdev_err(dev, "BUG! hardware in undefined state\n");
1049 			return;
1050 		}
1051 	} else {
1052 		err = at91_get_state_by_bec(dev, &new_state);
1053 		if (err)
1054 			return;
1055 	}
1056 
1057 	/* state hasn't changed */
1058 	if (likely(new_state == priv->can.state))
1059 		return;
1060 
1061 	skb = alloc_can_err_skb(dev, &cf);
1062 	if (unlikely(!skb))
1063 		return;
1064 
1065 	at91_irq_err_state(dev, cf, new_state);
1066 	netif_rx(skb);
1067 
1068 	dev->stats.rx_packets++;
1069 	dev->stats.rx_bytes += cf->can_dlc;
1070 
1071 	priv->can.state = new_state;
1072 }
1073 
1074 /*
1075  * interrupt handler
1076  */
1077 static irqreturn_t at91_irq(int irq, void *dev_id)
1078 {
1079 	struct net_device *dev = dev_id;
1080 	struct at91_priv *priv = netdev_priv(dev);
1081 	irqreturn_t handled = IRQ_NONE;
1082 	u32 reg_sr, reg_imr;
1083 
1084 	reg_sr = at91_read(priv, AT91_SR);
1085 	reg_imr = at91_read(priv, AT91_IMR);
1086 
1087 	/* Ignore masked interrupts */
1088 	reg_sr &= reg_imr;
1089 	if (!reg_sr)
1090 		goto exit;
1091 
1092 	handled = IRQ_HANDLED;
1093 
1094 	/* Receive or error interrupt? -> napi */
1095 	if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
1096 		/*
1097 		 * The error bits are clear on read,
1098 		 * save for later use.
1099 		 */
1100 		priv->reg_sr = reg_sr;
1101 		at91_write(priv, AT91_IDR,
1102 			   get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
1103 		napi_schedule(&priv->napi);
1104 	}
1105 
1106 	/* Transmission complete interrupt */
1107 	if (reg_sr & get_irq_mb_tx(priv))
1108 		at91_irq_tx(dev, reg_sr);
1109 
1110 	at91_irq_err(dev);
1111 
1112  exit:
1113 	return handled;
1114 }
1115 
1116 static int at91_open(struct net_device *dev)
1117 {
1118 	struct at91_priv *priv = netdev_priv(dev);
1119 	int err;
1120 
1121 	clk_enable(priv->clk);
1122 
1123 	/* check or determine and set bittime */
1124 	err = open_candev(dev);
1125 	if (err)
1126 		goto out;
1127 
1128 	/* register interrupt handler */
1129 	if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
1130 			dev->name, dev)) {
1131 		err = -EAGAIN;
1132 		goto out_close;
1133 	}
1134 
1135 	can_led_event(dev, CAN_LED_EVENT_OPEN);
1136 
1137 	/* start chip and queuing */
1138 	at91_chip_start(dev);
1139 	napi_enable(&priv->napi);
1140 	netif_start_queue(dev);
1141 
1142 	return 0;
1143 
1144  out_close:
1145 	close_candev(dev);
1146  out:
1147 	clk_disable(priv->clk);
1148 
1149 	return err;
1150 }
1151 
1152 /*
1153  * stop CAN bus activity
1154  */
1155 static int at91_close(struct net_device *dev)
1156 {
1157 	struct at91_priv *priv = netdev_priv(dev);
1158 
1159 	netif_stop_queue(dev);
1160 	napi_disable(&priv->napi);
1161 	at91_chip_stop(dev, CAN_STATE_STOPPED);
1162 
1163 	free_irq(dev->irq, dev);
1164 	clk_disable(priv->clk);
1165 
1166 	close_candev(dev);
1167 
1168 	can_led_event(dev, CAN_LED_EVENT_STOP);
1169 
1170 	return 0;
1171 }
1172 
1173 static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1174 {
1175 	switch (mode) {
1176 	case CAN_MODE_START:
1177 		at91_chip_start(dev);
1178 		netif_wake_queue(dev);
1179 		break;
1180 
1181 	default:
1182 		return -EOPNOTSUPP;
1183 	}
1184 
1185 	return 0;
1186 }
1187 
1188 static const struct net_device_ops at91_netdev_ops = {
1189 	.ndo_open	= at91_open,
1190 	.ndo_stop	= at91_close,
1191 	.ndo_start_xmit	= at91_start_xmit,
1192 };
1193 
1194 static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
1195 		struct device_attribute *attr, char *buf)
1196 {
1197 	struct at91_priv *priv = netdev_priv(to_net_dev(dev));
1198 
1199 	if (priv->mb0_id & CAN_EFF_FLAG)
1200 		return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
1201 	else
1202 		return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
1203 }
1204 
1205 static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
1206 		struct device_attribute *attr, const char *buf, size_t count)
1207 {
1208 	struct net_device *ndev = to_net_dev(dev);
1209 	struct at91_priv *priv = netdev_priv(ndev);
1210 	unsigned long can_id;
1211 	ssize_t ret;
1212 	int err;
1213 
1214 	rtnl_lock();
1215 
1216 	if (ndev->flags & IFF_UP) {
1217 		ret = -EBUSY;
1218 		goto out;
1219 	}
1220 
1221 	err = strict_strtoul(buf, 0, &can_id);
1222 	if (err) {
1223 		ret = err;
1224 		goto out;
1225 	}
1226 
1227 	if (can_id & CAN_EFF_FLAG)
1228 		can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
1229 	else
1230 		can_id &= CAN_SFF_MASK;
1231 
1232 	priv->mb0_id = can_id;
1233 	ret = count;
1234 
1235  out:
1236 	rtnl_unlock();
1237 	return ret;
1238 }
1239 
1240 static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO,
1241 	at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
1242 
1243 static struct attribute *at91_sysfs_attrs[] = {
1244 	&dev_attr_mb0_id.attr,
1245 	NULL,
1246 };
1247 
1248 static struct attribute_group at91_sysfs_attr_group = {
1249 	.attrs = at91_sysfs_attrs,
1250 };
1251 
1252 static int at91_can_probe(struct platform_device *pdev)
1253 {
1254 	const struct at91_devtype_data *devtype_data;
1255 	enum at91_devtype devtype;
1256 	struct net_device *dev;
1257 	struct at91_priv *priv;
1258 	struct resource *res;
1259 	struct clk *clk;
1260 	void __iomem *addr;
1261 	int err, irq;
1262 
1263 	devtype = pdev->id_entry->driver_data;
1264 	devtype_data = &at91_devtype_data[devtype];
1265 
1266 	clk = clk_get(&pdev->dev, "can_clk");
1267 	if (IS_ERR(clk)) {
1268 		dev_err(&pdev->dev, "no clock defined\n");
1269 		err = -ENODEV;
1270 		goto exit;
1271 	}
1272 
1273 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1274 	irq = platform_get_irq(pdev, 0);
1275 	if (!res || irq <= 0) {
1276 		err = -ENODEV;
1277 		goto exit_put;
1278 	}
1279 
1280 	if (!request_mem_region(res->start,
1281 				resource_size(res),
1282 				pdev->name)) {
1283 		err = -EBUSY;
1284 		goto exit_put;
1285 	}
1286 
1287 	addr = ioremap_nocache(res->start, resource_size(res));
1288 	if (!addr) {
1289 		err = -ENOMEM;
1290 		goto exit_release;
1291 	}
1292 
1293 	dev = alloc_candev(sizeof(struct at91_priv),
1294 			   1 << devtype_data->tx_shift);
1295 	if (!dev) {
1296 		err = -ENOMEM;
1297 		goto exit_iounmap;
1298 	}
1299 
1300 	dev->netdev_ops	= &at91_netdev_ops;
1301 	dev->irq = irq;
1302 	dev->flags |= IFF_ECHO;
1303 
1304 	priv = netdev_priv(dev);
1305 	priv->can.clock.freq = clk_get_rate(clk);
1306 	priv->can.bittiming_const = &at91_bittiming_const;
1307 	priv->can.do_set_mode = at91_set_mode;
1308 	priv->can.do_get_berr_counter = at91_get_berr_counter;
1309 	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
1310 	priv->dev = dev;
1311 	priv->reg_base = addr;
1312 	priv->devtype_data = *devtype_data;
1313 	priv->devtype_data.type = devtype;
1314 	priv->clk = clk;
1315 	priv->pdata = pdev->dev.platform_data;
1316 	priv->mb0_id = 0x7ff;
1317 
1318 	netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
1319 
1320 	if (at91_is_sam9263(priv))
1321 		dev->sysfs_groups[0] = &at91_sysfs_attr_group;
1322 
1323 	dev_set_drvdata(&pdev->dev, dev);
1324 	SET_NETDEV_DEV(dev, &pdev->dev);
1325 
1326 	err = register_candev(dev);
1327 	if (err) {
1328 		dev_err(&pdev->dev, "registering netdev failed\n");
1329 		goto exit_free;
1330 	}
1331 
1332 	devm_can_led_init(dev);
1333 
1334 	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1335 		 priv->reg_base, dev->irq);
1336 
1337 	return 0;
1338 
1339  exit_free:
1340 	free_candev(dev);
1341  exit_iounmap:
1342 	iounmap(addr);
1343  exit_release:
1344 	release_mem_region(res->start, resource_size(res));
1345  exit_put:
1346 	clk_put(clk);
1347  exit:
1348 	return err;
1349 }
1350 
1351 static int at91_can_remove(struct platform_device *pdev)
1352 {
1353 	struct net_device *dev = platform_get_drvdata(pdev);
1354 	struct at91_priv *priv = netdev_priv(dev);
1355 	struct resource *res;
1356 
1357 	unregister_netdev(dev);
1358 
1359 	platform_set_drvdata(pdev, NULL);
1360 
1361 	iounmap(priv->reg_base);
1362 
1363 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1364 	release_mem_region(res->start, resource_size(res));
1365 
1366 	clk_put(priv->clk);
1367 
1368 	free_candev(dev);
1369 
1370 	return 0;
1371 }
1372 
1373 static const struct platform_device_id at91_can_id_table[] = {
1374 	{
1375 		.name = "at91_can",
1376 		.driver_data = AT91_DEVTYPE_SAM9263,
1377 	}, {
1378 		.name = "at91sam9x5_can",
1379 		.driver_data = AT91_DEVTYPE_SAM9X5,
1380 	}, {
1381 		/* sentinel */
1382 	}
1383 };
1384 MODULE_DEVICE_TABLE(platform, at91_can_id_table);
1385 
1386 static struct platform_driver at91_can_driver = {
1387 	.probe = at91_can_probe,
1388 	.remove = at91_can_remove,
1389 	.driver = {
1390 		.name = KBUILD_MODNAME,
1391 		.owner = THIS_MODULE,
1392 	},
1393 	.id_table = at91_can_id_table,
1394 };
1395 
1396 module_platform_driver(at91_can_driver);
1397 
1398 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1399 MODULE_LICENSE("GPL v2");
1400 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");
1401