xref: /openbmc/linux/drivers/net/can/at91_can.c (revision 37be287c) 
1 /*
2  * at91_can.c - CAN network driver for AT91 SoC CAN controller
3  *
4  * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
5  * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
6  *
7  * This software may be distributed under the terms of the GNU General
8  * Public License ("GPL") version 2 as distributed in the 'COPYING'
9  * file from the main directory of the linux kernel source.
10  *
11  *
12  * Your platform definition file should specify something like:
13  *
14  * static struct at91_can_data ek_can_data = {
15  *	transceiver_switch = sam9263ek_transceiver_switch,
16  * };
17  *
18  * at91_add_device_can(&ek_can_data);
19  *
20  */
21 
22 #include <linux/clk.h>
23 #include <linux/errno.h>
24 #include <linux/if_arp.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/rtnetlink.h>
32 #include <linux/skbuff.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/types.h>
36 #include <linux/platform_data/atmel.h>
37 
38 #include <linux/can/dev.h>
39 #include <linux/can/error.h>
40 #include <linux/can/led.h>
41 
42 #define AT91_MB_MASK(i)		((1 << (i)) - 1)
43 
44 /* Common registers */
45 enum at91_reg {
46 	AT91_MR		= 0x000,
47 	AT91_IER	= 0x004,
48 	AT91_IDR	= 0x008,
49 	AT91_IMR	= 0x00C,
50 	AT91_SR		= 0x010,
51 	AT91_BR		= 0x014,
52 	AT91_TIM	= 0x018,
53 	AT91_TIMESTP	= 0x01C,
54 	AT91_ECR	= 0x020,
55 	AT91_TCR	= 0x024,
56 	AT91_ACR	= 0x028,
57 };
58 
59 /* Mailbox registers (0 <= i <= 15) */
60 #define AT91_MMR(i)		(enum at91_reg)(0x200 + ((i) * 0x20))
61 #define AT91_MAM(i)		(enum at91_reg)(0x204 + ((i) * 0x20))
62 #define AT91_MID(i)		(enum at91_reg)(0x208 + ((i) * 0x20))
63 #define AT91_MFID(i)		(enum at91_reg)(0x20C + ((i) * 0x20))
64 #define AT91_MSR(i)		(enum at91_reg)(0x210 + ((i) * 0x20))
65 #define AT91_MDL(i)		(enum at91_reg)(0x214 + ((i) * 0x20))
66 #define AT91_MDH(i)		(enum at91_reg)(0x218 + ((i) * 0x20))
67 #define AT91_MCR(i)		(enum at91_reg)(0x21C + ((i) * 0x20))
68 
69 /* Register bits */
70 #define AT91_MR_CANEN		BIT(0)
71 #define AT91_MR_LPM		BIT(1)
72 #define AT91_MR_ABM		BIT(2)
73 #define AT91_MR_OVL		BIT(3)
74 #define AT91_MR_TEOF		BIT(4)
75 #define AT91_MR_TTM		BIT(5)
76 #define AT91_MR_TIMFRZ		BIT(6)
77 #define AT91_MR_DRPT		BIT(7)
78 
79 #define AT91_SR_RBSY		BIT(29)
80 
81 #define AT91_MMR_PRIO_SHIFT	(16)
82 
83 #define AT91_MID_MIDE		BIT(29)
84 
85 #define AT91_MSR_MRTR		BIT(20)
86 #define AT91_MSR_MABT		BIT(22)
87 #define AT91_MSR_MRDY		BIT(23)
88 #define AT91_MSR_MMI		BIT(24)
89 
90 #define AT91_MCR_MRTR		BIT(20)
91 #define AT91_MCR_MTCR		BIT(23)
92 
93 /* Mailbox Modes */
94 enum at91_mb_mode {
95 	AT91_MB_MODE_DISABLED	= 0,
96 	AT91_MB_MODE_RX		= 1,
97 	AT91_MB_MODE_RX_OVRWR	= 2,
98 	AT91_MB_MODE_TX		= 3,
99 	AT91_MB_MODE_CONSUMER	= 4,
100 	AT91_MB_MODE_PRODUCER	= 5,
101 };
102 
103 /* Interrupt mask bits */
104 #define AT91_IRQ_ERRA		(1 << 16)
105 #define AT91_IRQ_WARN		(1 << 17)
106 #define AT91_IRQ_ERRP		(1 << 18)
107 #define AT91_IRQ_BOFF		(1 << 19)
108 #define AT91_IRQ_SLEEP		(1 << 20)
109 #define AT91_IRQ_WAKEUP		(1 << 21)
110 #define AT91_IRQ_TOVF		(1 << 22)
111 #define AT91_IRQ_TSTP		(1 << 23)
112 #define AT91_IRQ_CERR		(1 << 24)
113 #define AT91_IRQ_SERR		(1 << 25)
114 #define AT91_IRQ_AERR		(1 << 26)
115 #define AT91_IRQ_FERR		(1 << 27)
116 #define AT91_IRQ_BERR		(1 << 28)
117 
118 #define AT91_IRQ_ERR_ALL	(0x1fff0000)
119 #define AT91_IRQ_ERR_FRAME	(AT91_IRQ_CERR | AT91_IRQ_SERR | \
120 				 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
121 #define AT91_IRQ_ERR_LINE	(AT91_IRQ_ERRA | AT91_IRQ_WARN | \
122 				 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
123 
124 #define AT91_IRQ_ALL		(0x1fffffff)
125 
126 enum at91_devtype {
127 	AT91_DEVTYPE_SAM9263,
128 	AT91_DEVTYPE_SAM9X5,
129 };
130 
131 struct at91_devtype_data {
132 	unsigned int rx_first;
133 	unsigned int rx_split;
134 	unsigned int rx_last;
135 	unsigned int tx_shift;
136 	enum at91_devtype type;
137 };
138 
139 struct at91_priv {
140 	struct can_priv can;		/* must be the first member! */
141 	struct net_device *dev;
142 	struct napi_struct napi;
143 
144 	void __iomem *reg_base;
145 
146 	u32 reg_sr;
147 	unsigned int tx_next;
148 	unsigned int tx_echo;
149 	unsigned int rx_next;
150 	struct at91_devtype_data devtype_data;
151 
152 	struct clk *clk;
153 	struct at91_can_data *pdata;
154 
155 	canid_t mb0_id;
156 };
157 
158 static const struct at91_devtype_data at91_at91sam9263_data = {
159 	.rx_first = 1,
160 	.rx_split = 8,
161 	.rx_last = 11,
162 	.tx_shift = 2,
163 	.type = AT91_DEVTYPE_SAM9263,
164 };
165 
166 static const struct at91_devtype_data at91_at91sam9x5_data = {
167 	.rx_first = 0,
168 	.rx_split = 4,
169 	.rx_last = 5,
170 	.tx_shift = 1,
171 	.type = AT91_DEVTYPE_SAM9X5,
172 };
173 
174 static const struct can_bittiming_const at91_bittiming_const = {
175 	.name		= KBUILD_MODNAME,
176 	.tseg1_min	= 4,
177 	.tseg1_max	= 16,
178 	.tseg2_min	= 2,
179 	.tseg2_max	= 8,
180 	.sjw_max	= 4,
181 	.brp_min 	= 2,
182 	.brp_max	= 128,
183 	.brp_inc	= 1,
184 };
185 
186 #define AT91_IS(_model) \
187 static inline int at91_is_sam##_model(const struct at91_priv *priv) \
188 { \
189 	return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
190 }
191 
192 AT91_IS(9263);
193 AT91_IS(9X5);
194 
195 static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
196 {
197 	return priv->devtype_data.rx_first;
198 }
199 
200 static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
201 {
202 	return priv->devtype_data.rx_last;
203 }
204 
205 static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
206 {
207 	return priv->devtype_data.rx_split;
208 }
209 
210 static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
211 {
212 	return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
213 }
214 
215 static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
216 {
217 	return get_mb_rx_split(priv) - 1;
218 }
219 
220 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
221 {
222 	return AT91_MB_MASK(get_mb_rx_split(priv)) &
223 		~AT91_MB_MASK(get_mb_rx_first(priv));
224 }
225 
226 static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
227 {
228 	return priv->devtype_data.tx_shift;
229 }
230 
231 static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
232 {
233 	return 1 << get_mb_tx_shift(priv);
234 }
235 
236 static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
237 {
238 	return get_mb_rx_last(priv) + 1;
239 }
240 
241 static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
242 {
243 	return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
244 }
245 
246 static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
247 {
248 	return get_mb_tx_shift(priv);
249 }
250 
251 static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
252 {
253 	return 0xf << get_mb_tx_shift(priv);
254 }
255 
256 static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
257 {
258 	return AT91_MB_MASK(get_mb_tx_shift(priv));
259 }
260 
261 static inline unsigned int get_next_mask(const struct at91_priv *priv)
262 {
263 	return get_next_mb_mask(priv) | get_next_prio_mask(priv);
264 }
265 
266 static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
267 {
268 	return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
269 		~AT91_MB_MASK(get_mb_rx_first(priv));
270 }
271 
272 static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
273 {
274 	return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
275 		~AT91_MB_MASK(get_mb_tx_first(priv));
276 }
277 
278 static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
279 {
280 	return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
281 }
282 
283 static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
284 {
285 	return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
286 }
287 
288 static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
289 {
290 	return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
291 }
292 
293 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
294 {
295 	return __raw_readl(priv->reg_base + reg);
296 }
297 
298 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
299 		u32 value)
300 {
301 	__raw_writel(value, priv->reg_base + reg);
302 }
303 
304 static inline void set_mb_mode_prio(const struct at91_priv *priv,
305 		unsigned int mb, enum at91_mb_mode mode, int prio)
306 {
307 	at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
308 }
309 
310 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
311 		enum at91_mb_mode mode)
312 {
313 	set_mb_mode_prio(priv, mb, mode, 0);
314 }
315 
316 static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
317 {
318 	u32 reg_mid;
319 
320 	if (can_id & CAN_EFF_FLAG)
321 		reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
322 	else
323 		reg_mid = (can_id & CAN_SFF_MASK) << 18;
324 
325 	return reg_mid;
326 }
327 
328 /*
329  * Swtich transceiver on or off
330  */
331 static void at91_transceiver_switch(const struct at91_priv *priv, int on)
332 {
333 	if (priv->pdata && priv->pdata->transceiver_switch)
334 		priv->pdata->transceiver_switch(on);
335 }
336 
337 static void at91_setup_mailboxes(struct net_device *dev)
338 {
339 	struct at91_priv *priv = netdev_priv(dev);
340 	unsigned int i;
341 	u32 reg_mid;
342 
343 	/*
344 	 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
345 	 * mailbox is disabled. The next 11 mailboxes are used as a
346 	 * reception FIFO. The last mailbox is configured with
347 	 * overwrite option. The overwrite flag indicates a FIFO
348 	 * overflow.
349 	 */
350 	reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
351 	for (i = 0; i < get_mb_rx_first(priv); i++) {
352 		set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
353 		at91_write(priv, AT91_MID(i), reg_mid);
354 		at91_write(priv, AT91_MCR(i), 0x0);	/* clear dlc */
355 	}
356 
357 	for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
358 		set_mb_mode(priv, i, AT91_MB_MODE_RX);
359 	set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
360 
361 	/* reset acceptance mask and id register */
362 	for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
363 		at91_write(priv, AT91_MAM(i), 0x0);
364 		at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
365 	}
366 
367 	/* The last 4 mailboxes are used for transmitting. */
368 	for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
369 		set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
370 
371 	/* Reset tx and rx helper pointers */
372 	priv->tx_next = priv->tx_echo = 0;
373 	priv->rx_next = get_mb_rx_first(priv);
374 }
375 
376 static int at91_set_bittiming(struct net_device *dev)
377 {
378 	const struct at91_priv *priv = netdev_priv(dev);
379 	const struct can_bittiming *bt = &priv->can.bittiming;
380 	u32 reg_br;
381 
382 	reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
383 		((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
384 		((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
385 		((bt->phase_seg2 - 1) << 0);
386 
387 	netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
388 
389 	at91_write(priv, AT91_BR, reg_br);
390 
391 	return 0;
392 }
393 
394 static int at91_get_berr_counter(const struct net_device *dev,
395 		struct can_berr_counter *bec)
396 {
397 	const struct at91_priv *priv = netdev_priv(dev);
398 	u32 reg_ecr = at91_read(priv, AT91_ECR);
399 
400 	bec->rxerr = reg_ecr & 0xff;
401 	bec->txerr = reg_ecr >> 16;
402 
403 	return 0;
404 }
405 
406 static void at91_chip_start(struct net_device *dev)
407 {
408 	struct at91_priv *priv = netdev_priv(dev);
409 	u32 reg_mr, reg_ier;
410 
411 	/* disable interrupts */
412 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
413 
414 	/* disable chip */
415 	reg_mr = at91_read(priv, AT91_MR);
416 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
417 
418 	at91_set_bittiming(dev);
419 	at91_setup_mailboxes(dev);
420 	at91_transceiver_switch(priv, 1);
421 
422 	/* enable chip */
423 	at91_write(priv, AT91_MR, AT91_MR_CANEN);
424 
425 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
426 
427 	/* Enable interrupts */
428 	reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
429 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
430 	at91_write(priv, AT91_IER, reg_ier);
431 }
432 
433 static void at91_chip_stop(struct net_device *dev, enum can_state state)
434 {
435 	struct at91_priv *priv = netdev_priv(dev);
436 	u32 reg_mr;
437 
438 	/* disable interrupts */
439 	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
440 
441 	reg_mr = at91_read(priv, AT91_MR);
442 	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
443 
444 	at91_transceiver_switch(priv, 0);
445 	priv->can.state = state;
446 }
447 
448 /*
449  * theory of operation:
450  *
451  * According to the datasheet priority 0 is the highest priority, 15
452  * is the lowest. If two mailboxes have the same priority level the
453  * message of the mailbox with the lowest number is sent first.
454  *
455  * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
456  * the next mailbox with prio 0, and so on, until all mailboxes are
457  * used. Then we start from the beginning with mailbox
458  * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
459  * prio 1. When we reach the last mailbox with prio 15, we have to
460  * stop sending, waiting for all messages to be delivered, then start
461  * again with mailbox AT91_MB_TX_FIRST prio 0.
462  *
463  * We use the priv->tx_next as counter for the next transmission
464  * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
465  * encode the mailbox number, the upper 4 bits the mailbox priority:
466  *
467  * priv->tx_next = (prio << get_next_prio_shift(priv)) |
468  *                 (mb - get_mb_tx_first(priv));
469  *
470  */
471 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
472 {
473 	struct at91_priv *priv = netdev_priv(dev);
474 	struct net_device_stats *stats = &dev->stats;
475 	struct can_frame *cf = (struct can_frame *)skb->data;
476 	unsigned int mb, prio;
477 	u32 reg_mid, reg_mcr;
478 
479 	if (can_dropped_invalid_skb(dev, skb))
480 		return NETDEV_TX_OK;
481 
482 	mb = get_tx_next_mb(priv);
483 	prio = get_tx_next_prio(priv);
484 
485 	if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
486 		netif_stop_queue(dev);
487 
488 		netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
489 		return NETDEV_TX_BUSY;
490 	}
491 	reg_mid = at91_can_id_to_reg_mid(cf->can_id);
492 	reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
493 		(cf->can_dlc << 16) | AT91_MCR_MTCR;
494 
495 	/* disable MB while writing ID (see datasheet) */
496 	set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
497 	at91_write(priv, AT91_MID(mb), reg_mid);
498 	set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
499 
500 	at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
501 	at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
502 
503 	/* This triggers transmission */
504 	at91_write(priv, AT91_MCR(mb), reg_mcr);
505 
506 	stats->tx_bytes += cf->can_dlc;
507 
508 	/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
509 	can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv));
510 
511 	/*
512 	 * we have to stop the queue and deliver all messages in case
513 	 * of a prio+mb counter wrap around. This is the case if
514 	 * tx_next buffer prio and mailbox equals 0.
515 	 *
516 	 * also stop the queue if next buffer is still in use
517 	 * (== not ready)
518 	 */
519 	priv->tx_next++;
520 	if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
521 	      AT91_MSR_MRDY) ||
522 	    (priv->tx_next & get_next_mask(priv)) == 0)
523 		netif_stop_queue(dev);
524 
525 	/* Enable interrupt for this mailbox */
526 	at91_write(priv, AT91_IER, 1 << mb);
527 
528 	return NETDEV_TX_OK;
529 }
530 
531 /**
532  * at91_activate_rx_low - activate lower rx mailboxes
533  * @priv: a91 context
534  *
535  * Reenables the lower mailboxes for reception of new CAN messages
536  */
537 static inline void at91_activate_rx_low(const struct at91_priv *priv)
538 {
539 	u32 mask = get_mb_rx_low_mask(priv);
540 	at91_write(priv, AT91_TCR, mask);
541 }
542 
543 /**
544  * at91_activate_rx_mb - reactive single rx mailbox
545  * @priv: a91 context
546  * @mb: mailbox to reactivate
547  *
548  * Reenables given mailbox for reception of new CAN messages
549  */
550 static inline void at91_activate_rx_mb(const struct at91_priv *priv,
551 		unsigned int mb)
552 {
553 	u32 mask = 1 << mb;
554 	at91_write(priv, AT91_TCR, mask);
555 }
556 
557 /**
558  * at91_rx_overflow_err - send error frame due to rx overflow
559  * @dev: net device
560  */
561 static void at91_rx_overflow_err(struct net_device *dev)
562 {
563 	struct net_device_stats *stats = &dev->stats;
564 	struct sk_buff *skb;
565 	struct can_frame *cf;
566 
567 	netdev_dbg(dev, "RX buffer overflow\n");
568 	stats->rx_over_errors++;
569 	stats->rx_errors++;
570 
571 	skb = alloc_can_err_skb(dev, &cf);
572 	if (unlikely(!skb))
573 		return;
574 
575 	cf->can_id |= CAN_ERR_CRTL;
576 	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
577 	netif_receive_skb(skb);
578 
579 	stats->rx_packets++;
580 	stats->rx_bytes += cf->can_dlc;
581 }
582 
583 /**
584  * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
585  * @dev: net device
586  * @mb: mailbox number to read from
587  * @cf: can frame where to store message
588  *
589  * Reads a CAN message from the given mailbox and stores data into
590  * given can frame. "mb" and "cf" must be valid.
591  */
592 static void at91_read_mb(struct net_device *dev, unsigned int mb,
593 		struct can_frame *cf)
594 {
595 	const struct at91_priv *priv = netdev_priv(dev);
596 	u32 reg_msr, reg_mid;
597 
598 	reg_mid = at91_read(priv, AT91_MID(mb));
599 	if (reg_mid & AT91_MID_MIDE)
600 		cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
601 	else
602 		cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
603 
604 	reg_msr = at91_read(priv, AT91_MSR(mb));
605 	cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
606 
607 	if (reg_msr & AT91_MSR_MRTR)
608 		cf->can_id |= CAN_RTR_FLAG;
609 	else {
610 		*(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
611 		*(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
612 	}
613 
614 	/* allow RX of extended frames */
615 	at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
616 
617 	if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
618 		at91_rx_overflow_err(dev);
619 }
620 
621 /**
622  * at91_read_msg - read CAN message from mailbox
623  * @dev: net device
624  * @mb: mail box to read from
625  *
626  * Reads a CAN message from given mailbox, and put into linux network
627  * RX queue, does all housekeeping chores (stats, ...)
628  */
629 static void at91_read_msg(struct net_device *dev, unsigned int mb)
630 {
631 	struct net_device_stats *stats = &dev->stats;
632 	struct can_frame *cf;
633 	struct sk_buff *skb;
634 
635 	skb = alloc_can_skb(dev, &cf);
636 	if (unlikely(!skb)) {
637 		stats->rx_dropped++;
638 		return;
639 	}
640 
641 	at91_read_mb(dev, mb, cf);
642 	netif_receive_skb(skb);
643 
644 	stats->rx_packets++;
645 	stats->rx_bytes += cf->can_dlc;
646 
647 	can_led_event(dev, CAN_LED_EVENT_RX);
648 }
649 
650 /**
651  * at91_poll_rx - read multiple CAN messages from mailboxes
652  * @dev: net device
653  * @quota: max number of pkgs we're allowed to receive
654  *
655  * Theory of Operation:
656  *
657  * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
658  * on the chip are reserved for RX. We split them into 2 groups. The
659  * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
660  *
661  * Like it or not, but the chip always saves a received CAN message
662  * into the first free mailbox it finds (starting with the
663  * lowest). This makes it very difficult to read the messages in the
664  * right order from the chip. This is how we work around that problem:
665  *
666  * The first message goes into mb nr. 1 and issues an interrupt. All
667  * rx ints are disabled in the interrupt handler and a napi poll is
668  * scheduled. We read the mailbox, but do _not_ reenable the mb (to
669  * receive another message).
670  *
671  *    lower mbxs      upper
672  *     ____^______    __^__
673  *    /           \  /     \
674  * +-+-+-+-+-+-+-+-++-+-+-+-+
675  * | |x|x|x|x|x|x|x|| | | | |
676  * +-+-+-+-+-+-+-+-++-+-+-+-+
677  *  0 0 0 0 0 0  0 0 0 0 1 1  \ mail
678  *  0 1 2 3 4 5  6 7 8 9 0 1  / box
679  *  ^
680  *  |
681  *   \
682  *     unused, due to chip bug
683  *
684  * The variable priv->rx_next points to the next mailbox to read a
685  * message from. As long we're in the lower mailboxes we just read the
686  * mailbox but not reenable it.
687  *
688  * With completion of the last of the lower mailboxes, we reenable the
689  * whole first group, but continue to look for filled mailboxes in the
690  * upper mailboxes. Imagine the second group like overflow mailboxes,
691  * which takes CAN messages if the lower goup is full. While in the
692  * upper group we reenable the mailbox right after reading it. Giving
693  * the chip more room to store messages.
694  *
695  * After finishing we look again in the lower group if we've still
696  * quota.
697  *
698  */
699 static int at91_poll_rx(struct net_device *dev, int quota)
700 {
701 	struct at91_priv *priv = netdev_priv(dev);
702 	u32 reg_sr = at91_read(priv, AT91_SR);
703 	const unsigned long *addr = (unsigned long *)&reg_sr;
704 	unsigned int mb;
705 	int received = 0;
706 
707 	if (priv->rx_next > get_mb_rx_low_last(priv) &&
708 	    reg_sr & get_mb_rx_low_mask(priv))
709 		netdev_info(dev,
710 			"order of incoming frames cannot be guaranteed\n");
711 
712  again:
713 	for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
714 	     mb < get_mb_tx_first(priv) && quota > 0;
715 	     reg_sr = at91_read(priv, AT91_SR),
716 	     mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
717 		at91_read_msg(dev, mb);
718 
719 		/* reactivate mailboxes */
720 		if (mb == get_mb_rx_low_last(priv))
721 			/* all lower mailboxed, if just finished it */
722 			at91_activate_rx_low(priv);
723 		else if (mb > get_mb_rx_low_last(priv))
724 			/* only the mailbox we read */
725 			at91_activate_rx_mb(priv, mb);
726 
727 		received++;
728 		quota--;
729 	}
730 
731 	/* upper group completed, look again in lower */
732 	if (priv->rx_next > get_mb_rx_low_last(priv) &&
733 	    quota > 0 && mb > get_mb_rx_last(priv)) {
734 		priv->rx_next = get_mb_rx_first(priv);
735 		goto again;
736 	}
737 
738 	return received;
739 }
740 
741 static void at91_poll_err_frame(struct net_device *dev,
742 		struct can_frame *cf, u32 reg_sr)
743 {
744 	struct at91_priv *priv = netdev_priv(dev);
745 
746 	/* CRC error */
747 	if (reg_sr & AT91_IRQ_CERR) {
748 		netdev_dbg(dev, "CERR irq\n");
749 		dev->stats.rx_errors++;
750 		priv->can.can_stats.bus_error++;
751 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
752 	}
753 
754 	/* Stuffing Error */
755 	if (reg_sr & AT91_IRQ_SERR) {
756 		netdev_dbg(dev, "SERR irq\n");
757 		dev->stats.rx_errors++;
758 		priv->can.can_stats.bus_error++;
759 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
760 		cf->data[2] |= CAN_ERR_PROT_STUFF;
761 	}
762 
763 	/* Acknowledgement Error */
764 	if (reg_sr & AT91_IRQ_AERR) {
765 		netdev_dbg(dev, "AERR irq\n");
766 		dev->stats.tx_errors++;
767 		cf->can_id |= CAN_ERR_ACK;
768 	}
769 
770 	/* Form error */
771 	if (reg_sr & AT91_IRQ_FERR) {
772 		netdev_dbg(dev, "FERR irq\n");
773 		dev->stats.rx_errors++;
774 		priv->can.can_stats.bus_error++;
775 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
776 		cf->data[2] |= CAN_ERR_PROT_FORM;
777 	}
778 
779 	/* Bit Error */
780 	if (reg_sr & AT91_IRQ_BERR) {
781 		netdev_dbg(dev, "BERR irq\n");
782 		dev->stats.tx_errors++;
783 		priv->can.can_stats.bus_error++;
784 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
785 		cf->data[2] |= CAN_ERR_PROT_BIT;
786 	}
787 }
788 
789 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
790 {
791 	struct sk_buff *skb;
792 	struct can_frame *cf;
793 
794 	if (quota == 0)
795 		return 0;
796 
797 	skb = alloc_can_err_skb(dev, &cf);
798 	if (unlikely(!skb))
799 		return 0;
800 
801 	at91_poll_err_frame(dev, cf, reg_sr);
802 	netif_receive_skb(skb);
803 
804 	dev->stats.rx_packets++;
805 	dev->stats.rx_bytes += cf->can_dlc;
806 
807 	return 1;
808 }
809 
810 static int at91_poll(struct napi_struct *napi, int quota)
811 {
812 	struct net_device *dev = napi->dev;
813 	const struct at91_priv *priv = netdev_priv(dev);
814 	u32 reg_sr = at91_read(priv, AT91_SR);
815 	int work_done = 0;
816 
817 	if (reg_sr & get_irq_mb_rx(priv))
818 		work_done += at91_poll_rx(dev, quota - work_done);
819 
820 	/*
821 	 * The error bits are clear on read,
822 	 * so use saved value from irq handler.
823 	 */
824 	reg_sr |= priv->reg_sr;
825 	if (reg_sr & AT91_IRQ_ERR_FRAME)
826 		work_done += at91_poll_err(dev, quota - work_done, reg_sr);
827 
828 	if (work_done < quota) {
829 		/* enable IRQs for frame errors and all mailboxes >= rx_next */
830 		u32 reg_ier = AT91_IRQ_ERR_FRAME;
831 		reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
832 
833 		napi_complete(napi);
834 		at91_write(priv, AT91_IER, reg_ier);
835 	}
836 
837 	return work_done;
838 }
839 
840 /*
841  * theory of operation:
842  *
843  * priv->tx_echo holds the number of the oldest can_frame put for
844  * transmission into the hardware, but not yet ACKed by the CAN tx
845  * complete IRQ.
846  *
847  * We iterate from priv->tx_echo to priv->tx_next and check if the
848  * packet has been transmitted, echo it back to the CAN framework. If
849  * we discover a not yet transmitted package, stop looking for more.
850  *
851  */
852 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
853 {
854 	struct at91_priv *priv = netdev_priv(dev);
855 	u32 reg_msr;
856 	unsigned int mb;
857 
858 	/* masking of reg_sr not needed, already done by at91_irq */
859 
860 	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
861 		mb = get_tx_echo_mb(priv);
862 
863 		/* no event in mailbox? */
864 		if (!(reg_sr & (1 << mb)))
865 			break;
866 
867 		/* Disable irq for this TX mailbox */
868 		at91_write(priv, AT91_IDR, 1 << mb);
869 
870 		/*
871 		 * only echo if mailbox signals us a transfer
872 		 * complete (MSR_MRDY). Otherwise it's a tansfer
873 		 * abort. "can_bus_off()" takes care about the skbs
874 		 * parked in the echo queue.
875 		 */
876 		reg_msr = at91_read(priv, AT91_MSR(mb));
877 		if (likely(reg_msr & AT91_MSR_MRDY &&
878 			   ~reg_msr & AT91_MSR_MABT)) {
879 			/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
880 			can_get_echo_skb(dev, mb - get_mb_tx_first(priv));
881 			dev->stats.tx_packets++;
882 			can_led_event(dev, CAN_LED_EVENT_TX);
883 		}
884 	}
885 
886 	/*
887 	 * restart queue if we don't have a wrap around but restart if
888 	 * we get a TX int for the last can frame directly before a
889 	 * wrap around.
890 	 */
891 	if ((priv->tx_next & get_next_mask(priv)) != 0 ||
892 	    (priv->tx_echo & get_next_mask(priv)) == 0)
893 		netif_wake_queue(dev);
894 }
895 
896 static void at91_irq_err_state(struct net_device *dev,
897 		struct can_frame *cf, enum can_state new_state)
898 {
899 	struct at91_priv *priv = netdev_priv(dev);
900 	u32 reg_idr = 0, reg_ier = 0;
901 	struct can_berr_counter bec;
902 
903 	at91_get_berr_counter(dev, &bec);
904 
905 	switch (priv->can.state) {
906 	case CAN_STATE_ERROR_ACTIVE:
907 		/*
908 		 * from: ERROR_ACTIVE
909 		 * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
910 		 * =>  : there was a warning int
911 		 */
912 		if (new_state >= CAN_STATE_ERROR_WARNING &&
913 		    new_state <= CAN_STATE_BUS_OFF) {
914 			netdev_dbg(dev, "Error Warning IRQ\n");
915 			priv->can.can_stats.error_warning++;
916 
917 			cf->can_id |= CAN_ERR_CRTL;
918 			cf->data[1] = (bec.txerr > bec.rxerr) ?
919 				CAN_ERR_CRTL_TX_WARNING :
920 				CAN_ERR_CRTL_RX_WARNING;
921 		}
922 	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
923 		/*
924 		 * from: ERROR_ACTIVE, ERROR_WARNING
925 		 * to  : ERROR_PASSIVE, BUS_OFF
926 		 * =>  : error passive int
927 		 */
928 		if (new_state >= CAN_STATE_ERROR_PASSIVE &&
929 		    new_state <= CAN_STATE_BUS_OFF) {
930 			netdev_dbg(dev, "Error Passive IRQ\n");
931 			priv->can.can_stats.error_passive++;
932 
933 			cf->can_id |= CAN_ERR_CRTL;
934 			cf->data[1] = (bec.txerr > bec.rxerr) ?
935 				CAN_ERR_CRTL_TX_PASSIVE :
936 				CAN_ERR_CRTL_RX_PASSIVE;
937 		}
938 		break;
939 	case CAN_STATE_BUS_OFF:
940 		/*
941 		 * from: BUS_OFF
942 		 * to  : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
943 		 */
944 		if (new_state <= CAN_STATE_ERROR_PASSIVE) {
945 			cf->can_id |= CAN_ERR_RESTARTED;
946 
947 			netdev_dbg(dev, "restarted\n");
948 			priv->can.can_stats.restarts++;
949 
950 			netif_carrier_on(dev);
951 			netif_wake_queue(dev);
952 		}
953 		break;
954 	default:
955 		break;
956 	}
957 
958 
959 	/* process state changes depending on the new state */
960 	switch (new_state) {
961 	case CAN_STATE_ERROR_ACTIVE:
962 		/*
963 		 * actually we want to enable AT91_IRQ_WARN here, but
964 		 * it screws up the system under certain
965 		 * circumstances. so just enable AT91_IRQ_ERRP, thus
966 		 * the "fallthrough"
967 		 */
968 		netdev_dbg(dev, "Error Active\n");
969 		cf->can_id |= CAN_ERR_PROT;
970 		cf->data[2] = CAN_ERR_PROT_ACTIVE;
971 	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
972 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
973 		reg_ier = AT91_IRQ_ERRP;
974 		break;
975 	case CAN_STATE_ERROR_PASSIVE:
976 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
977 		reg_ier = AT91_IRQ_BOFF;
978 		break;
979 	case CAN_STATE_BUS_OFF:
980 		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
981 			AT91_IRQ_WARN | AT91_IRQ_BOFF;
982 		reg_ier = 0;
983 
984 		cf->can_id |= CAN_ERR_BUSOFF;
985 
986 		netdev_dbg(dev, "bus-off\n");
987 		netif_carrier_off(dev);
988 		priv->can.can_stats.bus_off++;
989 
990 		/* turn off chip, if restart is disabled */
991 		if (!priv->can.restart_ms) {
992 			at91_chip_stop(dev, CAN_STATE_BUS_OFF);
993 			return;
994 		}
995 		break;
996 	default:
997 		break;
998 	}
999 
1000 	at91_write(priv, AT91_IDR, reg_idr);
1001 	at91_write(priv, AT91_IER, reg_ier);
1002 }
1003 
1004 static int at91_get_state_by_bec(const struct net_device *dev,
1005 		enum can_state *state)
1006 {
1007 	struct can_berr_counter bec;
1008 	int err;
1009 
1010 	err = at91_get_berr_counter(dev, &bec);
1011 	if (err)
1012 		return err;
1013 
1014 	if (bec.txerr < 96 && bec.rxerr < 96)
1015 		*state = CAN_STATE_ERROR_ACTIVE;
1016 	else if (bec.txerr < 128 && bec.rxerr < 128)
1017 		*state = CAN_STATE_ERROR_WARNING;
1018 	else if (bec.txerr < 256 && bec.rxerr < 256)
1019 		*state = CAN_STATE_ERROR_PASSIVE;
1020 	else
1021 		*state = CAN_STATE_BUS_OFF;
1022 
1023 	return 0;
1024 }
1025 
1026 
1027 static void at91_irq_err(struct net_device *dev)
1028 {
1029 	struct at91_priv *priv = netdev_priv(dev);
1030 	struct sk_buff *skb;
1031 	struct can_frame *cf;
1032 	enum can_state new_state;
1033 	u32 reg_sr;
1034 	int err;
1035 
1036 	if (at91_is_sam9263(priv)) {
1037 		reg_sr = at91_read(priv, AT91_SR);
1038 
1039 		/* we need to look at the unmasked reg_sr */
1040 		if (unlikely(reg_sr & AT91_IRQ_BOFF))
1041 			new_state = CAN_STATE_BUS_OFF;
1042 		else if (unlikely(reg_sr & AT91_IRQ_ERRP))
1043 			new_state = CAN_STATE_ERROR_PASSIVE;
1044 		else if (unlikely(reg_sr & AT91_IRQ_WARN))
1045 			new_state = CAN_STATE_ERROR_WARNING;
1046 		else if (likely(reg_sr & AT91_IRQ_ERRA))
1047 			new_state = CAN_STATE_ERROR_ACTIVE;
1048 		else {
1049 			netdev_err(dev, "BUG! hardware in undefined state\n");
1050 			return;
1051 		}
1052 	} else {
1053 		err = at91_get_state_by_bec(dev, &new_state);
1054 		if (err)
1055 			return;
1056 	}
1057 
1058 	/* state hasn't changed */
1059 	if (likely(new_state == priv->can.state))
1060 		return;
1061 
1062 	skb = alloc_can_err_skb(dev, &cf);
1063 	if (unlikely(!skb))
1064 		return;
1065 
1066 	at91_irq_err_state(dev, cf, new_state);
1067 	netif_rx(skb);
1068 
1069 	dev->stats.rx_packets++;
1070 	dev->stats.rx_bytes += cf->can_dlc;
1071 
1072 	priv->can.state = new_state;
1073 }
1074 
1075 /*
1076  * interrupt handler
1077  */
1078 static irqreturn_t at91_irq(int irq, void *dev_id)
1079 {
1080 	struct net_device *dev = dev_id;
1081 	struct at91_priv *priv = netdev_priv(dev);
1082 	irqreturn_t handled = IRQ_NONE;
1083 	u32 reg_sr, reg_imr;
1084 
1085 	reg_sr = at91_read(priv, AT91_SR);
1086 	reg_imr = at91_read(priv, AT91_IMR);
1087 
1088 	/* Ignore masked interrupts */
1089 	reg_sr &= reg_imr;
1090 	if (!reg_sr)
1091 		goto exit;
1092 
1093 	handled = IRQ_HANDLED;
1094 
1095 	/* Receive or error interrupt? -> napi */
1096 	if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
1097 		/*
1098 		 * The error bits are clear on read,
1099 		 * save for later use.
1100 		 */
1101 		priv->reg_sr = reg_sr;
1102 		at91_write(priv, AT91_IDR,
1103 			   get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
1104 		napi_schedule(&priv->napi);
1105 	}
1106 
1107 	/* Transmission complete interrupt */
1108 	if (reg_sr & get_irq_mb_tx(priv))
1109 		at91_irq_tx(dev, reg_sr);
1110 
1111 	at91_irq_err(dev);
1112 
1113  exit:
1114 	return handled;
1115 }
1116 
1117 static int at91_open(struct net_device *dev)
1118 {
1119 	struct at91_priv *priv = netdev_priv(dev);
1120 	int err;
1121 
1122 	clk_enable(priv->clk);
1123 
1124 	/* check or determine and set bittime */
1125 	err = open_candev(dev);
1126 	if (err)
1127 		goto out;
1128 
1129 	/* register interrupt handler */
1130 	if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
1131 			dev->name, dev)) {
1132 		err = -EAGAIN;
1133 		goto out_close;
1134 	}
1135 
1136 	can_led_event(dev, CAN_LED_EVENT_OPEN);
1137 
1138 	/* start chip and queuing */
1139 	at91_chip_start(dev);
1140 	napi_enable(&priv->napi);
1141 	netif_start_queue(dev);
1142 
1143 	return 0;
1144 
1145  out_close:
1146 	close_candev(dev);
1147  out:
1148 	clk_disable(priv->clk);
1149 
1150 	return err;
1151 }
1152 
1153 /*
1154  * stop CAN bus activity
1155  */
1156 static int at91_close(struct net_device *dev)
1157 {
1158 	struct at91_priv *priv = netdev_priv(dev);
1159 
1160 	netif_stop_queue(dev);
1161 	napi_disable(&priv->napi);
1162 	at91_chip_stop(dev, CAN_STATE_STOPPED);
1163 
1164 	free_irq(dev->irq, dev);
1165 	clk_disable(priv->clk);
1166 
1167 	close_candev(dev);
1168 
1169 	can_led_event(dev, CAN_LED_EVENT_STOP);
1170 
1171 	return 0;
1172 }
1173 
1174 static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1175 {
1176 	switch (mode) {
1177 	case CAN_MODE_START:
1178 		at91_chip_start(dev);
1179 		netif_wake_queue(dev);
1180 		break;
1181 
1182 	default:
1183 		return -EOPNOTSUPP;
1184 	}
1185 
1186 	return 0;
1187 }
1188 
1189 static const struct net_device_ops at91_netdev_ops = {
1190 	.ndo_open	= at91_open,
1191 	.ndo_stop	= at91_close,
1192 	.ndo_start_xmit	= at91_start_xmit,
1193 };
1194 
1195 static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
1196 		struct device_attribute *attr, char *buf)
1197 {
1198 	struct at91_priv *priv = netdev_priv(to_net_dev(dev));
1199 
1200 	if (priv->mb0_id & CAN_EFF_FLAG)
1201 		return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
1202 	else
1203 		return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
1204 }
1205 
1206 static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
1207 		struct device_attribute *attr, const char *buf, size_t count)
1208 {
1209 	struct net_device *ndev = to_net_dev(dev);
1210 	struct at91_priv *priv = netdev_priv(ndev);
1211 	unsigned long can_id;
1212 	ssize_t ret;
1213 	int err;
1214 
1215 	rtnl_lock();
1216 
1217 	if (ndev->flags & IFF_UP) {
1218 		ret = -EBUSY;
1219 		goto out;
1220 	}
1221 
1222 	err = kstrtoul(buf, 0, &can_id);
1223 	if (err) {
1224 		ret = err;
1225 		goto out;
1226 	}
1227 
1228 	if (can_id & CAN_EFF_FLAG)
1229 		can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
1230 	else
1231 		can_id &= CAN_SFF_MASK;
1232 
1233 	priv->mb0_id = can_id;
1234 	ret = count;
1235 
1236  out:
1237 	rtnl_unlock();
1238 	return ret;
1239 }
1240 
1241 static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO,
1242 	at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
1243 
1244 static struct attribute *at91_sysfs_attrs[] = {
1245 	&dev_attr_mb0_id.attr,
1246 	NULL,
1247 };
1248 
1249 static struct attribute_group at91_sysfs_attr_group = {
1250 	.attrs = at91_sysfs_attrs,
1251 };
1252 
1253 #if defined(CONFIG_OF)
1254 static const struct of_device_id at91_can_dt_ids[] = {
1255 	{
1256 		.compatible = "atmel,at91sam9x5-can",
1257 		.data = &at91_at91sam9x5_data,
1258 	}, {
1259 		.compatible = "atmel,at91sam9263-can",
1260 		.data = &at91_at91sam9263_data,
1261 	}, {
1262 		/* sentinel */
1263 	}
1264 };
1265 MODULE_DEVICE_TABLE(of, at91_can_dt_ids);
1266 #endif
1267 
1268 static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev)
1269 {
1270 	if (pdev->dev.of_node) {
1271 		const struct of_device_id *match;
1272 
1273 		match = of_match_node(at91_can_dt_ids, pdev->dev.of_node);
1274 		if (!match) {
1275 			dev_err(&pdev->dev, "no matching node found in dtb\n");
1276 			return NULL;
1277 		}
1278 		return (const struct at91_devtype_data *)match->data;
1279 	}
1280 	return (const struct at91_devtype_data *)
1281 		platform_get_device_id(pdev)->driver_data;
1282 }
1283 
1284 static int at91_can_probe(struct platform_device *pdev)
1285 {
1286 	const struct at91_devtype_data *devtype_data;
1287 	struct net_device *dev;
1288 	struct at91_priv *priv;
1289 	struct resource *res;
1290 	struct clk *clk;
1291 	void __iomem *addr;
1292 	int err, irq;
1293 
1294 	devtype_data = at91_can_get_driver_data(pdev);
1295 	if (!devtype_data) {
1296 		dev_err(&pdev->dev, "no driver data\n");
1297 		err = -ENODEV;
1298 		goto exit;
1299 	}
1300 
1301 	clk = clk_get(&pdev->dev, "can_clk");
1302 	if (IS_ERR(clk)) {
1303 		dev_err(&pdev->dev, "no clock defined\n");
1304 		err = -ENODEV;
1305 		goto exit;
1306 	}
1307 
1308 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1309 	irq = platform_get_irq(pdev, 0);
1310 	if (!res || irq <= 0) {
1311 		err = -ENODEV;
1312 		goto exit_put;
1313 	}
1314 
1315 	if (!request_mem_region(res->start,
1316 				resource_size(res),
1317 				pdev->name)) {
1318 		err = -EBUSY;
1319 		goto exit_put;
1320 	}
1321 
1322 	addr = ioremap_nocache(res->start, resource_size(res));
1323 	if (!addr) {
1324 		err = -ENOMEM;
1325 		goto exit_release;
1326 	}
1327 
1328 	dev = alloc_candev(sizeof(struct at91_priv),
1329 			   1 << devtype_data->tx_shift);
1330 	if (!dev) {
1331 		err = -ENOMEM;
1332 		goto exit_iounmap;
1333 	}
1334 
1335 	dev->netdev_ops	= &at91_netdev_ops;
1336 	dev->irq = irq;
1337 	dev->flags |= IFF_ECHO;
1338 
1339 	priv = netdev_priv(dev);
1340 	priv->can.clock.freq = clk_get_rate(clk);
1341 	priv->can.bittiming_const = &at91_bittiming_const;
1342 	priv->can.do_set_mode = at91_set_mode;
1343 	priv->can.do_get_berr_counter = at91_get_berr_counter;
1344 	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
1345 	priv->dev = dev;
1346 	priv->reg_base = addr;
1347 	priv->devtype_data = *devtype_data;
1348 	priv->clk = clk;
1349 	priv->pdata = dev_get_platdata(&pdev->dev);
1350 	priv->mb0_id = 0x7ff;
1351 
1352 	netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
1353 
1354 	if (at91_is_sam9263(priv))
1355 		dev->sysfs_groups[0] = &at91_sysfs_attr_group;
1356 
1357 	platform_set_drvdata(pdev, dev);
1358 	SET_NETDEV_DEV(dev, &pdev->dev);
1359 
1360 	err = register_candev(dev);
1361 	if (err) {
1362 		dev_err(&pdev->dev, "registering netdev failed\n");
1363 		goto exit_free;
1364 	}
1365 
1366 	devm_can_led_init(dev);
1367 
1368 	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1369 		 priv->reg_base, dev->irq);
1370 
1371 	return 0;
1372 
1373  exit_free:
1374 	free_candev(dev);
1375  exit_iounmap:
1376 	iounmap(addr);
1377  exit_release:
1378 	release_mem_region(res->start, resource_size(res));
1379  exit_put:
1380 	clk_put(clk);
1381  exit:
1382 	return err;
1383 }
1384 
1385 static int at91_can_remove(struct platform_device *pdev)
1386 {
1387 	struct net_device *dev = platform_get_drvdata(pdev);
1388 	struct at91_priv *priv = netdev_priv(dev);
1389 	struct resource *res;
1390 
1391 	unregister_netdev(dev);
1392 
1393 	iounmap(priv->reg_base);
1394 
1395 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1396 	release_mem_region(res->start, resource_size(res));
1397 
1398 	clk_put(priv->clk);
1399 
1400 	free_candev(dev);
1401 
1402 	return 0;
1403 }
1404 
1405 static const struct platform_device_id at91_can_id_table[] = {
1406 	{
1407 		.name = "at91sam9x5_can",
1408 		.driver_data = (kernel_ulong_t)&at91_at91sam9x5_data,
1409 	}, {
1410 		.name = "at91_can",
1411 		.driver_data = (kernel_ulong_t)&at91_at91sam9263_data,
1412 	}, {
1413 		/* sentinel */
1414 	}
1415 };
1416 MODULE_DEVICE_TABLE(platform, at91_can_id_table);
1417 
1418 static struct platform_driver at91_can_driver = {
1419 	.probe = at91_can_probe,
1420 	.remove = at91_can_remove,
1421 	.driver = {
1422 		.name = KBUILD_MODNAME,
1423 		.owner = THIS_MODULE,
1424 		.of_match_table = of_match_ptr(at91_can_dt_ids),
1425 	},
1426 	.id_table = at91_can_id_table,
1427 };
1428 
1429 module_platform_driver(at91_can_driver);
1430 
1431 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1432 MODULE_LICENSE("GPL v2");
1433 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");
1434