1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * at91_can.c - CAN network driver for AT91 SoC CAN controller 4 * 5 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 6 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/errno.h> 11 #include <linux/if_arp.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/rtnetlink.h> 19 #include <linux/skbuff.h> 20 #include <linux/spinlock.h> 21 #include <linux/string.h> 22 #include <linux/types.h> 23 24 #include <linux/can/dev.h> 25 #include <linux/can/error.h> 26 #include <linux/can/led.h> 27 28 #define AT91_MB_MASK(i) ((1 << (i)) - 1) 29 30 /* Common registers */ 31 enum at91_reg { 32 AT91_MR = 0x000, 33 AT91_IER = 0x004, 34 AT91_IDR = 0x008, 35 AT91_IMR = 0x00C, 36 AT91_SR = 0x010, 37 AT91_BR = 0x014, 38 AT91_TIM = 0x018, 39 AT91_TIMESTP = 0x01C, 40 AT91_ECR = 0x020, 41 AT91_TCR = 0x024, 42 AT91_ACR = 0x028, 43 }; 44 45 /* Mailbox registers (0 <= i <= 15) */ 46 #define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20))) 47 #define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20))) 48 #define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20))) 49 #define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20))) 50 #define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20))) 51 #define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20))) 52 #define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20))) 53 #define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20))) 54 55 /* Register bits */ 56 #define AT91_MR_CANEN BIT(0) 57 #define AT91_MR_LPM BIT(1) 58 #define AT91_MR_ABM BIT(2) 59 #define AT91_MR_OVL BIT(3) 60 #define AT91_MR_TEOF BIT(4) 61 #define AT91_MR_TTM BIT(5) 62 #define AT91_MR_TIMFRZ BIT(6) 63 #define AT91_MR_DRPT BIT(7) 64 65 #define AT91_SR_RBSY BIT(29) 66 67 #define AT91_MMR_PRIO_SHIFT (16) 68 69 #define AT91_MID_MIDE BIT(29) 70 71 #define AT91_MSR_MRTR BIT(20) 72 #define AT91_MSR_MABT BIT(22) 73 #define AT91_MSR_MRDY BIT(23) 74 #define AT91_MSR_MMI BIT(24) 75 76 #define AT91_MCR_MRTR BIT(20) 77 #define AT91_MCR_MTCR BIT(23) 78 79 /* Mailbox Modes */ 80 enum at91_mb_mode { 81 AT91_MB_MODE_DISABLED = 0, 82 AT91_MB_MODE_RX = 1, 83 AT91_MB_MODE_RX_OVRWR = 2, 84 AT91_MB_MODE_TX = 3, 85 AT91_MB_MODE_CONSUMER = 4, 86 AT91_MB_MODE_PRODUCER = 5, 87 }; 88 89 /* Interrupt mask bits */ 90 #define AT91_IRQ_ERRA BIT(16) 91 #define AT91_IRQ_WARN BIT(17) 92 #define AT91_IRQ_ERRP BIT(18) 93 #define AT91_IRQ_BOFF BIT(19) 94 #define AT91_IRQ_SLEEP BIT(20) 95 #define AT91_IRQ_WAKEUP BIT(21) 96 #define AT91_IRQ_TOVF BIT(22) 97 #define AT91_IRQ_TSTP BIT(23) 98 #define AT91_IRQ_CERR BIT(24) 99 #define AT91_IRQ_SERR BIT(25) 100 #define AT91_IRQ_AERR BIT(26) 101 #define AT91_IRQ_FERR BIT(27) 102 #define AT91_IRQ_BERR BIT(28) 103 104 #define AT91_IRQ_ERR_ALL (0x1fff0000) 105 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 106 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 107 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 108 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 109 110 #define AT91_IRQ_ALL (0x1fffffff) 111 112 enum at91_devtype { 113 AT91_DEVTYPE_SAM9263, 114 AT91_DEVTYPE_SAM9X5, 115 }; 116 117 struct at91_devtype_data { 118 unsigned int rx_first; 119 unsigned int rx_split; 120 unsigned int rx_last; 121 unsigned int tx_shift; 122 enum at91_devtype type; 123 }; 124 125 struct at91_priv { 126 struct can_priv can; /* must be the first member! */ 127 struct napi_struct napi; 128 129 void __iomem *reg_base; 130 131 u32 reg_sr; 132 unsigned int tx_next; 133 unsigned int tx_echo; 134 unsigned int rx_next; 135 struct at91_devtype_data devtype_data; 136 137 struct clk *clk; 138 struct at91_can_data *pdata; 139 140 canid_t mb0_id; 141 }; 142 143 static const struct at91_devtype_data at91_at91sam9263_data = { 144 .rx_first = 1, 145 .rx_split = 8, 146 .rx_last = 11, 147 .tx_shift = 2, 148 .type = AT91_DEVTYPE_SAM9263, 149 }; 150 151 static const struct at91_devtype_data at91_at91sam9x5_data = { 152 .rx_first = 0, 153 .rx_split = 4, 154 .rx_last = 5, 155 .tx_shift = 1, 156 .type = AT91_DEVTYPE_SAM9X5, 157 }; 158 159 static const struct can_bittiming_const at91_bittiming_const = { 160 .name = KBUILD_MODNAME, 161 .tseg1_min = 4, 162 .tseg1_max = 16, 163 .tseg2_min = 2, 164 .tseg2_max = 8, 165 .sjw_max = 4, 166 .brp_min = 2, 167 .brp_max = 128, 168 .brp_inc = 1, 169 }; 170 171 #define AT91_IS(_model) \ 172 static inline int __maybe_unused at91_is_sam##_model(const struct at91_priv *priv) \ 173 { \ 174 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ 175 } 176 177 AT91_IS(9263); 178 AT91_IS(9X5); 179 180 static inline unsigned int get_mb_rx_first(const struct at91_priv *priv) 181 { 182 return priv->devtype_data.rx_first; 183 } 184 185 static inline unsigned int get_mb_rx_last(const struct at91_priv *priv) 186 { 187 return priv->devtype_data.rx_last; 188 } 189 190 static inline unsigned int get_mb_rx_split(const struct at91_priv *priv) 191 { 192 return priv->devtype_data.rx_split; 193 } 194 195 static inline unsigned int get_mb_rx_num(const struct at91_priv *priv) 196 { 197 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1; 198 } 199 200 static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 201 { 202 return get_mb_rx_split(priv) - 1; 203 } 204 205 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 206 { 207 return AT91_MB_MASK(get_mb_rx_split(priv)) & 208 ~AT91_MB_MASK(get_mb_rx_first(priv)); 209 } 210 211 static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv) 212 { 213 return priv->devtype_data.tx_shift; 214 } 215 216 static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 217 { 218 return 1 << get_mb_tx_shift(priv); 219 } 220 221 static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 222 { 223 return get_mb_rx_last(priv) + 1; 224 } 225 226 static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 227 { 228 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 229 } 230 231 static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 232 { 233 return get_mb_tx_shift(priv); 234 } 235 236 static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 237 { 238 return 0xf << get_mb_tx_shift(priv); 239 } 240 241 static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 242 { 243 return AT91_MB_MASK(get_mb_tx_shift(priv)); 244 } 245 246 static inline unsigned int get_next_mask(const struct at91_priv *priv) 247 { 248 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 249 } 250 251 static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 252 { 253 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) & 254 ~AT91_MB_MASK(get_mb_rx_first(priv)); 255 } 256 257 static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 258 { 259 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 260 ~AT91_MB_MASK(get_mb_tx_first(priv)); 261 } 262 263 static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 264 { 265 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 266 } 267 268 static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 269 { 270 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 271 } 272 273 static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 274 { 275 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 276 } 277 278 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 279 { 280 return readl_relaxed(priv->reg_base + reg); 281 } 282 283 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 284 u32 value) 285 { 286 writel_relaxed(value, priv->reg_base + reg); 287 } 288 289 static inline void set_mb_mode_prio(const struct at91_priv *priv, 290 unsigned int mb, enum at91_mb_mode mode, 291 int prio) 292 { 293 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 294 } 295 296 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 297 enum at91_mb_mode mode) 298 { 299 set_mb_mode_prio(priv, mb, mode, 0); 300 } 301 302 static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 303 { 304 u32 reg_mid; 305 306 if (can_id & CAN_EFF_FLAG) 307 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 308 else 309 reg_mid = (can_id & CAN_SFF_MASK) << 18; 310 311 return reg_mid; 312 } 313 314 static void at91_setup_mailboxes(struct net_device *dev) 315 { 316 struct at91_priv *priv = netdev_priv(dev); 317 unsigned int i; 318 u32 reg_mid; 319 320 /* Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 321 * mailbox is disabled. The next 11 mailboxes are used as a 322 * reception FIFO. The last mailbox is configured with 323 * overwrite option. The overwrite flag indicates a FIFO 324 * overflow. 325 */ 326 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 327 for (i = 0; i < get_mb_rx_first(priv); i++) { 328 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 329 at91_write(priv, AT91_MID(i), reg_mid); 330 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 331 } 332 333 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++) 334 set_mb_mode(priv, i, AT91_MB_MODE_RX); 335 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR); 336 337 /* reset acceptance mask and id register */ 338 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) { 339 at91_write(priv, AT91_MAM(i), 0x0); 340 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 341 } 342 343 /* The last 4 mailboxes are used for transmitting. */ 344 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 345 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 346 347 /* Reset tx and rx helper pointers */ 348 priv->tx_next = priv->tx_echo = 0; 349 priv->rx_next = get_mb_rx_first(priv); 350 } 351 352 static int at91_set_bittiming(struct net_device *dev) 353 { 354 const struct at91_priv *priv = netdev_priv(dev); 355 const struct can_bittiming *bt = &priv->can.bittiming; 356 u32 reg_br; 357 358 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 359 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 360 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 361 ((bt->phase_seg2 - 1) << 0); 362 363 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 364 365 at91_write(priv, AT91_BR, reg_br); 366 367 return 0; 368 } 369 370 static int at91_get_berr_counter(const struct net_device *dev, 371 struct can_berr_counter *bec) 372 { 373 const struct at91_priv *priv = netdev_priv(dev); 374 u32 reg_ecr = at91_read(priv, AT91_ECR); 375 376 bec->rxerr = reg_ecr & 0xff; 377 bec->txerr = reg_ecr >> 16; 378 379 return 0; 380 } 381 382 static void at91_chip_start(struct net_device *dev) 383 { 384 struct at91_priv *priv = netdev_priv(dev); 385 u32 reg_mr, reg_ier; 386 387 /* disable interrupts */ 388 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 389 390 /* disable chip */ 391 reg_mr = at91_read(priv, AT91_MR); 392 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 393 394 at91_set_bittiming(dev); 395 at91_setup_mailboxes(dev); 396 397 /* enable chip */ 398 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 399 reg_mr = AT91_MR_CANEN | AT91_MR_ABM; 400 else 401 reg_mr = AT91_MR_CANEN; 402 at91_write(priv, AT91_MR, reg_mr); 403 404 priv->can.state = CAN_STATE_ERROR_ACTIVE; 405 406 /* Enable interrupts */ 407 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 408 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 409 at91_write(priv, AT91_IER, reg_ier); 410 } 411 412 static void at91_chip_stop(struct net_device *dev, enum can_state state) 413 { 414 struct at91_priv *priv = netdev_priv(dev); 415 u32 reg_mr; 416 417 /* disable interrupts */ 418 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 419 420 reg_mr = at91_read(priv, AT91_MR); 421 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 422 423 priv->can.state = state; 424 } 425 426 /* theory of operation: 427 * 428 * According to the datasheet priority 0 is the highest priority, 15 429 * is the lowest. If two mailboxes have the same priority level the 430 * message of the mailbox with the lowest number is sent first. 431 * 432 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 433 * the next mailbox with prio 0, and so on, until all mailboxes are 434 * used. Then we start from the beginning with mailbox 435 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 436 * prio 1. When we reach the last mailbox with prio 15, we have to 437 * stop sending, waiting for all messages to be delivered, then start 438 * again with mailbox AT91_MB_TX_FIRST prio 0. 439 * 440 * We use the priv->tx_next as counter for the next transmission 441 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 442 * encode the mailbox number, the upper 4 bits the mailbox priority: 443 * 444 * priv->tx_next = (prio << get_next_prio_shift(priv)) | 445 * (mb - get_mb_tx_first(priv)); 446 * 447 */ 448 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 449 { 450 struct at91_priv *priv = netdev_priv(dev); 451 struct can_frame *cf = (struct can_frame *)skb->data; 452 unsigned int mb, prio; 453 u32 reg_mid, reg_mcr; 454 455 if (can_dropped_invalid_skb(dev, skb)) 456 return NETDEV_TX_OK; 457 458 mb = get_tx_next_mb(priv); 459 prio = get_tx_next_prio(priv); 460 461 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 462 netif_stop_queue(dev); 463 464 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 465 return NETDEV_TX_BUSY; 466 } 467 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 468 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 469 (cf->len << 16) | AT91_MCR_MTCR; 470 471 /* disable MB while writing ID (see datasheet) */ 472 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 473 at91_write(priv, AT91_MID(mb), reg_mid); 474 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 475 476 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 477 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 478 479 /* This triggers transmission */ 480 at91_write(priv, AT91_MCR(mb), reg_mcr); 481 482 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 483 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv), 0); 484 485 /* we have to stop the queue and deliver all messages in case 486 * of a prio+mb counter wrap around. This is the case if 487 * tx_next buffer prio and mailbox equals 0. 488 * 489 * also stop the queue if next buffer is still in use 490 * (== not ready) 491 */ 492 priv->tx_next++; 493 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 494 AT91_MSR_MRDY) || 495 (priv->tx_next & get_next_mask(priv)) == 0) 496 netif_stop_queue(dev); 497 498 /* Enable interrupt for this mailbox */ 499 at91_write(priv, AT91_IER, 1 << mb); 500 501 return NETDEV_TX_OK; 502 } 503 504 /** 505 * at91_activate_rx_low - activate lower rx mailboxes 506 * @priv: a91 context 507 * 508 * Reenables the lower mailboxes for reception of new CAN messages 509 */ 510 static inline void at91_activate_rx_low(const struct at91_priv *priv) 511 { 512 u32 mask = get_mb_rx_low_mask(priv); 513 514 at91_write(priv, AT91_TCR, mask); 515 } 516 517 /** 518 * at91_activate_rx_mb - reactive single rx mailbox 519 * @priv: a91 context 520 * @mb: mailbox to reactivate 521 * 522 * Reenables given mailbox for reception of new CAN messages 523 */ 524 static inline void at91_activate_rx_mb(const struct at91_priv *priv, 525 unsigned int mb) 526 { 527 u32 mask = 1 << mb; 528 529 at91_write(priv, AT91_TCR, mask); 530 } 531 532 /** 533 * at91_rx_overflow_err - send error frame due to rx overflow 534 * @dev: net device 535 */ 536 static void at91_rx_overflow_err(struct net_device *dev) 537 { 538 struct net_device_stats *stats = &dev->stats; 539 struct sk_buff *skb; 540 struct can_frame *cf; 541 542 netdev_dbg(dev, "RX buffer overflow\n"); 543 stats->rx_over_errors++; 544 stats->rx_errors++; 545 546 skb = alloc_can_err_skb(dev, &cf); 547 if (unlikely(!skb)) 548 return; 549 550 cf->can_id |= CAN_ERR_CRTL; 551 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 552 553 netif_receive_skb(skb); 554 } 555 556 /** 557 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 558 * @dev: net device 559 * @mb: mailbox number to read from 560 * @cf: can frame where to store message 561 * 562 * Reads a CAN message from the given mailbox and stores data into 563 * given can frame. "mb" and "cf" must be valid. 564 */ 565 static void at91_read_mb(struct net_device *dev, unsigned int mb, 566 struct can_frame *cf) 567 { 568 const struct at91_priv *priv = netdev_priv(dev); 569 u32 reg_msr, reg_mid; 570 571 reg_mid = at91_read(priv, AT91_MID(mb)); 572 if (reg_mid & AT91_MID_MIDE) 573 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 574 else 575 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 576 577 reg_msr = at91_read(priv, AT91_MSR(mb)); 578 cf->len = can_cc_dlc2len((reg_msr >> 16) & 0xf); 579 580 if (reg_msr & AT91_MSR_MRTR) { 581 cf->can_id |= CAN_RTR_FLAG; 582 } else { 583 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 584 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 585 } 586 587 /* allow RX of extended frames */ 588 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 589 590 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI)) 591 at91_rx_overflow_err(dev); 592 } 593 594 /** 595 * at91_read_msg - read CAN message from mailbox 596 * @dev: net device 597 * @mb: mail box to read from 598 * 599 * Reads a CAN message from given mailbox, and put into linux network 600 * RX queue, does all housekeeping chores (stats, ...) 601 */ 602 static void at91_read_msg(struct net_device *dev, unsigned int mb) 603 { 604 struct net_device_stats *stats = &dev->stats; 605 struct can_frame *cf; 606 struct sk_buff *skb; 607 608 skb = alloc_can_skb(dev, &cf); 609 if (unlikely(!skb)) { 610 stats->rx_dropped++; 611 return; 612 } 613 614 at91_read_mb(dev, mb, cf); 615 616 stats->rx_packets++; 617 if (!(cf->can_id & CAN_RTR_FLAG)) 618 stats->rx_bytes += cf->len; 619 620 netif_receive_skb(skb); 621 622 can_led_event(dev, CAN_LED_EVENT_RX); 623 } 624 625 /** 626 * at91_poll_rx - read multiple CAN messages from mailboxes 627 * @dev: net device 628 * @quota: max number of pkgs we're allowed to receive 629 * 630 * Theory of Operation: 631 * 632 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last()) 633 * on the chip are reserved for RX. We split them into 2 groups. The 634 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last(). 635 * 636 * Like it or not, but the chip always saves a received CAN message 637 * into the first free mailbox it finds (starting with the 638 * lowest). This makes it very difficult to read the messages in the 639 * right order from the chip. This is how we work around that problem: 640 * 641 * The first message goes into mb nr. 1 and issues an interrupt. All 642 * rx ints are disabled in the interrupt handler and a napi poll is 643 * scheduled. We read the mailbox, but do _not_ re-enable the mb (to 644 * receive another message). 645 * 646 * lower mbxs upper 647 * ____^______ __^__ 648 * / \ / \ 649 * +-+-+-+-+-+-+-+-++-+-+-+-+ 650 * | |x|x|x|x|x|x|x|| | | | | 651 * +-+-+-+-+-+-+-+-++-+-+-+-+ 652 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 653 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 654 * ^ 655 * | 656 * \ 657 * unused, due to chip bug 658 * 659 * The variable priv->rx_next points to the next mailbox to read a 660 * message from. As long we're in the lower mailboxes we just read the 661 * mailbox but not re-enable it. 662 * 663 * With completion of the last of the lower mailboxes, we re-enable the 664 * whole first group, but continue to look for filled mailboxes in the 665 * upper mailboxes. Imagine the second group like overflow mailboxes, 666 * which takes CAN messages if the lower goup is full. While in the 667 * upper group we re-enable the mailbox right after reading it. Giving 668 * the chip more room to store messages. 669 * 670 * After finishing we look again in the lower group if we've still 671 * quota. 672 * 673 */ 674 static int at91_poll_rx(struct net_device *dev, int quota) 675 { 676 struct at91_priv *priv = netdev_priv(dev); 677 u32 reg_sr = at91_read(priv, AT91_SR); 678 const unsigned long *addr = (unsigned long *)®_sr; 679 unsigned int mb; 680 int received = 0; 681 682 if (priv->rx_next > get_mb_rx_low_last(priv) && 683 reg_sr & get_mb_rx_low_mask(priv)) 684 netdev_info(dev, 685 "order of incoming frames cannot be guaranteed\n"); 686 687 again: 688 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 689 mb < get_mb_tx_first(priv) && quota > 0; 690 reg_sr = at91_read(priv, AT91_SR), 691 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 692 at91_read_msg(dev, mb); 693 694 /* reactivate mailboxes */ 695 if (mb == get_mb_rx_low_last(priv)) 696 /* all lower mailboxed, if just finished it */ 697 at91_activate_rx_low(priv); 698 else if (mb > get_mb_rx_low_last(priv)) 699 /* only the mailbox we read */ 700 at91_activate_rx_mb(priv, mb); 701 702 received++; 703 quota--; 704 } 705 706 /* upper group completed, look again in lower */ 707 if (priv->rx_next > get_mb_rx_low_last(priv) && 708 mb > get_mb_rx_last(priv)) { 709 priv->rx_next = get_mb_rx_first(priv); 710 if (quota > 0) 711 goto again; 712 } 713 714 return received; 715 } 716 717 static void at91_poll_err_frame(struct net_device *dev, 718 struct can_frame *cf, u32 reg_sr) 719 { 720 struct at91_priv *priv = netdev_priv(dev); 721 722 /* CRC error */ 723 if (reg_sr & AT91_IRQ_CERR) { 724 netdev_dbg(dev, "CERR irq\n"); 725 dev->stats.rx_errors++; 726 priv->can.can_stats.bus_error++; 727 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 728 } 729 730 /* Stuffing Error */ 731 if (reg_sr & AT91_IRQ_SERR) { 732 netdev_dbg(dev, "SERR irq\n"); 733 dev->stats.rx_errors++; 734 priv->can.can_stats.bus_error++; 735 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 736 cf->data[2] |= CAN_ERR_PROT_STUFF; 737 } 738 739 /* Acknowledgement Error */ 740 if (reg_sr & AT91_IRQ_AERR) { 741 netdev_dbg(dev, "AERR irq\n"); 742 dev->stats.tx_errors++; 743 cf->can_id |= CAN_ERR_ACK; 744 } 745 746 /* Form error */ 747 if (reg_sr & AT91_IRQ_FERR) { 748 netdev_dbg(dev, "FERR irq\n"); 749 dev->stats.rx_errors++; 750 priv->can.can_stats.bus_error++; 751 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 752 cf->data[2] |= CAN_ERR_PROT_FORM; 753 } 754 755 /* Bit Error */ 756 if (reg_sr & AT91_IRQ_BERR) { 757 netdev_dbg(dev, "BERR irq\n"); 758 dev->stats.tx_errors++; 759 priv->can.can_stats.bus_error++; 760 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 761 cf->data[2] |= CAN_ERR_PROT_BIT; 762 } 763 } 764 765 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 766 { 767 struct sk_buff *skb; 768 struct can_frame *cf; 769 770 if (quota == 0) 771 return 0; 772 773 skb = alloc_can_err_skb(dev, &cf); 774 if (unlikely(!skb)) 775 return 0; 776 777 at91_poll_err_frame(dev, cf, reg_sr); 778 779 netif_receive_skb(skb); 780 781 return 1; 782 } 783 784 static int at91_poll(struct napi_struct *napi, int quota) 785 { 786 struct net_device *dev = napi->dev; 787 const struct at91_priv *priv = netdev_priv(dev); 788 u32 reg_sr = at91_read(priv, AT91_SR); 789 int work_done = 0; 790 791 if (reg_sr & get_irq_mb_rx(priv)) 792 work_done += at91_poll_rx(dev, quota - work_done); 793 794 /* The error bits are clear on read, 795 * so use saved value from irq handler. 796 */ 797 reg_sr |= priv->reg_sr; 798 if (reg_sr & AT91_IRQ_ERR_FRAME) 799 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 800 801 if (work_done < quota) { 802 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 803 u32 reg_ier = AT91_IRQ_ERR_FRAME; 804 805 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 806 807 napi_complete_done(napi, work_done); 808 at91_write(priv, AT91_IER, reg_ier); 809 } 810 811 return work_done; 812 } 813 814 /* theory of operation: 815 * 816 * priv->tx_echo holds the number of the oldest can_frame put for 817 * transmission into the hardware, but not yet ACKed by the CAN tx 818 * complete IRQ. 819 * 820 * We iterate from priv->tx_echo to priv->tx_next and check if the 821 * packet has been transmitted, echo it back to the CAN framework. If 822 * we discover a not yet transmitted package, stop looking for more. 823 * 824 */ 825 static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 826 { 827 struct at91_priv *priv = netdev_priv(dev); 828 u32 reg_msr; 829 unsigned int mb; 830 831 /* masking of reg_sr not needed, already done by at91_irq */ 832 833 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 834 mb = get_tx_echo_mb(priv); 835 836 /* no event in mailbox? */ 837 if (!(reg_sr & (1 << mb))) 838 break; 839 840 /* Disable irq for this TX mailbox */ 841 at91_write(priv, AT91_IDR, 1 << mb); 842 843 /* only echo if mailbox signals us a transfer 844 * complete (MSR_MRDY). Otherwise it's a tansfer 845 * abort. "can_bus_off()" takes care about the skbs 846 * parked in the echo queue. 847 */ 848 reg_msr = at91_read(priv, AT91_MSR(mb)); 849 if (likely(reg_msr & AT91_MSR_MRDY && 850 ~reg_msr & AT91_MSR_MABT)) { 851 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 852 dev->stats.tx_bytes += 853 can_get_echo_skb(dev, 854 mb - get_mb_tx_first(priv), 855 NULL); 856 dev->stats.tx_packets++; 857 can_led_event(dev, CAN_LED_EVENT_TX); 858 } 859 } 860 861 /* restart queue if we don't have a wrap around but restart if 862 * we get a TX int for the last can frame directly before a 863 * wrap around. 864 */ 865 if ((priv->tx_next & get_next_mask(priv)) != 0 || 866 (priv->tx_echo & get_next_mask(priv)) == 0) 867 netif_wake_queue(dev); 868 } 869 870 static void at91_irq_err_state(struct net_device *dev, 871 struct can_frame *cf, enum can_state new_state) 872 { 873 struct at91_priv *priv = netdev_priv(dev); 874 u32 reg_idr = 0, reg_ier = 0; 875 struct can_berr_counter bec; 876 877 at91_get_berr_counter(dev, &bec); 878 879 switch (priv->can.state) { 880 case CAN_STATE_ERROR_ACTIVE: 881 /* from: ERROR_ACTIVE 882 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 883 * => : there was a warning int 884 */ 885 if (new_state >= CAN_STATE_ERROR_WARNING && 886 new_state <= CAN_STATE_BUS_OFF) { 887 netdev_dbg(dev, "Error Warning IRQ\n"); 888 priv->can.can_stats.error_warning++; 889 890 cf->can_id |= CAN_ERR_CRTL; 891 cf->data[1] = (bec.txerr > bec.rxerr) ? 892 CAN_ERR_CRTL_TX_WARNING : 893 CAN_ERR_CRTL_RX_WARNING; 894 } 895 fallthrough; 896 case CAN_STATE_ERROR_WARNING: 897 /* from: ERROR_ACTIVE, ERROR_WARNING 898 * to : ERROR_PASSIVE, BUS_OFF 899 * => : error passive int 900 */ 901 if (new_state >= CAN_STATE_ERROR_PASSIVE && 902 new_state <= CAN_STATE_BUS_OFF) { 903 netdev_dbg(dev, "Error Passive IRQ\n"); 904 priv->can.can_stats.error_passive++; 905 906 cf->can_id |= CAN_ERR_CRTL; 907 cf->data[1] = (bec.txerr > bec.rxerr) ? 908 CAN_ERR_CRTL_TX_PASSIVE : 909 CAN_ERR_CRTL_RX_PASSIVE; 910 } 911 break; 912 case CAN_STATE_BUS_OFF: 913 /* from: BUS_OFF 914 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 915 */ 916 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 917 cf->can_id |= CAN_ERR_RESTARTED; 918 919 netdev_dbg(dev, "restarted\n"); 920 priv->can.can_stats.restarts++; 921 922 netif_carrier_on(dev); 923 netif_wake_queue(dev); 924 } 925 break; 926 default: 927 break; 928 } 929 930 /* process state changes depending on the new state */ 931 switch (new_state) { 932 case CAN_STATE_ERROR_ACTIVE: 933 /* actually we want to enable AT91_IRQ_WARN here, but 934 * it screws up the system under certain 935 * circumstances. so just enable AT91_IRQ_ERRP, thus 936 * the "fallthrough" 937 */ 938 netdev_dbg(dev, "Error Active\n"); 939 cf->can_id |= CAN_ERR_PROT; 940 cf->data[2] = CAN_ERR_PROT_ACTIVE; 941 fallthrough; 942 case CAN_STATE_ERROR_WARNING: 943 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 944 reg_ier = AT91_IRQ_ERRP; 945 break; 946 case CAN_STATE_ERROR_PASSIVE: 947 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 948 reg_ier = AT91_IRQ_BOFF; 949 break; 950 case CAN_STATE_BUS_OFF: 951 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 952 AT91_IRQ_WARN | AT91_IRQ_BOFF; 953 reg_ier = 0; 954 955 cf->can_id |= CAN_ERR_BUSOFF; 956 957 netdev_dbg(dev, "bus-off\n"); 958 netif_carrier_off(dev); 959 priv->can.can_stats.bus_off++; 960 961 /* turn off chip, if restart is disabled */ 962 if (!priv->can.restart_ms) { 963 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 964 return; 965 } 966 break; 967 default: 968 break; 969 } 970 971 at91_write(priv, AT91_IDR, reg_idr); 972 at91_write(priv, AT91_IER, reg_ier); 973 } 974 975 static int at91_get_state_by_bec(const struct net_device *dev, 976 enum can_state *state) 977 { 978 struct can_berr_counter bec; 979 int err; 980 981 err = at91_get_berr_counter(dev, &bec); 982 if (err) 983 return err; 984 985 if (bec.txerr < 96 && bec.rxerr < 96) 986 *state = CAN_STATE_ERROR_ACTIVE; 987 else if (bec.txerr < 128 && bec.rxerr < 128) 988 *state = CAN_STATE_ERROR_WARNING; 989 else if (bec.txerr < 256 && bec.rxerr < 256) 990 *state = CAN_STATE_ERROR_PASSIVE; 991 else 992 *state = CAN_STATE_BUS_OFF; 993 994 return 0; 995 } 996 997 static void at91_irq_err(struct net_device *dev) 998 { 999 struct at91_priv *priv = netdev_priv(dev); 1000 struct sk_buff *skb; 1001 struct can_frame *cf; 1002 enum can_state new_state; 1003 u32 reg_sr; 1004 int err; 1005 1006 if (at91_is_sam9263(priv)) { 1007 reg_sr = at91_read(priv, AT91_SR); 1008 1009 /* we need to look at the unmasked reg_sr */ 1010 if (unlikely(reg_sr & AT91_IRQ_BOFF)) { 1011 new_state = CAN_STATE_BUS_OFF; 1012 } else if (unlikely(reg_sr & AT91_IRQ_ERRP)) { 1013 new_state = CAN_STATE_ERROR_PASSIVE; 1014 } else if (unlikely(reg_sr & AT91_IRQ_WARN)) { 1015 new_state = CAN_STATE_ERROR_WARNING; 1016 } else if (likely(reg_sr & AT91_IRQ_ERRA)) { 1017 new_state = CAN_STATE_ERROR_ACTIVE; 1018 } else { 1019 netdev_err(dev, "BUG! hardware in undefined state\n"); 1020 return; 1021 } 1022 } else { 1023 err = at91_get_state_by_bec(dev, &new_state); 1024 if (err) 1025 return; 1026 } 1027 1028 /* state hasn't changed */ 1029 if (likely(new_state == priv->can.state)) 1030 return; 1031 1032 skb = alloc_can_err_skb(dev, &cf); 1033 if (unlikely(!skb)) 1034 return; 1035 1036 at91_irq_err_state(dev, cf, new_state); 1037 1038 netif_rx(skb); 1039 1040 priv->can.state = new_state; 1041 } 1042 1043 /* interrupt handler 1044 */ 1045 static irqreturn_t at91_irq(int irq, void *dev_id) 1046 { 1047 struct net_device *dev = dev_id; 1048 struct at91_priv *priv = netdev_priv(dev); 1049 irqreturn_t handled = IRQ_NONE; 1050 u32 reg_sr, reg_imr; 1051 1052 reg_sr = at91_read(priv, AT91_SR); 1053 reg_imr = at91_read(priv, AT91_IMR); 1054 1055 /* Ignore masked interrupts */ 1056 reg_sr &= reg_imr; 1057 if (!reg_sr) 1058 goto exit; 1059 1060 handled = IRQ_HANDLED; 1061 1062 /* Receive or error interrupt? -> napi */ 1063 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1064 /* The error bits are clear on read, 1065 * save for later use. 1066 */ 1067 priv->reg_sr = reg_sr; 1068 at91_write(priv, AT91_IDR, 1069 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1070 napi_schedule(&priv->napi); 1071 } 1072 1073 /* Transmission complete interrupt */ 1074 if (reg_sr & get_irq_mb_tx(priv)) 1075 at91_irq_tx(dev, reg_sr); 1076 1077 at91_irq_err(dev); 1078 1079 exit: 1080 return handled; 1081 } 1082 1083 static int at91_open(struct net_device *dev) 1084 { 1085 struct at91_priv *priv = netdev_priv(dev); 1086 int err; 1087 1088 err = clk_prepare_enable(priv->clk); 1089 if (err) 1090 return err; 1091 1092 /* check or determine and set bittime */ 1093 err = open_candev(dev); 1094 if (err) 1095 goto out; 1096 1097 /* register interrupt handler */ 1098 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1099 dev->name, dev)) { 1100 err = -EAGAIN; 1101 goto out_close; 1102 } 1103 1104 can_led_event(dev, CAN_LED_EVENT_OPEN); 1105 1106 /* start chip and queuing */ 1107 at91_chip_start(dev); 1108 napi_enable(&priv->napi); 1109 netif_start_queue(dev); 1110 1111 return 0; 1112 1113 out_close: 1114 close_candev(dev); 1115 out: 1116 clk_disable_unprepare(priv->clk); 1117 1118 return err; 1119 } 1120 1121 /* stop CAN bus activity 1122 */ 1123 static int at91_close(struct net_device *dev) 1124 { 1125 struct at91_priv *priv = netdev_priv(dev); 1126 1127 netif_stop_queue(dev); 1128 napi_disable(&priv->napi); 1129 at91_chip_stop(dev, CAN_STATE_STOPPED); 1130 1131 free_irq(dev->irq, dev); 1132 clk_disable_unprepare(priv->clk); 1133 1134 close_candev(dev); 1135 1136 can_led_event(dev, CAN_LED_EVENT_STOP); 1137 1138 return 0; 1139 } 1140 1141 static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1142 { 1143 switch (mode) { 1144 case CAN_MODE_START: 1145 at91_chip_start(dev); 1146 netif_wake_queue(dev); 1147 break; 1148 1149 default: 1150 return -EOPNOTSUPP; 1151 } 1152 1153 return 0; 1154 } 1155 1156 static const struct net_device_ops at91_netdev_ops = { 1157 .ndo_open = at91_open, 1158 .ndo_stop = at91_close, 1159 .ndo_start_xmit = at91_start_xmit, 1160 .ndo_change_mtu = can_change_mtu, 1161 }; 1162 1163 static ssize_t mb0_id_show(struct device *dev, 1164 struct device_attribute *attr, char *buf) 1165 { 1166 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1167 1168 if (priv->mb0_id & CAN_EFF_FLAG) 1169 return sysfs_emit(buf, "0x%08x\n", priv->mb0_id); 1170 else 1171 return sysfs_emit(buf, "0x%03x\n", priv->mb0_id); 1172 } 1173 1174 static ssize_t mb0_id_store(struct device *dev, 1175 struct device_attribute *attr, 1176 const char *buf, size_t count) 1177 { 1178 struct net_device *ndev = to_net_dev(dev); 1179 struct at91_priv *priv = netdev_priv(ndev); 1180 unsigned long can_id; 1181 ssize_t ret; 1182 int err; 1183 1184 rtnl_lock(); 1185 1186 if (ndev->flags & IFF_UP) { 1187 ret = -EBUSY; 1188 goto out; 1189 } 1190 1191 err = kstrtoul(buf, 0, &can_id); 1192 if (err) { 1193 ret = err; 1194 goto out; 1195 } 1196 1197 if (can_id & CAN_EFF_FLAG) 1198 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1199 else 1200 can_id &= CAN_SFF_MASK; 1201 1202 priv->mb0_id = can_id; 1203 ret = count; 1204 1205 out: 1206 rtnl_unlock(); 1207 return ret; 1208 } 1209 1210 static DEVICE_ATTR_RW(mb0_id); 1211 1212 static struct attribute *at91_sysfs_attrs[] = { 1213 &dev_attr_mb0_id.attr, 1214 NULL, 1215 }; 1216 1217 static const struct attribute_group at91_sysfs_attr_group = { 1218 .attrs = at91_sysfs_attrs, 1219 }; 1220 1221 #if defined(CONFIG_OF) 1222 static const struct of_device_id at91_can_dt_ids[] = { 1223 { 1224 .compatible = "atmel,at91sam9x5-can", 1225 .data = &at91_at91sam9x5_data, 1226 }, { 1227 .compatible = "atmel,at91sam9263-can", 1228 .data = &at91_at91sam9263_data, 1229 }, { 1230 /* sentinel */ 1231 } 1232 }; 1233 MODULE_DEVICE_TABLE(of, at91_can_dt_ids); 1234 #endif 1235 1236 static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev) 1237 { 1238 if (pdev->dev.of_node) { 1239 const struct of_device_id *match; 1240 1241 match = of_match_node(at91_can_dt_ids, pdev->dev.of_node); 1242 if (!match) { 1243 dev_err(&pdev->dev, "no matching node found in dtb\n"); 1244 return NULL; 1245 } 1246 return (const struct at91_devtype_data *)match->data; 1247 } 1248 return (const struct at91_devtype_data *) 1249 platform_get_device_id(pdev)->driver_data; 1250 } 1251 1252 static int at91_can_probe(struct platform_device *pdev) 1253 { 1254 const struct at91_devtype_data *devtype_data; 1255 struct net_device *dev; 1256 struct at91_priv *priv; 1257 struct resource *res; 1258 struct clk *clk; 1259 void __iomem *addr; 1260 int err, irq; 1261 1262 devtype_data = at91_can_get_driver_data(pdev); 1263 if (!devtype_data) { 1264 dev_err(&pdev->dev, "no driver data\n"); 1265 err = -ENODEV; 1266 goto exit; 1267 } 1268 1269 clk = clk_get(&pdev->dev, "can_clk"); 1270 if (IS_ERR(clk)) { 1271 dev_err(&pdev->dev, "no clock defined\n"); 1272 err = -ENODEV; 1273 goto exit; 1274 } 1275 1276 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1277 irq = platform_get_irq(pdev, 0); 1278 if (!res || irq <= 0) { 1279 err = -ENODEV; 1280 goto exit_put; 1281 } 1282 1283 if (!request_mem_region(res->start, 1284 resource_size(res), 1285 pdev->name)) { 1286 err = -EBUSY; 1287 goto exit_put; 1288 } 1289 1290 addr = ioremap(res->start, resource_size(res)); 1291 if (!addr) { 1292 err = -ENOMEM; 1293 goto exit_release; 1294 } 1295 1296 dev = alloc_candev(sizeof(struct at91_priv), 1297 1 << devtype_data->tx_shift); 1298 if (!dev) { 1299 err = -ENOMEM; 1300 goto exit_iounmap; 1301 } 1302 1303 dev->netdev_ops = &at91_netdev_ops; 1304 dev->irq = irq; 1305 dev->flags |= IFF_ECHO; 1306 1307 priv = netdev_priv(dev); 1308 priv->can.clock.freq = clk_get_rate(clk); 1309 priv->can.bittiming_const = &at91_bittiming_const; 1310 priv->can.do_set_mode = at91_set_mode; 1311 priv->can.do_get_berr_counter = at91_get_berr_counter; 1312 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1313 CAN_CTRLMODE_LISTENONLY; 1314 priv->reg_base = addr; 1315 priv->devtype_data = *devtype_data; 1316 priv->clk = clk; 1317 priv->pdata = dev_get_platdata(&pdev->dev); 1318 priv->mb0_id = 0x7ff; 1319 1320 netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv)); 1321 1322 if (at91_is_sam9263(priv)) 1323 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1324 1325 platform_set_drvdata(pdev, dev); 1326 SET_NETDEV_DEV(dev, &pdev->dev); 1327 1328 err = register_candev(dev); 1329 if (err) { 1330 dev_err(&pdev->dev, "registering netdev failed\n"); 1331 goto exit_free; 1332 } 1333 1334 devm_can_led_init(dev); 1335 1336 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1337 priv->reg_base, dev->irq); 1338 1339 return 0; 1340 1341 exit_free: 1342 free_candev(dev); 1343 exit_iounmap: 1344 iounmap(addr); 1345 exit_release: 1346 release_mem_region(res->start, resource_size(res)); 1347 exit_put: 1348 clk_put(clk); 1349 exit: 1350 return err; 1351 } 1352 1353 static int at91_can_remove(struct platform_device *pdev) 1354 { 1355 struct net_device *dev = platform_get_drvdata(pdev); 1356 struct at91_priv *priv = netdev_priv(dev); 1357 struct resource *res; 1358 1359 unregister_netdev(dev); 1360 1361 iounmap(priv->reg_base); 1362 1363 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1364 release_mem_region(res->start, resource_size(res)); 1365 1366 clk_put(priv->clk); 1367 1368 free_candev(dev); 1369 1370 return 0; 1371 } 1372 1373 static const struct platform_device_id at91_can_id_table[] = { 1374 { 1375 .name = "at91sam9x5_can", 1376 .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data, 1377 }, { 1378 .name = "at91_can", 1379 .driver_data = (kernel_ulong_t)&at91_at91sam9263_data, 1380 }, { 1381 /* sentinel */ 1382 } 1383 }; 1384 MODULE_DEVICE_TABLE(platform, at91_can_id_table); 1385 1386 static struct platform_driver at91_can_driver = { 1387 .probe = at91_can_probe, 1388 .remove = at91_can_remove, 1389 .driver = { 1390 .name = KBUILD_MODNAME, 1391 .of_match_table = of_match_ptr(at91_can_dt_ids), 1392 }, 1393 .id_table = at91_can_id_table, 1394 }; 1395 1396 module_platform_driver(at91_can_driver); 1397 1398 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1399 MODULE_LICENSE("GPL v2"); 1400 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1401