1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 #define XILINX_OP_SE 0x50 /* Sector erase */ 12 #define XILINX_OP_PP 0x82 /* Page program */ 13 #define XILINX_OP_RDSR 0xd7 /* Read status register */ 14 15 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ 16 #define XSR_RDY BIT(7) /* Ready */ 17 18 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ 19 .id = { \ 20 ((_jedec_id) >> 16) & 0xff, \ 21 ((_jedec_id) >> 8) & 0xff, \ 22 (_jedec_id) & 0xff \ 23 }, \ 24 .id_len = 3, \ 25 .sector_size = (8 * (_page_size)), \ 26 .n_sectors = (_n_sectors), \ 27 .page_size = (_page_size), \ 28 .addr_width = 3, \ 29 .flags = SPI_NOR_NO_FR 30 31 /* Xilinx S3AN share MFR with Atmel SPI NOR */ 32 static const struct flash_info xilinx_nor_parts[] = { 33 /* Xilinx S3AN Internal Flash */ 34 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) }, 35 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) }, 36 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) }, 37 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) }, 38 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, 39 }; 40 41 /* 42 * This code converts an address to the Default Address Mode, that has non 43 * power of two page sizes. We must support this mode because it is the default 44 * mode supported by Xilinx tools, it can access the whole flash area and 45 * changing over to the Power-of-two mode is irreversible and corrupts the 46 * original data. 47 * Addr can safely be unsigned int, the biggest S3AN device is smaller than 48 * 4 MiB. 49 */ 50 static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr) 51 { 52 u32 page_size = nor->params->page_size; 53 u32 offset, page; 54 55 offset = addr % page_size; 56 page = addr / page_size; 57 page <<= (page_size > 512) ? 10 : 9; 58 59 return page | offset; 60 } 61 62 /** 63 * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes. 64 * @nor: pointer to 'struct spi_nor'. 65 * @sr: pointer to a DMA-able buffer where the value of the 66 * Status Register will be written. 67 * 68 * Return: 0 on success, -errno otherwise. 69 */ 70 static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr) 71 { 72 int ret; 73 74 if (nor->spimem) { 75 struct spi_mem_op op = 76 SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), 77 SPI_MEM_OP_NO_ADDR, 78 SPI_MEM_OP_NO_DUMMY, 79 SPI_MEM_OP_DATA_IN(1, sr, 0)); 80 81 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 82 83 ret = spi_mem_exec_op(nor->spimem, &op); 84 } else { 85 ret = spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr, 86 1); 87 } 88 89 if (ret) 90 dev_dbg(nor->dev, "error %d reading SR\n", ret); 91 92 return ret; 93 } 94 95 /** 96 * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to see 97 * if the flash is ready for new commands. 98 * @nor: pointer to 'struct spi_nor'. 99 * 100 * Return: 1 if ready, 0 if not ready, -errno on errors. 101 */ 102 static int xilinx_nor_sr_ready(struct spi_nor *nor) 103 { 104 int ret; 105 106 ret = xilinx_nor_read_sr(nor, nor->bouncebuf); 107 if (ret) 108 return ret; 109 110 return !!(nor->bouncebuf[0] & XSR_RDY); 111 } 112 113 static int xilinx_nor_setup(struct spi_nor *nor, 114 const struct spi_nor_hwcaps *hwcaps) 115 { 116 u32 page_size; 117 int ret; 118 119 ret = xilinx_nor_read_sr(nor, nor->bouncebuf); 120 if (ret) 121 return ret; 122 123 nor->erase_opcode = XILINX_OP_SE; 124 nor->program_opcode = XILINX_OP_PP; 125 nor->read_opcode = SPINOR_OP_READ; 126 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 127 128 /* 129 * This flashes have a page size of 264 or 528 bytes (known as 130 * Default addressing mode). It can be changed to a more standard 131 * Power of two mode where the page size is 256/512. This comes 132 * with a price: there is 3% less of space, the data is corrupted 133 * and the page size cannot be changed back to default addressing 134 * mode. 135 * 136 * The current addressing mode can be read from the XRDSR register 137 * and should not be changed, because is a destructive operation. 138 */ 139 if (nor->bouncebuf[0] & XSR_PAGESIZE) { 140 /* Flash in Power of 2 mode */ 141 page_size = (nor->params->page_size == 264) ? 256 : 512; 142 nor->params->page_size = page_size; 143 nor->mtd.writebufsize = page_size; 144 nor->params->size = 8 * page_size * nor->info->n_sectors; 145 nor->mtd.erasesize = 8 * page_size; 146 } else { 147 /* Flash in Default addressing mode */ 148 nor->params->convert_addr = s3an_nor_convert_addr; 149 nor->mtd.erasesize = nor->info->sector_size; 150 } 151 152 return 0; 153 } 154 155 static void xilinx_nor_late_init(struct spi_nor *nor) 156 { 157 nor->params->setup = xilinx_nor_setup; 158 nor->params->ready = xilinx_nor_sr_ready; 159 } 160 161 static const struct spi_nor_fixups xilinx_nor_fixups = { 162 .late_init = xilinx_nor_late_init, 163 }; 164 165 const struct spi_nor_manufacturer spi_nor_xilinx = { 166 .name = "xilinx", 167 .parts = xilinx_nor_parts, 168 .nparts = ARRAY_SIZE(xilinx_nor_parts), 169 .fixups = &xilinx_nor_fixups, 170 }; 171