1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 #define XILINX_OP_SE 0x50 /* Sector erase */ 12 #define XILINX_OP_PP 0x82 /* Page program */ 13 #define XILINX_OP_RDSR 0xd7 /* Read status register */ 14 15 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ 16 #define XSR_RDY BIT(7) /* Ready */ 17 18 #define XILINX_RDSR_OP(buf) \ 19 SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), \ 20 SPI_MEM_OP_NO_ADDR, \ 21 SPI_MEM_OP_NO_DUMMY, \ 22 SPI_MEM_OP_DATA_IN(1, buf, 0)) 23 24 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ 25 .id = { \ 26 ((_jedec_id) >> 16) & 0xff, \ 27 ((_jedec_id) >> 8) & 0xff, \ 28 (_jedec_id) & 0xff \ 29 }, \ 30 .id_len = 3, \ 31 .sector_size = (8 * (_page_size)), \ 32 .n_sectors = (_n_sectors), \ 33 .page_size = (_page_size), \ 34 .addr_nbytes = 3, \ 35 .flags = SPI_NOR_NO_FR 36 37 /* Xilinx S3AN share MFR with Atmel SPI NOR */ 38 static const struct flash_info xilinx_nor_parts[] = { 39 /* Xilinx S3AN Internal Flash */ 40 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) }, 41 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) }, 42 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) }, 43 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) }, 44 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, 45 }; 46 47 /* 48 * This code converts an address to the Default Address Mode, that has non 49 * power of two page sizes. We must support this mode because it is the default 50 * mode supported by Xilinx tools, it can access the whole flash area and 51 * changing over to the Power-of-two mode is irreversible and corrupts the 52 * original data. 53 * Addr can safely be unsigned int, the biggest S3AN device is smaller than 54 * 4 MiB. 55 */ 56 static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr) 57 { 58 u32 page_size = nor->params->page_size; 59 u32 offset, page; 60 61 offset = addr % page_size; 62 page = addr / page_size; 63 page <<= (page_size > 512) ? 10 : 9; 64 65 return page | offset; 66 } 67 68 /** 69 * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes. 70 * @nor: pointer to 'struct spi_nor'. 71 * @sr: pointer to a DMA-able buffer where the value of the 72 * Status Register will be written. 73 * 74 * Return: 0 on success, -errno otherwise. 75 */ 76 static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr) 77 { 78 int ret; 79 80 if (nor->spimem) { 81 struct spi_mem_op op = XILINX_RDSR_OP(sr); 82 83 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 84 85 ret = spi_mem_exec_op(nor->spimem, &op); 86 } else { 87 ret = spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr, 88 1); 89 } 90 91 if (ret) 92 dev_dbg(nor->dev, "error %d reading SR\n", ret); 93 94 return ret; 95 } 96 97 /** 98 * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to see 99 * if the flash is ready for new commands. 100 * @nor: pointer to 'struct spi_nor'. 101 * 102 * Return: 1 if ready, 0 if not ready, -errno on errors. 103 */ 104 static int xilinx_nor_sr_ready(struct spi_nor *nor) 105 { 106 int ret; 107 108 ret = xilinx_nor_read_sr(nor, nor->bouncebuf); 109 if (ret) 110 return ret; 111 112 return !!(nor->bouncebuf[0] & XSR_RDY); 113 } 114 115 static int xilinx_nor_setup(struct spi_nor *nor, 116 const struct spi_nor_hwcaps *hwcaps) 117 { 118 u32 page_size; 119 int ret; 120 121 ret = xilinx_nor_read_sr(nor, nor->bouncebuf); 122 if (ret) 123 return ret; 124 125 nor->erase_opcode = XILINX_OP_SE; 126 nor->program_opcode = XILINX_OP_PP; 127 nor->read_opcode = SPINOR_OP_READ; 128 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 129 130 /* 131 * This flashes have a page size of 264 or 528 bytes (known as 132 * Default addressing mode). It can be changed to a more standard 133 * Power of two mode where the page size is 256/512. This comes 134 * with a price: there is 3% less of space, the data is corrupted 135 * and the page size cannot be changed back to default addressing 136 * mode. 137 * 138 * The current addressing mode can be read from the XRDSR register 139 * and should not be changed, because is a destructive operation. 140 */ 141 if (nor->bouncebuf[0] & XSR_PAGESIZE) { 142 /* Flash in Power of 2 mode */ 143 page_size = (nor->params->page_size == 264) ? 256 : 512; 144 nor->params->page_size = page_size; 145 nor->mtd.writebufsize = page_size; 146 nor->params->size = 8 * page_size * nor->info->n_sectors; 147 nor->mtd.erasesize = 8 * page_size; 148 } else { 149 /* Flash in Default addressing mode */ 150 nor->params->convert_addr = s3an_nor_convert_addr; 151 nor->mtd.erasesize = nor->info->sector_size; 152 } 153 154 return 0; 155 } 156 157 static void xilinx_nor_late_init(struct spi_nor *nor) 158 { 159 nor->params->setup = xilinx_nor_setup; 160 nor->params->ready = xilinx_nor_sr_ready; 161 } 162 163 static const struct spi_nor_fixups xilinx_nor_fixups = { 164 .late_init = xilinx_nor_late_init, 165 }; 166 167 const struct spi_nor_manufacturer spi_nor_xilinx = { 168 .name = "xilinx", 169 .parts = xilinx_nor_parts, 170 .nparts = ARRAY_SIZE(xilinx_nor_parts), 171 .fixups = &xilinx_nor_fixups, 172 }; 173