1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 static int 12 w25q256_post_bfpt_fixups(struct spi_nor *nor, 13 const struct sfdp_parameter_header *bfpt_header, 14 const struct sfdp_bfpt *bfpt, 15 struct spi_nor_flash_parameter *params) 16 { 17 /* 18 * W25Q256JV supports 4B opcodes but W25Q256FV does not. 19 * Unfortunately, Winbond has re-used the same JEDEC ID for both 20 * variants which prevents us from defining a new entry in the parts 21 * table. 22 * To differentiate between W25Q256JV and W25Q256FV check SFDP header 23 * version: only JV has JESD216A compliant structure (version 5). 24 */ 25 if (bfpt_header->major == SFDP_JESD216_MAJOR && 26 bfpt_header->minor == SFDP_JESD216A_MINOR) 27 nor->flags |= SNOR_F_4B_OPCODES; 28 29 return 0; 30 } 31 32 static struct spi_nor_fixups w25q256_fixups = { 33 .post_bfpt = w25q256_post_bfpt_fixups, 34 }; 35 36 static const struct flash_info winbond_parts[] = { 37 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 38 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 39 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, 40 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, 41 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 42 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, 43 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 44 { "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32, 45 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 46 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 47 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 48 { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32, 49 SECT_4K | SPI_NOR_DUAL_READ | 50 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | 51 SPI_NOR_HAS_TB) }, 52 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 53 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 54 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 55 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, 56 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, 57 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 58 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 59 { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64, 60 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 61 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 62 }, 63 { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64, 64 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 65 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 66 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 67 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 68 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, 69 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 70 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 71 { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, 72 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 73 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 74 { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256, 75 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 76 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 77 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 78 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, 79 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, 80 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, 81 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 82 .fixups = &w25q256_fixups }, 83 { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512, 84 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 85 { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, 86 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 87 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, 88 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, 89 }; 90 91 /** 92 * winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes. 93 * @nor: pointer to 'struct spi_nor'. 94 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 95 * address mode. 96 * 97 * Return: 0 on success, -errno otherwise. 98 */ 99 static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 100 { 101 int ret; 102 103 ret = spi_nor_set_4byte_addr_mode(nor, enable); 104 if (ret || enable) 105 return ret; 106 107 /* 108 * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address 109 * Register to be set to 1, so all 3-byte-address reads come from the 110 * second 16M. We must clear the register to enable normal behavior. 111 */ 112 ret = spi_nor_write_enable(nor); 113 if (ret) 114 return ret; 115 116 ret = spi_nor_write_ear(nor, 0); 117 if (ret) 118 return ret; 119 120 return spi_nor_write_disable(nor); 121 } 122 123 static void winbond_default_init(struct spi_nor *nor) 124 { 125 nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode; 126 } 127 128 static const struct spi_nor_fixups winbond_fixups = { 129 .default_init = winbond_default_init, 130 }; 131 132 const struct spi_nor_manufacturer spi_nor_winbond = { 133 .name = "winbond", 134 .parts = winbond_parts, 135 .nparts = ARRAY_SIZE(winbond_parts), 136 .fixups = &winbond_fixups, 137 }; 138