1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 #define WINBOND_NOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ 12 #define WINBOND_NOR_OP_WREAR 0xc5 /* Write Extended Address Register */ 13 14 #define WINBOND_NOR_WREAR_OP(buf) \ 15 SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_WREAR, 0), \ 16 SPI_MEM_OP_NO_ADDR, \ 17 SPI_MEM_OP_NO_DUMMY, \ 18 SPI_MEM_OP_DATA_OUT(1, buf, 0)) 19 20 static int 21 w25q256_post_bfpt_fixups(struct spi_nor *nor, 22 const struct sfdp_parameter_header *bfpt_header, 23 const struct sfdp_bfpt *bfpt) 24 { 25 /* 26 * W25Q256JV supports 4B opcodes but W25Q256FV does not. 27 * Unfortunately, Winbond has re-used the same JEDEC ID for both 28 * variants which prevents us from defining a new entry in the parts 29 * table. 30 * To differentiate between W25Q256JV and W25Q256FV check SFDP header 31 * version: only JV has JESD216A compliant structure (version 5). 32 */ 33 if (bfpt_header->major == SFDP_JESD216_MAJOR && 34 bfpt_header->minor == SFDP_JESD216A_MINOR) 35 nor->flags |= SNOR_F_4B_OPCODES; 36 37 return 0; 38 } 39 40 static const struct spi_nor_fixups w25q256_fixups = { 41 .post_bfpt = w25q256_post_bfpt_fixups, 42 }; 43 44 static const struct flash_info winbond_nor_parts[] = { 45 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 46 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1) 47 NO_SFDP_FLAGS(SECT_4K) }, 48 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2) 49 NO_SFDP_FLAGS(SECT_4K) }, 50 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4) 51 NO_SFDP_FLAGS(SECT_4K) }, 52 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8) 53 NO_SFDP_FLAGS(SECT_4K) }, 54 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16) 55 NO_SFDP_FLAGS(SECT_4K) }, 56 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32) 57 NO_SFDP_FLAGS(SECT_4K) }, 58 { "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32) 59 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 60 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 61 SPI_NOR_QUAD_READ) }, 62 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64) 63 NO_SFDP_FLAGS(SECT_4K) }, 64 { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32) 65 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 66 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 67 SPI_NOR_QUAD_READ) }, 68 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4) 69 NO_SFDP_FLAGS(SECT_4K) }, 70 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4) 71 NO_SFDP_FLAGS(SECT_4K) }, 72 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4) 73 NO_SFDP_FLAGS(SECT_4K) }, 74 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64) 75 NO_SFDP_FLAGS(SECT_4K) }, 76 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64) 77 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 78 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 79 OTP_INFO(256, 3, 0x1000, 0x1000) }, 80 { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64) 81 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 82 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 83 SPI_NOR_QUAD_READ) }, 84 { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64) 85 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 86 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 87 OTP_INFO(256, 3, 0x1000, 0x1000) }, 88 { "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128) 89 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 90 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 91 SPI_NOR_QUAD_READ) }, 92 { "w25q128jwm", INFO(0xef8018, 0, 64 * 1024, 256) 93 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 94 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 95 SPI_NOR_QUAD_READ) }, 96 { "w25q256jwm", INFO(0xef8019, 0, 64 * 1024, 512) 97 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 98 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 99 SPI_NOR_QUAD_READ) }, 100 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128) 101 NO_SFDP_FLAGS(SECT_4K) }, 102 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128) 103 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 104 SPI_NOR_QUAD_READ) }, 105 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128) 106 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 107 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 108 SPI_NOR_QUAD_READ) }, 109 { "w25q64jvm", INFO(0xef7017, 0, 64 * 1024, 128) 110 NO_SFDP_FLAGS(SECT_4K) }, 111 { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256) 112 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 113 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 114 SPI_NOR_QUAD_READ) }, 115 { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256) 116 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 117 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 118 SPI_NOR_QUAD_READ) }, 119 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16) 120 NO_SFDP_FLAGS(SECT_4K) }, 121 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16) 122 NO_SFDP_FLAGS(SECT_4K) }, 123 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256) 124 NO_SFDP_FLAGS(SECT_4K) }, 125 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512) 126 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 127 .fixups = &w25q256_fixups }, 128 { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512) 129 PARSE_SFDP }, 130 { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512) 131 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 132 SPI_NOR_QUAD_READ) }, 133 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024) 134 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ | 135 SPI_NOR_DUAL_READ) }, 136 { "w25q512nwq", INFO(0xef6020, 0, 0, 0) 137 PARSE_SFDP 138 OTP_INFO(256, 3, 0x1000, 0x1000) }, 139 { "w25q512nwm", INFO(0xef8020, 0, 64 * 1024, 1024) 140 PARSE_SFDP 141 OTP_INFO(256, 3, 0x1000, 0x1000) }, 142 { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024) 143 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 144 SPI_NOR_QUAD_READ) }, 145 }; 146 147 /** 148 * winbond_nor_write_ear() - Write Extended Address Register. 149 * @nor: pointer to 'struct spi_nor'. 150 * @ear: value to write to the Extended Address Register. 151 * 152 * Return: 0 on success, -errno otherwise. 153 */ 154 static int winbond_nor_write_ear(struct spi_nor *nor, u8 ear) 155 { 156 int ret; 157 158 nor->bouncebuf[0] = ear; 159 160 if (nor->spimem) { 161 struct spi_mem_op op = WINBOND_NOR_WREAR_OP(nor->bouncebuf); 162 163 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 164 165 ret = spi_mem_exec_op(nor->spimem, &op); 166 } else { 167 ret = spi_nor_controller_ops_write_reg(nor, 168 WINBOND_NOR_OP_WREAR, 169 nor->bouncebuf, 1); 170 } 171 172 if (ret) 173 dev_dbg(nor->dev, "error %d writing EAR\n", ret); 174 175 return ret; 176 } 177 178 /** 179 * winbond_nor_set_4byte_addr_mode() - Set 4-byte address mode for Winbond 180 * flashes. 181 * @nor: pointer to 'struct spi_nor'. 182 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 183 * address mode. 184 * 185 * Return: 0 on success, -errno otherwise. 186 */ 187 static int winbond_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 188 { 189 int ret; 190 191 ret = spi_nor_set_4byte_addr_mode(nor, enable); 192 if (ret || enable) 193 return ret; 194 195 /* 196 * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address 197 * Register to be set to 1, so all 3-byte-address reads come from the 198 * second 16M. We must clear the register to enable normal behavior. 199 */ 200 ret = spi_nor_write_enable(nor); 201 if (ret) 202 return ret; 203 204 ret = winbond_nor_write_ear(nor, 0); 205 if (ret) 206 return ret; 207 208 return spi_nor_write_disable(nor); 209 } 210 211 static const struct spi_nor_otp_ops winbond_nor_otp_ops = { 212 .read = spi_nor_otp_read_secr, 213 .write = spi_nor_otp_write_secr, 214 .erase = spi_nor_otp_erase_secr, 215 .lock = spi_nor_otp_lock_sr2, 216 .is_locked = spi_nor_otp_is_locked_sr2, 217 }; 218 219 static void winbond_nor_default_init(struct spi_nor *nor) 220 { 221 nor->params->set_4byte_addr_mode = winbond_nor_set_4byte_addr_mode; 222 } 223 224 static void winbond_nor_late_init(struct spi_nor *nor) 225 { 226 if (nor->params->otp.org->n_regions) 227 nor->params->otp.ops = &winbond_nor_otp_ops; 228 } 229 230 static const struct spi_nor_fixups winbond_nor_fixups = { 231 .default_init = winbond_nor_default_init, 232 .late_init = winbond_nor_late_init, 233 }; 234 235 const struct spi_nor_manufacturer spi_nor_winbond = { 236 .name = "winbond", 237 .parts = winbond_nor_parts, 238 .nparts = ARRAY_SIZE(winbond_nor_parts), 239 .fixups = &winbond_nor_fixups, 240 }; 241