1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ 12 #define USE_CLSR BIT(0) 13 14 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 15 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ 16 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ 17 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 18 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb 19 #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 20 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ 21 #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 22 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 23 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 24 #define SPINOR_OP_CYPRESS_RD_FAST 0xee 25 26 /** 27 * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. 28 * @nor: pointer to a 'struct spi_nor' 29 * @enable: whether to enable or disable Octal DTR 30 * 31 * This also sets the memory access latency cycles to 24 to allow the flash to 32 * run at up to 200MHz. 33 * 34 * Return: 0 on success, -errno otherwise. 35 */ 36 static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 37 { 38 struct spi_mem_op op; 39 u8 *buf = nor->bouncebuf; 40 int ret; 41 42 if (enable) { 43 /* Use 24 dummy cycles for memory array reads. */ 44 ret = spi_nor_write_enable(nor); 45 if (ret) 46 return ret; 47 48 *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; 49 op = (struct spi_mem_op) 50 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), 51 SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V, 52 1), 53 SPI_MEM_OP_NO_DUMMY, 54 SPI_MEM_OP_DATA_OUT(1, buf, 1)); 55 56 ret = spi_mem_exec_op(nor->spimem, &op); 57 if (ret) 58 return ret; 59 60 ret = spi_nor_wait_till_ready(nor); 61 if (ret) 62 return ret; 63 64 nor->read_dummy = 24; 65 } 66 67 /* Set/unset the octal and DTR enable bits. */ 68 ret = spi_nor_write_enable(nor); 69 if (ret) 70 return ret; 71 72 if (enable) { 73 buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; 74 } else { 75 /* 76 * The register is 1-byte wide, but 1-byte transactions are not 77 * allowed in 8D-8D-8D mode. Since there is no register at the 78 * next location, just initialize the value to 0 and let the 79 * transaction go on. 80 */ 81 buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; 82 buf[1] = 0; 83 } 84 85 op = (struct spi_mem_op) 86 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), 87 SPI_MEM_OP_ADDR(enable ? 3 : 4, 88 SPINOR_REG_CYPRESS_CFR5V, 89 1), 90 SPI_MEM_OP_NO_DUMMY, 91 SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); 92 93 if (!enable) 94 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); 95 96 ret = spi_mem_exec_op(nor->spimem, &op); 97 if (ret) 98 return ret; 99 100 /* Read flash ID to make sure the switch was successful. */ 101 op = (struct spi_mem_op) 102 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), 103 SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1), 104 SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1), 105 SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), 106 buf, 1)); 107 108 if (enable) 109 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); 110 111 ret = spi_mem_exec_op(nor->spimem, &op); 112 if (ret) 113 return ret; 114 115 if (memcmp(buf, nor->info->id, nor->info->id_len)) 116 return -EINVAL; 117 118 return 0; 119 } 120 121 static void s28hs512t_default_init(struct spi_nor *nor) 122 { 123 nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; 124 nor->params->writesize = 16; 125 } 126 127 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor) 128 { 129 /* 130 * On older versions of the flash the xSPI Profile 1.0 table has the 131 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. 132 */ 133 if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) 134 nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = 135 SPINOR_OP_CYPRESS_RD_FAST; 136 137 /* This flash is also missing the 4-byte Page Program opcode bit. */ 138 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], 139 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); 140 /* 141 * Since xSPI Page Program opcode is backward compatible with 142 * Legacy SPI, use Legacy SPI opcode there as well. 143 */ 144 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR], 145 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); 146 147 /* 148 * The xSPI Profile 1.0 table advertises the number of additional 149 * address bytes needed for Read Status Register command as 0 but the 150 * actual value for that is 4. 151 */ 152 nor->params->rdsr_addr_nbytes = 4; 153 } 154 155 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor, 156 const struct sfdp_parameter_header *bfpt_header, 157 const struct sfdp_bfpt *bfpt) 158 { 159 /* 160 * The BFPT table advertises a 512B page size but the page size is 161 * actually configurable (with the default being 256B). Read from 162 * CFR3V[4] and set the correct size. 163 */ 164 struct spi_mem_op op = 165 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), 166 SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR3V, 1), 167 SPI_MEM_OP_NO_DUMMY, 168 SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); 169 int ret; 170 171 ret = spi_mem_exec_op(nor->spimem, &op); 172 if (ret) 173 return ret; 174 175 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ) 176 nor->params->page_size = 512; 177 else 178 nor->params->page_size = 256; 179 180 return 0; 181 } 182 183 static const struct spi_nor_fixups s28hs512t_fixups = { 184 .default_init = s28hs512t_default_init, 185 .post_sfdp = s28hs512t_post_sfdp_fixup, 186 .post_bfpt = s28hs512t_post_bfpt_fixup, 187 }; 188 189 static int 190 s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor, 191 const struct sfdp_parameter_header *bfpt_header, 192 const struct sfdp_bfpt *bfpt) 193 { 194 /* 195 * The S25FS-S chip family reports 512-byte pages in BFPT but 196 * in reality the write buffer still wraps at the safe default 197 * of 256 bytes. Overwrite the page size advertised by BFPT 198 * to get the writes working. 199 */ 200 nor->params->page_size = 256; 201 202 return 0; 203 } 204 205 static const struct spi_nor_fixups s25fs_s_nor_fixups = { 206 .post_bfpt = s25fs_s_nor_post_bfpt_fixups, 207 }; 208 209 static const struct flash_info spansion_nor_parts[] = { 210 /* Spansion/Cypress -- single (large) sector size only, at least 211 * for the chips listed here (without boot sectors). 212 */ 213 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64) 214 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 215 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128) 216 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 217 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64) 218 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 219 MFR_FLAGS(USE_CLSR) 220 }, 221 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256) 222 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 223 MFR_FLAGS(USE_CLSR) 224 }, 225 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128) 226 NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | 227 SPI_NOR_QUAD_READ) 228 MFR_FLAGS(USE_CLSR) 229 }, 230 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512) 231 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 232 MFR_FLAGS(USE_CLSR) 233 }, 234 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256) 235 FLAGS(SPI_NOR_HAS_LOCK) 236 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 237 MFR_FLAGS(USE_CLSR) 238 }, 239 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256) 240 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 241 MFR_FLAGS(USE_CLSR) 242 .fixups = &s25fs_s_nor_fixups, }, 243 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128) 244 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 245 MFR_FLAGS(USE_CLSR) 246 }, 247 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512) 248 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 249 MFR_FLAGS(USE_CLSR) 250 }, 251 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256) 252 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 253 MFR_FLAGS(USE_CLSR) 254 .fixups = &s25fs_s_nor_fixups, }, 255 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) }, 256 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) }, 257 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64) 258 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 259 MFR_FLAGS(USE_CLSR) 260 }, 261 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256) 262 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 263 MFR_FLAGS(USE_CLSR) 264 }, 265 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) }, 266 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) }, 267 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) }, 268 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) }, 269 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) }, 270 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8) 271 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 272 SPI_NOR_QUAD_READ) }, 273 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16) 274 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 275 SPI_NOR_QUAD_READ) }, 276 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32) 277 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 278 SPI_NOR_QUAD_READ) }, 279 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128) 280 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 281 SPI_NOR_QUAD_READ) }, 282 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32) 283 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 284 SPI_NOR_QUAD_READ) }, 285 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64) 286 NO_SFDP_FLAGS(SECT_4K) }, 287 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128) 288 NO_SFDP_FLAGS(SECT_4K) }, 289 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8) 290 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) }, 291 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16) 292 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) }, 293 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128) 294 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 295 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 296 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256) 297 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 298 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 299 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512) 300 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 301 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 302 { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) 303 FLAGS(SPI_NOR_NO_ERASE) }, 304 { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) 305 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ | 306 SPI_NOR_OCTAL_DTR_PP) 307 .fixups = &s28hs512t_fixups, 308 }, 309 }; 310 311 /** 312 * spansion_nor_clear_sr() - Clear the Status Register. 313 * @nor: pointer to 'struct spi_nor'. 314 */ 315 static void spansion_nor_clear_sr(struct spi_nor *nor) 316 { 317 int ret; 318 319 if (nor->spimem) { 320 struct spi_mem_op op = 321 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), 322 SPI_MEM_OP_NO_ADDR, 323 SPI_MEM_OP_NO_DUMMY, 324 SPI_MEM_OP_NO_DATA); 325 326 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 327 328 ret = spi_mem_exec_op(nor->spimem, &op); 329 } else { 330 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, 331 NULL, 0); 332 } 333 334 if (ret) 335 dev_dbg(nor->dev, "error %d clearing SR\n", ret); 336 } 337 338 /** 339 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the 340 * flash is ready for new commands and clear it if there are any errors. 341 * @nor: pointer to 'struct spi_nor'. 342 * 343 * Return: 1 if ready, 0 if not ready, -errno on errors. 344 */ 345 static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor) 346 { 347 int ret; 348 349 ret = spi_nor_read_sr(nor, nor->bouncebuf); 350 if (ret) 351 return ret; 352 353 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 354 if (nor->bouncebuf[0] & SR_E_ERR) 355 dev_err(nor->dev, "Erase Error occurred\n"); 356 else 357 dev_err(nor->dev, "Programming Error occurred\n"); 358 359 spansion_nor_clear_sr(nor); 360 361 /* 362 * WEL bit remains set to one when an erase or page program 363 * error occurs. Issue a Write Disable command to protect 364 * against inadvertent writes that can possibly corrupt the 365 * contents of the memory. 366 */ 367 ret = spi_nor_write_disable(nor); 368 if (ret) 369 return ret; 370 371 return -EIO; 372 } 373 374 return !(nor->bouncebuf[0] & SR_WIP); 375 } 376 377 static void spansion_nor_late_init(struct spi_nor *nor) 378 { 379 if (nor->params->size > SZ_16M) { 380 nor->flags |= SNOR_F_4B_OPCODES; 381 /* No small sector erase for 4-byte command set */ 382 nor->erase_opcode = SPINOR_OP_SE; 383 nor->mtd.erasesize = nor->info->sector_size; 384 } 385 386 if (nor->info->mfr_flags & USE_CLSR) 387 nor->params->ready = spansion_nor_sr_ready_and_clear; 388 } 389 390 static const struct spi_nor_fixups spansion_nor_fixups = { 391 .late_init = spansion_nor_late_init, 392 }; 393 394 const struct spi_nor_manufacturer spi_nor_spansion = { 395 .name = "spansion", 396 .parts = spansion_nor_parts, 397 .nparts = ARRAY_SIZE(spansion_nor_parts), 398 .fixups = &spansion_nor_fixups, 399 }; 400