1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 static int 12 s25fs_s_post_bfpt_fixups(struct spi_nor *nor, 13 const struct sfdp_parameter_header *bfpt_header, 14 const struct sfdp_bfpt *bfpt, 15 struct spi_nor_flash_parameter *params) 16 { 17 /* 18 * The S25FS-S chip family reports 512-byte pages in BFPT but 19 * in reality the write buffer still wraps at the safe default 20 * of 256 bytes. Overwrite the page size advertised by BFPT 21 * to get the writes working. 22 */ 23 params->page_size = 256; 24 25 return 0; 26 } 27 28 static struct spi_nor_fixups s25fs_s_fixups = { 29 .post_bfpt = s25fs_s_post_bfpt_fixups, 30 }; 31 32 static const struct flash_info spansion_parts[] = { 33 /* Spansion/Cypress -- single (large) sector size only, at least 34 * for the chips listed here (without boot sectors). 35 */ 36 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 37 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 38 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 39 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 40 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, 41 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 42 USE_CLSR) }, 43 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, 44 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 45 USE_CLSR) }, 46 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128, 47 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 48 USE_CLSR) }, 49 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512, 50 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 51 USE_CLSR) }, 52 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256, 53 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 54 SPI_NOR_HAS_LOCK | USE_CLSR) }, 55 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256, 56 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) 57 .fixups = &s25fs_s_fixups, }, 58 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128, 59 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 60 USE_CLSR) }, 61 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 62 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 63 USE_CLSR) }, 64 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, 65 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) 66 .fixups = &s25fs_s_fixups, }, 67 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 68 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 69 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 70 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 71 USE_CLSR) }, 72 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 73 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 74 USE_CLSR) }, 75 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, 76 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 77 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 78 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 79 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 80 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, 81 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 82 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, 83 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 84 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, 85 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 86 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, 87 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 88 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, 89 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 90 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, 91 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, 92 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, 93 SECT_4K | SPI_NOR_DUAL_READ) }, 94 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, 95 SECT_4K | SPI_NOR_DUAL_READ) }, 96 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, 97 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 98 SPI_NOR_4B_OPCODES) }, 99 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, 100 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 101 SPI_NOR_4B_OPCODES) }, 102 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, 103 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 104 SPI_NOR_4B_OPCODES) }, 105 { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1, 106 SPI_NOR_NO_ERASE) }, 107 }; 108 109 static void spansion_post_sfdp_fixups(struct spi_nor *nor) 110 { 111 if (nor->params->size <= SZ_16M) 112 return; 113 114 nor->flags |= SNOR_F_4B_OPCODES; 115 /* No small sector erase for 4-byte command set */ 116 nor->erase_opcode = SPINOR_OP_SE; 117 nor->mtd.erasesize = nor->info->sector_size; 118 } 119 120 static const struct spi_nor_fixups spansion_fixups = { 121 .post_sfdp = spansion_post_sfdp_fixups, 122 }; 123 124 const struct spi_nor_manufacturer spi_nor_spansion = { 125 .name = "spansion", 126 .parts = spansion_parts, 127 .nparts = ARRAY_SIZE(spansion_parts), 128 .fixups = &spansion_fixups, 129 }; 130