1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ 12 #define USE_CLSR BIT(0) 13 14 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 15 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ 16 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ 17 #define SPINOR_REG_CYPRESS_VREG 0x00800000 18 #define SPINOR_REG_CYPRESS_STR1 0x0 19 #define SPINOR_REG_CYPRESS_STR1V \ 20 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1) 21 #define SPINOR_REG_CYPRESS_CFR1 0x2 22 #define SPINOR_REG_CYPRESS_CFR1V \ 23 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR1) 24 #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ 25 #define SPINOR_REG_CYPRESS_CFR2 0x3 26 #define SPINOR_REG_CYPRESS_CFR2V \ 27 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2) 28 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb 29 #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) 30 #define SPINOR_REG_CYPRESS_CFR3 0x4 31 #define SPINOR_REG_CYPRESS_CFR3V \ 32 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR3) 33 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ 34 #define SPINOR_REG_CYPRESS_CFR5 0x6 35 #define SPINOR_REG_CYPRESS_CFR5V \ 36 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR5) 37 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) 38 #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) 39 #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) 40 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ 41 (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ 42 SPINOR_REG_CYPRESS_CFR5_OPI) 43 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 44 #define SPINOR_OP_CYPRESS_RD_FAST 0xee 45 #define SPINOR_REG_CYPRESS_ARCFN 0x00000006 46 47 /* Cypress SPI NOR flash operations. */ 48 #define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ 49 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ 50 SPI_MEM_OP_ADDR(naddr, addr, 0), \ 51 SPI_MEM_OP_NO_DUMMY, \ 52 SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) 53 54 #define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, ndummy, buf) \ 55 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \ 56 SPI_MEM_OP_ADDR(naddr, addr, 0), \ 57 SPI_MEM_OP_DUMMY(ndummy, 0), \ 58 SPI_MEM_OP_DATA_IN(1, buf, 0)) 59 60 #define SPANSION_CLSR_OP \ 61 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \ 62 SPI_MEM_OP_NO_ADDR, \ 63 SPI_MEM_OP_NO_DUMMY, \ 64 SPI_MEM_OP_NO_DATA) 65 66 /** 67 * spansion_nor_clear_sr() - Clear the Status Register. 68 * @nor: pointer to 'struct spi_nor'. 69 */ 70 static void spansion_nor_clear_sr(struct spi_nor *nor) 71 { 72 int ret; 73 74 if (nor->spimem) { 75 struct spi_mem_op op = SPANSION_CLSR_OP; 76 77 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 78 79 ret = spi_mem_exec_op(nor->spimem, &op); 80 } else { 81 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, 82 NULL, 0); 83 } 84 85 if (ret) 86 dev_dbg(nor->dev, "error %d clearing SR\n", ret); 87 } 88 89 static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 addr) 90 { 91 struct spi_mem_op op = 92 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, addr, 93 0, nor->bouncebuf); 94 int ret; 95 96 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 97 if (ret) 98 return ret; 99 100 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 101 if (nor->bouncebuf[0] & SR_E_ERR) 102 dev_err(nor->dev, "Erase Error occurred\n"); 103 else 104 dev_err(nor->dev, "Programming Error occurred\n"); 105 106 spansion_nor_clear_sr(nor); 107 108 ret = spi_nor_write_disable(nor); 109 if (ret) 110 return ret; 111 112 return -EIO; 113 } 114 115 return !(nor->bouncebuf[0] & SR_WIP); 116 } 117 /** 118 * cypress_nor_sr_ready_and_clear() - Query the Status Register of each die by 119 * using Read Any Register command to see if the whole flash is ready for new 120 * commands and clear it if there are any errors. 121 * @nor: pointer to 'struct spi_nor'. 122 * 123 * Return: 1 if ready, 0 if not ready, -errno on errors. 124 */ 125 static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor) 126 { 127 struct spi_nor_flash_parameter *params = nor->params; 128 u64 addr; 129 int ret; 130 u8 i; 131 132 for (i = 0; i < params->n_dice; i++) { 133 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1; 134 ret = cypress_nor_sr_ready_and_clear_reg(nor, addr); 135 if (ret < 0) 136 return ret; 137 else if (ret == 0) 138 return 0; 139 } 140 141 return 1; 142 } 143 144 static int cypress_nor_octal_dtr_en(struct spi_nor *nor) 145 { 146 struct spi_mem_op op; 147 u8 *buf = nor->bouncebuf; 148 int ret; 149 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; 150 151 /* Use 24 dummy cycles for memory array reads. */ 152 *buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; 153 op = (struct spi_mem_op) 154 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, 155 SPINOR_REG_CYPRESS_CFR2V, 1, buf); 156 157 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 158 if (ret) 159 return ret; 160 161 nor->read_dummy = 24; 162 163 /* Set the octal and DTR enable bits. */ 164 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; 165 op = (struct spi_mem_op) 166 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, 167 SPINOR_REG_CYPRESS_CFR5V, 1, buf); 168 169 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 170 if (ret) 171 return ret; 172 173 /* Read flash ID to make sure the switch was successful. */ 174 ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, 175 SNOR_PROTO_8_8_8_DTR); 176 if (ret) { 177 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); 178 return ret; 179 } 180 181 if (memcmp(buf, nor->info->id, nor->info->id_len)) 182 return -EINVAL; 183 184 return 0; 185 } 186 187 static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) 188 { 189 struct spi_mem_op op; 190 u8 *buf = nor->bouncebuf; 191 int ret; 192 193 /* 194 * The register is 1-byte wide, but 1-byte transactions are not allowed 195 * in 8D-8D-8D mode. Since there is no register at the next location, 196 * just initialize the value to 0 and let the transaction go on. 197 */ 198 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; 199 buf[1] = 0; 200 op = (struct spi_mem_op) 201 CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, 202 SPINOR_REG_CYPRESS_CFR5V, 2, buf); 203 ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); 204 if (ret) 205 return ret; 206 207 /* Read flash ID to make sure the switch was successful. */ 208 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); 209 if (ret) { 210 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); 211 return ret; 212 } 213 214 if (memcmp(buf, nor->info->id, nor->info->id_len)) 215 return -EINVAL; 216 217 return 0; 218 } 219 220 static int cypress_nor_quad_enable_volatile_reg(struct spi_nor *nor, u64 addr) 221 { 222 struct spi_mem_op op; 223 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; 224 u8 cfr1v_written; 225 int ret; 226 227 op = (struct spi_mem_op) 228 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, 229 nor->bouncebuf); 230 231 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 232 if (ret) 233 return ret; 234 235 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) 236 return 0; 237 238 /* Update the Quad Enable bit. */ 239 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; 240 op = (struct spi_mem_op) 241 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, 242 nor->bouncebuf); 243 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 244 if (ret) 245 return ret; 246 247 cfr1v_written = nor->bouncebuf[0]; 248 249 /* Read back and check it. */ 250 op = (struct spi_mem_op) 251 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, 252 nor->bouncebuf); 253 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 254 if (ret) 255 return ret; 256 257 if (nor->bouncebuf[0] != cfr1v_written) { 258 dev_err(nor->dev, "CFR1: Read back test failed\n"); 259 return -EIO; 260 } 261 262 return 0; 263 } 264 265 /** 266 * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile 267 * register. 268 * @nor: pointer to a 'struct spi_nor' 269 * 270 * It is recommended to update volatile registers in the field application due 271 * to a risk of the non-volatile registers corruption by power interrupt. This 272 * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable 273 * bit in the CFR1 non-volatile in advance (typically by a Flash programmer 274 * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is 275 * also set during Flash power-up. 276 * 277 * Return: 0 on success, -errno otherwise. 278 */ 279 static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) 280 { 281 struct spi_nor_flash_parameter *params = nor->params; 282 u64 addr; 283 u8 i; 284 int ret; 285 286 if (!params->n_dice) 287 return cypress_nor_quad_enable_volatile_reg(nor, 288 SPINOR_REG_CYPRESS_CFR1V); 289 290 for (i = 0; i < params->n_dice; i++) { 291 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; 292 ret = cypress_nor_quad_enable_volatile_reg(nor, addr); 293 if (ret) 294 return ret; 295 } 296 297 return 0; 298 } 299 300 /** 301 * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mode 302 * (3 or 4-byte) by querying status 303 * register 1 (SR1). 304 * @nor: pointer to a 'struct spi_nor' 305 * @addr_mode: ponter to a buffer where we return the determined 306 * address mode. 307 * 308 * This function tries to determine current address mode by comparing SR1 value 309 * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address). 310 * 311 * Return: 0 on success, -errno otherwise. 312 */ 313 static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor, 314 u8 *addr_mode) 315 { 316 struct spi_mem_op op = 317 CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0, 318 nor->bouncebuf); 319 bool is3byte, is4byte; 320 int ret; 321 322 ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]); 323 if (ret) 324 return ret; 325 326 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 327 if (ret) 328 return ret; 329 330 is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); 331 332 op = (struct spi_mem_op) 333 CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0, 334 nor->bouncebuf); 335 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 336 if (ret) 337 return ret; 338 339 is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); 340 341 if (is3byte == is4byte) 342 return -EIO; 343 if (is3byte) 344 *addr_mode = 3; 345 else 346 *addr_mode = 4; 347 348 return 0; 349 } 350 351 /** 352 * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mode of 353 * current address mode. 354 * @nor: pointer to a 'struct spi_nor' 355 * 356 * Determine current address mode by reading SR1 with different methods, then 357 * query CFR2V[7] to confirm. If determination is failed, force enter to 4-byte 358 * address mode. 359 * 360 * Return: 0 on success, -errno otherwise. 361 */ 362 static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor) 363 { 364 struct spi_mem_op op; 365 u8 addr_mode; 366 int ret; 367 368 /* 369 * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable 370 * that sets bit-1 in SR1. 371 */ 372 ret = spi_nor_write_enable(nor); 373 if (ret) 374 return ret; 375 ret = cypress_nor_determine_addr_mode_by_sr1(nor, &addr_mode); 376 if (ret) { 377 ret = spi_nor_set_4byte_addr_mode(nor, true); 378 if (ret) 379 return ret; 380 return spi_nor_write_disable(nor); 381 } 382 ret = spi_nor_write_disable(nor); 383 if (ret) 384 return ret; 385 386 /* 387 * Query CFR2V and make sure no contradiction between determined address 388 * mode and CFR2V[7]. 389 */ 390 op = (struct spi_mem_op) 391 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode, SPINOR_REG_CYPRESS_CFR2V, 392 0, nor->bouncebuf); 393 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 394 if (ret) 395 return ret; 396 397 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { 398 if (addr_mode != 4) 399 return spi_nor_set_4byte_addr_mode(nor, true); 400 } else { 401 if (addr_mode != 3) 402 return spi_nor_set_4byte_addr_mode(nor, true); 403 } 404 405 nor->params->addr_nbytes = addr_mode; 406 nor->params->addr_mode_nbytes = addr_mode; 407 408 return 0; 409 } 410 411 static int cypress_nor_get_page_size_single_chip(struct spi_nor *nor) 412 { 413 struct spi_mem_op op = 414 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, 415 SPINOR_REG_CYPRESS_CFR3V, 0, 416 nor->bouncebuf); 417 int ret; 418 419 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 420 if (ret) 421 return ret; 422 423 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) 424 nor->params->page_size = 512; 425 else 426 nor->params->page_size = 256; 427 428 return 0; 429 } 430 431 432 static int cypress_nor_get_page_size_mcp(struct spi_nor *nor) 433 { 434 struct spi_mem_op op = 435 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, 436 0, 0, nor->bouncebuf); 437 struct spi_nor_flash_parameter *params = nor->params; 438 int ret; 439 u8 i; 440 441 /* 442 * Use the minimum common page size configuration. Programming 256-byte 443 * under 512-byte page size configuration is safe. 444 */ 445 params->page_size = 256; 446 for (i = 0; i < params->n_dice; i++) { 447 op.addr.val = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR3; 448 449 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 450 if (ret) 451 return ret; 452 453 if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ)) 454 return 0; 455 } 456 457 params->page_size = 512; 458 459 return 0; 460 } 461 462 /** 463 * cypress_nor_get_page_size() - Get flash page size configuration. 464 * @nor: pointer to a 'struct spi_nor' 465 * 466 * The BFPT table advertises a 512B or 256B page size depending on part but the 467 * page size is actually configurable (with the default being 256B). Read from 468 * CFR3V[4] and set the correct size. 469 * 470 * Return: 0 on success, -errno otherwise. 471 */ 472 static int cypress_nor_get_page_size(struct spi_nor *nor) 473 { 474 if (nor->params->n_dice) 475 return cypress_nor_get_page_size_mcp(nor); 476 return cypress_nor_get_page_size_single_chip(nor); 477 } 478 479 static void cypress_nor_ecc_init(struct spi_nor *nor) 480 { 481 /* 482 * Programming is supported only in 16-byte ECC data unit granularity. 483 * Byte-programming, bit-walking, or multiple program operations to the 484 * same ECC data unit without an erase are not allowed. 485 */ 486 nor->params->writesize = 16; 487 nor->flags |= SNOR_F_ECC; 488 } 489 490 static int 491 s25fs256t_post_bfpt_fixup(struct spi_nor *nor, 492 const struct sfdp_parameter_header *bfpt_header, 493 const struct sfdp_bfpt *bfpt) 494 { 495 struct spi_mem_op op; 496 int ret; 497 498 ret = cypress_nor_set_addr_mode_nbytes(nor); 499 if (ret) 500 return ret; 501 502 /* Read Architecture Configuration Register (ARCFN) */ 503 op = (struct spi_mem_op) 504 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, 505 SPINOR_REG_CYPRESS_ARCFN, 1, 506 nor->bouncebuf); 507 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 508 if (ret) 509 return ret; 510 511 /* ARCFN value must be 0 if uniform sector is selected */ 512 if (nor->bouncebuf[0]) 513 return -ENODEV; 514 515 return cypress_nor_get_page_size(nor); 516 } 517 518 static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) 519 { 520 struct spi_nor_flash_parameter *params = nor->params; 521 522 /* PP_1_1_4_4B is supported but missing in 4BAIT. */ 523 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 524 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 525 SPINOR_OP_PP_1_1_4_4B, 526 SNOR_PROTO_1_1_4); 527 528 return 0; 529 } 530 531 static void s25fs256t_late_init(struct spi_nor *nor) 532 { 533 cypress_nor_ecc_init(nor); 534 } 535 536 static struct spi_nor_fixups s25fs256t_fixups = { 537 .post_bfpt = s25fs256t_post_bfpt_fixup, 538 .post_sfdp = s25fs256t_post_sfdp_fixup, 539 .late_init = s25fs256t_late_init, 540 }; 541 542 static int 543 s25hx_t_post_bfpt_fixup(struct spi_nor *nor, 544 const struct sfdp_parameter_header *bfpt_header, 545 const struct sfdp_bfpt *bfpt) 546 { 547 int ret; 548 549 ret = cypress_nor_set_addr_mode_nbytes(nor); 550 if (ret) 551 return ret; 552 553 /* Replace Quad Enable with volatile version */ 554 nor->params->quad_enable = cypress_nor_quad_enable_volatile; 555 556 return 0; 557 } 558 559 static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) 560 { 561 struct spi_nor_erase_type *erase_type = 562 nor->params->erase_map.erase_type; 563 unsigned int i; 564 565 /* 566 * In some parts, 3byte erase opcodes are advertised by 4BAIT. 567 * Convert them to 4byte erase opcodes. 568 */ 569 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 570 switch (erase_type[i].opcode) { 571 case SPINOR_OP_SE: 572 erase_type[i].opcode = SPINOR_OP_SE_4B; 573 break; 574 case SPINOR_OP_BE_4K: 575 erase_type[i].opcode = SPINOR_OP_BE_4K_4B; 576 break; 577 default: 578 break; 579 } 580 } 581 582 /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ 583 if (nor->params->size == SZ_256M) 584 nor->params->n_dice = 2; 585 586 return cypress_nor_get_page_size(nor); 587 } 588 589 static void s25hx_t_late_init(struct spi_nor *nor) 590 { 591 struct spi_nor_flash_parameter *params = nor->params; 592 593 /* Fast Read 4B requires mode cycles */ 594 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; 595 596 cypress_nor_ecc_init(nor); 597 598 /* Replace ready() with multi die version */ 599 if (params->n_dice) 600 params->ready = cypress_nor_sr_ready_and_clear; 601 } 602 603 static struct spi_nor_fixups s25hx_t_fixups = { 604 .post_bfpt = s25hx_t_post_bfpt_fixup, 605 .post_sfdp = s25hx_t_post_sfdp_fixup, 606 .late_init = s25hx_t_late_init, 607 }; 608 609 /** 610 * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. 611 * @nor: pointer to a 'struct spi_nor' 612 * @enable: whether to enable or disable Octal DTR 613 * 614 * This also sets the memory access latency cycles to 24 to allow the flash to 615 * run at up to 200MHz. 616 * 617 * Return: 0 on success, -errno otherwise. 618 */ 619 static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 620 { 621 return enable ? cypress_nor_octal_dtr_en(nor) : 622 cypress_nor_octal_dtr_dis(nor); 623 } 624 625 static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) 626 { 627 /* 628 * On older versions of the flash the xSPI Profile 1.0 table has the 629 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. 630 */ 631 if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) 632 nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = 633 SPINOR_OP_CYPRESS_RD_FAST; 634 635 /* This flash is also missing the 4-byte Page Program opcode bit. */ 636 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], 637 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); 638 /* 639 * Since xSPI Page Program opcode is backward compatible with 640 * Legacy SPI, use Legacy SPI opcode there as well. 641 */ 642 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR], 643 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); 644 645 /* 646 * The xSPI Profile 1.0 table advertises the number of additional 647 * address bytes needed for Read Status Register command as 0 but the 648 * actual value for that is 4. 649 */ 650 nor->params->rdsr_addr_nbytes = 4; 651 652 return cypress_nor_get_page_size(nor); 653 } 654 655 static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, 656 const struct sfdp_parameter_header *bfpt_header, 657 const struct sfdp_bfpt *bfpt) 658 { 659 int ret; 660 661 ret = cypress_nor_set_addr_mode_nbytes(nor); 662 if (ret) 663 return ret; 664 665 return 0; 666 } 667 668 static void s28hx_t_late_init(struct spi_nor *nor) 669 { 670 nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; 671 cypress_nor_ecc_init(nor); 672 } 673 674 static const struct spi_nor_fixups s28hx_t_fixups = { 675 .post_sfdp = s28hx_t_post_sfdp_fixup, 676 .post_bfpt = s28hx_t_post_bfpt_fixup, 677 .late_init = s28hx_t_late_init, 678 }; 679 680 static int 681 s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor, 682 const struct sfdp_parameter_header *bfpt_header, 683 const struct sfdp_bfpt *bfpt) 684 { 685 /* 686 * The S25FS-S chip family reports 512-byte pages in BFPT but 687 * in reality the write buffer still wraps at the safe default 688 * of 256 bytes. Overwrite the page size advertised by BFPT 689 * to get the writes working. 690 */ 691 nor->params->page_size = 256; 692 693 return 0; 694 } 695 696 static const struct spi_nor_fixups s25fs_s_nor_fixups = { 697 .post_bfpt = s25fs_s_nor_post_bfpt_fixups, 698 }; 699 700 static const struct flash_info spansion_nor_parts[] = { 701 /* Spansion/Cypress -- single (large) sector size only, at least 702 * for the chips listed here (without boot sectors). 703 */ 704 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64) 705 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 706 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128) 707 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 708 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64) 709 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 710 MFR_FLAGS(USE_CLSR) 711 }, 712 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256) 713 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 714 MFR_FLAGS(USE_CLSR) 715 }, 716 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128) 717 NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | 718 SPI_NOR_QUAD_READ) 719 MFR_FLAGS(USE_CLSR) 720 }, 721 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512) 722 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 723 MFR_FLAGS(USE_CLSR) 724 }, 725 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256) 726 FLAGS(SPI_NOR_HAS_LOCK) 727 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 728 MFR_FLAGS(USE_CLSR) 729 }, 730 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256) 731 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 732 MFR_FLAGS(USE_CLSR) 733 .fixups = &s25fs_s_nor_fixups, }, 734 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128) 735 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 736 MFR_FLAGS(USE_CLSR) 737 }, 738 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512) 739 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 740 MFR_FLAGS(USE_CLSR) 741 }, 742 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256) 743 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 744 MFR_FLAGS(USE_CLSR) 745 .fixups = &s25fs_s_nor_fixups, }, 746 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) }, 747 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) }, 748 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64) 749 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 750 MFR_FLAGS(USE_CLSR) 751 }, 752 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256) 753 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 754 MFR_FLAGS(USE_CLSR) 755 }, 756 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) }, 757 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) }, 758 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) }, 759 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) }, 760 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) }, 761 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8) 762 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 763 SPI_NOR_QUAD_READ) }, 764 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16) 765 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 766 SPI_NOR_QUAD_READ) }, 767 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32) 768 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 769 SPI_NOR_QUAD_READ) }, 770 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128) 771 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 772 SPI_NOR_QUAD_READ) }, 773 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32) 774 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 775 SPI_NOR_QUAD_READ) }, 776 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64) 777 NO_SFDP_FLAGS(SECT_4K) }, 778 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128) 779 NO_SFDP_FLAGS(SECT_4K) }, 780 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8) 781 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) }, 782 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16) 783 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) }, 784 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128) 785 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 786 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 787 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256) 788 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 789 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 790 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512) 791 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 792 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 793 { "s25fs256t", INFO6(0x342b19, 0x0f0890, 0, 0) 794 PARSE_SFDP 795 .fixups = &s25fs256t_fixups }, 796 { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) 797 PARSE_SFDP 798 MFR_FLAGS(USE_CLSR) 799 .fixups = &s25hx_t_fixups }, 800 { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) 801 PARSE_SFDP 802 MFR_FLAGS(USE_CLSR) 803 .fixups = &s25hx_t_fixups }, 804 { "s25hl02gt", INFO6(0x342a1c, 0x0f0090, 0, 0) 805 PARSE_SFDP 806 FLAGS(NO_CHIP_ERASE) 807 .fixups = &s25hx_t_fixups }, 808 { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) 809 PARSE_SFDP 810 MFR_FLAGS(USE_CLSR) 811 .fixups = &s25hx_t_fixups }, 812 { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) 813 PARSE_SFDP 814 MFR_FLAGS(USE_CLSR) 815 .fixups = &s25hx_t_fixups }, 816 { "s25hs02gt", INFO6(0x342b1c, 0x0f0090, 0, 0) 817 PARSE_SFDP 818 FLAGS(NO_CHIP_ERASE) 819 .fixups = &s25hx_t_fixups }, 820 { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) 821 FLAGS(SPI_NOR_NO_ERASE) }, 822 { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256) 823 PARSE_SFDP 824 .fixups = &s28hx_t_fixups, 825 }, 826 { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512) 827 PARSE_SFDP 828 .fixups = &s28hx_t_fixups, 829 }, 830 { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) 831 PARSE_SFDP 832 .fixups = &s28hx_t_fixups, 833 }, 834 { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512) 835 PARSE_SFDP 836 .fixups = &s28hx_t_fixups, 837 }, 838 }; 839 840 /** 841 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the 842 * flash is ready for new commands and clear it if there are any errors. 843 * @nor: pointer to 'struct spi_nor'. 844 * 845 * Return: 1 if ready, 0 if not ready, -errno on errors. 846 */ 847 static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor) 848 { 849 int ret; 850 851 ret = spi_nor_read_sr(nor, nor->bouncebuf); 852 if (ret) 853 return ret; 854 855 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 856 if (nor->bouncebuf[0] & SR_E_ERR) 857 dev_err(nor->dev, "Erase Error occurred\n"); 858 else 859 dev_err(nor->dev, "Programming Error occurred\n"); 860 861 spansion_nor_clear_sr(nor); 862 863 /* 864 * WEL bit remains set to one when an erase or page program 865 * error occurs. Issue a Write Disable command to protect 866 * against inadvertent writes that can possibly corrupt the 867 * contents of the memory. 868 */ 869 ret = spi_nor_write_disable(nor); 870 if (ret) 871 return ret; 872 873 return -EIO; 874 } 875 876 return !(nor->bouncebuf[0] & SR_WIP); 877 } 878 879 static void spansion_nor_late_init(struct spi_nor *nor) 880 { 881 if (nor->params->size > SZ_16M) { 882 nor->flags |= SNOR_F_4B_OPCODES; 883 /* No small sector erase for 4-byte command set */ 884 nor->erase_opcode = SPINOR_OP_SE; 885 nor->mtd.erasesize = nor->info->sector_size; 886 } 887 888 if (nor->info->mfr_flags & USE_CLSR) 889 nor->params->ready = spansion_nor_sr_ready_and_clear; 890 } 891 892 static const struct spi_nor_fixups spansion_nor_fixups = { 893 .late_init = spansion_nor_late_init, 894 }; 895 896 const struct spi_nor_manufacturer spi_nor_spansion = { 897 .name = "spansion", 898 .parts = spansion_nor_parts, 899 .nparts = ARRAY_SIZE(spansion_nor_parts), 900 .fixups = &spansion_nor_fixups, 901 }; 902