1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ 12 #define USE_CLSR BIT(0) 13 14 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 15 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ 16 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ 17 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 18 #define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad Enable */ 19 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 20 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb 21 #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 22 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ 23 #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 24 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 25 #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 26 #define SPINOR_OP_CYPRESS_RD_FAST 0xee 27 28 /* Cypress SPI NOR flash operations. */ 29 #define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ 30 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ 31 SPI_MEM_OP_ADDR(naddr, addr, 0), \ 32 SPI_MEM_OP_NO_DUMMY, \ 33 SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) 34 35 #define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, buf) \ 36 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \ 37 SPI_MEM_OP_ADDR(naddr, addr, 0), \ 38 SPI_MEM_OP_NO_DUMMY, \ 39 SPI_MEM_OP_DATA_IN(1, buf, 0)) 40 41 #define SPANSION_CLSR_OP \ 42 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \ 43 SPI_MEM_OP_NO_ADDR, \ 44 SPI_MEM_OP_NO_DUMMY, \ 45 SPI_MEM_OP_NO_DATA) 46 47 static int cypress_nor_octal_dtr_en(struct spi_nor *nor) 48 { 49 struct spi_mem_op op; 50 u8 *buf = nor->bouncebuf; 51 int ret; 52 53 /* Use 24 dummy cycles for memory array reads. */ 54 *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; 55 op = (struct spi_mem_op) 56 CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf); 57 58 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 59 if (ret) 60 return ret; 61 62 nor->read_dummy = 24; 63 64 /* Set the octal and DTR enable bits. */ 65 buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; 66 op = (struct spi_mem_op) 67 CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf); 68 69 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 70 if (ret) 71 return ret; 72 73 /* Read flash ID to make sure the switch was successful. */ 74 ret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); 75 if (ret) { 76 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); 77 return ret; 78 } 79 80 if (memcmp(buf, nor->info->id, nor->info->id_len)) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) 87 { 88 struct spi_mem_op op; 89 u8 *buf = nor->bouncebuf; 90 int ret; 91 92 /* 93 * The register is 1-byte wide, but 1-byte transactions are not allowed 94 * in 8D-8D-8D mode. Since there is no register at the next location, 95 * just initialize the value to 0 and let the transaction go on. 96 */ 97 buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; 98 buf[1] = 0; 99 op = (struct spi_mem_op) 100 CYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf); 101 ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); 102 if (ret) 103 return ret; 104 105 /* Read flash ID to make sure the switch was successful. */ 106 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); 107 if (ret) { 108 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); 109 return ret; 110 } 111 112 if (memcmp(buf, nor->info->id, nor->info->id_len)) 113 return -EINVAL; 114 115 return 0; 116 } 117 118 /** 119 * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile 120 * register. 121 * @nor: pointer to a 'struct spi_nor' 122 * 123 * It is recommended to update volatile registers in the field application due 124 * to a risk of the non-volatile registers corruption by power interrupt. This 125 * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable 126 * bit in the CFR1 non-volatile in advance (typically by a Flash programmer 127 * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is 128 * also set during Flash power-up. 129 * 130 * Return: 0 on success, -errno otherwise. 131 */ 132 static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) 133 { 134 struct spi_mem_op op; 135 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; 136 u8 cfr1v_written; 137 int ret; 138 139 op = (struct spi_mem_op) 140 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, 141 SPINOR_REG_CYPRESS_CFR1V, 142 nor->bouncebuf); 143 144 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 145 if (ret) 146 return ret; 147 148 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN) 149 return 0; 150 151 /* Update the Quad Enable bit. */ 152 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN; 153 op = (struct spi_mem_op) 154 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, 155 SPINOR_REG_CYPRESS_CFR1V, 1, 156 nor->bouncebuf); 157 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 158 if (ret) 159 return ret; 160 161 cfr1v_written = nor->bouncebuf[0]; 162 163 /* Read back and check it. */ 164 op = (struct spi_mem_op) 165 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, 166 SPINOR_REG_CYPRESS_CFR1V, 167 nor->bouncebuf); 168 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 169 if (ret) 170 return ret; 171 172 if (nor->bouncebuf[0] != cfr1v_written) { 173 dev_err(nor->dev, "CFR1: Read back test failed\n"); 174 return -EIO; 175 } 176 177 return 0; 178 } 179 180 /** 181 * cypress_nor_set_page_size() - Set page size which corresponds to the flash 182 * configuration. 183 * @nor: pointer to a 'struct spi_nor' 184 * 185 * The BFPT table advertises a 512B or 256B page size depending on part but the 186 * page size is actually configurable (with the default being 256B). Read from 187 * CFR3V[4] and set the correct size. 188 * 189 * Return: 0 on success, -errno otherwise. 190 */ 191 static int cypress_nor_set_page_size(struct spi_nor *nor) 192 { 193 struct spi_mem_op op = 194 CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR3V, 195 nor->bouncebuf); 196 int ret; 197 198 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 199 if (ret) 200 return ret; 201 202 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ) 203 nor->params->page_size = 512; 204 else 205 nor->params->page_size = 256; 206 207 return 0; 208 } 209 210 static int 211 s25hx_t_post_bfpt_fixup(struct spi_nor *nor, 212 const struct sfdp_parameter_header *bfpt_header, 213 const struct sfdp_bfpt *bfpt) 214 { 215 /* Replace Quad Enable with volatile version */ 216 nor->params->quad_enable = cypress_nor_quad_enable_volatile; 217 218 return cypress_nor_set_page_size(nor); 219 } 220 221 static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor) 222 { 223 struct spi_nor_erase_type *erase_type = 224 nor->params->erase_map.erase_type; 225 unsigned int i; 226 227 /* 228 * In some parts, 3byte erase opcodes are advertised by 4BAIT. 229 * Convert them to 4byte erase opcodes. 230 */ 231 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 232 switch (erase_type[i].opcode) { 233 case SPINOR_OP_SE: 234 erase_type[i].opcode = SPINOR_OP_SE_4B; 235 break; 236 case SPINOR_OP_BE_4K: 237 erase_type[i].opcode = SPINOR_OP_BE_4K_4B; 238 break; 239 default: 240 break; 241 } 242 } 243 } 244 245 static void s25hx_t_late_init(struct spi_nor *nor) 246 { 247 struct spi_nor_flash_parameter *params = nor->params; 248 249 /* Fast Read 4B requires mode cycles */ 250 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; 251 252 /* The writesize should be ECC data unit size */ 253 params->writesize = 16; 254 } 255 256 static struct spi_nor_fixups s25hx_t_fixups = { 257 .post_bfpt = s25hx_t_post_bfpt_fixup, 258 .post_sfdp = s25hx_t_post_sfdp_fixup, 259 .late_init = s25hx_t_late_init, 260 }; 261 262 /** 263 * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. 264 * @nor: pointer to a 'struct spi_nor' 265 * @enable: whether to enable or disable Octal DTR 266 * 267 * This also sets the memory access latency cycles to 24 to allow the flash to 268 * run at up to 200MHz. 269 * 270 * Return: 0 on success, -errno otherwise. 271 */ 272 static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 273 { 274 return enable ? cypress_nor_octal_dtr_en(nor) : 275 cypress_nor_octal_dtr_dis(nor); 276 } 277 278 static void s28hs512t_default_init(struct spi_nor *nor) 279 { 280 nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; 281 nor->params->writesize = 16; 282 } 283 284 static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor) 285 { 286 /* 287 * On older versions of the flash the xSPI Profile 1.0 table has the 288 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. 289 */ 290 if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) 291 nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = 292 SPINOR_OP_CYPRESS_RD_FAST; 293 294 /* This flash is also missing the 4-byte Page Program opcode bit. */ 295 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], 296 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); 297 /* 298 * Since xSPI Page Program opcode is backward compatible with 299 * Legacy SPI, use Legacy SPI opcode there as well. 300 */ 301 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR], 302 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); 303 304 /* 305 * The xSPI Profile 1.0 table advertises the number of additional 306 * address bytes needed for Read Status Register command as 0 but the 307 * actual value for that is 4. 308 */ 309 nor->params->rdsr_addr_nbytes = 4; 310 } 311 312 static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor, 313 const struct sfdp_parameter_header *bfpt_header, 314 const struct sfdp_bfpt *bfpt) 315 { 316 return cypress_nor_set_page_size(nor); 317 } 318 319 static const struct spi_nor_fixups s28hs512t_fixups = { 320 .default_init = s28hs512t_default_init, 321 .post_sfdp = s28hs512t_post_sfdp_fixup, 322 .post_bfpt = s28hs512t_post_bfpt_fixup, 323 }; 324 325 static int 326 s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor, 327 const struct sfdp_parameter_header *bfpt_header, 328 const struct sfdp_bfpt *bfpt) 329 { 330 /* 331 * The S25FS-S chip family reports 512-byte pages in BFPT but 332 * in reality the write buffer still wraps at the safe default 333 * of 256 bytes. Overwrite the page size advertised by BFPT 334 * to get the writes working. 335 */ 336 nor->params->page_size = 256; 337 338 return 0; 339 } 340 341 static const struct spi_nor_fixups s25fs_s_nor_fixups = { 342 .post_bfpt = s25fs_s_nor_post_bfpt_fixups, 343 }; 344 345 static const struct flash_info spansion_nor_parts[] = { 346 /* Spansion/Cypress -- single (large) sector size only, at least 347 * for the chips listed here (without boot sectors). 348 */ 349 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64) 350 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 351 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128) 352 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 353 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64) 354 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 355 MFR_FLAGS(USE_CLSR) 356 }, 357 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256) 358 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 359 MFR_FLAGS(USE_CLSR) 360 }, 361 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128) 362 NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | 363 SPI_NOR_QUAD_READ) 364 MFR_FLAGS(USE_CLSR) 365 }, 366 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512) 367 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 368 MFR_FLAGS(USE_CLSR) 369 }, 370 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256) 371 FLAGS(SPI_NOR_HAS_LOCK) 372 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 373 MFR_FLAGS(USE_CLSR) 374 }, 375 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256) 376 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 377 MFR_FLAGS(USE_CLSR) 378 .fixups = &s25fs_s_nor_fixups, }, 379 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128) 380 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 381 MFR_FLAGS(USE_CLSR) 382 }, 383 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512) 384 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 385 MFR_FLAGS(USE_CLSR) 386 }, 387 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256) 388 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 389 MFR_FLAGS(USE_CLSR) 390 .fixups = &s25fs_s_nor_fixups, }, 391 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) }, 392 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) }, 393 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64) 394 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 395 MFR_FLAGS(USE_CLSR) 396 }, 397 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256) 398 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 399 MFR_FLAGS(USE_CLSR) 400 }, 401 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) }, 402 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) }, 403 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) }, 404 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) }, 405 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) }, 406 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8) 407 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 408 SPI_NOR_QUAD_READ) }, 409 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16) 410 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 411 SPI_NOR_QUAD_READ) }, 412 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32) 413 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 414 SPI_NOR_QUAD_READ) }, 415 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128) 416 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 417 SPI_NOR_QUAD_READ) }, 418 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32) 419 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 420 SPI_NOR_QUAD_READ) }, 421 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64) 422 NO_SFDP_FLAGS(SECT_4K) }, 423 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128) 424 NO_SFDP_FLAGS(SECT_4K) }, 425 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8) 426 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) }, 427 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16) 428 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) }, 429 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128) 430 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 431 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 432 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256) 433 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 434 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 435 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512) 436 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 437 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, 438 { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) 439 PARSE_SFDP 440 MFR_FLAGS(USE_CLSR) 441 .fixups = &s25hx_t_fixups }, 442 { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) 443 PARSE_SFDP 444 MFR_FLAGS(USE_CLSR) 445 .fixups = &s25hx_t_fixups }, 446 { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) 447 PARSE_SFDP 448 MFR_FLAGS(USE_CLSR) 449 .fixups = &s25hx_t_fixups }, 450 { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) 451 PARSE_SFDP 452 MFR_FLAGS(USE_CLSR) 453 .fixups = &s25hx_t_fixups }, 454 { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) 455 FLAGS(SPI_NOR_NO_ERASE) }, 456 { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) 457 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ | 458 SPI_NOR_OCTAL_DTR_PP) 459 .fixups = &s28hs512t_fixups, 460 }, 461 }; 462 463 /** 464 * spansion_nor_clear_sr() - Clear the Status Register. 465 * @nor: pointer to 'struct spi_nor'. 466 */ 467 static void spansion_nor_clear_sr(struct spi_nor *nor) 468 { 469 int ret; 470 471 if (nor->spimem) { 472 struct spi_mem_op op = SPANSION_CLSR_OP; 473 474 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 475 476 ret = spi_mem_exec_op(nor->spimem, &op); 477 } else { 478 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, 479 NULL, 0); 480 } 481 482 if (ret) 483 dev_dbg(nor->dev, "error %d clearing SR\n", ret); 484 } 485 486 /** 487 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the 488 * flash is ready for new commands and clear it if there are any errors. 489 * @nor: pointer to 'struct spi_nor'. 490 * 491 * Return: 1 if ready, 0 if not ready, -errno on errors. 492 */ 493 static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor) 494 { 495 int ret; 496 497 ret = spi_nor_read_sr(nor, nor->bouncebuf); 498 if (ret) 499 return ret; 500 501 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 502 if (nor->bouncebuf[0] & SR_E_ERR) 503 dev_err(nor->dev, "Erase Error occurred\n"); 504 else 505 dev_err(nor->dev, "Programming Error occurred\n"); 506 507 spansion_nor_clear_sr(nor); 508 509 /* 510 * WEL bit remains set to one when an erase or page program 511 * error occurs. Issue a Write Disable command to protect 512 * against inadvertent writes that can possibly corrupt the 513 * contents of the memory. 514 */ 515 ret = spi_nor_write_disable(nor); 516 if (ret) 517 return ret; 518 519 return -EIO; 520 } 521 522 return !(nor->bouncebuf[0] & SR_WIP); 523 } 524 525 static void spansion_nor_late_init(struct spi_nor *nor) 526 { 527 if (nor->params->size > SZ_16M) { 528 nor->flags |= SNOR_F_4B_OPCODES; 529 /* No small sector erase for 4-byte command set */ 530 nor->erase_opcode = SPINOR_OP_SE; 531 nor->mtd.erasesize = nor->info->sector_size; 532 } 533 534 if (nor->info->mfr_flags & USE_CLSR) 535 nor->params->ready = spansion_nor_sr_ready_and_clear; 536 } 537 538 static const struct spi_nor_fixups spansion_nor_fixups = { 539 .late_init = spansion_nor_late_init, 540 }; 541 542 const struct spi_nor_manufacturer spi_nor_spansion = { 543 .name = "spansion", 544 .parts = spansion_nor_parts, 545 .nparts = ARRAY_SIZE(spansion_nor_parts), 546 .fixups = &spansion_nor_fixups, 547 }; 548