1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 /* flash_info mfr_flag. Used to read proprietary FSR register. */ 12 #define USE_FSR BIT(0) 13 14 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 15 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ 16 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ 17 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */ 18 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */ 19 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */ 20 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */ 21 #define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */ 22 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */ 23 #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */ 24 25 /* Flag Status Register bits */ 26 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ 27 #define FSR_E_ERR BIT(5) /* Erase operation status */ 28 #define FSR_P_ERR BIT(4) /* Program operation status */ 29 #define FSR_PT_ERR BIT(1) /* Protection error bit */ 30 31 static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 32 { 33 struct spi_mem_op op; 34 u8 *buf = nor->bouncebuf; 35 int ret; 36 37 if (enable) { 38 /* Use 20 dummy cycles for memory array reads. */ 39 ret = spi_nor_write_enable(nor); 40 if (ret) 41 return ret; 42 43 *buf = 20; 44 op = (struct spi_mem_op) 45 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), 46 SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1), 47 SPI_MEM_OP_NO_DUMMY, 48 SPI_MEM_OP_DATA_OUT(1, buf, 1)); 49 50 ret = spi_mem_exec_op(nor->spimem, &op); 51 if (ret) 52 return ret; 53 54 ret = spi_nor_wait_till_ready(nor); 55 if (ret) 56 return ret; 57 } 58 59 ret = spi_nor_write_enable(nor); 60 if (ret) 61 return ret; 62 63 if (enable) { 64 buf[0] = SPINOR_MT_OCT_DTR; 65 } else { 66 /* 67 * The register is 1-byte wide, but 1-byte transactions are not 68 * allowed in 8D-8D-8D mode. The next register is the dummy 69 * cycle configuration register. Since the transaction needs to 70 * be at least 2 bytes wide, set the next register to its 71 * default value. This also makes sense because the value was 72 * changed when enabling 8D-8D-8D mode, it should be reset when 73 * disabling. 74 */ 75 buf[0] = SPINOR_MT_EXSPI; 76 buf[1] = SPINOR_REG_MT_CFR1V_DEF; 77 } 78 79 op = (struct spi_mem_op) 80 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), 81 SPI_MEM_OP_ADDR(enable ? 3 : 4, 82 SPINOR_REG_MT_CFR0V, 1), 83 SPI_MEM_OP_NO_DUMMY, 84 SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); 85 86 if (!enable) 87 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); 88 89 ret = spi_mem_exec_op(nor->spimem, &op); 90 if (ret) 91 return ret; 92 93 /* Read flash ID to make sure the switch was successful. */ 94 op = (struct spi_mem_op) 95 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), 96 SPI_MEM_OP_NO_ADDR, 97 SPI_MEM_OP_DUMMY(enable ? 8 : 0, 1), 98 SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), 99 buf, 1)); 100 101 if (enable) 102 spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); 103 104 ret = spi_mem_exec_op(nor->spimem, &op); 105 if (ret) 106 return ret; 107 108 if (memcmp(buf, nor->info->id, nor->info->id_len)) 109 return -EINVAL; 110 111 return 0; 112 } 113 114 static void mt35xu512aba_default_init(struct spi_nor *nor) 115 { 116 nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable; 117 } 118 119 static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor) 120 { 121 /* Set the Fast Read settings. */ 122 nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; 123 spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], 124 0, 20, SPINOR_OP_MT_DTR_RD, 125 SNOR_PROTO_8_8_8_DTR); 126 127 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; 128 nor->params->rdsr_dummy = 8; 129 nor->params->rdsr_addr_nbytes = 0; 130 131 /* 132 * The BFPT quad enable field is set to a reserved value so the quad 133 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we 134 * disable it. 135 */ 136 nor->params->quad_enable = NULL; 137 } 138 139 static const struct spi_nor_fixups mt35xu512aba_fixups = { 140 .default_init = mt35xu512aba_default_init, 141 .post_sfdp = mt35xu512aba_post_sfdp_fixup, 142 }; 143 144 static const struct flash_info micron_nor_parts[] = { 145 { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512) 146 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ | 147 SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) 148 FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE) 149 MFR_FLAGS(USE_FSR) 150 .fixups = &mt35xu512aba_fixups 151 }, 152 { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048) 153 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ) 154 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) 155 MFR_FLAGS(USE_FSR) 156 }, 157 }; 158 159 static const struct flash_info st_nor_parts[] = { 160 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32) 161 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, 162 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64) 163 NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) }, 164 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64) 165 NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) }, 166 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128) 167 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, 168 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128) 169 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) }, 170 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256) 171 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 172 SPI_NOR_BP3_SR_BIT6) 173 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 174 MFR_FLAGS(USE_FSR) 175 }, 176 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256) 177 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 178 SPI_NOR_BP3_SR_BIT6) 179 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 180 MFR_FLAGS(USE_FSR) 181 }, 182 { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512) 183 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 184 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) 185 MFR_FLAGS(USE_FSR) 186 }, 187 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512) 188 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 189 SPI_NOR_QUAD_READ) 190 MFR_FLAGS(USE_FSR) 191 }, 192 { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512) 193 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 194 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) 195 MFR_FLAGS(USE_FSR) 196 }, 197 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512) 198 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 199 MFR_FLAGS(USE_FSR) 200 }, 201 { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024) 202 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 203 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) 204 MFR_FLAGS(USE_FSR) 205 }, 206 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024) 207 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 208 SPI_NOR_BP3_SR_BIT6) 209 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 210 MFR_FLAGS(USE_FSR) 211 }, 212 { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024) 213 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 214 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) 215 MFR_FLAGS(USE_FSR) 216 }, 217 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024) 218 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 219 SPI_NOR_BP3_SR_BIT6) 220 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 221 MFR_FLAGS(USE_FSR) 222 }, 223 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048) 224 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 225 SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE) 226 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 227 MFR_FLAGS(USE_FSR) 228 }, 229 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048) 230 FLAGS(NO_CHIP_ERASE) 231 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 232 MFR_FLAGS(USE_FSR) 233 }, 234 { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096) 235 FLAGS(NO_CHIP_ERASE) 236 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) 237 MFR_FLAGS(USE_FSR) 238 }, 239 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096) 240 FLAGS(NO_CHIP_ERASE) 241 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 242 SPI_NOR_QUAD_READ) 243 MFR_FLAGS(USE_FSR) 244 }, 245 246 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2) }, 247 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4) }, 248 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4) }, 249 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8) }, 250 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16) }, 251 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32) }, 252 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64) }, 253 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128) }, 254 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64) }, 255 256 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2) }, 257 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4) }, 258 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4) }, 259 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8) }, 260 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16) }, 261 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32) }, 262 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64) }, 263 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128) }, 264 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64) }, 265 266 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2) }, 267 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16) }, 268 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32) }, 269 270 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4) }, 271 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16) }, 272 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32) 273 NO_SFDP_FLAGS(SECT_4K) }, 274 275 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32) 276 NO_SFDP_FLAGS(SECT_4K) }, 277 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64) 278 NO_SFDP_FLAGS(SECT_4K) }, 279 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64) 280 NO_SFDP_FLAGS(SECT_4K) }, 281 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64) 282 NO_SFDP_FLAGS(SECT_4K) }, 283 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128) }, 284 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) }, 285 }; 286 287 /** 288 * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and 289 * Micron flashes. 290 * @nor: pointer to 'struct spi_nor'. 291 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 292 * address mode. 293 * 294 * Return: 0 on success, -errno otherwise. 295 */ 296 static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 297 { 298 int ret; 299 300 ret = spi_nor_write_enable(nor); 301 if (ret) 302 return ret; 303 304 ret = spi_nor_set_4byte_addr_mode(nor, enable); 305 if (ret) 306 return ret; 307 308 return spi_nor_write_disable(nor); 309 } 310 311 /** 312 * micron_st_nor_read_fsr() - Read the Flag Status Register. 313 * @nor: pointer to 'struct spi_nor' 314 * @fsr: pointer to a DMA-able buffer where the value of the 315 * Flag Status Register will be written. Should be at least 2 316 * bytes. 317 * 318 * Return: 0 on success, -errno otherwise. 319 */ 320 static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr) 321 { 322 int ret; 323 324 if (nor->spimem) { 325 struct spi_mem_op op = 326 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), 327 SPI_MEM_OP_NO_ADDR, 328 SPI_MEM_OP_NO_DUMMY, 329 SPI_MEM_OP_DATA_IN(1, fsr, 0)); 330 331 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 332 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 333 op.dummy.nbytes = nor->params->rdsr_dummy; 334 /* 335 * We don't want to read only one byte in DTR mode. So, 336 * read 2 and then discard the second byte. 337 */ 338 op.data.nbytes = 2; 339 } 340 341 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 342 343 ret = spi_mem_exec_op(nor->spimem, &op); 344 } else { 345 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, 346 1); 347 } 348 349 if (ret) 350 dev_dbg(nor->dev, "error %d reading FSR\n", ret); 351 352 return ret; 353 } 354 355 /** 356 * micron_st_nor_clear_fsr() - Clear the Flag Status Register. 357 * @nor: pointer to 'struct spi_nor'. 358 */ 359 static void micron_st_nor_clear_fsr(struct spi_nor *nor) 360 { 361 int ret; 362 363 if (nor->spimem) { 364 struct spi_mem_op op = 365 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), 366 SPI_MEM_OP_NO_ADDR, 367 SPI_MEM_OP_NO_DUMMY, 368 SPI_MEM_OP_NO_DATA); 369 370 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 371 372 ret = spi_mem_exec_op(nor->spimem, &op); 373 } else { 374 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, 375 NULL, 0); 376 } 377 378 if (ret) 379 dev_dbg(nor->dev, "error %d clearing FSR\n", ret); 380 } 381 382 /** 383 * micron_st_nor_ready() - Query the Status Register as well as the Flag Status 384 * Register to see if the flash is ready for new commands. If there are any 385 * errors in the FSR clear them. 386 * @nor: pointer to 'struct spi_nor'. 387 * 388 * Return: 1 if ready, 0 if not ready, -errno on errors. 389 */ 390 static int micron_st_nor_ready(struct spi_nor *nor) 391 { 392 int sr_ready, ret; 393 394 sr_ready = spi_nor_sr_ready(nor); 395 if (sr_ready < 0) 396 return sr_ready; 397 398 ret = micron_st_nor_read_fsr(nor, nor->bouncebuf); 399 if (ret) 400 return ret; 401 402 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { 403 if (nor->bouncebuf[0] & FSR_E_ERR) 404 dev_err(nor->dev, "Erase operation failed.\n"); 405 else 406 dev_err(nor->dev, "Program operation failed.\n"); 407 408 if (nor->bouncebuf[0] & FSR_PT_ERR) 409 dev_err(nor->dev, 410 "Attempted to modify a protected sector.\n"); 411 412 micron_st_nor_clear_fsr(nor); 413 414 /* 415 * WEL bit remains set to one when an erase or page program 416 * error occurs. Issue a Write Disable command to protect 417 * against inadvertent writes that can possibly corrupt the 418 * contents of the memory. 419 */ 420 ret = spi_nor_write_disable(nor); 421 if (ret) 422 return ret; 423 424 return -EIO; 425 } 426 427 return sr_ready && !!(nor->bouncebuf[0] & FSR_READY); 428 } 429 430 static void micron_st_nor_default_init(struct spi_nor *nor) 431 { 432 nor->flags |= SNOR_F_HAS_LOCK; 433 nor->flags &= ~SNOR_F_HAS_16BIT_SR; 434 nor->params->quad_enable = NULL; 435 nor->params->set_4byte_addr_mode = micron_st_nor_set_4byte_addr_mode; 436 } 437 438 static void micron_st_nor_late_init(struct spi_nor *nor) 439 { 440 if (nor->info->mfr_flags & USE_FSR) 441 nor->params->ready = micron_st_nor_ready; 442 } 443 444 static const struct spi_nor_fixups micron_st_nor_fixups = { 445 .default_init = micron_st_nor_default_init, 446 .late_init = micron_st_nor_late_init, 447 }; 448 449 const struct spi_nor_manufacturer spi_nor_micron = { 450 .name = "micron", 451 .parts = micron_nor_parts, 452 .nparts = ARRAY_SIZE(micron_nor_parts), 453 .fixups = µn_st_nor_fixups, 454 }; 455 456 const struct spi_nor_manufacturer spi_nor_st = { 457 .name = "st", 458 .parts = st_nor_parts, 459 .nparts = ARRAY_SIZE(st_nor_parts), 460 .fixups = µn_st_nor_fixups, 461 }; 462