1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H 8 #define __LINUX_MTD_SPI_NOR_INTERNAL_H 9 10 #include "sfdp.h" 11 12 #define SPI_NOR_MAX_ID_LEN 6 13 14 enum spi_nor_option_flags { 15 SNOR_F_USE_FSR = BIT(0), 16 SNOR_F_HAS_SR_TB = BIT(1), 17 SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 18 SNOR_F_READY_XSR_RDY = BIT(3), 19 SNOR_F_USE_CLSR = BIT(4), 20 SNOR_F_BROKEN_RESET = BIT(5), 21 SNOR_F_4B_OPCODES = BIT(6), 22 SNOR_F_HAS_4BAIT = BIT(7), 23 SNOR_F_HAS_LOCK = BIT(8), 24 SNOR_F_HAS_16BIT_SR = BIT(9), 25 SNOR_F_NO_READ_CR = BIT(10), 26 SNOR_F_HAS_SR_TB_BIT6 = BIT(11), 27 SNOR_F_HAS_4BIT_BP = BIT(12), 28 SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), 29 SNOR_F_IO_MODE_EN_VOLATILE = BIT(14), 30 SNOR_F_SOFT_RESET = BIT(15), 31 SNOR_F_SWP_IS_VOLATILE = BIT(16), 32 }; 33 34 struct spi_nor_read_command { 35 u8 num_mode_clocks; 36 u8 num_wait_states; 37 u8 opcode; 38 enum spi_nor_protocol proto; 39 }; 40 41 struct spi_nor_pp_command { 42 u8 opcode; 43 enum spi_nor_protocol proto; 44 }; 45 46 enum spi_nor_read_command_index { 47 SNOR_CMD_READ, 48 SNOR_CMD_READ_FAST, 49 SNOR_CMD_READ_1_1_1_DTR, 50 51 /* Dual SPI */ 52 SNOR_CMD_READ_1_1_2, 53 SNOR_CMD_READ_1_2_2, 54 SNOR_CMD_READ_2_2_2, 55 SNOR_CMD_READ_1_2_2_DTR, 56 57 /* Quad SPI */ 58 SNOR_CMD_READ_1_1_4, 59 SNOR_CMD_READ_1_4_4, 60 SNOR_CMD_READ_4_4_4, 61 SNOR_CMD_READ_1_4_4_DTR, 62 63 /* Octal SPI */ 64 SNOR_CMD_READ_1_1_8, 65 SNOR_CMD_READ_1_8_8, 66 SNOR_CMD_READ_8_8_8, 67 SNOR_CMD_READ_1_8_8_DTR, 68 SNOR_CMD_READ_8_8_8_DTR, 69 70 SNOR_CMD_READ_MAX 71 }; 72 73 enum spi_nor_pp_command_index { 74 SNOR_CMD_PP, 75 76 /* Quad SPI */ 77 SNOR_CMD_PP_1_1_4, 78 SNOR_CMD_PP_1_4_4, 79 SNOR_CMD_PP_4_4_4, 80 81 /* Octal SPI */ 82 SNOR_CMD_PP_1_1_8, 83 SNOR_CMD_PP_1_8_8, 84 SNOR_CMD_PP_8_8_8, 85 SNOR_CMD_PP_8_8_8_DTR, 86 87 SNOR_CMD_PP_MAX 88 }; 89 90 /** 91 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type 92 * @size: the size of the sector/block erased by the erase type. 93 * JEDEC JESD216B imposes erase sizes to be a power of 2. 94 * @size_shift: @size is a power of 2, the shift is stored in 95 * @size_shift. 96 * @size_mask: the size mask based on @size_shift. 97 * @opcode: the SPI command op code to erase the sector/block. 98 * @idx: Erase Type index as sorted in the Basic Flash Parameter 99 * Table. It will be used to synchronize the supported 100 * Erase Types with the ones identified in the SFDP 101 * optional tables. 102 */ 103 struct spi_nor_erase_type { 104 u32 size; 105 u32 size_shift; 106 u32 size_mask; 107 u8 opcode; 108 u8 idx; 109 }; 110 111 /** 112 * struct spi_nor_erase_command - Used for non-uniform erases 113 * The structure is used to describe a list of erase commands to be executed 114 * once we validate that the erase can be performed. The elements in the list 115 * are run-length encoded. 116 * @list: for inclusion into the list of erase commands. 117 * @count: how many times the same erase command should be 118 * consecutively used. 119 * @size: the size of the sector/block erased by the command. 120 * @opcode: the SPI command op code to erase the sector/block. 121 */ 122 struct spi_nor_erase_command { 123 struct list_head list; 124 u32 count; 125 u32 size; 126 u8 opcode; 127 }; 128 129 /** 130 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region 131 * @offset: the offset in the data array of erase region start. 132 * LSB bits are used as a bitmask encoding flags to 133 * determine if this region is overlaid, if this region is 134 * the last in the SPI NOR flash memory and to indicate 135 * all the supported erase commands inside this region. 136 * The erase types are sorted in ascending order with the 137 * smallest Erase Type size being at BIT(0). 138 * @size: the size of the region in bytes. 139 */ 140 struct spi_nor_erase_region { 141 u64 offset; 142 u64 size; 143 }; 144 145 #define SNOR_ERASE_TYPE_MAX 4 146 #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0) 147 148 #define SNOR_LAST_REGION BIT(4) 149 #define SNOR_OVERLAID_REGION BIT(5) 150 151 #define SNOR_ERASE_FLAGS_MAX 6 152 #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0) 153 154 /** 155 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map 156 * @regions: array of erase regions. The regions are consecutive in 157 * address space. Walking through the regions is done 158 * incrementally. 159 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform 160 * sector size (legacy implementation). 161 * @erase_type: an array of erase types shared by all the regions. 162 * The erase types are sorted in ascending order, with the 163 * smallest Erase Type size being the first member in the 164 * erase_type array. 165 * @uniform_erase_type: bitmask encoding erase types that can erase the 166 * entire memory. This member is completed at init by 167 * uniform and non-uniform SPI NOR flash memories if they 168 * support at least one erase type that can erase the 169 * entire memory. 170 */ 171 struct spi_nor_erase_map { 172 struct spi_nor_erase_region *regions; 173 struct spi_nor_erase_region uniform_region; 174 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX]; 175 u8 uniform_erase_type; 176 }; 177 178 /** 179 * struct spi_nor_locking_ops - SPI NOR locking methods 180 * @lock: lock a region of the SPI NOR. 181 * @unlock: unlock a region of the SPI NOR. 182 * @is_locked: check if a region of the SPI NOR is completely locked 183 */ 184 struct spi_nor_locking_ops { 185 int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 186 int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 187 int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 188 }; 189 190 /** 191 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings. 192 * Includes legacy flash parameters and settings that can be overwritten 193 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 194 * Serial Flash Discoverable Parameters (SFDP) tables. 195 * 196 * @size: the flash memory density in bytes. 197 * @writesize Minimal writable flash unit size. Defaults to 1. Set to 198 * ECC unit size for ECC-ed flashes. 199 * @page_size: the page size of the SPI NOR flash memory. 200 * @rdsr_dummy: dummy cycles needed for Read Status Register command. 201 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register 202 * command. 203 * @hwcaps: describes the read and page program hardware 204 * capabilities. 205 * @reads: read capabilities ordered by priority: the higher index 206 * in the array, the higher priority. 207 * @page_programs: page program capabilities ordered by priority: the 208 * higher index in the array, the higher priority. 209 * @erase_map: the erase map parsed from the SFDP Sector Map Parameter 210 * Table. 211 * @octal_dtr_enable: enables SPI NOR octal DTR mode. 212 * @quad_enable: enables SPI NOR quad mode. 213 * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. 214 * @convert_addr: converts an absolute address into something the flash 215 * will understand. Particularly useful when pagesize is 216 * not a power-of-2. 217 * @setup: configures the SPI NOR memory. Useful for SPI NOR 218 * flashes that have peculiarities to the SPI NOR standard 219 * e.g. different opcodes, specific address calculation, 220 * page size, etc. 221 * @locking_ops: SPI NOR locking methods. 222 */ 223 struct spi_nor_flash_parameter { 224 u64 size; 225 u32 writesize; 226 u32 page_size; 227 u8 rdsr_dummy; 228 u8 rdsr_addr_nbytes; 229 230 struct spi_nor_hwcaps hwcaps; 231 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 232 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 233 234 struct spi_nor_erase_map erase_map; 235 236 int (*octal_dtr_enable)(struct spi_nor *nor, bool enable); 237 int (*quad_enable)(struct spi_nor *nor); 238 int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); 239 u32 (*convert_addr)(struct spi_nor *nor, u32 addr); 240 int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); 241 242 const struct spi_nor_locking_ops *locking_ops; 243 }; 244 245 /** 246 * struct spi_nor_fixups - SPI NOR fixup hooks 247 * @default_init: called after default flash parameters init. Used to tweak 248 * flash parameters when information provided by the flash_info 249 * table is incomplete or wrong. 250 * @post_bfpt: called after the BFPT table has been parsed 251 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs 252 * that do not support RDSFDP). Typically used to tweak various 253 * parameters that could not be extracted by other means (i.e. 254 * when information provided by the SFDP/flash_info tables are 255 * incomplete or wrong). 256 * 257 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP 258 * table is broken or not available. 259 */ 260 struct spi_nor_fixups { 261 void (*default_init)(struct spi_nor *nor); 262 int (*post_bfpt)(struct spi_nor *nor, 263 const struct sfdp_parameter_header *bfpt_header, 264 const struct sfdp_bfpt *bfpt, 265 struct spi_nor_flash_parameter *params); 266 void (*post_sfdp)(struct spi_nor *nor); 267 }; 268 269 struct flash_info { 270 char *name; 271 272 /* 273 * This array stores the ID bytes. 274 * The first three bytes are the JEDIC ID. 275 * JEDEC ID zero means "no ID" (mostly older chips). 276 */ 277 u8 id[SPI_NOR_MAX_ID_LEN]; 278 u8 id_len; 279 280 /* The size listed here is what works with SPINOR_OP_SE, which isn't 281 * necessarily called a "sector" by the vendor. 282 */ 283 unsigned sector_size; 284 u16 n_sectors; 285 286 u16 page_size; 287 u16 addr_width; 288 289 u32 flags; 290 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ 291 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ 292 #define SST_WRITE BIT(2) /* use SST byte programming */ 293 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ 294 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ 295 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ 296 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ 297 #define USE_FSR BIT(7) /* use flag status register */ 298 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ 299 #define SPI_NOR_HAS_TB BIT(9) /* 300 * Flash SR has Top/Bottom (TB) protect 301 * bit. Must be used with 302 * SPI_NOR_HAS_LOCK. 303 */ 304 #define SPI_NOR_XSR_RDY BIT(10) /* 305 * S3AN flashes have specific opcode to 306 * read the status register. 307 */ 308 #define SPI_NOR_4B_OPCODES BIT(11) /* 309 * Use dedicated 4byte address op codes 310 * to support memory size above 128Mib. 311 */ 312 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ 313 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ 314 #define USE_CLSR BIT(14) /* use CLSR command */ 315 #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ 316 #define SPI_NOR_TB_SR_BIT6 BIT(16) /* 317 * Top/Bottom (TB) is bit 6 of 318 * status register. Must be used with 319 * SPI_NOR_HAS_TB. 320 */ 321 #define SPI_NOR_4BIT_BP BIT(17) /* 322 * Flash SR has 4 bit fields (BP0-3) 323 * for block protection. 324 */ 325 #define SPI_NOR_BP3_SR_BIT6 BIT(18) /* 326 * BP3 is bit 6 of status register. 327 * Must be used with SPI_NOR_4BIT_BP. 328 */ 329 #define SPI_NOR_OCTAL_DTR_READ BIT(19) /* Flash supports octal DTR Read. */ 330 #define SPI_NOR_OCTAL_DTR_PP BIT(20) /* Flash supports Octal DTR Page Program */ 331 #define SPI_NOR_IO_MODE_EN_VOLATILE BIT(21) /* 332 * Flash enables the best 333 * available I/O mode via a 334 * volatile bit. 335 */ 336 #define SPI_NOR_SWP_IS_VOLATILE BIT(22) /* 337 * Flash has volatile software write 338 * protection bits. Usually these will 339 * power-up in a write-protected state. 340 */ 341 342 /* Part specific fixup hooks. */ 343 const struct spi_nor_fixups *fixups; 344 }; 345 346 /* Used when the "_ext_id" is two bytes at most */ 347 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 348 .id = { \ 349 ((_jedec_id) >> 16) & 0xff, \ 350 ((_jedec_id) >> 8) & 0xff, \ 351 (_jedec_id) & 0xff, \ 352 ((_ext_id) >> 8) & 0xff, \ 353 (_ext_id) & 0xff, \ 354 }, \ 355 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 356 .sector_size = (_sector_size), \ 357 .n_sectors = (_n_sectors), \ 358 .page_size = 256, \ 359 .flags = (_flags), 360 361 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 362 .id = { \ 363 ((_jedec_id) >> 16) & 0xff, \ 364 ((_jedec_id) >> 8) & 0xff, \ 365 (_jedec_id) & 0xff, \ 366 ((_ext_id) >> 16) & 0xff, \ 367 ((_ext_id) >> 8) & 0xff, \ 368 (_ext_id) & 0xff, \ 369 }, \ 370 .id_len = 6, \ 371 .sector_size = (_sector_size), \ 372 .n_sectors = (_n_sectors), \ 373 .page_size = 256, \ 374 .flags = (_flags), 375 376 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ 377 .sector_size = (_sector_size), \ 378 .n_sectors = (_n_sectors), \ 379 .page_size = (_page_size), \ 380 .addr_width = (_addr_width), \ 381 .flags = (_flags), 382 383 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ 384 .id = { \ 385 ((_jedec_id) >> 16) & 0xff, \ 386 ((_jedec_id) >> 8) & 0xff, \ 387 (_jedec_id) & 0xff \ 388 }, \ 389 .id_len = 3, \ 390 .sector_size = (8*_page_size), \ 391 .n_sectors = (_n_sectors), \ 392 .page_size = _page_size, \ 393 .addr_width = 3, \ 394 .flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY, 395 396 /** 397 * struct spi_nor_manufacturer - SPI NOR manufacturer object 398 * @name: manufacturer name 399 * @parts: array of parts supported by this manufacturer 400 * @nparts: number of entries in the parts array 401 * @fixups: hooks called at various points in time during spi_nor_scan() 402 */ 403 struct spi_nor_manufacturer { 404 const char *name; 405 const struct flash_info *parts; 406 unsigned int nparts; 407 const struct spi_nor_fixups *fixups; 408 }; 409 410 /* Manufacturer drivers. */ 411 extern const struct spi_nor_manufacturer spi_nor_atmel; 412 extern const struct spi_nor_manufacturer spi_nor_catalyst; 413 extern const struct spi_nor_manufacturer spi_nor_eon; 414 extern const struct spi_nor_manufacturer spi_nor_esmt; 415 extern const struct spi_nor_manufacturer spi_nor_everspin; 416 extern const struct spi_nor_manufacturer spi_nor_fujitsu; 417 extern const struct spi_nor_manufacturer spi_nor_gigadevice; 418 extern const struct spi_nor_manufacturer spi_nor_intel; 419 extern const struct spi_nor_manufacturer spi_nor_issi; 420 extern const struct spi_nor_manufacturer spi_nor_macronix; 421 extern const struct spi_nor_manufacturer spi_nor_micron; 422 extern const struct spi_nor_manufacturer spi_nor_st; 423 extern const struct spi_nor_manufacturer spi_nor_spansion; 424 extern const struct spi_nor_manufacturer spi_nor_sst; 425 extern const struct spi_nor_manufacturer spi_nor_winbond; 426 extern const struct spi_nor_manufacturer spi_nor_xilinx; 427 extern const struct spi_nor_manufacturer spi_nor_xmc; 428 429 void spi_nor_spimem_setup_op(const struct spi_nor *nor, 430 struct spi_mem_op *op, 431 const enum spi_nor_protocol proto); 432 int spi_nor_write_enable(struct spi_nor *nor); 433 int spi_nor_write_disable(struct spi_nor *nor); 434 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); 435 int spi_nor_write_ear(struct spi_nor *nor, u8 ear); 436 int spi_nor_wait_till_ready(struct spi_nor *nor); 437 int spi_nor_global_block_unlock(struct spi_nor *nor); 438 int spi_nor_lock_and_prep(struct spi_nor *nor); 439 void spi_nor_unlock_and_unprep(struct spi_nor *nor); 440 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); 441 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); 442 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); 443 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); 444 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); 445 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); 446 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); 447 448 int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); 449 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 450 u8 *buf); 451 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 452 const u8 *buf); 453 454 int spi_nor_hwcaps_read2cmd(u32 hwcaps); 455 u8 spi_nor_convert_3to4_read(u8 opcode); 456 void spi_nor_set_read_settings(struct spi_nor_read_command *read, 457 u8 num_mode_clocks, 458 u8 num_wait_states, 459 u8 opcode, 460 enum spi_nor_protocol proto); 461 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 462 enum spi_nor_protocol proto); 463 464 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 465 u8 opcode); 466 struct spi_nor_erase_region * 467 spi_nor_region_next(struct spi_nor_erase_region *region); 468 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 469 u8 erase_mask, u64 flash_size); 470 471 int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 472 const struct sfdp_parameter_header *bfpt_header, 473 const struct sfdp_bfpt *bfpt, 474 struct spi_nor_flash_parameter *params); 475 476 static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd) 477 { 478 return mtd->priv; 479 } 480 481 #endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */ 482