1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/err.h> 11 #include <linux/errno.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/mutex.h> 15 #include <linux/math64.h> 16 #include <linux/sizes.h> 17 #include <linux/slab.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/of_platform.h> 21 #include <linux/sched/task_stack.h> 22 #include <linux/spi/flash.h> 23 #include <linux/mtd/spi-nor.h> 24 25 #include "core.h" 26 27 /* Define max times to check status register before we give up. */ 28 29 /* 30 * For everything but full-chip erase; probably could be much smaller, but kept 31 * around for safety for now 32 */ 33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 34 35 /* 36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up 37 * for larger flash 38 */ 39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) 40 41 #define SPI_NOR_MAX_ADDR_WIDTH 4 42 43 #define SPI_NOR_SRST_SLEEP_MIN 200 44 #define SPI_NOR_SRST_SLEEP_MAX 400 45 46 /** 47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the 48 * extension type. 49 * @nor: pointer to a 'struct spi_nor' 50 * @op: pointer to the 'struct spi_mem_op' whose properties 51 * need to be initialized. 52 * 53 * Right now, only "repeat" and "invert" are supported. 54 * 55 * Return: The opcode extension. 56 */ 57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, 58 const struct spi_mem_op *op) 59 { 60 switch (nor->cmd_ext_type) { 61 case SPI_NOR_EXT_INVERT: 62 return ~op->cmd.opcode; 63 64 case SPI_NOR_EXT_REPEAT: 65 return op->cmd.opcode; 66 67 default: 68 dev_err(nor->dev, "Unknown command extension type\n"); 69 return 0; 70 } 71 } 72 73 /** 74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. 75 * @nor: pointer to a 'struct spi_nor' 76 * @op: pointer to the 'struct spi_mem_op' whose properties 77 * need to be initialized. 78 * @proto: the protocol from which the properties need to be set. 79 */ 80 void spi_nor_spimem_setup_op(const struct spi_nor *nor, 81 struct spi_mem_op *op, 82 const enum spi_nor_protocol proto) 83 { 84 u8 ext; 85 86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); 87 88 if (op->addr.nbytes) 89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); 90 91 if (op->dummy.nbytes) 92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); 93 94 if (op->data.nbytes) 95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); 96 97 if (spi_nor_protocol_is_dtr(proto)) { 98 /* 99 * SPIMEM supports mixed DTR modes, but right now we can only 100 * have all phases either DTR or STR. IOW, SPIMEM can have 101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4 102 * phases to either DTR or STR. 103 */ 104 op->cmd.dtr = true; 105 op->addr.dtr = true; 106 op->dummy.dtr = true; 107 op->data.dtr = true; 108 109 /* 2 bytes per clock cycle in DTR mode. */ 110 op->dummy.nbytes *= 2; 111 112 ext = spi_nor_get_cmd_ext(nor, op); 113 op->cmd.opcode = (op->cmd.opcode << 8) | ext; 114 op->cmd.nbytes = 2; 115 } 116 } 117 118 /** 119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data 120 * transfer 121 * @nor: pointer to 'struct spi_nor' 122 * @op: pointer to 'struct spi_mem_op' template for transfer 123 * 124 * If we have to use the bounce buffer, the data field in @op will be updated. 125 * 126 * Return: true if the bounce buffer is needed, false if not 127 */ 128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op) 129 { 130 /* op->data.buf.in occupies the same memory as op->data.buf.out */ 131 if (object_is_on_stack(op->data.buf.in) || 132 !virt_addr_valid(op->data.buf.in)) { 133 if (op->data.nbytes > nor->bouncebuf_size) 134 op->data.nbytes = nor->bouncebuf_size; 135 op->data.buf.in = nor->bouncebuf; 136 return true; 137 } 138 139 return false; 140 } 141 142 /** 143 * spi_nor_spimem_exec_op() - execute a memory operation 144 * @nor: pointer to 'struct spi_nor' 145 * @op: pointer to 'struct spi_mem_op' template for transfer 146 * 147 * Return: 0 on success, -error otherwise. 148 */ 149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) 150 { 151 int error; 152 153 error = spi_mem_adjust_op_size(nor->spimem, op); 154 if (error) 155 return error; 156 157 return spi_mem_exec_op(nor->spimem, op); 158 } 159 160 static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, 161 u8 *buf, size_t len) 162 { 163 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 164 return -EOPNOTSUPP; 165 166 return nor->controller_ops->read_reg(nor, opcode, buf, len); 167 } 168 169 static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, 170 const u8 *buf, size_t len) 171 { 172 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 173 return -EOPNOTSUPP; 174 175 return nor->controller_ops->write_reg(nor, opcode, buf, len); 176 } 177 178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs) 179 { 180 if (spi_nor_protocol_is_dtr(nor->write_proto)) 181 return -EOPNOTSUPP; 182 183 return nor->controller_ops->erase(nor, offs); 184 } 185 186 /** 187 * spi_nor_spimem_read_data() - read data from flash's memory region via 188 * spi-mem 189 * @nor: pointer to 'struct spi_nor' 190 * @from: offset to read from 191 * @len: number of bytes to read 192 * @buf: pointer to dst buffer 193 * 194 * Return: number of bytes read successfully, -errno otherwise 195 */ 196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, 197 size_t len, u8 *buf) 198 { 199 struct spi_mem_op op = 200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 201 SPI_MEM_OP_ADDR(nor->addr_width, from, 0), 202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 203 SPI_MEM_OP_DATA_IN(len, buf, 0)); 204 bool usebouncebuf; 205 ssize_t nbytes; 206 int error; 207 208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto); 209 210 /* convert the dummy cycles to the number of bytes */ 211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 212 if (spi_nor_protocol_is_dtr(nor->read_proto)) 213 op.dummy.nbytes *= 2; 214 215 usebouncebuf = spi_nor_spimem_bounce(nor, &op); 216 217 if (nor->dirmap.rdesc) { 218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val, 219 op.data.nbytes, op.data.buf.in); 220 } else { 221 error = spi_nor_spimem_exec_op(nor, &op); 222 if (error) 223 return error; 224 nbytes = op.data.nbytes; 225 } 226 227 if (usebouncebuf && nbytes > 0) 228 memcpy(buf, op.data.buf.in, nbytes); 229 230 return nbytes; 231 } 232 233 /** 234 * spi_nor_read_data() - read data from flash memory 235 * @nor: pointer to 'struct spi_nor' 236 * @from: offset to read from 237 * @len: number of bytes to read 238 * @buf: pointer to dst buffer 239 * 240 * Return: number of bytes read successfully, -errno otherwise 241 */ 242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) 243 { 244 if (nor->spimem) 245 return spi_nor_spimem_read_data(nor, from, len, buf); 246 247 return nor->controller_ops->read(nor, from, len, buf); 248 } 249 250 /** 251 * spi_nor_spimem_write_data() - write data to flash memory via 252 * spi-mem 253 * @nor: pointer to 'struct spi_nor' 254 * @to: offset to write to 255 * @len: number of bytes to write 256 * @buf: pointer to src buffer 257 * 258 * Return: number of bytes written successfully, -errno otherwise 259 */ 260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, 261 size_t len, const u8 *buf) 262 { 263 struct spi_mem_op op = 264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 265 SPI_MEM_OP_ADDR(nor->addr_width, to, 0), 266 SPI_MEM_OP_NO_DUMMY, 267 SPI_MEM_OP_DATA_OUT(len, buf, 0)); 268 ssize_t nbytes; 269 int error; 270 271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 272 op.addr.nbytes = 0; 273 274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 275 276 if (spi_nor_spimem_bounce(nor, &op)) 277 memcpy(nor->bouncebuf, buf, op.data.nbytes); 278 279 if (nor->dirmap.wdesc) { 280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val, 281 op.data.nbytes, op.data.buf.out); 282 } else { 283 error = spi_nor_spimem_exec_op(nor, &op); 284 if (error) 285 return error; 286 nbytes = op.data.nbytes; 287 } 288 289 return nbytes; 290 } 291 292 /** 293 * spi_nor_write_data() - write data to flash memory 294 * @nor: pointer to 'struct spi_nor' 295 * @to: offset to write to 296 * @len: number of bytes to write 297 * @buf: pointer to src buffer 298 * 299 * Return: number of bytes written successfully, -errno otherwise 300 */ 301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 302 const u8 *buf) 303 { 304 if (nor->spimem) 305 return spi_nor_spimem_write_data(nor, to, len, buf); 306 307 return nor->controller_ops->write(nor, to, len, buf); 308 } 309 310 /** 311 * spi_nor_write_enable() - Set write enable latch with Write Enable command. 312 * @nor: pointer to 'struct spi_nor'. 313 * 314 * Return: 0 on success, -errno otherwise. 315 */ 316 int spi_nor_write_enable(struct spi_nor *nor) 317 { 318 int ret; 319 320 if (nor->spimem) { 321 struct spi_mem_op op = 322 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), 323 SPI_MEM_OP_NO_ADDR, 324 SPI_MEM_OP_NO_DUMMY, 325 SPI_MEM_OP_NO_DATA); 326 327 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 328 329 ret = spi_mem_exec_op(nor->spimem, &op); 330 } else { 331 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, 332 NULL, 0); 333 } 334 335 if (ret) 336 dev_dbg(nor->dev, "error %d on Write Enable\n", ret); 337 338 return ret; 339 } 340 341 /** 342 * spi_nor_write_disable() - Send Write Disable instruction to the chip. 343 * @nor: pointer to 'struct spi_nor'. 344 * 345 * Return: 0 on success, -errno otherwise. 346 */ 347 int spi_nor_write_disable(struct spi_nor *nor) 348 { 349 int ret; 350 351 if (nor->spimem) { 352 struct spi_mem_op op = 353 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), 354 SPI_MEM_OP_NO_ADDR, 355 SPI_MEM_OP_NO_DUMMY, 356 SPI_MEM_OP_NO_DATA); 357 358 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 359 360 ret = spi_mem_exec_op(nor->spimem, &op); 361 } else { 362 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, 363 NULL, 0); 364 } 365 366 if (ret) 367 dev_dbg(nor->dev, "error %d on Write Disable\n", ret); 368 369 return ret; 370 } 371 372 /** 373 * spi_nor_read_sr() - Read the Status Register. 374 * @nor: pointer to 'struct spi_nor'. 375 * @sr: pointer to a DMA-able buffer where the value of the 376 * Status Register will be written. Should be at least 2 bytes. 377 * 378 * Return: 0 on success, -errno otherwise. 379 */ 380 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) 381 { 382 int ret; 383 384 if (nor->spimem) { 385 struct spi_mem_op op = 386 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), 387 SPI_MEM_OP_NO_ADDR, 388 SPI_MEM_OP_NO_DUMMY, 389 SPI_MEM_OP_DATA_IN(1, sr, 0)); 390 391 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 392 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 393 op.dummy.nbytes = nor->params->rdsr_dummy; 394 /* 395 * We don't want to read only one byte in DTR mode. So, 396 * read 2 and then discard the second byte. 397 */ 398 op.data.nbytes = 2; 399 } 400 401 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 402 403 ret = spi_mem_exec_op(nor->spimem, &op); 404 } else { 405 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, 406 1); 407 } 408 409 if (ret) 410 dev_dbg(nor->dev, "error %d reading SR\n", ret); 411 412 return ret; 413 } 414 415 /** 416 * spi_nor_read_fsr() - Read the Flag Status Register. 417 * @nor: pointer to 'struct spi_nor' 418 * @fsr: pointer to a DMA-able buffer where the value of the 419 * Flag Status Register will be written. Should be at least 2 420 * bytes. 421 * 422 * Return: 0 on success, -errno otherwise. 423 */ 424 static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) 425 { 426 int ret; 427 428 if (nor->spimem) { 429 struct spi_mem_op op = 430 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), 431 SPI_MEM_OP_NO_ADDR, 432 SPI_MEM_OP_NO_DUMMY, 433 SPI_MEM_OP_DATA_IN(1, fsr, 0)); 434 435 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 436 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 437 op.dummy.nbytes = nor->params->rdsr_dummy; 438 /* 439 * We don't want to read only one byte in DTR mode. So, 440 * read 2 and then discard the second byte. 441 */ 442 op.data.nbytes = 2; 443 } 444 445 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 446 447 ret = spi_mem_exec_op(nor->spimem, &op); 448 } else { 449 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, 450 1); 451 } 452 453 if (ret) 454 dev_dbg(nor->dev, "error %d reading FSR\n", ret); 455 456 return ret; 457 } 458 459 /** 460 * spi_nor_read_cr() - Read the Configuration Register using the 461 * SPINOR_OP_RDCR (35h) command. 462 * @nor: pointer to 'struct spi_nor' 463 * @cr: pointer to a DMA-able buffer where the value of the 464 * Configuration Register will be written. 465 * 466 * Return: 0 on success, -errno otherwise. 467 */ 468 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) 469 { 470 int ret; 471 472 if (nor->spimem) { 473 struct spi_mem_op op = 474 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), 475 SPI_MEM_OP_NO_ADDR, 476 SPI_MEM_OP_NO_DUMMY, 477 SPI_MEM_OP_DATA_IN(1, cr, 0)); 478 479 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 480 481 ret = spi_mem_exec_op(nor->spimem, &op); 482 } else { 483 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, 484 1); 485 } 486 487 if (ret) 488 dev_dbg(nor->dev, "error %d reading CR\n", ret); 489 490 return ret; 491 } 492 493 /** 494 * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode. 495 * @nor: pointer to 'struct spi_nor'. 496 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 497 * address mode. 498 * 499 * Return: 0 on success, -errno otherwise. 500 */ 501 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 502 { 503 int ret; 504 505 if (nor->spimem) { 506 struct spi_mem_op op = 507 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? 508 SPINOR_OP_EN4B : 509 SPINOR_OP_EX4B, 510 0), 511 SPI_MEM_OP_NO_ADDR, 512 SPI_MEM_OP_NO_DUMMY, 513 SPI_MEM_OP_NO_DATA); 514 515 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 516 517 ret = spi_mem_exec_op(nor->spimem, &op); 518 } else { 519 ret = spi_nor_controller_ops_write_reg(nor, 520 enable ? SPINOR_OP_EN4B : 521 SPINOR_OP_EX4B, 522 NULL, 0); 523 } 524 525 if (ret) 526 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 527 528 return ret; 529 } 530 531 /** 532 * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion 533 * flashes. 534 * @nor: pointer to 'struct spi_nor'. 535 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 536 * address mode. 537 * 538 * Return: 0 on success, -errno otherwise. 539 */ 540 static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 541 { 542 int ret; 543 544 nor->bouncebuf[0] = enable << 7; 545 546 if (nor->spimem) { 547 struct spi_mem_op op = 548 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), 549 SPI_MEM_OP_NO_ADDR, 550 SPI_MEM_OP_NO_DUMMY, 551 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); 552 553 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 554 555 ret = spi_mem_exec_op(nor->spimem, &op); 556 } else { 557 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR, 558 nor->bouncebuf, 1); 559 } 560 561 if (ret) 562 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 563 564 return ret; 565 } 566 567 /** 568 * spi_nor_write_ear() - Write Extended Address Register. 569 * @nor: pointer to 'struct spi_nor'. 570 * @ear: value to write to the Extended Address Register. 571 * 572 * Return: 0 on success, -errno otherwise. 573 */ 574 int spi_nor_write_ear(struct spi_nor *nor, u8 ear) 575 { 576 int ret; 577 578 nor->bouncebuf[0] = ear; 579 580 if (nor->spimem) { 581 struct spi_mem_op op = 582 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0), 583 SPI_MEM_OP_NO_ADDR, 584 SPI_MEM_OP_NO_DUMMY, 585 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); 586 587 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 588 589 ret = spi_mem_exec_op(nor->spimem, &op); 590 } else { 591 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREAR, 592 nor->bouncebuf, 1); 593 } 594 595 if (ret) 596 dev_dbg(nor->dev, "error %d writing EAR\n", ret); 597 598 return ret; 599 } 600 601 /** 602 * spi_nor_xread_sr() - Read the Status Register on S3AN flashes. 603 * @nor: pointer to 'struct spi_nor'. 604 * @sr: pointer to a DMA-able buffer where the value of the 605 * Status Register will be written. 606 * 607 * Return: 0 on success, -errno otherwise. 608 */ 609 int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) 610 { 611 int ret; 612 613 if (nor->spimem) { 614 struct spi_mem_op op = 615 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0), 616 SPI_MEM_OP_NO_ADDR, 617 SPI_MEM_OP_NO_DUMMY, 618 SPI_MEM_OP_DATA_IN(1, sr, 0)); 619 620 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 621 622 ret = spi_mem_exec_op(nor->spimem, &op); 623 } else { 624 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr, 625 1); 626 } 627 628 if (ret) 629 dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); 630 631 return ret; 632 } 633 634 /** 635 * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if 636 * the flash is ready for new commands. 637 * @nor: pointer to 'struct spi_nor'. 638 * 639 * Return: 1 if ready, 0 if not ready, -errno on errors. 640 */ 641 static int spi_nor_xsr_ready(struct spi_nor *nor) 642 { 643 int ret; 644 645 ret = spi_nor_xread_sr(nor, nor->bouncebuf); 646 if (ret) 647 return ret; 648 649 return !!(nor->bouncebuf[0] & XSR_RDY); 650 } 651 652 /** 653 * spi_nor_clear_sr() - Clear the Status Register. 654 * @nor: pointer to 'struct spi_nor'. 655 */ 656 static void spi_nor_clear_sr(struct spi_nor *nor) 657 { 658 int ret; 659 660 if (nor->spimem) { 661 struct spi_mem_op op = 662 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), 663 SPI_MEM_OP_NO_ADDR, 664 SPI_MEM_OP_NO_DUMMY, 665 SPI_MEM_OP_NO_DATA); 666 667 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 668 669 ret = spi_mem_exec_op(nor->spimem, &op); 670 } else { 671 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, 672 NULL, 0); 673 } 674 675 if (ret) 676 dev_dbg(nor->dev, "error %d clearing SR\n", ret); 677 } 678 679 /** 680 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready 681 * for new commands. 682 * @nor: pointer to 'struct spi_nor'. 683 * 684 * Return: 1 if ready, 0 if not ready, -errno on errors. 685 */ 686 static int spi_nor_sr_ready(struct spi_nor *nor) 687 { 688 int ret = spi_nor_read_sr(nor, nor->bouncebuf); 689 690 if (ret) 691 return ret; 692 693 if (nor->flags & SNOR_F_USE_CLSR && 694 nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 695 if (nor->bouncebuf[0] & SR_E_ERR) 696 dev_err(nor->dev, "Erase Error occurred\n"); 697 else 698 dev_err(nor->dev, "Programming Error occurred\n"); 699 700 spi_nor_clear_sr(nor); 701 702 /* 703 * WEL bit remains set to one when an erase or page program 704 * error occurs. Issue a Write Disable command to protect 705 * against inadvertent writes that can possibly corrupt the 706 * contents of the memory. 707 */ 708 ret = spi_nor_write_disable(nor); 709 if (ret) 710 return ret; 711 712 return -EIO; 713 } 714 715 return !(nor->bouncebuf[0] & SR_WIP); 716 } 717 718 /** 719 * spi_nor_clear_fsr() - Clear the Flag Status Register. 720 * @nor: pointer to 'struct spi_nor'. 721 */ 722 static void spi_nor_clear_fsr(struct spi_nor *nor) 723 { 724 int ret; 725 726 if (nor->spimem) { 727 struct spi_mem_op op = 728 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), 729 SPI_MEM_OP_NO_ADDR, 730 SPI_MEM_OP_NO_DUMMY, 731 SPI_MEM_OP_NO_DATA); 732 733 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 734 735 ret = spi_mem_exec_op(nor->spimem, &op); 736 } else { 737 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, 738 NULL, 0); 739 } 740 741 if (ret) 742 dev_dbg(nor->dev, "error %d clearing FSR\n", ret); 743 } 744 745 /** 746 * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is 747 * ready for new commands. 748 * @nor: pointer to 'struct spi_nor'. 749 * 750 * Return: 1 if ready, 0 if not ready, -errno on errors. 751 */ 752 static int spi_nor_fsr_ready(struct spi_nor *nor) 753 { 754 int ret = spi_nor_read_fsr(nor, nor->bouncebuf); 755 756 if (ret) 757 return ret; 758 759 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { 760 if (nor->bouncebuf[0] & FSR_E_ERR) 761 dev_err(nor->dev, "Erase operation failed.\n"); 762 else 763 dev_err(nor->dev, "Program operation failed.\n"); 764 765 if (nor->bouncebuf[0] & FSR_PT_ERR) 766 dev_err(nor->dev, 767 "Attempted to modify a protected sector.\n"); 768 769 spi_nor_clear_fsr(nor); 770 771 /* 772 * WEL bit remains set to one when an erase or page program 773 * error occurs. Issue a Write Disable command to protect 774 * against inadvertent writes that can possibly corrupt the 775 * contents of the memory. 776 */ 777 ret = spi_nor_write_disable(nor); 778 if (ret) 779 return ret; 780 781 return -EIO; 782 } 783 784 return !!(nor->bouncebuf[0] & FSR_READY); 785 } 786 787 /** 788 * spi_nor_ready() - Query the flash to see if it is ready for new commands. 789 * @nor: pointer to 'struct spi_nor'. 790 * 791 * Return: 1 if ready, 0 if not ready, -errno on errors. 792 */ 793 static int spi_nor_ready(struct spi_nor *nor) 794 { 795 int sr, fsr; 796 797 if (nor->flags & SNOR_F_READY_XSR_RDY) 798 sr = spi_nor_xsr_ready(nor); 799 else 800 sr = spi_nor_sr_ready(nor); 801 if (sr < 0) 802 return sr; 803 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 804 if (fsr < 0) 805 return fsr; 806 return sr && fsr; 807 } 808 809 /** 810 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the 811 * Status Register until ready, or timeout occurs. 812 * @nor: pointer to "struct spi_nor". 813 * @timeout_jiffies: jiffies to wait until timeout. 814 * 815 * Return: 0 on success, -errno otherwise. 816 */ 817 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 818 unsigned long timeout_jiffies) 819 { 820 unsigned long deadline; 821 int timeout = 0, ret; 822 823 deadline = jiffies + timeout_jiffies; 824 825 while (!timeout) { 826 if (time_after_eq(jiffies, deadline)) 827 timeout = 1; 828 829 ret = spi_nor_ready(nor); 830 if (ret < 0) 831 return ret; 832 if (ret) 833 return 0; 834 835 cond_resched(); 836 } 837 838 dev_dbg(nor->dev, "flash operation timed out\n"); 839 840 return -ETIMEDOUT; 841 } 842 843 /** 844 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the 845 * flash to be ready, or timeout occurs. 846 * @nor: pointer to "struct spi_nor". 847 * 848 * Return: 0 on success, -errno otherwise. 849 */ 850 int spi_nor_wait_till_ready(struct spi_nor *nor) 851 { 852 return spi_nor_wait_till_ready_with_timeout(nor, 853 DEFAULT_READY_WAIT_JIFFIES); 854 } 855 856 /** 857 * spi_nor_global_block_unlock() - Unlock Global Block Protection. 858 * @nor: pointer to 'struct spi_nor'. 859 * 860 * Return: 0 on success, -errno otherwise. 861 */ 862 int spi_nor_global_block_unlock(struct spi_nor *nor) 863 { 864 int ret; 865 866 ret = spi_nor_write_enable(nor); 867 if (ret) 868 return ret; 869 870 if (nor->spimem) { 871 struct spi_mem_op op = 872 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), 873 SPI_MEM_OP_NO_ADDR, 874 SPI_MEM_OP_NO_DUMMY, 875 SPI_MEM_OP_NO_DATA); 876 877 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 878 879 ret = spi_mem_exec_op(nor->spimem, &op); 880 } else { 881 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK, 882 NULL, 0); 883 } 884 885 if (ret) { 886 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); 887 return ret; 888 } 889 890 return spi_nor_wait_till_ready(nor); 891 } 892 893 /** 894 * spi_nor_write_sr() - Write the Status Register. 895 * @nor: pointer to 'struct spi_nor'. 896 * @sr: pointer to DMA-able buffer to write to the Status Register. 897 * @len: number of bytes to write to the Status Register. 898 * 899 * Return: 0 on success, -errno otherwise. 900 */ 901 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) 902 { 903 int ret; 904 905 ret = spi_nor_write_enable(nor); 906 if (ret) 907 return ret; 908 909 if (nor->spimem) { 910 struct spi_mem_op op = 911 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), 912 SPI_MEM_OP_NO_ADDR, 913 SPI_MEM_OP_NO_DUMMY, 914 SPI_MEM_OP_DATA_OUT(len, sr, 0)); 915 916 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 917 918 ret = spi_mem_exec_op(nor->spimem, &op); 919 } else { 920 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, 921 len); 922 } 923 924 if (ret) { 925 dev_dbg(nor->dev, "error %d writing SR\n", ret); 926 return ret; 927 } 928 929 return spi_nor_wait_till_ready(nor); 930 } 931 932 /** 933 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and 934 * ensure that the byte written match the received value. 935 * @nor: pointer to a 'struct spi_nor'. 936 * @sr1: byte value to be written to the Status Register. 937 * 938 * Return: 0 on success, -errno otherwise. 939 */ 940 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) 941 { 942 int ret; 943 944 nor->bouncebuf[0] = sr1; 945 946 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); 947 if (ret) 948 return ret; 949 950 ret = spi_nor_read_sr(nor, nor->bouncebuf); 951 if (ret) 952 return ret; 953 954 if (nor->bouncebuf[0] != sr1) { 955 dev_dbg(nor->dev, "SR1: read back test failed\n"); 956 return -EIO; 957 } 958 959 return 0; 960 } 961 962 /** 963 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the 964 * Status Register 2 in one shot. Ensure that the byte written in the Status 965 * Register 1 match the received value, and that the 16-bit Write did not 966 * affect what was already in the Status Register 2. 967 * @nor: pointer to a 'struct spi_nor'. 968 * @sr1: byte value to be written to the Status Register 1. 969 * 970 * Return: 0 on success, -errno otherwise. 971 */ 972 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 973 { 974 int ret; 975 u8 *sr_cr = nor->bouncebuf; 976 u8 cr_written; 977 978 /* Make sure we don't overwrite the contents of Status Register 2. */ 979 if (!(nor->flags & SNOR_F_NO_READ_CR)) { 980 ret = spi_nor_read_cr(nor, &sr_cr[1]); 981 if (ret) 982 return ret; 983 } else if (nor->params->quad_enable) { 984 /* 985 * If the Status Register 2 Read command (35h) is not 986 * supported, we should at least be sure we don't 987 * change the value of the SR2 Quad Enable bit. 988 * 989 * We can safely assume that when the Quad Enable method is 990 * set, the value of the QE bit is one, as a consequence of the 991 * nor->params->quad_enable() call. 992 * 993 * We can safely assume that the Quad Enable bit is present in 994 * the Status Register 2 at BIT(1). According to the JESD216 995 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit 996 * Write Status (01h) command is available just for the cases 997 * in which the QE bit is described in SR2 at BIT(1). 998 */ 999 sr_cr[1] = SR2_QUAD_EN_BIT1; 1000 } else { 1001 sr_cr[1] = 0; 1002 } 1003 1004 sr_cr[0] = sr1; 1005 1006 ret = spi_nor_write_sr(nor, sr_cr, 2); 1007 if (ret) 1008 return ret; 1009 1010 if (nor->flags & SNOR_F_NO_READ_CR) 1011 return 0; 1012 1013 cr_written = sr_cr[1]; 1014 1015 ret = spi_nor_read_cr(nor, &sr_cr[1]); 1016 if (ret) 1017 return ret; 1018 1019 if (cr_written != sr_cr[1]) { 1020 dev_dbg(nor->dev, "CR: read back test failed\n"); 1021 return -EIO; 1022 } 1023 1024 return 0; 1025 } 1026 1027 /** 1028 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the 1029 * Configuration Register in one shot. Ensure that the byte written in the 1030 * Configuration Register match the received value, and that the 16-bit Write 1031 * did not affect what was already in the Status Register 1. 1032 * @nor: pointer to a 'struct spi_nor'. 1033 * @cr: byte value to be written to the Configuration Register. 1034 * 1035 * Return: 0 on success, -errno otherwise. 1036 */ 1037 static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) 1038 { 1039 int ret; 1040 u8 *sr_cr = nor->bouncebuf; 1041 u8 sr_written; 1042 1043 /* Keep the current value of the Status Register 1. */ 1044 ret = spi_nor_read_sr(nor, sr_cr); 1045 if (ret) 1046 return ret; 1047 1048 sr_cr[1] = cr; 1049 1050 ret = spi_nor_write_sr(nor, sr_cr, 2); 1051 if (ret) 1052 return ret; 1053 1054 sr_written = sr_cr[0]; 1055 1056 ret = spi_nor_read_sr(nor, sr_cr); 1057 if (ret) 1058 return ret; 1059 1060 if (sr_written != sr_cr[0]) { 1061 dev_dbg(nor->dev, "SR: Read back test failed\n"); 1062 return -EIO; 1063 } 1064 1065 if (nor->flags & SNOR_F_NO_READ_CR) 1066 return 0; 1067 1068 ret = spi_nor_read_cr(nor, &sr_cr[1]); 1069 if (ret) 1070 return ret; 1071 1072 if (cr != sr_cr[1]) { 1073 dev_dbg(nor->dev, "CR: read back test failed\n"); 1074 return -EIO; 1075 } 1076 1077 return 0; 1078 } 1079 1080 /** 1081 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that 1082 * the byte written match the received value without affecting other bits in the 1083 * Status Register 1 and 2. 1084 * @nor: pointer to a 'struct spi_nor'. 1085 * @sr1: byte value to be written to the Status Register. 1086 * 1087 * Return: 0 on success, -errno otherwise. 1088 */ 1089 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) 1090 { 1091 if (nor->flags & SNOR_F_HAS_16BIT_SR) 1092 return spi_nor_write_16bit_sr_and_check(nor, sr1); 1093 1094 return spi_nor_write_sr1_and_check(nor, sr1); 1095 } 1096 1097 /** 1098 * spi_nor_write_sr2() - Write the Status Register 2 using the 1099 * SPINOR_OP_WRSR2 (3eh) command. 1100 * @nor: pointer to 'struct spi_nor'. 1101 * @sr2: pointer to DMA-able buffer to write to the Status Register 2. 1102 * 1103 * Return: 0 on success, -errno otherwise. 1104 */ 1105 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) 1106 { 1107 int ret; 1108 1109 ret = spi_nor_write_enable(nor); 1110 if (ret) 1111 return ret; 1112 1113 if (nor->spimem) { 1114 struct spi_mem_op op = 1115 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), 1116 SPI_MEM_OP_NO_ADDR, 1117 SPI_MEM_OP_NO_DUMMY, 1118 SPI_MEM_OP_DATA_OUT(1, sr2, 0)); 1119 1120 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1121 1122 ret = spi_mem_exec_op(nor->spimem, &op); 1123 } else { 1124 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, 1125 sr2, 1); 1126 } 1127 1128 if (ret) { 1129 dev_dbg(nor->dev, "error %d writing SR2\n", ret); 1130 return ret; 1131 } 1132 1133 return spi_nor_wait_till_ready(nor); 1134 } 1135 1136 /** 1137 * spi_nor_read_sr2() - Read the Status Register 2 using the 1138 * SPINOR_OP_RDSR2 (3fh) command. 1139 * @nor: pointer to 'struct spi_nor'. 1140 * @sr2: pointer to DMA-able buffer where the value of the 1141 * Status Register 2 will be written. 1142 * 1143 * Return: 0 on success, -errno otherwise. 1144 */ 1145 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) 1146 { 1147 int ret; 1148 1149 if (nor->spimem) { 1150 struct spi_mem_op op = 1151 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), 1152 SPI_MEM_OP_NO_ADDR, 1153 SPI_MEM_OP_NO_DUMMY, 1154 SPI_MEM_OP_DATA_IN(1, sr2, 0)); 1155 1156 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1157 1158 ret = spi_mem_exec_op(nor->spimem, &op); 1159 } else { 1160 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, 1161 1); 1162 } 1163 1164 if (ret) 1165 dev_dbg(nor->dev, "error %d reading SR2\n", ret); 1166 1167 return ret; 1168 } 1169 1170 /** 1171 * spi_nor_erase_chip() - Erase the entire flash memory. 1172 * @nor: pointer to 'struct spi_nor'. 1173 * 1174 * Return: 0 on success, -errno otherwise. 1175 */ 1176 static int spi_nor_erase_chip(struct spi_nor *nor) 1177 { 1178 int ret; 1179 1180 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); 1181 1182 if (nor->spimem) { 1183 struct spi_mem_op op = 1184 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), 1185 SPI_MEM_OP_NO_ADDR, 1186 SPI_MEM_OP_NO_DUMMY, 1187 SPI_MEM_OP_NO_DATA); 1188 1189 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 1190 1191 ret = spi_mem_exec_op(nor->spimem, &op); 1192 } else { 1193 ret = spi_nor_controller_ops_write_reg(nor, 1194 SPINOR_OP_CHIP_ERASE, 1195 NULL, 0); 1196 } 1197 1198 if (ret) 1199 dev_dbg(nor->dev, "error %d erasing chip\n", ret); 1200 1201 return ret; 1202 } 1203 1204 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 1205 { 1206 size_t i; 1207 1208 for (i = 0; i < size; i++) 1209 if (table[i][0] == opcode) 1210 return table[i][1]; 1211 1212 /* No conversion found, keep input op code. */ 1213 return opcode; 1214 } 1215 1216 u8 spi_nor_convert_3to4_read(u8 opcode) 1217 { 1218 static const u8 spi_nor_3to4_read[][2] = { 1219 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 1220 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 1221 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 1222 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 1223 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 1224 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 1225 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, 1226 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, 1227 1228 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 1229 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 1230 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 1231 }; 1232 1233 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 1234 ARRAY_SIZE(spi_nor_3to4_read)); 1235 } 1236 1237 static u8 spi_nor_convert_3to4_program(u8 opcode) 1238 { 1239 static const u8 spi_nor_3to4_program[][2] = { 1240 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 1241 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 1242 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 1243 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, 1244 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, 1245 }; 1246 1247 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 1248 ARRAY_SIZE(spi_nor_3to4_program)); 1249 } 1250 1251 static u8 spi_nor_convert_3to4_erase(u8 opcode) 1252 { 1253 static const u8 spi_nor_3to4_erase[][2] = { 1254 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 1255 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 1256 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 1257 }; 1258 1259 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 1260 ARRAY_SIZE(spi_nor_3to4_erase)); 1261 } 1262 1263 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor) 1264 { 1265 return !!nor->params->erase_map.uniform_erase_type; 1266 } 1267 1268 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor) 1269 { 1270 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 1271 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 1272 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 1273 1274 if (!spi_nor_has_uniform_erase(nor)) { 1275 struct spi_nor_erase_map *map = &nor->params->erase_map; 1276 struct spi_nor_erase_type *erase; 1277 int i; 1278 1279 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1280 erase = &map->erase_type[i]; 1281 erase->opcode = 1282 spi_nor_convert_3to4_erase(erase->opcode); 1283 } 1284 } 1285 } 1286 1287 int spi_nor_lock_and_prep(struct spi_nor *nor) 1288 { 1289 int ret = 0; 1290 1291 mutex_lock(&nor->lock); 1292 1293 if (nor->controller_ops && nor->controller_ops->prepare) { 1294 ret = nor->controller_ops->prepare(nor); 1295 if (ret) { 1296 mutex_unlock(&nor->lock); 1297 return ret; 1298 } 1299 } 1300 return ret; 1301 } 1302 1303 void spi_nor_unlock_and_unprep(struct spi_nor *nor) 1304 { 1305 if (nor->controller_ops && nor->controller_ops->unprepare) 1306 nor->controller_ops->unprepare(nor); 1307 mutex_unlock(&nor->lock); 1308 } 1309 1310 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr) 1311 { 1312 if (!nor->params->convert_addr) 1313 return addr; 1314 1315 return nor->params->convert_addr(nor, addr); 1316 } 1317 1318 /* 1319 * Initiate the erasure of a single sector 1320 */ 1321 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 1322 { 1323 int i; 1324 1325 addr = spi_nor_convert_addr(nor, addr); 1326 1327 if (nor->spimem) { 1328 struct spi_mem_op op = 1329 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0), 1330 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), 1331 SPI_MEM_OP_NO_DUMMY, 1332 SPI_MEM_OP_NO_DATA); 1333 1334 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 1335 1336 return spi_mem_exec_op(nor->spimem, &op); 1337 } else if (nor->controller_ops->erase) { 1338 return spi_nor_controller_ops_erase(nor, addr); 1339 } 1340 1341 /* 1342 * Default implementation, if driver doesn't have a specialized HW 1343 * control 1344 */ 1345 for (i = nor->addr_width - 1; i >= 0; i--) { 1346 nor->bouncebuf[i] = addr & 0xff; 1347 addr >>= 8; 1348 } 1349 1350 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, 1351 nor->bouncebuf, nor->addr_width); 1352 } 1353 1354 /** 1355 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend 1356 * @erase: pointer to a structure that describes a SPI NOR erase type 1357 * @dividend: dividend value 1358 * @remainder: pointer to u32 remainder (will be updated) 1359 * 1360 * Return: the result of the division 1361 */ 1362 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase, 1363 u64 dividend, u32 *remainder) 1364 { 1365 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 1366 *remainder = (u32)dividend & erase->size_mask; 1367 return dividend >> erase->size_shift; 1368 } 1369 1370 /** 1371 * spi_nor_find_best_erase_type() - find the best erase type for the given 1372 * offset in the serial flash memory and the 1373 * number of bytes to erase. The region in 1374 * which the address fits is expected to be 1375 * provided. 1376 * @map: the erase map of the SPI NOR 1377 * @region: pointer to a structure that describes a SPI NOR erase region 1378 * @addr: offset in the serial flash memory 1379 * @len: number of bytes to erase 1380 * 1381 * Return: a pointer to the best fitted erase type, NULL otherwise. 1382 */ 1383 static const struct spi_nor_erase_type * 1384 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, 1385 const struct spi_nor_erase_region *region, 1386 u64 addr, u32 len) 1387 { 1388 const struct spi_nor_erase_type *erase; 1389 u32 rem; 1390 int i; 1391 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 1392 1393 /* 1394 * Erase types are ordered by size, with the smallest erase type at 1395 * index 0. 1396 */ 1397 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 1398 /* Does the erase region support the tested erase type? */ 1399 if (!(erase_mask & BIT(i))) 1400 continue; 1401 1402 erase = &map->erase_type[i]; 1403 1404 /* Alignment is not mandatory for overlaid regions */ 1405 if (region->offset & SNOR_OVERLAID_REGION && 1406 region->size <= len) 1407 return erase; 1408 1409 /* Don't erase more than what the user has asked for. */ 1410 if (erase->size > len) 1411 continue; 1412 1413 spi_nor_div_by_erase_size(erase, addr, &rem); 1414 if (rem) 1415 continue; 1416 else 1417 return erase; 1418 } 1419 1420 return NULL; 1421 } 1422 1423 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region) 1424 { 1425 return region->offset & SNOR_LAST_REGION; 1426 } 1427 1428 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region) 1429 { 1430 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; 1431 } 1432 1433 /** 1434 * spi_nor_region_next() - get the next spi nor region 1435 * @region: pointer to a structure that describes a SPI NOR erase region 1436 * 1437 * Return: the next spi nor region or NULL if last region. 1438 */ 1439 struct spi_nor_erase_region * 1440 spi_nor_region_next(struct spi_nor_erase_region *region) 1441 { 1442 if (spi_nor_region_is_last(region)) 1443 return NULL; 1444 region++; 1445 return region; 1446 } 1447 1448 /** 1449 * spi_nor_find_erase_region() - find the region of the serial flash memory in 1450 * which the offset fits 1451 * @map: the erase map of the SPI NOR 1452 * @addr: offset in the serial flash memory 1453 * 1454 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno) 1455 * otherwise. 1456 */ 1457 static struct spi_nor_erase_region * 1458 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr) 1459 { 1460 struct spi_nor_erase_region *region = map->regions; 1461 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1462 u64 region_end = region_start + region->size; 1463 1464 while (addr < region_start || addr >= region_end) { 1465 region = spi_nor_region_next(region); 1466 if (!region) 1467 return ERR_PTR(-EINVAL); 1468 1469 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1470 region_end = region_start + region->size; 1471 } 1472 1473 return region; 1474 } 1475 1476 /** 1477 * spi_nor_init_erase_cmd() - initialize an erase command 1478 * @region: pointer to a structure that describes a SPI NOR erase region 1479 * @erase: pointer to a structure that describes a SPI NOR erase type 1480 * 1481 * Return: the pointer to the allocated erase command, ERR_PTR(-errno) 1482 * otherwise. 1483 */ 1484 static struct spi_nor_erase_command * 1485 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region, 1486 const struct spi_nor_erase_type *erase) 1487 { 1488 struct spi_nor_erase_command *cmd; 1489 1490 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); 1491 if (!cmd) 1492 return ERR_PTR(-ENOMEM); 1493 1494 INIT_LIST_HEAD(&cmd->list); 1495 cmd->opcode = erase->opcode; 1496 cmd->count = 1; 1497 1498 if (region->offset & SNOR_OVERLAID_REGION) 1499 cmd->size = region->size; 1500 else 1501 cmd->size = erase->size; 1502 1503 return cmd; 1504 } 1505 1506 /** 1507 * spi_nor_destroy_erase_cmd_list() - destroy erase command list 1508 * @erase_list: list of erase commands 1509 */ 1510 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list) 1511 { 1512 struct spi_nor_erase_command *cmd, *next; 1513 1514 list_for_each_entry_safe(cmd, next, erase_list, list) { 1515 list_del(&cmd->list); 1516 kfree(cmd); 1517 } 1518 } 1519 1520 /** 1521 * spi_nor_init_erase_cmd_list() - initialize erase command list 1522 * @nor: pointer to a 'struct spi_nor' 1523 * @erase_list: list of erase commands to be executed once we validate that the 1524 * erase can be performed 1525 * @addr: offset in the serial flash memory 1526 * @len: number of bytes to erase 1527 * 1528 * Builds the list of best fitted erase commands and verifies if the erase can 1529 * be performed. 1530 * 1531 * Return: 0 on success, -errno otherwise. 1532 */ 1533 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, 1534 struct list_head *erase_list, 1535 u64 addr, u32 len) 1536 { 1537 const struct spi_nor_erase_map *map = &nor->params->erase_map; 1538 const struct spi_nor_erase_type *erase, *prev_erase = NULL; 1539 struct spi_nor_erase_region *region; 1540 struct spi_nor_erase_command *cmd = NULL; 1541 u64 region_end; 1542 int ret = -EINVAL; 1543 1544 region = spi_nor_find_erase_region(map, addr); 1545 if (IS_ERR(region)) 1546 return PTR_ERR(region); 1547 1548 region_end = spi_nor_region_end(region); 1549 1550 while (len) { 1551 erase = spi_nor_find_best_erase_type(map, region, addr, len); 1552 if (!erase) 1553 goto destroy_erase_cmd_list; 1554 1555 if (prev_erase != erase || 1556 erase->size != cmd->size || 1557 region->offset & SNOR_OVERLAID_REGION) { 1558 cmd = spi_nor_init_erase_cmd(region, erase); 1559 if (IS_ERR(cmd)) { 1560 ret = PTR_ERR(cmd); 1561 goto destroy_erase_cmd_list; 1562 } 1563 1564 list_add_tail(&cmd->list, erase_list); 1565 } else { 1566 cmd->count++; 1567 } 1568 1569 addr += cmd->size; 1570 len -= cmd->size; 1571 1572 if (len && addr >= region_end) { 1573 region = spi_nor_region_next(region); 1574 if (!region) 1575 goto destroy_erase_cmd_list; 1576 region_end = spi_nor_region_end(region); 1577 } 1578 1579 prev_erase = erase; 1580 } 1581 1582 return 0; 1583 1584 destroy_erase_cmd_list: 1585 spi_nor_destroy_erase_cmd_list(erase_list); 1586 return ret; 1587 } 1588 1589 /** 1590 * spi_nor_erase_multi_sectors() - perform a non-uniform erase 1591 * @nor: pointer to a 'struct spi_nor' 1592 * @addr: offset in the serial flash memory 1593 * @len: number of bytes to erase 1594 * 1595 * Build a list of best fitted erase commands and execute it once we validate 1596 * that the erase can be performed. 1597 * 1598 * Return: 0 on success, -errno otherwise. 1599 */ 1600 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) 1601 { 1602 LIST_HEAD(erase_list); 1603 struct spi_nor_erase_command *cmd, *next; 1604 int ret; 1605 1606 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len); 1607 if (ret) 1608 return ret; 1609 1610 list_for_each_entry_safe(cmd, next, &erase_list, list) { 1611 nor->erase_opcode = cmd->opcode; 1612 while (cmd->count) { 1613 ret = spi_nor_write_enable(nor); 1614 if (ret) 1615 goto destroy_erase_cmd_list; 1616 1617 ret = spi_nor_erase_sector(nor, addr); 1618 if (ret) 1619 goto destroy_erase_cmd_list; 1620 1621 addr += cmd->size; 1622 cmd->count--; 1623 1624 ret = spi_nor_wait_till_ready(nor); 1625 if (ret) 1626 goto destroy_erase_cmd_list; 1627 } 1628 list_del(&cmd->list); 1629 kfree(cmd); 1630 } 1631 1632 return 0; 1633 1634 destroy_erase_cmd_list: 1635 spi_nor_destroy_erase_cmd_list(&erase_list); 1636 return ret; 1637 } 1638 1639 /* 1640 * Erase an address range on the nor chip. The address range may extend 1641 * one or more erase sectors. Return an error if there is a problem erasing. 1642 */ 1643 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 1644 { 1645 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1646 u32 addr, len; 1647 uint32_t rem; 1648 int ret; 1649 1650 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 1651 (long long)instr->len); 1652 1653 if (spi_nor_has_uniform_erase(nor)) { 1654 div_u64_rem(instr->len, mtd->erasesize, &rem); 1655 if (rem) 1656 return -EINVAL; 1657 } 1658 1659 addr = instr->addr; 1660 len = instr->len; 1661 1662 ret = spi_nor_lock_and_prep(nor); 1663 if (ret) 1664 return ret; 1665 1666 /* whole-chip erase? */ 1667 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { 1668 unsigned long timeout; 1669 1670 ret = spi_nor_write_enable(nor); 1671 if (ret) 1672 goto erase_err; 1673 1674 ret = spi_nor_erase_chip(nor); 1675 if (ret) 1676 goto erase_err; 1677 1678 /* 1679 * Scale the timeout linearly with the size of the flash, with 1680 * a minimum calibrated to an old 2MB flash. We could try to 1681 * pull these from CFI/SFDP, but these values should be good 1682 * enough for now. 1683 */ 1684 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, 1685 CHIP_ERASE_2MB_READY_WAIT_JIFFIES * 1686 (unsigned long)(mtd->size / SZ_2M)); 1687 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); 1688 if (ret) 1689 goto erase_err; 1690 1691 /* REVISIT in some cases we could speed up erasing large regions 1692 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up 1693 * to use "small sector erase", but that's not always optimal. 1694 */ 1695 1696 /* "sector"-at-a-time erase */ 1697 } else if (spi_nor_has_uniform_erase(nor)) { 1698 while (len) { 1699 ret = spi_nor_write_enable(nor); 1700 if (ret) 1701 goto erase_err; 1702 1703 ret = spi_nor_erase_sector(nor, addr); 1704 if (ret) 1705 goto erase_err; 1706 1707 addr += mtd->erasesize; 1708 len -= mtd->erasesize; 1709 1710 ret = spi_nor_wait_till_ready(nor); 1711 if (ret) 1712 goto erase_err; 1713 } 1714 1715 /* erase multiple sectors */ 1716 } else { 1717 ret = spi_nor_erase_multi_sectors(nor, addr, len); 1718 if (ret) 1719 goto erase_err; 1720 } 1721 1722 ret = spi_nor_write_disable(nor); 1723 1724 erase_err: 1725 spi_nor_unlock_and_unprep(nor); 1726 1727 return ret; 1728 } 1729 1730 static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor) 1731 { 1732 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 1733 1734 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6) 1735 return mask | SR_BP3_BIT6; 1736 1737 if (nor->flags & SNOR_F_HAS_4BIT_BP) 1738 return mask | SR_BP3; 1739 1740 return mask; 1741 } 1742 1743 static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) 1744 { 1745 if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) 1746 return SR_TB_BIT6; 1747 else 1748 return SR_TB_BIT5; 1749 } 1750 1751 static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) 1752 { 1753 unsigned int bp_slots, bp_slots_needed; 1754 u8 mask = spi_nor_get_sr_bp_mask(nor); 1755 1756 /* Reserved one for "protect none" and one for "protect all". */ 1757 bp_slots = (1 << hweight8(mask)) - 2; 1758 bp_slots_needed = ilog2(nor->info->n_sectors); 1759 1760 if (bp_slots_needed > bp_slots) 1761 return nor->info->sector_size << 1762 (bp_slots_needed - bp_slots); 1763 else 1764 return nor->info->sector_size; 1765 } 1766 1767 static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, 1768 uint64_t *len) 1769 { 1770 struct mtd_info *mtd = &nor->mtd; 1771 u64 min_prot_len; 1772 u8 mask = spi_nor_get_sr_bp_mask(nor); 1773 u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1774 u8 bp, val = sr & mask; 1775 1776 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) 1777 val = (val & ~SR_BP3_BIT6) | SR_BP3; 1778 1779 bp = val >> SR_BP_SHIFT; 1780 1781 if (!bp) { 1782 /* No protection */ 1783 *ofs = 0; 1784 *len = 0; 1785 return; 1786 } 1787 1788 min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1789 *len = min_prot_len << (bp - 1); 1790 1791 if (*len > mtd->size) 1792 *len = mtd->size; 1793 1794 if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask) 1795 *ofs = 0; 1796 else 1797 *ofs = mtd->size - *len; 1798 } 1799 1800 /* 1801 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 1802 * @locked is false); 0 otherwise 1803 */ 1804 static int spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, 1805 uint64_t len, u8 sr, bool locked) 1806 { 1807 loff_t lock_offs; 1808 uint64_t lock_len; 1809 1810 if (!len) 1811 return 1; 1812 1813 spi_nor_get_locked_range_sr(nor, sr, &lock_offs, &lock_len); 1814 1815 if (locked) 1816 /* Requested range is a sub-range of locked range */ 1817 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 1818 else 1819 /* Requested range does not overlap with locked range */ 1820 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 1821 } 1822 1823 static int spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1824 u8 sr) 1825 { 1826 return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); 1827 } 1828 1829 static int spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1830 u8 sr) 1831 { 1832 return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); 1833 } 1834 1835 /* 1836 * Lock a region of the flash. Compatible with ST Micro and similar flash. 1837 * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status 1838 * register 1839 * (SR). Does not support these features found in newer SR bitfields: 1840 * - SEC: sector/block protect - only handle SEC=0 (block protect) 1841 * - CMP: complement protect - only support CMP=0 (range is not complemented) 1842 * 1843 * Support for the following is provided conditionally for some flash: 1844 * - TB: top/bottom protect 1845 * 1846 * Sample table portion for 8MB flash (Winbond w25q64fw): 1847 * 1848 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 1849 * -------------------------------------------------------------------------- 1850 * X | X | 0 | 0 | 0 | NONE | NONE 1851 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 1852 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 1853 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 1854 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 1855 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 1856 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 1857 * X | X | 1 | 1 | 1 | 8 MB | ALL 1858 * ------|-------|-------|-------|-------|---------------|------------------- 1859 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 1860 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 1861 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 1862 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 1863 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 1864 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 1865 * 1866 * Returns negative on errors, 0 on success. 1867 */ 1868 static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1869 { 1870 struct mtd_info *mtd = &nor->mtd; 1871 u64 min_prot_len; 1872 int ret, status_old, status_new; 1873 u8 mask = spi_nor_get_sr_bp_mask(nor); 1874 u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1875 u8 pow, val; 1876 loff_t lock_len; 1877 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1878 bool use_top; 1879 1880 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1881 if (ret) 1882 return ret; 1883 1884 status_old = nor->bouncebuf[0]; 1885 1886 /* If nothing in our range is unlocked, we don't need to do anything */ 1887 if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) 1888 return 0; 1889 1890 /* If anything below us is unlocked, we can't use 'bottom' protection */ 1891 if (!spi_nor_is_locked_sr(nor, 0, ofs, status_old)) 1892 can_be_bottom = false; 1893 1894 /* If anything above us is unlocked, we can't use 'top' protection */ 1895 if (!spi_nor_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 1896 status_old)) 1897 can_be_top = false; 1898 1899 if (!can_be_bottom && !can_be_top) 1900 return -EINVAL; 1901 1902 /* Prefer top, if both are valid */ 1903 use_top = can_be_top; 1904 1905 /* lock_len: length of region that should end up locked */ 1906 if (use_top) 1907 lock_len = mtd->size - ofs; 1908 else 1909 lock_len = ofs + len; 1910 1911 if (lock_len == mtd->size) { 1912 val = mask; 1913 } else { 1914 min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1915 pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; 1916 val = pow << SR_BP_SHIFT; 1917 1918 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) 1919 val = (val & ~SR_BP3) | SR_BP3_BIT6; 1920 1921 if (val & ~mask) 1922 return -EINVAL; 1923 1924 /* Don't "lock" with no region! */ 1925 if (!(val & mask)) 1926 return -EINVAL; 1927 } 1928 1929 status_new = (status_old & ~mask & ~tb_mask) | val; 1930 1931 /* Disallow further writes if WP pin is asserted */ 1932 status_new |= SR_SRWD; 1933 1934 if (!use_top) 1935 status_new |= tb_mask; 1936 1937 /* Don't bother if they're the same */ 1938 if (status_new == status_old) 1939 return 0; 1940 1941 /* Only modify protection if it will not unlock other areas */ 1942 if ((status_new & mask) < (status_old & mask)) 1943 return -EINVAL; 1944 1945 return spi_nor_write_sr_and_check(nor, status_new); 1946 } 1947 1948 /* 1949 * Unlock a region of the flash. See spi_nor_sr_lock() for more info 1950 * 1951 * Returns negative on errors, 0 on success. 1952 */ 1953 static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1954 { 1955 struct mtd_info *mtd = &nor->mtd; 1956 u64 min_prot_len; 1957 int ret, status_old, status_new; 1958 u8 mask = spi_nor_get_sr_bp_mask(nor); 1959 u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1960 u8 pow, val; 1961 loff_t lock_len; 1962 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1963 bool use_top; 1964 1965 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1966 if (ret) 1967 return ret; 1968 1969 status_old = nor->bouncebuf[0]; 1970 1971 /* If nothing in our range is locked, we don't need to do anything */ 1972 if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) 1973 return 0; 1974 1975 /* If anything below us is locked, we can't use 'top' protection */ 1976 if (!spi_nor_is_unlocked_sr(nor, 0, ofs, status_old)) 1977 can_be_top = false; 1978 1979 /* If anything above us is locked, we can't use 'bottom' protection */ 1980 if (!spi_nor_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 1981 status_old)) 1982 can_be_bottom = false; 1983 1984 if (!can_be_bottom && !can_be_top) 1985 return -EINVAL; 1986 1987 /* Prefer top, if both are valid */ 1988 use_top = can_be_top; 1989 1990 /* lock_len: length of region that should remain locked */ 1991 if (use_top) 1992 lock_len = mtd->size - (ofs + len); 1993 else 1994 lock_len = ofs; 1995 1996 if (lock_len == 0) { 1997 val = 0; /* fully unlocked */ 1998 } else { 1999 min_prot_len = spi_nor_get_min_prot_length_sr(nor); 2000 pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; 2001 val = pow << SR_BP_SHIFT; 2002 2003 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) 2004 val = (val & ~SR_BP3) | SR_BP3_BIT6; 2005 2006 /* Some power-of-two sizes are not supported */ 2007 if (val & ~mask) 2008 return -EINVAL; 2009 } 2010 2011 status_new = (status_old & ~mask & ~tb_mask) | val; 2012 2013 /* Don't protect status register if we're fully unlocked */ 2014 if (lock_len == 0) 2015 status_new &= ~SR_SRWD; 2016 2017 if (!use_top) 2018 status_new |= tb_mask; 2019 2020 /* Don't bother if they're the same */ 2021 if (status_new == status_old) 2022 return 0; 2023 2024 /* Only modify protection if it will not lock other areas */ 2025 if ((status_new & mask) > (status_old & mask)) 2026 return -EINVAL; 2027 2028 return spi_nor_write_sr_and_check(nor, status_new); 2029 } 2030 2031 /* 2032 * Check if a region of the flash is (completely) locked. See spi_nor_sr_lock() 2033 * for more info. 2034 * 2035 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 2036 * negative on errors. 2037 */ 2038 static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 2039 { 2040 int ret; 2041 2042 ret = spi_nor_read_sr(nor, nor->bouncebuf); 2043 if (ret) 2044 return ret; 2045 2046 return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); 2047 } 2048 2049 static const struct spi_nor_locking_ops spi_nor_sr_locking_ops = { 2050 .lock = spi_nor_sr_lock, 2051 .unlock = spi_nor_sr_unlock, 2052 .is_locked = spi_nor_sr_is_locked, 2053 }; 2054 2055 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2056 { 2057 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2058 int ret; 2059 2060 ret = spi_nor_lock_and_prep(nor); 2061 if (ret) 2062 return ret; 2063 2064 ret = nor->params->locking_ops->lock(nor, ofs, len); 2065 2066 spi_nor_unlock_and_unprep(nor); 2067 return ret; 2068 } 2069 2070 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2071 { 2072 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2073 int ret; 2074 2075 ret = spi_nor_lock_and_prep(nor); 2076 if (ret) 2077 return ret; 2078 2079 ret = nor->params->locking_ops->unlock(nor, ofs, len); 2080 2081 spi_nor_unlock_and_unprep(nor); 2082 return ret; 2083 } 2084 2085 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2086 { 2087 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2088 int ret; 2089 2090 ret = spi_nor_lock_and_prep(nor); 2091 if (ret) 2092 return ret; 2093 2094 ret = nor->params->locking_ops->is_locked(nor, ofs, len); 2095 2096 spi_nor_unlock_and_unprep(nor); 2097 return ret; 2098 } 2099 2100 /** 2101 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status 2102 * Register 1. 2103 * @nor: pointer to a 'struct spi_nor' 2104 * 2105 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. 2106 * 2107 * Return: 0 on success, -errno otherwise. 2108 */ 2109 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) 2110 { 2111 int ret; 2112 2113 ret = spi_nor_read_sr(nor, nor->bouncebuf); 2114 if (ret) 2115 return ret; 2116 2117 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) 2118 return 0; 2119 2120 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; 2121 2122 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); 2123 } 2124 2125 /** 2126 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status 2127 * Register 2. 2128 * @nor: pointer to a 'struct spi_nor'. 2129 * 2130 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. 2131 * 2132 * Return: 0 on success, -errno otherwise. 2133 */ 2134 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) 2135 { 2136 int ret; 2137 2138 if (nor->flags & SNOR_F_NO_READ_CR) 2139 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); 2140 2141 ret = spi_nor_read_cr(nor, nor->bouncebuf); 2142 if (ret) 2143 return ret; 2144 2145 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) 2146 return 0; 2147 2148 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; 2149 2150 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); 2151 } 2152 2153 /** 2154 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. 2155 * @nor: pointer to a 'struct spi_nor' 2156 * 2157 * Set the Quad Enable (QE) bit in the Status Register 2. 2158 * 2159 * This is one of the procedures to set the QE bit described in the SFDP 2160 * (JESD216 rev B) specification but no manufacturer using this procedure has 2161 * been identified yet, hence the name of the function. 2162 * 2163 * Return: 0 on success, -errno otherwise. 2164 */ 2165 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 2166 { 2167 u8 *sr2 = nor->bouncebuf; 2168 int ret; 2169 u8 sr2_written; 2170 2171 /* Check current Quad Enable bit value. */ 2172 ret = spi_nor_read_sr2(nor, sr2); 2173 if (ret) 2174 return ret; 2175 if (*sr2 & SR2_QUAD_EN_BIT7) 2176 return 0; 2177 2178 /* Update the Quad Enable bit. */ 2179 *sr2 |= SR2_QUAD_EN_BIT7; 2180 2181 ret = spi_nor_write_sr2(nor, sr2); 2182 if (ret) 2183 return ret; 2184 2185 sr2_written = *sr2; 2186 2187 /* Read back and check it. */ 2188 ret = spi_nor_read_sr2(nor, sr2); 2189 if (ret) 2190 return ret; 2191 2192 if (*sr2 != sr2_written) { 2193 dev_dbg(nor->dev, "SR2: Read back test failed\n"); 2194 return -EIO; 2195 } 2196 2197 return 0; 2198 } 2199 2200 static const struct spi_nor_manufacturer *manufacturers[] = { 2201 &spi_nor_atmel, 2202 &spi_nor_catalyst, 2203 &spi_nor_eon, 2204 &spi_nor_esmt, 2205 &spi_nor_everspin, 2206 &spi_nor_fujitsu, 2207 &spi_nor_gigadevice, 2208 &spi_nor_intel, 2209 &spi_nor_issi, 2210 &spi_nor_macronix, 2211 &spi_nor_micron, 2212 &spi_nor_st, 2213 &spi_nor_spansion, 2214 &spi_nor_sst, 2215 &spi_nor_winbond, 2216 &spi_nor_xilinx, 2217 &spi_nor_xmc, 2218 }; 2219 2220 static const struct flash_info * 2221 spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int nparts, 2222 const u8 *id) 2223 { 2224 unsigned int i; 2225 2226 for (i = 0; i < nparts; i++) { 2227 if (parts[i].id_len && 2228 !memcmp(parts[i].id, id, parts[i].id_len)) 2229 return &parts[i]; 2230 } 2231 2232 return NULL; 2233 } 2234 2235 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 2236 { 2237 const struct flash_info *info; 2238 u8 *id = nor->bouncebuf; 2239 unsigned int i; 2240 int ret; 2241 2242 if (nor->spimem) { 2243 struct spi_mem_op op = 2244 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), 2245 SPI_MEM_OP_NO_ADDR, 2246 SPI_MEM_OP_NO_DUMMY, 2247 SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); 2248 2249 ret = spi_mem_exec_op(nor->spimem, &op); 2250 } else { 2251 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, 2252 SPI_NOR_MAX_ID_LEN); 2253 } 2254 if (ret) { 2255 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); 2256 return ERR_PTR(ret); 2257 } 2258 2259 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 2260 info = spi_nor_search_part_by_id(manufacturers[i]->parts, 2261 manufacturers[i]->nparts, 2262 id); 2263 if (info) { 2264 nor->manufacturer = manufacturers[i]; 2265 return info; 2266 } 2267 } 2268 2269 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", 2270 SPI_NOR_MAX_ID_LEN, id); 2271 return ERR_PTR(-ENODEV); 2272 } 2273 2274 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 2275 size_t *retlen, u_char *buf) 2276 { 2277 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2278 ssize_t ret; 2279 2280 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 2281 2282 ret = spi_nor_lock_and_prep(nor); 2283 if (ret) 2284 return ret; 2285 2286 while (len) { 2287 loff_t addr = from; 2288 2289 addr = spi_nor_convert_addr(nor, addr); 2290 2291 ret = spi_nor_read_data(nor, addr, len, buf); 2292 if (ret == 0) { 2293 /* We shouldn't see 0-length reads */ 2294 ret = -EIO; 2295 goto read_err; 2296 } 2297 if (ret < 0) 2298 goto read_err; 2299 2300 WARN_ON(ret > len); 2301 *retlen += ret; 2302 buf += ret; 2303 from += ret; 2304 len -= ret; 2305 } 2306 ret = 0; 2307 2308 read_err: 2309 spi_nor_unlock_and_unprep(nor); 2310 return ret; 2311 } 2312 2313 /* 2314 * Write an address range to the nor chip. Data must be written in 2315 * FLASH_PAGESIZE chunks. The address range may be any size provided 2316 * it is within the physical boundaries. 2317 */ 2318 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 2319 size_t *retlen, const u_char *buf) 2320 { 2321 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2322 size_t page_offset, page_remain, i; 2323 ssize_t ret; 2324 2325 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 2326 2327 ret = spi_nor_lock_and_prep(nor); 2328 if (ret) 2329 return ret; 2330 2331 for (i = 0; i < len; ) { 2332 ssize_t written; 2333 loff_t addr = to + i; 2334 2335 /* 2336 * If page_size is a power of two, the offset can be quickly 2337 * calculated with an AND operation. On the other cases we 2338 * need to do a modulus operation (more expensive). 2339 * Power of two numbers have only one bit set and we can use 2340 * the instruction hweight32 to detect if we need to do a 2341 * modulus (do_div()) or not. 2342 */ 2343 if (hweight32(nor->page_size) == 1) { 2344 page_offset = addr & (nor->page_size - 1); 2345 } else { 2346 uint64_t aux = addr; 2347 2348 page_offset = do_div(aux, nor->page_size); 2349 } 2350 /* the size of data remaining on the first page */ 2351 page_remain = min_t(size_t, 2352 nor->page_size - page_offset, len - i); 2353 2354 addr = spi_nor_convert_addr(nor, addr); 2355 2356 ret = spi_nor_write_enable(nor); 2357 if (ret) 2358 goto write_err; 2359 2360 ret = spi_nor_write_data(nor, addr, page_remain, buf + i); 2361 if (ret < 0) 2362 goto write_err; 2363 written = ret; 2364 2365 ret = spi_nor_wait_till_ready(nor); 2366 if (ret) 2367 goto write_err; 2368 *retlen += written; 2369 i += written; 2370 } 2371 2372 write_err: 2373 spi_nor_unlock_and_unprep(nor); 2374 return ret; 2375 } 2376 2377 static int spi_nor_check(struct spi_nor *nor) 2378 { 2379 if (!nor->dev || 2380 (!nor->spimem && !nor->controller_ops) || 2381 (!nor->spimem && nor->controller_ops && 2382 (!nor->controller_ops->read || 2383 !nor->controller_ops->write || 2384 !nor->controller_ops->read_reg || 2385 !nor->controller_ops->write_reg))) { 2386 pr_err("spi-nor: please fill all the necessary fields!\n"); 2387 return -EINVAL; 2388 } 2389 2390 if (nor->spimem && nor->controller_ops) { 2391 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n"); 2392 return -EINVAL; 2393 } 2394 2395 return 0; 2396 } 2397 2398 void 2399 spi_nor_set_read_settings(struct spi_nor_read_command *read, 2400 u8 num_mode_clocks, 2401 u8 num_wait_states, 2402 u8 opcode, 2403 enum spi_nor_protocol proto) 2404 { 2405 read->num_mode_clocks = num_mode_clocks; 2406 read->num_wait_states = num_wait_states; 2407 read->opcode = opcode; 2408 read->proto = proto; 2409 } 2410 2411 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 2412 enum spi_nor_protocol proto) 2413 { 2414 pp->opcode = opcode; 2415 pp->proto = proto; 2416 } 2417 2418 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2419 { 2420 size_t i; 2421 2422 for (i = 0; i < size; i++) 2423 if (table[i][0] == (int)hwcaps) 2424 return table[i][1]; 2425 2426 return -EINVAL; 2427 } 2428 2429 int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2430 { 2431 static const int hwcaps_read2cmd[][2] = { 2432 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2433 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2434 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2435 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2436 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2437 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2438 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2439 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2440 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2441 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2442 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2443 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2444 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2445 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2446 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2447 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR }, 2448 }; 2449 2450 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2451 ARRAY_SIZE(hwcaps_read2cmd)); 2452 } 2453 2454 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2455 { 2456 static const int hwcaps_pp2cmd[][2] = { 2457 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2458 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2459 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2460 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2461 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2462 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2463 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2464 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR }, 2465 }; 2466 2467 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2468 ARRAY_SIZE(hwcaps_pp2cmd)); 2469 } 2470 2471 /** 2472 * spi_nor_spimem_check_op - check if the operation is supported 2473 * by controller 2474 *@nor: pointer to a 'struct spi_nor' 2475 *@op: pointer to op template to be checked 2476 * 2477 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2478 */ 2479 static int spi_nor_spimem_check_op(struct spi_nor *nor, 2480 struct spi_mem_op *op) 2481 { 2482 /* 2483 * First test with 4 address bytes. The opcode itself might 2484 * be a 3B addressing opcode but we don't care, because 2485 * SPI controller implementation should not check the opcode, 2486 * but just the sequence. 2487 */ 2488 op->addr.nbytes = 4; 2489 if (!spi_mem_supports_op(nor->spimem, op)) { 2490 if (nor->mtd.size > SZ_16M) 2491 return -EOPNOTSUPP; 2492 2493 /* If flash size <= 16MB, 3 address bytes are sufficient */ 2494 op->addr.nbytes = 3; 2495 if (!spi_mem_supports_op(nor->spimem, op)) 2496 return -EOPNOTSUPP; 2497 } 2498 2499 return 0; 2500 } 2501 2502 /** 2503 * spi_nor_spimem_check_readop - check if the read op is supported 2504 * by controller 2505 *@nor: pointer to a 'struct spi_nor' 2506 *@read: pointer to op template to be checked 2507 * 2508 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2509 */ 2510 static int spi_nor_spimem_check_readop(struct spi_nor *nor, 2511 const struct spi_nor_read_command *read) 2512 { 2513 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), 2514 SPI_MEM_OP_ADDR(3, 0, 0), 2515 SPI_MEM_OP_DUMMY(1, 0), 2516 SPI_MEM_OP_DATA_IN(1, NULL, 0)); 2517 2518 spi_nor_spimem_setup_op(nor, &op, read->proto); 2519 2520 /* convert the dummy cycles to the number of bytes */ 2521 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 2522 if (spi_nor_protocol_is_dtr(nor->read_proto)) 2523 op.dummy.nbytes *= 2; 2524 2525 return spi_nor_spimem_check_op(nor, &op); 2526 } 2527 2528 /** 2529 * spi_nor_spimem_check_pp - check if the page program op is supported 2530 * by controller 2531 *@nor: pointer to a 'struct spi_nor' 2532 *@pp: pointer to op template to be checked 2533 * 2534 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2535 */ 2536 static int spi_nor_spimem_check_pp(struct spi_nor *nor, 2537 const struct spi_nor_pp_command *pp) 2538 { 2539 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0), 2540 SPI_MEM_OP_ADDR(3, 0, 0), 2541 SPI_MEM_OP_NO_DUMMY, 2542 SPI_MEM_OP_DATA_OUT(1, NULL, 0)); 2543 2544 spi_nor_spimem_setup_op(nor, &op, pp->proto); 2545 2546 return spi_nor_spimem_check_op(nor, &op); 2547 } 2548 2549 /** 2550 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol 2551 * based on SPI controller capabilities 2552 * @nor: pointer to a 'struct spi_nor' 2553 * @hwcaps: pointer to resulting capabilities after adjusting 2554 * according to controller and flash's capability 2555 */ 2556 static void 2557 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) 2558 { 2559 struct spi_nor_flash_parameter *params = nor->params; 2560 unsigned int cap; 2561 2562 /* X-X-X modes are not supported yet, mask them all. */ 2563 *hwcaps &= ~SNOR_HWCAPS_X_X_X; 2564 2565 /* 2566 * If the reset line is broken, we do not want to enter a stateful 2567 * mode. 2568 */ 2569 if (nor->flags & SNOR_F_BROKEN_RESET) 2570 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR); 2571 2572 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { 2573 int rdidx, ppidx; 2574 2575 if (!(*hwcaps & BIT(cap))) 2576 continue; 2577 2578 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); 2579 if (rdidx >= 0 && 2580 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx])) 2581 *hwcaps &= ~BIT(cap); 2582 2583 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); 2584 if (ppidx < 0) 2585 continue; 2586 2587 if (spi_nor_spimem_check_pp(nor, 2588 ¶ms->page_programs[ppidx])) 2589 *hwcaps &= ~BIT(cap); 2590 } 2591 } 2592 2593 /** 2594 * spi_nor_set_erase_type() - set a SPI NOR erase type 2595 * @erase: pointer to a structure that describes a SPI NOR erase type 2596 * @size: the size of the sector/block erased by the erase type 2597 * @opcode: the SPI command op code to erase the sector/block 2598 */ 2599 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 2600 u8 opcode) 2601 { 2602 erase->size = size; 2603 erase->opcode = opcode; 2604 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 2605 erase->size_shift = ffs(erase->size) - 1; 2606 erase->size_mask = (1 << erase->size_shift) - 1; 2607 } 2608 2609 /** 2610 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map 2611 * @map: the erase map of the SPI NOR 2612 * @erase_mask: bitmask encoding erase types that can erase the entire 2613 * flash memory 2614 * @flash_size: the spi nor flash memory size 2615 */ 2616 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 2617 u8 erase_mask, u64 flash_size) 2618 { 2619 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */ 2620 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) | 2621 SNOR_LAST_REGION; 2622 map->uniform_region.size = flash_size; 2623 map->regions = &map->uniform_region; 2624 map->uniform_erase_type = erase_mask; 2625 } 2626 2627 int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 2628 const struct sfdp_parameter_header *bfpt_header, 2629 const struct sfdp_bfpt *bfpt, 2630 struct spi_nor_flash_parameter *params) 2631 { 2632 int ret; 2633 2634 if (nor->manufacturer && nor->manufacturer->fixups && 2635 nor->manufacturer->fixups->post_bfpt) { 2636 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header, 2637 bfpt, params); 2638 if (ret) 2639 return ret; 2640 } 2641 2642 if (nor->info->fixups && nor->info->fixups->post_bfpt) 2643 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt, 2644 params); 2645 2646 return 0; 2647 } 2648 2649 static int spi_nor_select_read(struct spi_nor *nor, 2650 u32 shared_hwcaps) 2651 { 2652 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2653 const struct spi_nor_read_command *read; 2654 2655 if (best_match < 0) 2656 return -EINVAL; 2657 2658 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2659 if (cmd < 0) 2660 return -EINVAL; 2661 2662 read = &nor->params->reads[cmd]; 2663 nor->read_opcode = read->opcode; 2664 nor->read_proto = read->proto; 2665 2666 /* 2667 * In the SPI NOR framework, we don't need to make the difference 2668 * between mode clock cycles and wait state clock cycles. 2669 * Indeed, the value of the mode clock cycles is used by a QSPI 2670 * flash memory to know whether it should enter or leave its 0-4-4 2671 * (Continuous Read / XIP) mode. 2672 * eXecution In Place is out of the scope of the mtd sub-system. 2673 * Hence we choose to merge both mode and wait state clock cycles 2674 * into the so called dummy clock cycles. 2675 */ 2676 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2677 return 0; 2678 } 2679 2680 static int spi_nor_select_pp(struct spi_nor *nor, 2681 u32 shared_hwcaps) 2682 { 2683 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2684 const struct spi_nor_pp_command *pp; 2685 2686 if (best_match < 0) 2687 return -EINVAL; 2688 2689 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2690 if (cmd < 0) 2691 return -EINVAL; 2692 2693 pp = &nor->params->page_programs[cmd]; 2694 nor->program_opcode = pp->opcode; 2695 nor->write_proto = pp->proto; 2696 return 0; 2697 } 2698 2699 /** 2700 * spi_nor_select_uniform_erase() - select optimum uniform erase type 2701 * @map: the erase map of the SPI NOR 2702 * @wanted_size: the erase type size to search for. Contains the value of 2703 * info->sector_size or of the "small sector" size in case 2704 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined. 2705 * 2706 * Once the optimum uniform sector erase command is found, disable all the 2707 * other. 2708 * 2709 * Return: pointer to erase type on success, NULL otherwise. 2710 */ 2711 static const struct spi_nor_erase_type * 2712 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map, 2713 const u32 wanted_size) 2714 { 2715 const struct spi_nor_erase_type *tested_erase, *erase = NULL; 2716 int i; 2717 u8 uniform_erase_type = map->uniform_erase_type; 2718 2719 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2720 if (!(uniform_erase_type & BIT(i))) 2721 continue; 2722 2723 tested_erase = &map->erase_type[i]; 2724 2725 /* 2726 * If the current erase size is the one, stop here: 2727 * we have found the right uniform Sector Erase command. 2728 */ 2729 if (tested_erase->size == wanted_size) { 2730 erase = tested_erase; 2731 break; 2732 } 2733 2734 /* 2735 * Otherwise, the current erase size is still a valid candidate. 2736 * Select the biggest valid candidate. 2737 */ 2738 if (!erase && tested_erase->size) 2739 erase = tested_erase; 2740 /* keep iterating to find the wanted_size */ 2741 } 2742 2743 if (!erase) 2744 return NULL; 2745 2746 /* Disable all other Sector Erase commands. */ 2747 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK; 2748 map->uniform_erase_type |= BIT(erase - map->erase_type); 2749 return erase; 2750 } 2751 2752 static int spi_nor_select_erase(struct spi_nor *nor) 2753 { 2754 struct spi_nor_erase_map *map = &nor->params->erase_map; 2755 const struct spi_nor_erase_type *erase = NULL; 2756 struct mtd_info *mtd = &nor->mtd; 2757 u32 wanted_size = nor->info->sector_size; 2758 int i; 2759 2760 /* 2761 * The previous implementation handling Sector Erase commands assumed 2762 * that the SPI flash memory has an uniform layout then used only one 2763 * of the supported erase sizes for all Sector Erase commands. 2764 * So to be backward compatible, the new implementation also tries to 2765 * manage the SPI flash memory as uniform with a single erase sector 2766 * size, when possible. 2767 */ 2768 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 2769 /* prefer "small sector" erase if possible */ 2770 wanted_size = 4096u; 2771 #endif 2772 2773 if (spi_nor_has_uniform_erase(nor)) { 2774 erase = spi_nor_select_uniform_erase(map, wanted_size); 2775 if (!erase) 2776 return -EINVAL; 2777 nor->erase_opcode = erase->opcode; 2778 mtd->erasesize = erase->size; 2779 return 0; 2780 } 2781 2782 /* 2783 * For non-uniform SPI flash memory, set mtd->erasesize to the 2784 * maximum erase sector size. No need to set nor->erase_opcode. 2785 */ 2786 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2787 if (map->erase_type[i].size) { 2788 erase = &map->erase_type[i]; 2789 break; 2790 } 2791 } 2792 2793 if (!erase) 2794 return -EINVAL; 2795 2796 mtd->erasesize = erase->size; 2797 return 0; 2798 } 2799 2800 static int spi_nor_default_setup(struct spi_nor *nor, 2801 const struct spi_nor_hwcaps *hwcaps) 2802 { 2803 struct spi_nor_flash_parameter *params = nor->params; 2804 u32 ignored_mask, shared_mask; 2805 int err; 2806 2807 /* 2808 * Keep only the hardware capabilities supported by both the SPI 2809 * controller and the SPI flash memory. 2810 */ 2811 shared_mask = hwcaps->mask & params->hwcaps.mask; 2812 2813 if (nor->spimem) { 2814 /* 2815 * When called from spi_nor_probe(), all caps are set and we 2816 * need to discard some of them based on what the SPI 2817 * controller actually supports (using spi_mem_supports_op()). 2818 */ 2819 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask); 2820 } else { 2821 /* 2822 * SPI n-n-n protocols are not supported when the SPI 2823 * controller directly implements the spi_nor interface. 2824 * Yet another reason to switch to spi-mem. 2825 */ 2826 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR; 2827 if (shared_mask & ignored_mask) { 2828 dev_dbg(nor->dev, 2829 "SPI n-n-n protocols are not supported.\n"); 2830 shared_mask &= ~ignored_mask; 2831 } 2832 } 2833 2834 /* Select the (Fast) Read command. */ 2835 err = spi_nor_select_read(nor, shared_mask); 2836 if (err) { 2837 dev_dbg(nor->dev, 2838 "can't select read settings supported by both the SPI controller and memory.\n"); 2839 return err; 2840 } 2841 2842 /* Select the Page Program command. */ 2843 err = spi_nor_select_pp(nor, shared_mask); 2844 if (err) { 2845 dev_dbg(nor->dev, 2846 "can't select write settings supported by both the SPI controller and memory.\n"); 2847 return err; 2848 } 2849 2850 /* Select the Sector Erase command. */ 2851 err = spi_nor_select_erase(nor); 2852 if (err) { 2853 dev_dbg(nor->dev, 2854 "can't select erase settings supported by both the SPI controller and memory.\n"); 2855 return err; 2856 } 2857 2858 return 0; 2859 } 2860 2861 static int spi_nor_setup(struct spi_nor *nor, 2862 const struct spi_nor_hwcaps *hwcaps) 2863 { 2864 if (!nor->params->setup) 2865 return 0; 2866 2867 return nor->params->setup(nor, hwcaps); 2868 } 2869 2870 /** 2871 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and 2872 * settings based on MFR register and ->default_init() hook. 2873 * @nor: pointer to a 'struct spi_nor'. 2874 */ 2875 static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 2876 { 2877 if (nor->manufacturer && nor->manufacturer->fixups && 2878 nor->manufacturer->fixups->default_init) 2879 nor->manufacturer->fixups->default_init(nor); 2880 2881 if (nor->info->fixups && nor->info->fixups->default_init) 2882 nor->info->fixups->default_init(nor); 2883 } 2884 2885 /** 2886 * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings 2887 * based on JESD216 SFDP standard. 2888 * @nor: pointer to a 'struct spi_nor'. 2889 * 2890 * The method has a roll-back mechanism: in case the SFDP parsing fails, the 2891 * legacy flash parameters and settings will be restored. 2892 */ 2893 static void spi_nor_sfdp_init_params(struct spi_nor *nor) 2894 { 2895 struct spi_nor_flash_parameter sfdp_params; 2896 2897 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params)); 2898 2899 if (spi_nor_parse_sfdp(nor, nor->params)) { 2900 memcpy(nor->params, &sfdp_params, sizeof(*nor->params)); 2901 nor->addr_width = 0; 2902 nor->flags &= ~SNOR_F_4B_OPCODES; 2903 } 2904 } 2905 2906 /** 2907 * spi_nor_info_init_params() - Initialize the flash's parameters and settings 2908 * based on nor->info data. 2909 * @nor: pointer to a 'struct spi_nor'. 2910 */ 2911 static void spi_nor_info_init_params(struct spi_nor *nor) 2912 { 2913 struct spi_nor_flash_parameter *params = nor->params; 2914 struct spi_nor_erase_map *map = ¶ms->erase_map; 2915 const struct flash_info *info = nor->info; 2916 struct device_node *np = spi_nor_get_flash_node(nor); 2917 u8 i, erase_mask; 2918 2919 /* Initialize legacy flash parameters and settings. */ 2920 params->quad_enable = spi_nor_sr2_bit1_quad_enable; 2921 params->set_4byte_addr_mode = spansion_set_4byte_addr_mode; 2922 params->setup = spi_nor_default_setup; 2923 /* Default to 16-bit Write Status (01h) Command */ 2924 nor->flags |= SNOR_F_HAS_16BIT_SR; 2925 2926 /* Set SPI NOR sizes. */ 2927 params->writesize = 1; 2928 params->size = (u64)info->sector_size * info->n_sectors; 2929 params->page_size = info->page_size; 2930 2931 if (!(info->flags & SPI_NOR_NO_FR)) { 2932 /* Default to Fast Read for DT and non-DT platform devices. */ 2933 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2934 2935 /* Mask out Fast Read if not requested at DT instantiation. */ 2936 if (np && !of_property_read_bool(np, "m25p,fast-read")) 2937 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2938 } 2939 2940 /* (Fast) Read settings. */ 2941 params->hwcaps.mask |= SNOR_HWCAPS_READ; 2942 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 2943 0, 0, SPINOR_OP_READ, 2944 SNOR_PROTO_1_1_1); 2945 2946 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) 2947 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 2948 0, 8, SPINOR_OP_READ_FAST, 2949 SNOR_PROTO_1_1_1); 2950 2951 if (info->flags & SPI_NOR_DUAL_READ) { 2952 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2953 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2954 0, 8, SPINOR_OP_READ_1_1_2, 2955 SNOR_PROTO_1_1_2); 2956 } 2957 2958 if (info->flags & SPI_NOR_QUAD_READ) { 2959 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2960 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2961 0, 8, SPINOR_OP_READ_1_1_4, 2962 SNOR_PROTO_1_1_4); 2963 } 2964 2965 if (info->flags & SPI_NOR_OCTAL_READ) { 2966 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; 2967 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], 2968 0, 8, SPINOR_OP_READ_1_1_8, 2969 SNOR_PROTO_1_1_8); 2970 } 2971 2972 if (info->flags & SPI_NOR_OCTAL_DTR_READ) { 2973 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; 2974 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], 2975 0, 20, SPINOR_OP_READ_FAST, 2976 SNOR_PROTO_8_8_8_DTR); 2977 } 2978 2979 /* Page Program settings. */ 2980 params->hwcaps.mask |= SNOR_HWCAPS_PP; 2981 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 2982 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 2983 2984 if (info->flags & SPI_NOR_OCTAL_DTR_PP) { 2985 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; 2986 /* 2987 * Since xSPI Page Program opcode is backward compatible with 2988 * Legacy SPI, use Legacy SPI opcode there as well. 2989 */ 2990 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], 2991 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); 2992 } 2993 2994 /* 2995 * Sector Erase settings. Sort Erase Types in ascending order, with the 2996 * smallest erase size starting at BIT(0). 2997 */ 2998 erase_mask = 0; 2999 i = 0; 3000 if (info->flags & SECT_4K_PMC) { 3001 erase_mask |= BIT(i); 3002 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 3003 SPINOR_OP_BE_4K_PMC); 3004 i++; 3005 } else if (info->flags & SECT_4K) { 3006 erase_mask |= BIT(i); 3007 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 3008 SPINOR_OP_BE_4K); 3009 i++; 3010 } 3011 erase_mask |= BIT(i); 3012 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size, 3013 SPINOR_OP_SE); 3014 spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 3015 } 3016 3017 /** 3018 * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings 3019 * after SFDP has been parsed (is also called for SPI NORs that do not 3020 * support RDSFDP). 3021 * @nor: pointer to a 'struct spi_nor' 3022 * 3023 * Typically used to tweak various parameters that could not be extracted by 3024 * other means (i.e. when information provided by the SFDP/flash_info tables 3025 * are incomplete or wrong). 3026 */ 3027 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor) 3028 { 3029 if (nor->manufacturer && nor->manufacturer->fixups && 3030 nor->manufacturer->fixups->post_sfdp) 3031 nor->manufacturer->fixups->post_sfdp(nor); 3032 3033 if (nor->info->fixups && nor->info->fixups->post_sfdp) 3034 nor->info->fixups->post_sfdp(nor); 3035 } 3036 3037 /** 3038 * spi_nor_late_init_params() - Late initialization of default flash parameters. 3039 * @nor: pointer to a 'struct spi_nor' 3040 * 3041 * Used to set default flash parameters and settings when the ->default_init() 3042 * hook or the SFDP parser let voids. 3043 */ 3044 static void spi_nor_late_init_params(struct spi_nor *nor) 3045 { 3046 /* 3047 * NOR protection support. When locking_ops are not provided, we pick 3048 * the default ones. 3049 */ 3050 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) 3051 nor->params->locking_ops = &spi_nor_sr_locking_ops; 3052 } 3053 3054 /** 3055 * spi_nor_init_params() - Initialize the flash's parameters and settings. 3056 * @nor: pointer to a 'struct spi_nor'. 3057 * 3058 * The flash parameters and settings are initialized based on a sequence of 3059 * calls that are ordered by priority: 3060 * 3061 * 1/ Default flash parameters initialization. The initializations are done 3062 * based on nor->info data: 3063 * spi_nor_info_init_params() 3064 * 3065 * which can be overwritten by: 3066 * 2/ Manufacturer flash parameters initialization. The initializations are 3067 * done based on MFR register, or when the decisions can not be done solely 3068 * based on MFR, by using specific flash_info tweeks, ->default_init(): 3069 * spi_nor_manufacturer_init_params() 3070 * 3071 * which can be overwritten by: 3072 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and 3073 * should be more accurate that the above. 3074 * spi_nor_sfdp_init_params() 3075 * 3076 * Please note that there is a ->post_bfpt() fixup hook that can overwrite 3077 * the flash parameters and settings immediately after parsing the Basic 3078 * Flash Parameter Table. 3079 * 3080 * which can be overwritten by: 3081 * 4/ Post SFDP flash parameters initialization. Used to tweak various 3082 * parameters that could not be extracted by other means (i.e. when 3083 * information provided by the SFDP/flash_info tables are incomplete or 3084 * wrong). 3085 * spi_nor_post_sfdp_fixups() 3086 * 3087 * 5/ Late default flash parameters initialization, used when the 3088 * ->default_init() hook or the SFDP parser do not set specific params. 3089 * spi_nor_late_init_params() 3090 */ 3091 static int spi_nor_init_params(struct spi_nor *nor) 3092 { 3093 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); 3094 if (!nor->params) 3095 return -ENOMEM; 3096 3097 spi_nor_info_init_params(nor); 3098 3099 spi_nor_manufacturer_init_params(nor); 3100 3101 if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 3102 SPI_NOR_OCTAL_READ | SPI_NOR_OCTAL_DTR_READ)) && 3103 !(nor->info->flags & SPI_NOR_SKIP_SFDP)) 3104 spi_nor_sfdp_init_params(nor); 3105 3106 spi_nor_post_sfdp_fixups(nor); 3107 3108 spi_nor_late_init_params(nor); 3109 3110 return 0; 3111 } 3112 3113 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed 3114 * @nor: pointer to a 'struct spi_nor' 3115 * @enable: whether to enable or disable Octal DTR 3116 * 3117 * Return: 0 on success, -errno otherwise. 3118 */ 3119 static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 3120 { 3121 int ret; 3122 3123 if (!nor->params->octal_dtr_enable) 3124 return 0; 3125 3126 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && 3127 nor->write_proto == SNOR_PROTO_8_8_8_DTR)) 3128 return 0; 3129 3130 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) 3131 return 0; 3132 3133 ret = nor->params->octal_dtr_enable(nor, enable); 3134 if (ret) 3135 return ret; 3136 3137 if (enable) 3138 nor->reg_proto = SNOR_PROTO_8_8_8_DTR; 3139 else 3140 nor->reg_proto = SNOR_PROTO_1_1_1; 3141 3142 return 0; 3143 } 3144 3145 /** 3146 * spi_nor_quad_enable() - enable Quad I/O if needed. 3147 * @nor: pointer to a 'struct spi_nor' 3148 * 3149 * Return: 0 on success, -errno otherwise. 3150 */ 3151 static int spi_nor_quad_enable(struct spi_nor *nor) 3152 { 3153 if (!nor->params->quad_enable) 3154 return 0; 3155 3156 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || 3157 spi_nor_get_protocol_width(nor->write_proto) == 4)) 3158 return 0; 3159 3160 return nor->params->quad_enable(nor); 3161 } 3162 3163 /** 3164 * spi_nor_try_unlock_all() - Tries to unlock the entire flash memory array. 3165 * @nor: pointer to a 'struct spi_nor'. 3166 * 3167 * Some SPI NOR flashes are write protected by default after a power-on reset 3168 * cycle, in order to avoid inadvertent writes during power-up. Backward 3169 * compatibility imposes to unlock the entire flash memory array at power-up 3170 * by default. 3171 * 3172 * Unprotecting the entire flash array will fail for boards which are hardware 3173 * write-protected. Thus any errors are ignored. 3174 */ 3175 static void spi_nor_try_unlock_all(struct spi_nor *nor) 3176 { 3177 int ret; 3178 3179 if (!(nor->flags & SNOR_F_HAS_LOCK)) 3180 return; 3181 3182 dev_dbg(nor->dev, "Unprotecting entire flash array\n"); 3183 3184 ret = spi_nor_unlock(&nor->mtd, 0, nor->params->size); 3185 if (ret) 3186 dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n"); 3187 } 3188 3189 static int spi_nor_init(struct spi_nor *nor) 3190 { 3191 int err; 3192 3193 err = spi_nor_octal_dtr_enable(nor, true); 3194 if (err) { 3195 dev_dbg(nor->dev, "octal mode not supported\n"); 3196 return err; 3197 } 3198 3199 err = spi_nor_quad_enable(nor); 3200 if (err) { 3201 dev_dbg(nor->dev, "quad mode not supported\n"); 3202 return err; 3203 } 3204 3205 /* 3206 * Some SPI NOR flashes are write protected by default after a power-on 3207 * reset cycle, in order to avoid inadvertent writes during power-up. 3208 * Backward compatibility imposes to unlock the entire flash memory 3209 * array at power-up by default. Depending on the kernel configuration 3210 * (1) do nothing, (2) always unlock the entire flash array or (3) 3211 * unlock the entire flash array only when the software write 3212 * protection bits are volatile. The latter is indicated by 3213 * SNOR_F_SWP_IS_VOLATILE. 3214 */ 3215 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) || 3216 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) && 3217 nor->flags & SNOR_F_SWP_IS_VOLATILE)) 3218 spi_nor_try_unlock_all(nor); 3219 3220 if (nor->addr_width == 4 && 3221 nor->read_proto != SNOR_PROTO_8_8_8_DTR && 3222 !(nor->flags & SNOR_F_4B_OPCODES)) { 3223 /* 3224 * If the RESET# pin isn't hooked up properly, or the system 3225 * otherwise doesn't perform a reset command in the boot 3226 * sequence, it's impossible to 100% protect against unexpected 3227 * reboots (e.g., crashes). Warn the user (or hopefully, system 3228 * designer) that this is bad. 3229 */ 3230 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, 3231 "enabling reset hack; may not recover from unexpected reboots\n"); 3232 nor->params->set_4byte_addr_mode(nor, true); 3233 } 3234 3235 return 0; 3236 } 3237 3238 static void spi_nor_soft_reset(struct spi_nor *nor) 3239 { 3240 struct spi_mem_op op; 3241 int ret; 3242 3243 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), 3244 SPI_MEM_OP_NO_DUMMY, 3245 SPI_MEM_OP_NO_ADDR, 3246 SPI_MEM_OP_NO_DATA); 3247 3248 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3249 3250 ret = spi_mem_exec_op(nor->spimem, &op); 3251 if (ret) { 3252 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3253 return; 3254 } 3255 3256 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), 3257 SPI_MEM_OP_NO_DUMMY, 3258 SPI_MEM_OP_NO_ADDR, 3259 SPI_MEM_OP_NO_DATA); 3260 3261 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3262 3263 ret = spi_mem_exec_op(nor->spimem, &op); 3264 if (ret) { 3265 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3266 return; 3267 } 3268 3269 /* 3270 * Software Reset is not instant, and the delay varies from flash to 3271 * flash. Looking at a few flashes, most range somewhere below 100 3272 * microseconds. So, sleep for a range of 200-400 us. 3273 */ 3274 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX); 3275 } 3276 3277 /* mtd suspend handler */ 3278 static int spi_nor_suspend(struct mtd_info *mtd) 3279 { 3280 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3281 int ret; 3282 3283 /* Disable octal DTR mode if we enabled it. */ 3284 ret = spi_nor_octal_dtr_enable(nor, false); 3285 if (ret) 3286 dev_err(nor->dev, "suspend() failed\n"); 3287 3288 return ret; 3289 } 3290 3291 /* mtd resume handler */ 3292 static void spi_nor_resume(struct mtd_info *mtd) 3293 { 3294 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3295 struct device *dev = nor->dev; 3296 int ret; 3297 3298 /* re-initialize the nor chip */ 3299 ret = spi_nor_init(nor); 3300 if (ret) 3301 dev_err(dev, "resume() failed\n"); 3302 } 3303 3304 void spi_nor_restore(struct spi_nor *nor) 3305 { 3306 /* restore the addressing mode */ 3307 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && 3308 nor->flags & SNOR_F_BROKEN_RESET) 3309 nor->params->set_4byte_addr_mode(nor, false); 3310 3311 if (nor->flags & SNOR_F_SOFT_RESET) 3312 spi_nor_soft_reset(nor); 3313 } 3314 EXPORT_SYMBOL_GPL(spi_nor_restore); 3315 3316 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, 3317 const char *name) 3318 { 3319 unsigned int i, j; 3320 3321 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 3322 for (j = 0; j < manufacturers[i]->nparts; j++) { 3323 if (!strcmp(name, manufacturers[i]->parts[j].name)) { 3324 nor->manufacturer = manufacturers[i]; 3325 return &manufacturers[i]->parts[j]; 3326 } 3327 } 3328 } 3329 3330 return NULL; 3331 } 3332 3333 static int spi_nor_set_addr_width(struct spi_nor *nor) 3334 { 3335 if (nor->addr_width) { 3336 /* already configured from SFDP */ 3337 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { 3338 /* 3339 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So 3340 * in this protocol an odd address width cannot be used because 3341 * then the address phase would only span a cycle and a half. 3342 * Half a cycle would be left over. We would then have to start 3343 * the dummy phase in the middle of a cycle and so too the data 3344 * phase, and we will end the transaction with half a cycle left 3345 * over. 3346 * 3347 * Force all 8D-8D-8D flashes to use an address width of 4 to 3348 * avoid this situation. 3349 */ 3350 nor->addr_width = 4; 3351 } else if (nor->info->addr_width) { 3352 nor->addr_width = nor->info->addr_width; 3353 } else { 3354 nor->addr_width = 3; 3355 } 3356 3357 if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) { 3358 /* enable 4-byte addressing if the device exceeds 16MiB */ 3359 nor->addr_width = 4; 3360 } 3361 3362 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 3363 dev_dbg(nor->dev, "address width is too large: %u\n", 3364 nor->addr_width); 3365 return -EINVAL; 3366 } 3367 3368 /* Set 4byte opcodes when possible. */ 3369 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES && 3370 !(nor->flags & SNOR_F_HAS_4BAIT)) 3371 spi_nor_set_4byte_opcodes(nor); 3372 3373 return 0; 3374 } 3375 3376 static void spi_nor_debugfs_init(struct spi_nor *nor, 3377 const struct flash_info *info) 3378 { 3379 struct mtd_info *mtd = &nor->mtd; 3380 3381 mtd->dbg.partname = info->name; 3382 mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN", 3383 info->id_len, info->id); 3384 } 3385 3386 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, 3387 const char *name) 3388 { 3389 const struct flash_info *info = NULL; 3390 3391 if (name) 3392 info = spi_nor_match_id(nor, name); 3393 /* Try to auto-detect if chip name wasn't specified or not found */ 3394 if (!info) 3395 info = spi_nor_read_id(nor); 3396 if (IS_ERR_OR_NULL(info)) 3397 return ERR_PTR(-ENOENT); 3398 3399 /* 3400 * If caller has specified name of flash model that can normally be 3401 * detected using JEDEC, let's verify it. 3402 */ 3403 if (name && info->id_len) { 3404 const struct flash_info *jinfo; 3405 3406 jinfo = spi_nor_read_id(nor); 3407 if (IS_ERR(jinfo)) { 3408 return jinfo; 3409 } else if (jinfo != info) { 3410 /* 3411 * JEDEC knows better, so overwrite platform ID. We 3412 * can't trust partitions any longer, but we'll let 3413 * mtd apply them anyway, since some partitions may be 3414 * marked read-only, and we don't want to lose that 3415 * information, even if it's not 100% accurate. 3416 */ 3417 dev_warn(nor->dev, "found %s, expected %s\n", 3418 jinfo->name, info->name); 3419 info = jinfo; 3420 } 3421 } 3422 3423 return info; 3424 } 3425 3426 int spi_nor_scan(struct spi_nor *nor, const char *name, 3427 const struct spi_nor_hwcaps *hwcaps) 3428 { 3429 const struct flash_info *info; 3430 struct device *dev = nor->dev; 3431 struct mtd_info *mtd = &nor->mtd; 3432 struct device_node *np = spi_nor_get_flash_node(nor); 3433 int ret; 3434 int i; 3435 3436 ret = spi_nor_check(nor); 3437 if (ret) 3438 return ret; 3439 3440 /* Reset SPI protocol for all commands. */ 3441 nor->reg_proto = SNOR_PROTO_1_1_1; 3442 nor->read_proto = SNOR_PROTO_1_1_1; 3443 nor->write_proto = SNOR_PROTO_1_1_1; 3444 3445 /* 3446 * We need the bounce buffer early to read/write registers when going 3447 * through the spi-mem layer (buffers have to be DMA-able). 3448 * For spi-mem drivers, we'll reallocate a new buffer if 3449 * nor->page_size turns out to be greater than PAGE_SIZE (which 3450 * shouldn't happen before long since NOR pages are usually less 3451 * than 1KB) after spi_nor_scan() returns. 3452 */ 3453 nor->bouncebuf_size = PAGE_SIZE; 3454 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 3455 GFP_KERNEL); 3456 if (!nor->bouncebuf) 3457 return -ENOMEM; 3458 3459 info = spi_nor_get_flash_info(nor, name); 3460 if (IS_ERR(info)) 3461 return PTR_ERR(info); 3462 3463 nor->info = info; 3464 3465 spi_nor_debugfs_init(nor, info); 3466 3467 mutex_init(&nor->lock); 3468 3469 /* 3470 * Make sure the XSR_RDY flag is set before calling 3471 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR 3472 * with Atmel SPI NOR. 3473 */ 3474 if (info->flags & SPI_NOR_XSR_RDY) 3475 nor->flags |= SNOR_F_READY_XSR_RDY; 3476 3477 if (info->flags & SPI_NOR_HAS_LOCK) 3478 nor->flags |= SNOR_F_HAS_LOCK; 3479 3480 mtd->_write = spi_nor_write; 3481 3482 /* Init flash parameters based on flash_info struct and SFDP */ 3483 ret = spi_nor_init_params(nor); 3484 if (ret) 3485 return ret; 3486 3487 if (!mtd->name) 3488 mtd->name = dev_name(dev); 3489 mtd->priv = nor; 3490 mtd->type = MTD_NORFLASH; 3491 mtd->writesize = nor->params->writesize; 3492 mtd->flags = MTD_CAP_NORFLASH; 3493 mtd->size = nor->params->size; 3494 mtd->_erase = spi_nor_erase; 3495 mtd->_read = spi_nor_read; 3496 mtd->_suspend = spi_nor_suspend; 3497 mtd->_resume = spi_nor_resume; 3498 3499 if (nor->params->locking_ops) { 3500 mtd->_lock = spi_nor_lock; 3501 mtd->_unlock = spi_nor_unlock; 3502 mtd->_is_locked = spi_nor_is_locked; 3503 } 3504 3505 if (info->flags & USE_FSR) 3506 nor->flags |= SNOR_F_USE_FSR; 3507 if (info->flags & SPI_NOR_HAS_TB) { 3508 nor->flags |= SNOR_F_HAS_SR_TB; 3509 if (info->flags & SPI_NOR_TB_SR_BIT6) 3510 nor->flags |= SNOR_F_HAS_SR_TB_BIT6; 3511 } 3512 3513 if (info->flags & NO_CHIP_ERASE) 3514 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 3515 if (info->flags & USE_CLSR) 3516 nor->flags |= SNOR_F_USE_CLSR; 3517 if (info->flags & SPI_NOR_SWP_IS_VOLATILE) 3518 nor->flags |= SNOR_F_SWP_IS_VOLATILE; 3519 3520 if (info->flags & SPI_NOR_4BIT_BP) { 3521 nor->flags |= SNOR_F_HAS_4BIT_BP; 3522 if (info->flags & SPI_NOR_BP3_SR_BIT6) 3523 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; 3524 } 3525 3526 if (info->flags & SPI_NOR_NO_ERASE) 3527 mtd->flags |= MTD_NO_ERASE; 3528 3529 mtd->dev.parent = dev; 3530 nor->page_size = nor->params->page_size; 3531 mtd->writebufsize = nor->page_size; 3532 3533 if (of_property_read_bool(np, "broken-flash-reset")) 3534 nor->flags |= SNOR_F_BROKEN_RESET; 3535 3536 /* 3537 * Configure the SPI memory: 3538 * - select op codes for (Fast) Read, Page Program and Sector Erase. 3539 * - set the number of dummy cycles (mode cycles + wait states). 3540 * - set the SPI protocols for register and memory accesses. 3541 */ 3542 ret = spi_nor_setup(nor, hwcaps); 3543 if (ret) 3544 return ret; 3545 3546 if (info->flags & SPI_NOR_4B_OPCODES) 3547 nor->flags |= SNOR_F_4B_OPCODES; 3548 3549 if (info->flags & SPI_NOR_IO_MODE_EN_VOLATILE) 3550 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; 3551 3552 ret = spi_nor_set_addr_width(nor); 3553 if (ret) 3554 return ret; 3555 3556 /* Send all the required SPI flash commands to initialize device */ 3557 ret = spi_nor_init(nor); 3558 if (ret) 3559 return ret; 3560 3561 dev_info(dev, "%s (%lld Kbytes)\n", info->name, 3562 (long long)mtd->size >> 10); 3563 3564 dev_dbg(dev, 3565 "mtd .name = %s, .size = 0x%llx (%lldMiB), " 3566 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 3567 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), 3568 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); 3569 3570 if (mtd->numeraseregions) 3571 for (i = 0; i < mtd->numeraseregions; i++) 3572 dev_dbg(dev, 3573 "mtd.eraseregions[%d] = { .offset = 0x%llx, " 3574 ".erasesize = 0x%.8x (%uKiB), " 3575 ".numblocks = %d }\n", 3576 i, (long long)mtd->eraseregions[i].offset, 3577 mtd->eraseregions[i].erasesize, 3578 mtd->eraseregions[i].erasesize / 1024, 3579 mtd->eraseregions[i].numblocks); 3580 return 0; 3581 } 3582 EXPORT_SYMBOL_GPL(spi_nor_scan); 3583 3584 static int spi_nor_create_read_dirmap(struct spi_nor *nor) 3585 { 3586 struct spi_mem_dirmap_info info = { 3587 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 3588 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0), 3589 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 3590 SPI_MEM_OP_DATA_IN(0, NULL, 0)), 3591 .offset = 0, 3592 .length = nor->mtd.size, 3593 }; 3594 struct spi_mem_op *op = &info.op_tmpl; 3595 3596 spi_nor_spimem_setup_op(nor, op, nor->read_proto); 3597 3598 /* convert the dummy cycles to the number of bytes */ 3599 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8; 3600 if (spi_nor_protocol_is_dtr(nor->read_proto)) 3601 op->dummy.nbytes *= 2; 3602 3603 /* 3604 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3605 * of data bytes is non-zero, the data buswidth won't be set here. So, 3606 * do it explicitly. 3607 */ 3608 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 3609 3610 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3611 &info); 3612 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc); 3613 } 3614 3615 static int spi_nor_create_write_dirmap(struct spi_nor *nor) 3616 { 3617 struct spi_mem_dirmap_info info = { 3618 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 3619 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0), 3620 SPI_MEM_OP_NO_DUMMY, 3621 SPI_MEM_OP_DATA_OUT(0, NULL, 0)), 3622 .offset = 0, 3623 .length = nor->mtd.size, 3624 }; 3625 struct spi_mem_op *op = &info.op_tmpl; 3626 3627 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 3628 op->addr.nbytes = 0; 3629 3630 spi_nor_spimem_setup_op(nor, op, nor->write_proto); 3631 3632 /* 3633 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3634 * of data bytes is non-zero, the data buswidth won't be set here. So, 3635 * do it explicitly. 3636 */ 3637 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 3638 3639 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3640 &info); 3641 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc); 3642 } 3643 3644 static int spi_nor_probe(struct spi_mem *spimem) 3645 { 3646 struct spi_device *spi = spimem->spi; 3647 struct flash_platform_data *data = dev_get_platdata(&spi->dev); 3648 struct spi_nor *nor; 3649 /* 3650 * Enable all caps by default. The core will mask them after 3651 * checking what's really supported using spi_mem_supports_op(). 3652 */ 3653 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; 3654 char *flash_name; 3655 int ret; 3656 3657 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL); 3658 if (!nor) 3659 return -ENOMEM; 3660 3661 nor->spimem = spimem; 3662 nor->dev = &spi->dev; 3663 spi_nor_set_flash_node(nor, spi->dev.of_node); 3664 3665 spi_mem_set_drvdata(spimem, nor); 3666 3667 if (data && data->name) 3668 nor->mtd.name = data->name; 3669 3670 if (!nor->mtd.name) 3671 nor->mtd.name = spi_mem_get_name(spimem); 3672 3673 /* 3674 * For some (historical?) reason many platforms provide two different 3675 * names in flash_platform_data: "name" and "type". Quite often name is 3676 * set to "m25p80" and then "type" provides a real chip name. 3677 * If that's the case, respect "type" and ignore a "name". 3678 */ 3679 if (data && data->type) 3680 flash_name = data->type; 3681 else if (!strcmp(spi->modalias, "spi-nor")) 3682 flash_name = NULL; /* auto-detect */ 3683 else 3684 flash_name = spi->modalias; 3685 3686 ret = spi_nor_scan(nor, flash_name, &hwcaps); 3687 if (ret) 3688 return ret; 3689 3690 /* 3691 * None of the existing parts have > 512B pages, but let's play safe 3692 * and add this logic so that if anyone ever adds support for such 3693 * a NOR we don't end up with buffer overflows. 3694 */ 3695 if (nor->page_size > PAGE_SIZE) { 3696 nor->bouncebuf_size = nor->page_size; 3697 devm_kfree(nor->dev, nor->bouncebuf); 3698 nor->bouncebuf = devm_kmalloc(nor->dev, 3699 nor->bouncebuf_size, 3700 GFP_KERNEL); 3701 if (!nor->bouncebuf) 3702 return -ENOMEM; 3703 } 3704 3705 ret = spi_nor_create_read_dirmap(nor); 3706 if (ret) 3707 return ret; 3708 3709 ret = spi_nor_create_write_dirmap(nor); 3710 if (ret) 3711 return ret; 3712 3713 return mtd_device_register(&nor->mtd, data ? data->parts : NULL, 3714 data ? data->nr_parts : 0); 3715 } 3716 3717 static int spi_nor_remove(struct spi_mem *spimem) 3718 { 3719 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3720 3721 spi_nor_restore(nor); 3722 3723 /* Clean up MTD stuff. */ 3724 return mtd_device_unregister(&nor->mtd); 3725 } 3726 3727 static void spi_nor_shutdown(struct spi_mem *spimem) 3728 { 3729 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3730 3731 spi_nor_restore(nor); 3732 } 3733 3734 /* 3735 * Do NOT add to this array without reading the following: 3736 * 3737 * Historically, many flash devices are bound to this driver by their name. But 3738 * since most of these flash are compatible to some extent, and their 3739 * differences can often be differentiated by the JEDEC read-ID command, we 3740 * encourage new users to add support to the spi-nor library, and simply bind 3741 * against a generic string here (e.g., "jedec,spi-nor"). 3742 * 3743 * Many flash names are kept here in this list (as well as in spi-nor.c) to 3744 * keep them available as module aliases for existing platforms. 3745 */ 3746 static const struct spi_device_id spi_nor_dev_ids[] = { 3747 /* 3748 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and 3749 * hack around the fact that the SPI core does not provide uevent 3750 * matching for .of_match_table 3751 */ 3752 {"spi-nor"}, 3753 3754 /* 3755 * Entries not used in DTs that should be safe to drop after replacing 3756 * them with "spi-nor" in platform data. 3757 */ 3758 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, 3759 3760 /* 3761 * Entries that were used in DTs without "jedec,spi-nor" fallback and 3762 * should be kept for backward compatibility. 3763 */ 3764 {"at25df321a"}, {"at25df641"}, {"at26df081a"}, 3765 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, 3766 {"mx25l25635e"},{"mx66l51235l"}, 3767 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, 3768 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, 3769 {"s25fl064k"}, 3770 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, 3771 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, 3772 {"m25p64"}, {"m25p128"}, 3773 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, 3774 {"w25q80bl"}, {"w25q128"}, {"w25q256"}, 3775 3776 /* Flashes that can't be detected using JEDEC */ 3777 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, 3778 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, 3779 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, 3780 3781 /* Everspin MRAMs (non-JEDEC) */ 3782 { "mr25h128" }, /* 128 Kib, 40 MHz */ 3783 { "mr25h256" }, /* 256 Kib, 40 MHz */ 3784 { "mr25h10" }, /* 1 Mib, 40 MHz */ 3785 { "mr25h40" }, /* 4 Mib, 40 MHz */ 3786 3787 { }, 3788 }; 3789 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids); 3790 3791 static const struct of_device_id spi_nor_of_table[] = { 3792 /* 3793 * Generic compatibility for SPI NOR that can be identified by the 3794 * JEDEC READ ID opcode (0x9F). Use this, if possible. 3795 */ 3796 { .compatible = "jedec,spi-nor" }, 3797 { /* sentinel */ }, 3798 }; 3799 MODULE_DEVICE_TABLE(of, spi_nor_of_table); 3800 3801 /* 3802 * REVISIT: many of these chips have deep power-down modes, which 3803 * should clearly be entered on suspend() to minimize power use. 3804 * And also when they're otherwise idle... 3805 */ 3806 static struct spi_mem_driver spi_nor_driver = { 3807 .spidrv = { 3808 .driver = { 3809 .name = "spi-nor", 3810 .of_match_table = spi_nor_of_table, 3811 }, 3812 .id_table = spi_nor_dev_ids, 3813 }, 3814 .probe = spi_nor_probe, 3815 .remove = spi_nor_remove, 3816 .shutdown = spi_nor_shutdown, 3817 }; 3818 module_spi_mem_driver(spi_nor_driver); 3819 3820 MODULE_LICENSE("GPL v2"); 3821 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); 3822 MODULE_AUTHOR("Mike Lavender"); 3823 MODULE_DESCRIPTION("framework for SPI NOR"); 3824