1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/err.h> 11 #include <linux/errno.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/mutex.h> 15 #include <linux/math64.h> 16 #include <linux/sizes.h> 17 #include <linux/slab.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/of_platform.h> 21 #include <linux/sched/task_stack.h> 22 #include <linux/spi/flash.h> 23 #include <linux/mtd/spi-nor.h> 24 25 #include "core.h" 26 27 /* Define max times to check status register before we give up. */ 28 29 /* 30 * For everything but full-chip erase; probably could be much smaller, but kept 31 * around for safety for now 32 */ 33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 34 35 /* 36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up 37 * for larger flash 38 */ 39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) 40 41 #define SPI_NOR_MAX_ADDR_WIDTH 4 42 43 #define SPI_NOR_SRST_SLEEP_MIN 200 44 #define SPI_NOR_SRST_SLEEP_MAX 400 45 46 /** 47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the 48 * extension type. 49 * @nor: pointer to a 'struct spi_nor' 50 * @op: pointer to the 'struct spi_mem_op' whose properties 51 * need to be initialized. 52 * 53 * Right now, only "repeat" and "invert" are supported. 54 * 55 * Return: The opcode extension. 56 */ 57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, 58 const struct spi_mem_op *op) 59 { 60 switch (nor->cmd_ext_type) { 61 case SPI_NOR_EXT_INVERT: 62 return ~op->cmd.opcode; 63 64 case SPI_NOR_EXT_REPEAT: 65 return op->cmd.opcode; 66 67 default: 68 dev_err(nor->dev, "Unknown command extension type\n"); 69 return 0; 70 } 71 } 72 73 /** 74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. 75 * @nor: pointer to a 'struct spi_nor' 76 * @op: pointer to the 'struct spi_mem_op' whose properties 77 * need to be initialized. 78 * @proto: the protocol from which the properties need to be set. 79 */ 80 void spi_nor_spimem_setup_op(const struct spi_nor *nor, 81 struct spi_mem_op *op, 82 const enum spi_nor_protocol proto) 83 { 84 u8 ext; 85 86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); 87 88 if (op->addr.nbytes) 89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); 90 91 if (op->dummy.nbytes) 92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); 93 94 if (op->data.nbytes) 95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); 96 97 if (spi_nor_protocol_is_dtr(proto)) { 98 /* 99 * SPIMEM supports mixed DTR modes, but right now we can only 100 * have all phases either DTR or STR. IOW, SPIMEM can have 101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4 102 * phases to either DTR or STR. 103 */ 104 op->cmd.dtr = true; 105 op->addr.dtr = true; 106 op->dummy.dtr = true; 107 op->data.dtr = true; 108 109 /* 2 bytes per clock cycle in DTR mode. */ 110 op->dummy.nbytes *= 2; 111 112 ext = spi_nor_get_cmd_ext(nor, op); 113 op->cmd.opcode = (op->cmd.opcode << 8) | ext; 114 op->cmd.nbytes = 2; 115 } 116 } 117 118 /** 119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data 120 * transfer 121 * @nor: pointer to 'struct spi_nor' 122 * @op: pointer to 'struct spi_mem_op' template for transfer 123 * 124 * If we have to use the bounce buffer, the data field in @op will be updated. 125 * 126 * Return: true if the bounce buffer is needed, false if not 127 */ 128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op) 129 { 130 /* op->data.buf.in occupies the same memory as op->data.buf.out */ 131 if (object_is_on_stack(op->data.buf.in) || 132 !virt_addr_valid(op->data.buf.in)) { 133 if (op->data.nbytes > nor->bouncebuf_size) 134 op->data.nbytes = nor->bouncebuf_size; 135 op->data.buf.in = nor->bouncebuf; 136 return true; 137 } 138 139 return false; 140 } 141 142 /** 143 * spi_nor_spimem_exec_op() - execute a memory operation 144 * @nor: pointer to 'struct spi_nor' 145 * @op: pointer to 'struct spi_mem_op' template for transfer 146 * 147 * Return: 0 on success, -error otherwise. 148 */ 149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) 150 { 151 int error; 152 153 error = spi_mem_adjust_op_size(nor->spimem, op); 154 if (error) 155 return error; 156 157 return spi_mem_exec_op(nor->spimem, op); 158 } 159 160 static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, 161 u8 *buf, size_t len) 162 { 163 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 164 return -EOPNOTSUPP; 165 166 return nor->controller_ops->read_reg(nor, opcode, buf, len); 167 } 168 169 static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, 170 const u8 *buf, size_t len) 171 { 172 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 173 return -EOPNOTSUPP; 174 175 return nor->controller_ops->write_reg(nor, opcode, buf, len); 176 } 177 178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs) 179 { 180 if (spi_nor_protocol_is_dtr(nor->write_proto)) 181 return -EOPNOTSUPP; 182 183 return nor->controller_ops->erase(nor, offs); 184 } 185 186 /** 187 * spi_nor_spimem_read_data() - read data from flash's memory region via 188 * spi-mem 189 * @nor: pointer to 'struct spi_nor' 190 * @from: offset to read from 191 * @len: number of bytes to read 192 * @buf: pointer to dst buffer 193 * 194 * Return: number of bytes read successfully, -errno otherwise 195 */ 196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, 197 size_t len, u8 *buf) 198 { 199 struct spi_mem_op op = 200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 201 SPI_MEM_OP_ADDR(nor->addr_width, from, 0), 202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 203 SPI_MEM_OP_DATA_IN(len, buf, 0)); 204 bool usebouncebuf; 205 ssize_t nbytes; 206 int error; 207 208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto); 209 210 /* convert the dummy cycles to the number of bytes */ 211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 212 if (spi_nor_protocol_is_dtr(nor->read_proto)) 213 op.dummy.nbytes *= 2; 214 215 usebouncebuf = spi_nor_spimem_bounce(nor, &op); 216 217 if (nor->dirmap.rdesc) { 218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val, 219 op.data.nbytes, op.data.buf.in); 220 } else { 221 error = spi_nor_spimem_exec_op(nor, &op); 222 if (error) 223 return error; 224 nbytes = op.data.nbytes; 225 } 226 227 if (usebouncebuf && nbytes > 0) 228 memcpy(buf, op.data.buf.in, nbytes); 229 230 return nbytes; 231 } 232 233 /** 234 * spi_nor_read_data() - read data from flash memory 235 * @nor: pointer to 'struct spi_nor' 236 * @from: offset to read from 237 * @len: number of bytes to read 238 * @buf: pointer to dst buffer 239 * 240 * Return: number of bytes read successfully, -errno otherwise 241 */ 242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) 243 { 244 if (nor->spimem) 245 return spi_nor_spimem_read_data(nor, from, len, buf); 246 247 return nor->controller_ops->read(nor, from, len, buf); 248 } 249 250 /** 251 * spi_nor_spimem_write_data() - write data to flash memory via 252 * spi-mem 253 * @nor: pointer to 'struct spi_nor' 254 * @to: offset to write to 255 * @len: number of bytes to write 256 * @buf: pointer to src buffer 257 * 258 * Return: number of bytes written successfully, -errno otherwise 259 */ 260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, 261 size_t len, const u8 *buf) 262 { 263 struct spi_mem_op op = 264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 265 SPI_MEM_OP_ADDR(nor->addr_width, to, 0), 266 SPI_MEM_OP_NO_DUMMY, 267 SPI_MEM_OP_DATA_OUT(len, buf, 0)); 268 ssize_t nbytes; 269 int error; 270 271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 272 op.addr.nbytes = 0; 273 274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 275 276 if (spi_nor_spimem_bounce(nor, &op)) 277 memcpy(nor->bouncebuf, buf, op.data.nbytes); 278 279 if (nor->dirmap.wdesc) { 280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val, 281 op.data.nbytes, op.data.buf.out); 282 } else { 283 error = spi_nor_spimem_exec_op(nor, &op); 284 if (error) 285 return error; 286 nbytes = op.data.nbytes; 287 } 288 289 return nbytes; 290 } 291 292 /** 293 * spi_nor_write_data() - write data to flash memory 294 * @nor: pointer to 'struct spi_nor' 295 * @to: offset to write to 296 * @len: number of bytes to write 297 * @buf: pointer to src buffer 298 * 299 * Return: number of bytes written successfully, -errno otherwise 300 */ 301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 302 const u8 *buf) 303 { 304 if (nor->spimem) 305 return spi_nor_spimem_write_data(nor, to, len, buf); 306 307 return nor->controller_ops->write(nor, to, len, buf); 308 } 309 310 /** 311 * spi_nor_write_enable() - Set write enable latch with Write Enable command. 312 * @nor: pointer to 'struct spi_nor'. 313 * 314 * Return: 0 on success, -errno otherwise. 315 */ 316 int spi_nor_write_enable(struct spi_nor *nor) 317 { 318 int ret; 319 320 if (nor->spimem) { 321 struct spi_mem_op op = 322 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), 323 SPI_MEM_OP_NO_ADDR, 324 SPI_MEM_OP_NO_DUMMY, 325 SPI_MEM_OP_NO_DATA); 326 327 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 328 329 ret = spi_mem_exec_op(nor->spimem, &op); 330 } else { 331 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, 332 NULL, 0); 333 } 334 335 if (ret) 336 dev_dbg(nor->dev, "error %d on Write Enable\n", ret); 337 338 return ret; 339 } 340 341 /** 342 * spi_nor_write_disable() - Send Write Disable instruction to the chip. 343 * @nor: pointer to 'struct spi_nor'. 344 * 345 * Return: 0 on success, -errno otherwise. 346 */ 347 int spi_nor_write_disable(struct spi_nor *nor) 348 { 349 int ret; 350 351 if (nor->spimem) { 352 struct spi_mem_op op = 353 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), 354 SPI_MEM_OP_NO_ADDR, 355 SPI_MEM_OP_NO_DUMMY, 356 SPI_MEM_OP_NO_DATA); 357 358 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 359 360 ret = spi_mem_exec_op(nor->spimem, &op); 361 } else { 362 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, 363 NULL, 0); 364 } 365 366 if (ret) 367 dev_dbg(nor->dev, "error %d on Write Disable\n", ret); 368 369 return ret; 370 } 371 372 /** 373 * spi_nor_read_sr() - Read the Status Register. 374 * @nor: pointer to 'struct spi_nor'. 375 * @sr: pointer to a DMA-able buffer where the value of the 376 * Status Register will be written. Should be at least 2 bytes. 377 * 378 * Return: 0 on success, -errno otherwise. 379 */ 380 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) 381 { 382 int ret; 383 384 if (nor->spimem) { 385 struct spi_mem_op op = 386 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), 387 SPI_MEM_OP_NO_ADDR, 388 SPI_MEM_OP_NO_DUMMY, 389 SPI_MEM_OP_DATA_IN(1, sr, 0)); 390 391 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 392 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 393 op.dummy.nbytes = nor->params->rdsr_dummy; 394 /* 395 * We don't want to read only one byte in DTR mode. So, 396 * read 2 and then discard the second byte. 397 */ 398 op.data.nbytes = 2; 399 } 400 401 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 402 403 ret = spi_mem_exec_op(nor->spimem, &op); 404 } else { 405 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, 406 1); 407 } 408 409 if (ret) 410 dev_dbg(nor->dev, "error %d reading SR\n", ret); 411 412 return ret; 413 } 414 415 /** 416 * spi_nor_read_fsr() - Read the Flag Status Register. 417 * @nor: pointer to 'struct spi_nor' 418 * @fsr: pointer to a DMA-able buffer where the value of the 419 * Flag Status Register will be written. Should be at least 2 420 * bytes. 421 * 422 * Return: 0 on success, -errno otherwise. 423 */ 424 static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) 425 { 426 int ret; 427 428 if (nor->spimem) { 429 struct spi_mem_op op = 430 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), 431 SPI_MEM_OP_NO_ADDR, 432 SPI_MEM_OP_NO_DUMMY, 433 SPI_MEM_OP_DATA_IN(1, fsr, 0)); 434 435 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 436 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 437 op.dummy.nbytes = nor->params->rdsr_dummy; 438 /* 439 * We don't want to read only one byte in DTR mode. So, 440 * read 2 and then discard the second byte. 441 */ 442 op.data.nbytes = 2; 443 } 444 445 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 446 447 ret = spi_mem_exec_op(nor->spimem, &op); 448 } else { 449 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, 450 1); 451 } 452 453 if (ret) 454 dev_dbg(nor->dev, "error %d reading FSR\n", ret); 455 456 return ret; 457 } 458 459 /** 460 * spi_nor_read_cr() - Read the Configuration Register using the 461 * SPINOR_OP_RDCR (35h) command. 462 * @nor: pointer to 'struct spi_nor' 463 * @cr: pointer to a DMA-able buffer where the value of the 464 * Configuration Register will be written. 465 * 466 * Return: 0 on success, -errno otherwise. 467 */ 468 static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) 469 { 470 int ret; 471 472 if (nor->spimem) { 473 struct spi_mem_op op = 474 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), 475 SPI_MEM_OP_NO_ADDR, 476 SPI_MEM_OP_NO_DUMMY, 477 SPI_MEM_OP_DATA_IN(1, cr, 0)); 478 479 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 480 481 ret = spi_mem_exec_op(nor->spimem, &op); 482 } else { 483 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, 484 1); 485 } 486 487 if (ret) 488 dev_dbg(nor->dev, "error %d reading CR\n", ret); 489 490 return ret; 491 } 492 493 /** 494 * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode. 495 * @nor: pointer to 'struct spi_nor'. 496 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 497 * address mode. 498 * 499 * Return: 0 on success, -errno otherwise. 500 */ 501 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 502 { 503 int ret; 504 505 if (nor->spimem) { 506 struct spi_mem_op op = 507 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? 508 SPINOR_OP_EN4B : 509 SPINOR_OP_EX4B, 510 0), 511 SPI_MEM_OP_NO_ADDR, 512 SPI_MEM_OP_NO_DUMMY, 513 SPI_MEM_OP_NO_DATA); 514 515 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 516 517 ret = spi_mem_exec_op(nor->spimem, &op); 518 } else { 519 ret = spi_nor_controller_ops_write_reg(nor, 520 enable ? SPINOR_OP_EN4B : 521 SPINOR_OP_EX4B, 522 NULL, 0); 523 } 524 525 if (ret) 526 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 527 528 return ret; 529 } 530 531 /** 532 * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion 533 * flashes. 534 * @nor: pointer to 'struct spi_nor'. 535 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 536 * address mode. 537 * 538 * Return: 0 on success, -errno otherwise. 539 */ 540 static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 541 { 542 int ret; 543 544 nor->bouncebuf[0] = enable << 7; 545 546 if (nor->spimem) { 547 struct spi_mem_op op = 548 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), 549 SPI_MEM_OP_NO_ADDR, 550 SPI_MEM_OP_NO_DUMMY, 551 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); 552 553 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 554 555 ret = spi_mem_exec_op(nor->spimem, &op); 556 } else { 557 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR, 558 nor->bouncebuf, 1); 559 } 560 561 if (ret) 562 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 563 564 return ret; 565 } 566 567 /** 568 * spi_nor_write_ear() - Write Extended Address Register. 569 * @nor: pointer to 'struct spi_nor'. 570 * @ear: value to write to the Extended Address Register. 571 * 572 * Return: 0 on success, -errno otherwise. 573 */ 574 int spi_nor_write_ear(struct spi_nor *nor, u8 ear) 575 { 576 int ret; 577 578 nor->bouncebuf[0] = ear; 579 580 if (nor->spimem) { 581 struct spi_mem_op op = 582 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0), 583 SPI_MEM_OP_NO_ADDR, 584 SPI_MEM_OP_NO_DUMMY, 585 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); 586 587 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 588 589 ret = spi_mem_exec_op(nor->spimem, &op); 590 } else { 591 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREAR, 592 nor->bouncebuf, 1); 593 } 594 595 if (ret) 596 dev_dbg(nor->dev, "error %d writing EAR\n", ret); 597 598 return ret; 599 } 600 601 /** 602 * spi_nor_xread_sr() - Read the Status Register on S3AN flashes. 603 * @nor: pointer to 'struct spi_nor'. 604 * @sr: pointer to a DMA-able buffer where the value of the 605 * Status Register will be written. 606 * 607 * Return: 0 on success, -errno otherwise. 608 */ 609 int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) 610 { 611 int ret; 612 613 if (nor->spimem) { 614 struct spi_mem_op op = 615 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0), 616 SPI_MEM_OP_NO_ADDR, 617 SPI_MEM_OP_NO_DUMMY, 618 SPI_MEM_OP_DATA_IN(1, sr, 0)); 619 620 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 621 622 ret = spi_mem_exec_op(nor->spimem, &op); 623 } else { 624 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr, 625 1); 626 } 627 628 if (ret) 629 dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); 630 631 return ret; 632 } 633 634 /** 635 * spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if 636 * the flash is ready for new commands. 637 * @nor: pointer to 'struct spi_nor'. 638 * 639 * Return: 1 if ready, 0 if not ready, -errno on errors. 640 */ 641 static int spi_nor_xsr_ready(struct spi_nor *nor) 642 { 643 int ret; 644 645 ret = spi_nor_xread_sr(nor, nor->bouncebuf); 646 if (ret) 647 return ret; 648 649 return !!(nor->bouncebuf[0] & XSR_RDY); 650 } 651 652 /** 653 * spi_nor_clear_sr() - Clear the Status Register. 654 * @nor: pointer to 'struct spi_nor'. 655 */ 656 static void spi_nor_clear_sr(struct spi_nor *nor) 657 { 658 int ret; 659 660 if (nor->spimem) { 661 struct spi_mem_op op = 662 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), 663 SPI_MEM_OP_NO_ADDR, 664 SPI_MEM_OP_NO_DUMMY, 665 SPI_MEM_OP_NO_DATA); 666 667 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 668 669 ret = spi_mem_exec_op(nor->spimem, &op); 670 } else { 671 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, 672 NULL, 0); 673 } 674 675 if (ret) 676 dev_dbg(nor->dev, "error %d clearing SR\n", ret); 677 } 678 679 /** 680 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready 681 * for new commands. 682 * @nor: pointer to 'struct spi_nor'. 683 * 684 * Return: 1 if ready, 0 if not ready, -errno on errors. 685 */ 686 static int spi_nor_sr_ready(struct spi_nor *nor) 687 { 688 int ret = spi_nor_read_sr(nor, nor->bouncebuf); 689 690 if (ret) 691 return ret; 692 693 if (nor->flags & SNOR_F_USE_CLSR && 694 nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 695 if (nor->bouncebuf[0] & SR_E_ERR) 696 dev_err(nor->dev, "Erase Error occurred\n"); 697 else 698 dev_err(nor->dev, "Programming Error occurred\n"); 699 700 spi_nor_clear_sr(nor); 701 702 /* 703 * WEL bit remains set to one when an erase or page program 704 * error occurs. Issue a Write Disable command to protect 705 * against inadvertent writes that can possibly corrupt the 706 * contents of the memory. 707 */ 708 ret = spi_nor_write_disable(nor); 709 if (ret) 710 return ret; 711 712 return -EIO; 713 } 714 715 return !(nor->bouncebuf[0] & SR_WIP); 716 } 717 718 /** 719 * spi_nor_clear_fsr() - Clear the Flag Status Register. 720 * @nor: pointer to 'struct spi_nor'. 721 */ 722 static void spi_nor_clear_fsr(struct spi_nor *nor) 723 { 724 int ret; 725 726 if (nor->spimem) { 727 struct spi_mem_op op = 728 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), 729 SPI_MEM_OP_NO_ADDR, 730 SPI_MEM_OP_NO_DUMMY, 731 SPI_MEM_OP_NO_DATA); 732 733 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 734 735 ret = spi_mem_exec_op(nor->spimem, &op); 736 } else { 737 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, 738 NULL, 0); 739 } 740 741 if (ret) 742 dev_dbg(nor->dev, "error %d clearing FSR\n", ret); 743 } 744 745 /** 746 * spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is 747 * ready for new commands. 748 * @nor: pointer to 'struct spi_nor'. 749 * 750 * Return: 1 if ready, 0 if not ready, -errno on errors. 751 */ 752 static int spi_nor_fsr_ready(struct spi_nor *nor) 753 { 754 int ret = spi_nor_read_fsr(nor, nor->bouncebuf); 755 756 if (ret) 757 return ret; 758 759 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { 760 if (nor->bouncebuf[0] & FSR_E_ERR) 761 dev_err(nor->dev, "Erase operation failed.\n"); 762 else 763 dev_err(nor->dev, "Program operation failed.\n"); 764 765 if (nor->bouncebuf[0] & FSR_PT_ERR) 766 dev_err(nor->dev, 767 "Attempted to modify a protected sector.\n"); 768 769 spi_nor_clear_fsr(nor); 770 771 /* 772 * WEL bit remains set to one when an erase or page program 773 * error occurs. Issue a Write Disable command to protect 774 * against inadvertent writes that can possibly corrupt the 775 * contents of the memory. 776 */ 777 ret = spi_nor_write_disable(nor); 778 if (ret) 779 return ret; 780 781 return -EIO; 782 } 783 784 return !!(nor->bouncebuf[0] & FSR_READY); 785 } 786 787 /** 788 * spi_nor_ready() - Query the flash to see if it is ready for new commands. 789 * @nor: pointer to 'struct spi_nor'. 790 * 791 * Return: 1 if ready, 0 if not ready, -errno on errors. 792 */ 793 static int spi_nor_ready(struct spi_nor *nor) 794 { 795 int sr, fsr; 796 797 if (nor->flags & SNOR_F_READY_XSR_RDY) 798 sr = spi_nor_xsr_ready(nor); 799 else 800 sr = spi_nor_sr_ready(nor); 801 if (sr < 0) 802 return sr; 803 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 804 if (fsr < 0) 805 return fsr; 806 return sr && fsr; 807 } 808 809 /** 810 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the 811 * Status Register until ready, or timeout occurs. 812 * @nor: pointer to "struct spi_nor". 813 * @timeout_jiffies: jiffies to wait until timeout. 814 * 815 * Return: 0 on success, -errno otherwise. 816 */ 817 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 818 unsigned long timeout_jiffies) 819 { 820 unsigned long deadline; 821 int timeout = 0, ret; 822 823 deadline = jiffies + timeout_jiffies; 824 825 while (!timeout) { 826 if (time_after_eq(jiffies, deadline)) 827 timeout = 1; 828 829 ret = spi_nor_ready(nor); 830 if (ret < 0) 831 return ret; 832 if (ret) 833 return 0; 834 835 cond_resched(); 836 } 837 838 dev_dbg(nor->dev, "flash operation timed out\n"); 839 840 return -ETIMEDOUT; 841 } 842 843 /** 844 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the 845 * flash to be ready, or timeout occurs. 846 * @nor: pointer to "struct spi_nor". 847 * 848 * Return: 0 on success, -errno otherwise. 849 */ 850 int spi_nor_wait_till_ready(struct spi_nor *nor) 851 { 852 return spi_nor_wait_till_ready_with_timeout(nor, 853 DEFAULT_READY_WAIT_JIFFIES); 854 } 855 856 /** 857 * spi_nor_write_sr() - Write the Status Register. 858 * @nor: pointer to 'struct spi_nor'. 859 * @sr: pointer to DMA-able buffer to write to the Status Register. 860 * @len: number of bytes to write to the Status Register. 861 * 862 * Return: 0 on success, -errno otherwise. 863 */ 864 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) 865 { 866 int ret; 867 868 ret = spi_nor_write_enable(nor); 869 if (ret) 870 return ret; 871 872 if (nor->spimem) { 873 struct spi_mem_op op = 874 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), 875 SPI_MEM_OP_NO_ADDR, 876 SPI_MEM_OP_NO_DUMMY, 877 SPI_MEM_OP_DATA_OUT(len, sr, 0)); 878 879 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 880 881 ret = spi_mem_exec_op(nor->spimem, &op); 882 } else { 883 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, 884 len); 885 } 886 887 if (ret) { 888 dev_dbg(nor->dev, "error %d writing SR\n", ret); 889 return ret; 890 } 891 892 return spi_nor_wait_till_ready(nor); 893 } 894 895 /** 896 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and 897 * ensure that the byte written match the received value. 898 * @nor: pointer to a 'struct spi_nor'. 899 * @sr1: byte value to be written to the Status Register. 900 * 901 * Return: 0 on success, -errno otherwise. 902 */ 903 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) 904 { 905 int ret; 906 907 nor->bouncebuf[0] = sr1; 908 909 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); 910 if (ret) 911 return ret; 912 913 ret = spi_nor_read_sr(nor, nor->bouncebuf); 914 if (ret) 915 return ret; 916 917 if (nor->bouncebuf[0] != sr1) { 918 dev_dbg(nor->dev, "SR1: read back test failed\n"); 919 return -EIO; 920 } 921 922 return 0; 923 } 924 925 /** 926 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the 927 * Status Register 2 in one shot. Ensure that the byte written in the Status 928 * Register 1 match the received value, and that the 16-bit Write did not 929 * affect what was already in the Status Register 2. 930 * @nor: pointer to a 'struct spi_nor'. 931 * @sr1: byte value to be written to the Status Register 1. 932 * 933 * Return: 0 on success, -errno otherwise. 934 */ 935 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 936 { 937 int ret; 938 u8 *sr_cr = nor->bouncebuf; 939 u8 cr_written; 940 941 /* Make sure we don't overwrite the contents of Status Register 2. */ 942 if (!(nor->flags & SNOR_F_NO_READ_CR)) { 943 ret = spi_nor_read_cr(nor, &sr_cr[1]); 944 if (ret) 945 return ret; 946 } else if (nor->params->quad_enable) { 947 /* 948 * If the Status Register 2 Read command (35h) is not 949 * supported, we should at least be sure we don't 950 * change the value of the SR2 Quad Enable bit. 951 * 952 * We can safely assume that when the Quad Enable method is 953 * set, the value of the QE bit is one, as a consequence of the 954 * nor->params->quad_enable() call. 955 * 956 * We can safely assume that the Quad Enable bit is present in 957 * the Status Register 2 at BIT(1). According to the JESD216 958 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit 959 * Write Status (01h) command is available just for the cases 960 * in which the QE bit is described in SR2 at BIT(1). 961 */ 962 sr_cr[1] = SR2_QUAD_EN_BIT1; 963 } else { 964 sr_cr[1] = 0; 965 } 966 967 sr_cr[0] = sr1; 968 969 ret = spi_nor_write_sr(nor, sr_cr, 2); 970 if (ret) 971 return ret; 972 973 if (nor->flags & SNOR_F_NO_READ_CR) 974 return 0; 975 976 cr_written = sr_cr[1]; 977 978 ret = spi_nor_read_cr(nor, &sr_cr[1]); 979 if (ret) 980 return ret; 981 982 if (cr_written != sr_cr[1]) { 983 dev_dbg(nor->dev, "CR: read back test failed\n"); 984 return -EIO; 985 } 986 987 return 0; 988 } 989 990 /** 991 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the 992 * Configuration Register in one shot. Ensure that the byte written in the 993 * Configuration Register match the received value, and that the 16-bit Write 994 * did not affect what was already in the Status Register 1. 995 * @nor: pointer to a 'struct spi_nor'. 996 * @cr: byte value to be written to the Configuration Register. 997 * 998 * Return: 0 on success, -errno otherwise. 999 */ 1000 static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) 1001 { 1002 int ret; 1003 u8 *sr_cr = nor->bouncebuf; 1004 u8 sr_written; 1005 1006 /* Keep the current value of the Status Register 1. */ 1007 ret = spi_nor_read_sr(nor, sr_cr); 1008 if (ret) 1009 return ret; 1010 1011 sr_cr[1] = cr; 1012 1013 ret = spi_nor_write_sr(nor, sr_cr, 2); 1014 if (ret) 1015 return ret; 1016 1017 sr_written = sr_cr[0]; 1018 1019 ret = spi_nor_read_sr(nor, sr_cr); 1020 if (ret) 1021 return ret; 1022 1023 if (sr_written != sr_cr[0]) { 1024 dev_dbg(nor->dev, "SR: Read back test failed\n"); 1025 return -EIO; 1026 } 1027 1028 if (nor->flags & SNOR_F_NO_READ_CR) 1029 return 0; 1030 1031 ret = spi_nor_read_cr(nor, &sr_cr[1]); 1032 if (ret) 1033 return ret; 1034 1035 if (cr != sr_cr[1]) { 1036 dev_dbg(nor->dev, "CR: read back test failed\n"); 1037 return -EIO; 1038 } 1039 1040 return 0; 1041 } 1042 1043 /** 1044 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that 1045 * the byte written match the received value without affecting other bits in the 1046 * Status Register 1 and 2. 1047 * @nor: pointer to a 'struct spi_nor'. 1048 * @sr1: byte value to be written to the Status Register. 1049 * 1050 * Return: 0 on success, -errno otherwise. 1051 */ 1052 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) 1053 { 1054 if (nor->flags & SNOR_F_HAS_16BIT_SR) 1055 return spi_nor_write_16bit_sr_and_check(nor, sr1); 1056 1057 return spi_nor_write_sr1_and_check(nor, sr1); 1058 } 1059 1060 /** 1061 * spi_nor_write_sr2() - Write the Status Register 2 using the 1062 * SPINOR_OP_WRSR2 (3eh) command. 1063 * @nor: pointer to 'struct spi_nor'. 1064 * @sr2: pointer to DMA-able buffer to write to the Status Register 2. 1065 * 1066 * Return: 0 on success, -errno otherwise. 1067 */ 1068 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) 1069 { 1070 int ret; 1071 1072 ret = spi_nor_write_enable(nor); 1073 if (ret) 1074 return ret; 1075 1076 if (nor->spimem) { 1077 struct spi_mem_op op = 1078 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), 1079 SPI_MEM_OP_NO_ADDR, 1080 SPI_MEM_OP_NO_DUMMY, 1081 SPI_MEM_OP_DATA_OUT(1, sr2, 0)); 1082 1083 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1084 1085 ret = spi_mem_exec_op(nor->spimem, &op); 1086 } else { 1087 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, 1088 sr2, 1); 1089 } 1090 1091 if (ret) { 1092 dev_dbg(nor->dev, "error %d writing SR2\n", ret); 1093 return ret; 1094 } 1095 1096 return spi_nor_wait_till_ready(nor); 1097 } 1098 1099 /** 1100 * spi_nor_read_sr2() - Read the Status Register 2 using the 1101 * SPINOR_OP_RDSR2 (3fh) command. 1102 * @nor: pointer to 'struct spi_nor'. 1103 * @sr2: pointer to DMA-able buffer where the value of the 1104 * Status Register 2 will be written. 1105 * 1106 * Return: 0 on success, -errno otherwise. 1107 */ 1108 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) 1109 { 1110 int ret; 1111 1112 if (nor->spimem) { 1113 struct spi_mem_op op = 1114 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), 1115 SPI_MEM_OP_NO_ADDR, 1116 SPI_MEM_OP_NO_DUMMY, 1117 SPI_MEM_OP_DATA_IN(1, sr2, 0)); 1118 1119 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1120 1121 ret = spi_mem_exec_op(nor->spimem, &op); 1122 } else { 1123 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, 1124 1); 1125 } 1126 1127 if (ret) 1128 dev_dbg(nor->dev, "error %d reading SR2\n", ret); 1129 1130 return ret; 1131 } 1132 1133 /** 1134 * spi_nor_erase_chip() - Erase the entire flash memory. 1135 * @nor: pointer to 'struct spi_nor'. 1136 * 1137 * Return: 0 on success, -errno otherwise. 1138 */ 1139 static int spi_nor_erase_chip(struct spi_nor *nor) 1140 { 1141 int ret; 1142 1143 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); 1144 1145 if (nor->spimem) { 1146 struct spi_mem_op op = 1147 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), 1148 SPI_MEM_OP_NO_ADDR, 1149 SPI_MEM_OP_NO_DUMMY, 1150 SPI_MEM_OP_NO_DATA); 1151 1152 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 1153 1154 ret = spi_mem_exec_op(nor->spimem, &op); 1155 } else { 1156 ret = spi_nor_controller_ops_write_reg(nor, 1157 SPINOR_OP_CHIP_ERASE, 1158 NULL, 0); 1159 } 1160 1161 if (ret) 1162 dev_dbg(nor->dev, "error %d erasing chip\n", ret); 1163 1164 return ret; 1165 } 1166 1167 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 1168 { 1169 size_t i; 1170 1171 for (i = 0; i < size; i++) 1172 if (table[i][0] == opcode) 1173 return table[i][1]; 1174 1175 /* No conversion found, keep input op code. */ 1176 return opcode; 1177 } 1178 1179 u8 spi_nor_convert_3to4_read(u8 opcode) 1180 { 1181 static const u8 spi_nor_3to4_read[][2] = { 1182 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 1183 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 1184 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 1185 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 1186 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 1187 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 1188 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, 1189 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, 1190 1191 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 1192 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 1193 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 1194 }; 1195 1196 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 1197 ARRAY_SIZE(spi_nor_3to4_read)); 1198 } 1199 1200 static u8 spi_nor_convert_3to4_program(u8 opcode) 1201 { 1202 static const u8 spi_nor_3to4_program[][2] = { 1203 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 1204 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 1205 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 1206 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, 1207 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, 1208 }; 1209 1210 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 1211 ARRAY_SIZE(spi_nor_3to4_program)); 1212 } 1213 1214 static u8 spi_nor_convert_3to4_erase(u8 opcode) 1215 { 1216 static const u8 spi_nor_3to4_erase[][2] = { 1217 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 1218 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 1219 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 1220 }; 1221 1222 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 1223 ARRAY_SIZE(spi_nor_3to4_erase)); 1224 } 1225 1226 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor) 1227 { 1228 return !!nor->params->erase_map.uniform_erase_type; 1229 } 1230 1231 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor) 1232 { 1233 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 1234 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 1235 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 1236 1237 if (!spi_nor_has_uniform_erase(nor)) { 1238 struct spi_nor_erase_map *map = &nor->params->erase_map; 1239 struct spi_nor_erase_type *erase; 1240 int i; 1241 1242 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1243 erase = &map->erase_type[i]; 1244 erase->opcode = 1245 spi_nor_convert_3to4_erase(erase->opcode); 1246 } 1247 } 1248 } 1249 1250 int spi_nor_lock_and_prep(struct spi_nor *nor) 1251 { 1252 int ret = 0; 1253 1254 mutex_lock(&nor->lock); 1255 1256 if (nor->controller_ops && nor->controller_ops->prepare) { 1257 ret = nor->controller_ops->prepare(nor); 1258 if (ret) { 1259 mutex_unlock(&nor->lock); 1260 return ret; 1261 } 1262 } 1263 return ret; 1264 } 1265 1266 void spi_nor_unlock_and_unprep(struct spi_nor *nor) 1267 { 1268 if (nor->controller_ops && nor->controller_ops->unprepare) 1269 nor->controller_ops->unprepare(nor); 1270 mutex_unlock(&nor->lock); 1271 } 1272 1273 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr) 1274 { 1275 if (!nor->params->convert_addr) 1276 return addr; 1277 1278 return nor->params->convert_addr(nor, addr); 1279 } 1280 1281 /* 1282 * Initiate the erasure of a single sector 1283 */ 1284 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 1285 { 1286 int i; 1287 1288 addr = spi_nor_convert_addr(nor, addr); 1289 1290 if (nor->spimem) { 1291 struct spi_mem_op op = 1292 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0), 1293 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), 1294 SPI_MEM_OP_NO_DUMMY, 1295 SPI_MEM_OP_NO_DATA); 1296 1297 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 1298 1299 return spi_mem_exec_op(nor->spimem, &op); 1300 } else if (nor->controller_ops->erase) { 1301 return spi_nor_controller_ops_erase(nor, addr); 1302 } 1303 1304 /* 1305 * Default implementation, if driver doesn't have a specialized HW 1306 * control 1307 */ 1308 for (i = nor->addr_width - 1; i >= 0; i--) { 1309 nor->bouncebuf[i] = addr & 0xff; 1310 addr >>= 8; 1311 } 1312 1313 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, 1314 nor->bouncebuf, nor->addr_width); 1315 } 1316 1317 /** 1318 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend 1319 * @erase: pointer to a structure that describes a SPI NOR erase type 1320 * @dividend: dividend value 1321 * @remainder: pointer to u32 remainder (will be updated) 1322 * 1323 * Return: the result of the division 1324 */ 1325 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase, 1326 u64 dividend, u32 *remainder) 1327 { 1328 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 1329 *remainder = (u32)dividend & erase->size_mask; 1330 return dividend >> erase->size_shift; 1331 } 1332 1333 /** 1334 * spi_nor_find_best_erase_type() - find the best erase type for the given 1335 * offset in the serial flash memory and the 1336 * number of bytes to erase. The region in 1337 * which the address fits is expected to be 1338 * provided. 1339 * @map: the erase map of the SPI NOR 1340 * @region: pointer to a structure that describes a SPI NOR erase region 1341 * @addr: offset in the serial flash memory 1342 * @len: number of bytes to erase 1343 * 1344 * Return: a pointer to the best fitted erase type, NULL otherwise. 1345 */ 1346 static const struct spi_nor_erase_type * 1347 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, 1348 const struct spi_nor_erase_region *region, 1349 u64 addr, u32 len) 1350 { 1351 const struct spi_nor_erase_type *erase; 1352 u32 rem; 1353 int i; 1354 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 1355 1356 /* 1357 * Erase types are ordered by size, with the smallest erase type at 1358 * index 0. 1359 */ 1360 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 1361 /* Does the erase region support the tested erase type? */ 1362 if (!(erase_mask & BIT(i))) 1363 continue; 1364 1365 erase = &map->erase_type[i]; 1366 1367 /* Don't erase more than what the user has asked for. */ 1368 if (erase->size > len) 1369 continue; 1370 1371 /* Alignment is not mandatory for overlaid regions */ 1372 if (region->offset & SNOR_OVERLAID_REGION) 1373 return erase; 1374 1375 spi_nor_div_by_erase_size(erase, addr, &rem); 1376 if (rem) 1377 continue; 1378 else 1379 return erase; 1380 } 1381 1382 return NULL; 1383 } 1384 1385 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region) 1386 { 1387 return region->offset & SNOR_LAST_REGION; 1388 } 1389 1390 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region) 1391 { 1392 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; 1393 } 1394 1395 /** 1396 * spi_nor_region_next() - get the next spi nor region 1397 * @region: pointer to a structure that describes a SPI NOR erase region 1398 * 1399 * Return: the next spi nor region or NULL if last region. 1400 */ 1401 struct spi_nor_erase_region * 1402 spi_nor_region_next(struct spi_nor_erase_region *region) 1403 { 1404 if (spi_nor_region_is_last(region)) 1405 return NULL; 1406 region++; 1407 return region; 1408 } 1409 1410 /** 1411 * spi_nor_find_erase_region() - find the region of the serial flash memory in 1412 * which the offset fits 1413 * @map: the erase map of the SPI NOR 1414 * @addr: offset in the serial flash memory 1415 * 1416 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno) 1417 * otherwise. 1418 */ 1419 static struct spi_nor_erase_region * 1420 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr) 1421 { 1422 struct spi_nor_erase_region *region = map->regions; 1423 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1424 u64 region_end = region_start + region->size; 1425 1426 while (addr < region_start || addr >= region_end) { 1427 region = spi_nor_region_next(region); 1428 if (!region) 1429 return ERR_PTR(-EINVAL); 1430 1431 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1432 region_end = region_start + region->size; 1433 } 1434 1435 return region; 1436 } 1437 1438 /** 1439 * spi_nor_init_erase_cmd() - initialize an erase command 1440 * @region: pointer to a structure that describes a SPI NOR erase region 1441 * @erase: pointer to a structure that describes a SPI NOR erase type 1442 * 1443 * Return: the pointer to the allocated erase command, ERR_PTR(-errno) 1444 * otherwise. 1445 */ 1446 static struct spi_nor_erase_command * 1447 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region, 1448 const struct spi_nor_erase_type *erase) 1449 { 1450 struct spi_nor_erase_command *cmd; 1451 1452 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); 1453 if (!cmd) 1454 return ERR_PTR(-ENOMEM); 1455 1456 INIT_LIST_HEAD(&cmd->list); 1457 cmd->opcode = erase->opcode; 1458 cmd->count = 1; 1459 1460 if (region->offset & SNOR_OVERLAID_REGION) 1461 cmd->size = region->size; 1462 else 1463 cmd->size = erase->size; 1464 1465 return cmd; 1466 } 1467 1468 /** 1469 * spi_nor_destroy_erase_cmd_list() - destroy erase command list 1470 * @erase_list: list of erase commands 1471 */ 1472 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list) 1473 { 1474 struct spi_nor_erase_command *cmd, *next; 1475 1476 list_for_each_entry_safe(cmd, next, erase_list, list) { 1477 list_del(&cmd->list); 1478 kfree(cmd); 1479 } 1480 } 1481 1482 /** 1483 * spi_nor_init_erase_cmd_list() - initialize erase command list 1484 * @nor: pointer to a 'struct spi_nor' 1485 * @erase_list: list of erase commands to be executed once we validate that the 1486 * erase can be performed 1487 * @addr: offset in the serial flash memory 1488 * @len: number of bytes to erase 1489 * 1490 * Builds the list of best fitted erase commands and verifies if the erase can 1491 * be performed. 1492 * 1493 * Return: 0 on success, -errno otherwise. 1494 */ 1495 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, 1496 struct list_head *erase_list, 1497 u64 addr, u32 len) 1498 { 1499 const struct spi_nor_erase_map *map = &nor->params->erase_map; 1500 const struct spi_nor_erase_type *erase, *prev_erase = NULL; 1501 struct spi_nor_erase_region *region; 1502 struct spi_nor_erase_command *cmd = NULL; 1503 u64 region_end; 1504 int ret = -EINVAL; 1505 1506 region = spi_nor_find_erase_region(map, addr); 1507 if (IS_ERR(region)) 1508 return PTR_ERR(region); 1509 1510 region_end = spi_nor_region_end(region); 1511 1512 while (len) { 1513 erase = spi_nor_find_best_erase_type(map, region, addr, len); 1514 if (!erase) 1515 goto destroy_erase_cmd_list; 1516 1517 if (prev_erase != erase || 1518 region->offset & SNOR_OVERLAID_REGION) { 1519 cmd = spi_nor_init_erase_cmd(region, erase); 1520 if (IS_ERR(cmd)) { 1521 ret = PTR_ERR(cmd); 1522 goto destroy_erase_cmd_list; 1523 } 1524 1525 list_add_tail(&cmd->list, erase_list); 1526 } else { 1527 cmd->count++; 1528 } 1529 1530 addr += cmd->size; 1531 len -= cmd->size; 1532 1533 if (len && addr >= region_end) { 1534 region = spi_nor_region_next(region); 1535 if (!region) 1536 goto destroy_erase_cmd_list; 1537 region_end = spi_nor_region_end(region); 1538 } 1539 1540 prev_erase = erase; 1541 } 1542 1543 return 0; 1544 1545 destroy_erase_cmd_list: 1546 spi_nor_destroy_erase_cmd_list(erase_list); 1547 return ret; 1548 } 1549 1550 /** 1551 * spi_nor_erase_multi_sectors() - perform a non-uniform erase 1552 * @nor: pointer to a 'struct spi_nor' 1553 * @addr: offset in the serial flash memory 1554 * @len: number of bytes to erase 1555 * 1556 * Build a list of best fitted erase commands and execute it once we validate 1557 * that the erase can be performed. 1558 * 1559 * Return: 0 on success, -errno otherwise. 1560 */ 1561 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) 1562 { 1563 LIST_HEAD(erase_list); 1564 struct spi_nor_erase_command *cmd, *next; 1565 int ret; 1566 1567 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len); 1568 if (ret) 1569 return ret; 1570 1571 list_for_each_entry_safe(cmd, next, &erase_list, list) { 1572 nor->erase_opcode = cmd->opcode; 1573 while (cmd->count) { 1574 ret = spi_nor_write_enable(nor); 1575 if (ret) 1576 goto destroy_erase_cmd_list; 1577 1578 ret = spi_nor_erase_sector(nor, addr); 1579 if (ret) 1580 goto destroy_erase_cmd_list; 1581 1582 addr += cmd->size; 1583 cmd->count--; 1584 1585 ret = spi_nor_wait_till_ready(nor); 1586 if (ret) 1587 goto destroy_erase_cmd_list; 1588 } 1589 list_del(&cmd->list); 1590 kfree(cmd); 1591 } 1592 1593 return 0; 1594 1595 destroy_erase_cmd_list: 1596 spi_nor_destroy_erase_cmd_list(&erase_list); 1597 return ret; 1598 } 1599 1600 /* 1601 * Erase an address range on the nor chip. The address range may extend 1602 * one or more erase sectors. Return an error if there is a problem erasing. 1603 */ 1604 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 1605 { 1606 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1607 u32 addr, len; 1608 uint32_t rem; 1609 int ret; 1610 1611 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 1612 (long long)instr->len); 1613 1614 if (spi_nor_has_uniform_erase(nor)) { 1615 div_u64_rem(instr->len, mtd->erasesize, &rem); 1616 if (rem) 1617 return -EINVAL; 1618 } 1619 1620 addr = instr->addr; 1621 len = instr->len; 1622 1623 ret = spi_nor_lock_and_prep(nor); 1624 if (ret) 1625 return ret; 1626 1627 /* whole-chip erase? */ 1628 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { 1629 unsigned long timeout; 1630 1631 ret = spi_nor_write_enable(nor); 1632 if (ret) 1633 goto erase_err; 1634 1635 ret = spi_nor_erase_chip(nor); 1636 if (ret) 1637 goto erase_err; 1638 1639 /* 1640 * Scale the timeout linearly with the size of the flash, with 1641 * a minimum calibrated to an old 2MB flash. We could try to 1642 * pull these from CFI/SFDP, but these values should be good 1643 * enough for now. 1644 */ 1645 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, 1646 CHIP_ERASE_2MB_READY_WAIT_JIFFIES * 1647 (unsigned long)(mtd->size / SZ_2M)); 1648 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); 1649 if (ret) 1650 goto erase_err; 1651 1652 /* REVISIT in some cases we could speed up erasing large regions 1653 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up 1654 * to use "small sector erase", but that's not always optimal. 1655 */ 1656 1657 /* "sector"-at-a-time erase */ 1658 } else if (spi_nor_has_uniform_erase(nor)) { 1659 while (len) { 1660 ret = spi_nor_write_enable(nor); 1661 if (ret) 1662 goto erase_err; 1663 1664 ret = spi_nor_erase_sector(nor, addr); 1665 if (ret) 1666 goto erase_err; 1667 1668 addr += mtd->erasesize; 1669 len -= mtd->erasesize; 1670 1671 ret = spi_nor_wait_till_ready(nor); 1672 if (ret) 1673 goto erase_err; 1674 } 1675 1676 /* erase multiple sectors */ 1677 } else { 1678 ret = spi_nor_erase_multi_sectors(nor, addr, len); 1679 if (ret) 1680 goto erase_err; 1681 } 1682 1683 ret = spi_nor_write_disable(nor); 1684 1685 erase_err: 1686 spi_nor_unlock_and_unprep(nor); 1687 1688 return ret; 1689 } 1690 1691 static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor) 1692 { 1693 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 1694 1695 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6) 1696 return mask | SR_BP3_BIT6; 1697 1698 if (nor->flags & SNOR_F_HAS_4BIT_BP) 1699 return mask | SR_BP3; 1700 1701 return mask; 1702 } 1703 1704 static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor) 1705 { 1706 if (nor->flags & SNOR_F_HAS_SR_TB_BIT6) 1707 return SR_TB_BIT6; 1708 else 1709 return SR_TB_BIT5; 1710 } 1711 1712 static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) 1713 { 1714 unsigned int bp_slots, bp_slots_needed; 1715 u8 mask = spi_nor_get_sr_bp_mask(nor); 1716 1717 /* Reserved one for "protect none" and one for "protect all". */ 1718 bp_slots = (1 << hweight8(mask)) - 2; 1719 bp_slots_needed = ilog2(nor->info->n_sectors); 1720 1721 if (bp_slots_needed > bp_slots) 1722 return nor->info->sector_size << 1723 (bp_slots_needed - bp_slots); 1724 else 1725 return nor->info->sector_size; 1726 } 1727 1728 static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, 1729 uint64_t *len) 1730 { 1731 struct mtd_info *mtd = &nor->mtd; 1732 u64 min_prot_len; 1733 u8 mask = spi_nor_get_sr_bp_mask(nor); 1734 u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1735 u8 bp, val = sr & mask; 1736 1737 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6) 1738 val = (val & ~SR_BP3_BIT6) | SR_BP3; 1739 1740 bp = val >> SR_BP_SHIFT; 1741 1742 if (!bp) { 1743 /* No protection */ 1744 *ofs = 0; 1745 *len = 0; 1746 return; 1747 } 1748 1749 min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1750 *len = min_prot_len << (bp - 1); 1751 1752 if (*len > mtd->size) 1753 *len = mtd->size; 1754 1755 if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask) 1756 *ofs = 0; 1757 else 1758 *ofs = mtd->size - *len; 1759 } 1760 1761 /* 1762 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 1763 * @locked is false); 0 otherwise 1764 */ 1765 static int spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, 1766 uint64_t len, u8 sr, bool locked) 1767 { 1768 loff_t lock_offs; 1769 uint64_t lock_len; 1770 1771 if (!len) 1772 return 1; 1773 1774 spi_nor_get_locked_range_sr(nor, sr, &lock_offs, &lock_len); 1775 1776 if (locked) 1777 /* Requested range is a sub-range of locked range */ 1778 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 1779 else 1780 /* Requested range does not overlap with locked range */ 1781 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 1782 } 1783 1784 static int spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1785 u8 sr) 1786 { 1787 return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); 1788 } 1789 1790 static int spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 1791 u8 sr) 1792 { 1793 return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); 1794 } 1795 1796 /* 1797 * Lock a region of the flash. Compatible with ST Micro and similar flash. 1798 * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status 1799 * register 1800 * (SR). Does not support these features found in newer SR bitfields: 1801 * - SEC: sector/block protect - only handle SEC=0 (block protect) 1802 * - CMP: complement protect - only support CMP=0 (range is not complemented) 1803 * 1804 * Support for the following is provided conditionally for some flash: 1805 * - TB: top/bottom protect 1806 * 1807 * Sample table portion for 8MB flash (Winbond w25q64fw): 1808 * 1809 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 1810 * -------------------------------------------------------------------------- 1811 * X | X | 0 | 0 | 0 | NONE | NONE 1812 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 1813 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 1814 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 1815 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 1816 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 1817 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 1818 * X | X | 1 | 1 | 1 | 8 MB | ALL 1819 * ------|-------|-------|-------|-------|---------------|------------------- 1820 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 1821 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 1822 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 1823 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 1824 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 1825 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 1826 * 1827 * Returns negative on errors, 0 on success. 1828 */ 1829 static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1830 { 1831 struct mtd_info *mtd = &nor->mtd; 1832 u64 min_prot_len; 1833 int ret, status_old, status_new; 1834 u8 mask = spi_nor_get_sr_bp_mask(nor); 1835 u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1836 u8 pow, val; 1837 loff_t lock_len; 1838 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1839 bool use_top; 1840 1841 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1842 if (ret) 1843 return ret; 1844 1845 status_old = nor->bouncebuf[0]; 1846 1847 /* If nothing in our range is unlocked, we don't need to do anything */ 1848 if (spi_nor_is_locked_sr(nor, ofs, len, status_old)) 1849 return 0; 1850 1851 /* If anything below us is unlocked, we can't use 'bottom' protection */ 1852 if (!spi_nor_is_locked_sr(nor, 0, ofs, status_old)) 1853 can_be_bottom = false; 1854 1855 /* If anything above us is unlocked, we can't use 'top' protection */ 1856 if (!spi_nor_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 1857 status_old)) 1858 can_be_top = false; 1859 1860 if (!can_be_bottom && !can_be_top) 1861 return -EINVAL; 1862 1863 /* Prefer top, if both are valid */ 1864 use_top = can_be_top; 1865 1866 /* lock_len: length of region that should end up locked */ 1867 if (use_top) 1868 lock_len = mtd->size - ofs; 1869 else 1870 lock_len = ofs + len; 1871 1872 if (lock_len == mtd->size) { 1873 val = mask; 1874 } else { 1875 min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1876 pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; 1877 val = pow << SR_BP_SHIFT; 1878 1879 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) 1880 val = (val & ~SR_BP3) | SR_BP3_BIT6; 1881 1882 if (val & ~mask) 1883 return -EINVAL; 1884 1885 /* Don't "lock" with no region! */ 1886 if (!(val & mask)) 1887 return -EINVAL; 1888 } 1889 1890 status_new = (status_old & ~mask & ~tb_mask) | val; 1891 1892 /* Disallow further writes if WP pin is asserted */ 1893 status_new |= SR_SRWD; 1894 1895 if (!use_top) 1896 status_new |= tb_mask; 1897 1898 /* Don't bother if they're the same */ 1899 if (status_new == status_old) 1900 return 0; 1901 1902 /* Only modify protection if it will not unlock other areas */ 1903 if ((status_new & mask) < (status_old & mask)) 1904 return -EINVAL; 1905 1906 return spi_nor_write_sr_and_check(nor, status_new); 1907 } 1908 1909 /* 1910 * Unlock a region of the flash. See spi_nor_sr_lock() for more info 1911 * 1912 * Returns negative on errors, 0 on success. 1913 */ 1914 static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1915 { 1916 struct mtd_info *mtd = &nor->mtd; 1917 u64 min_prot_len; 1918 int ret, status_old, status_new; 1919 u8 mask = spi_nor_get_sr_bp_mask(nor); 1920 u8 tb_mask = spi_nor_get_sr_tb_mask(nor); 1921 u8 pow, val; 1922 loff_t lock_len; 1923 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 1924 bool use_top; 1925 1926 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1927 if (ret) 1928 return ret; 1929 1930 status_old = nor->bouncebuf[0]; 1931 1932 /* If nothing in our range is locked, we don't need to do anything */ 1933 if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old)) 1934 return 0; 1935 1936 /* If anything below us is locked, we can't use 'top' protection */ 1937 if (!spi_nor_is_unlocked_sr(nor, 0, ofs, status_old)) 1938 can_be_top = false; 1939 1940 /* If anything above us is locked, we can't use 'bottom' protection */ 1941 if (!spi_nor_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 1942 status_old)) 1943 can_be_bottom = false; 1944 1945 if (!can_be_bottom && !can_be_top) 1946 return -EINVAL; 1947 1948 /* Prefer top, if both are valid */ 1949 use_top = can_be_top; 1950 1951 /* lock_len: length of region that should remain locked */ 1952 if (use_top) 1953 lock_len = mtd->size - (ofs + len); 1954 else 1955 lock_len = ofs; 1956 1957 if (lock_len == 0) { 1958 val = 0; /* fully unlocked */ 1959 } else { 1960 min_prot_len = spi_nor_get_min_prot_length_sr(nor); 1961 pow = ilog2(lock_len) - ilog2(min_prot_len) + 1; 1962 val = pow << SR_BP_SHIFT; 1963 1964 if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3) 1965 val = (val & ~SR_BP3) | SR_BP3_BIT6; 1966 1967 /* Some power-of-two sizes are not supported */ 1968 if (val & ~mask) 1969 return -EINVAL; 1970 } 1971 1972 status_new = (status_old & ~mask & ~tb_mask) | val; 1973 1974 /* Don't protect status register if we're fully unlocked */ 1975 if (lock_len == 0) 1976 status_new &= ~SR_SRWD; 1977 1978 if (!use_top) 1979 status_new |= tb_mask; 1980 1981 /* Don't bother if they're the same */ 1982 if (status_new == status_old) 1983 return 0; 1984 1985 /* Only modify protection if it will not lock other areas */ 1986 if ((status_new & mask) > (status_old & mask)) 1987 return -EINVAL; 1988 1989 return spi_nor_write_sr_and_check(nor, status_new); 1990 } 1991 1992 /* 1993 * Check if a region of the flash is (completely) locked. See spi_nor_sr_lock() 1994 * for more info. 1995 * 1996 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 1997 * negative on errors. 1998 */ 1999 static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 2000 { 2001 int ret; 2002 2003 ret = spi_nor_read_sr(nor, nor->bouncebuf); 2004 if (ret) 2005 return ret; 2006 2007 return spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]); 2008 } 2009 2010 static const struct spi_nor_locking_ops spi_nor_sr_locking_ops = { 2011 .lock = spi_nor_sr_lock, 2012 .unlock = spi_nor_sr_unlock, 2013 .is_locked = spi_nor_sr_is_locked, 2014 }; 2015 2016 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2017 { 2018 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2019 int ret; 2020 2021 ret = spi_nor_lock_and_prep(nor); 2022 if (ret) 2023 return ret; 2024 2025 ret = nor->params->locking_ops->lock(nor, ofs, len); 2026 2027 spi_nor_unlock_and_unprep(nor); 2028 return ret; 2029 } 2030 2031 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2032 { 2033 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2034 int ret; 2035 2036 ret = spi_nor_lock_and_prep(nor); 2037 if (ret) 2038 return ret; 2039 2040 ret = nor->params->locking_ops->unlock(nor, ofs, len); 2041 2042 spi_nor_unlock_and_unprep(nor); 2043 return ret; 2044 } 2045 2046 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2047 { 2048 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2049 int ret; 2050 2051 ret = spi_nor_lock_and_prep(nor); 2052 if (ret) 2053 return ret; 2054 2055 ret = nor->params->locking_ops->is_locked(nor, ofs, len); 2056 2057 spi_nor_unlock_and_unprep(nor); 2058 return ret; 2059 } 2060 2061 /** 2062 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status 2063 * Register 1. 2064 * @nor: pointer to a 'struct spi_nor' 2065 * 2066 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. 2067 * 2068 * Return: 0 on success, -errno otherwise. 2069 */ 2070 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) 2071 { 2072 int ret; 2073 2074 ret = spi_nor_read_sr(nor, nor->bouncebuf); 2075 if (ret) 2076 return ret; 2077 2078 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) 2079 return 0; 2080 2081 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; 2082 2083 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); 2084 } 2085 2086 /** 2087 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status 2088 * Register 2. 2089 * @nor: pointer to a 'struct spi_nor'. 2090 * 2091 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. 2092 * 2093 * Return: 0 on success, -errno otherwise. 2094 */ 2095 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) 2096 { 2097 int ret; 2098 2099 if (nor->flags & SNOR_F_NO_READ_CR) 2100 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); 2101 2102 ret = spi_nor_read_cr(nor, nor->bouncebuf); 2103 if (ret) 2104 return ret; 2105 2106 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) 2107 return 0; 2108 2109 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; 2110 2111 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); 2112 } 2113 2114 /** 2115 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. 2116 * @nor: pointer to a 'struct spi_nor' 2117 * 2118 * Set the Quad Enable (QE) bit in the Status Register 2. 2119 * 2120 * This is one of the procedures to set the QE bit described in the SFDP 2121 * (JESD216 rev B) specification but no manufacturer using this procedure has 2122 * been identified yet, hence the name of the function. 2123 * 2124 * Return: 0 on success, -errno otherwise. 2125 */ 2126 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 2127 { 2128 u8 *sr2 = nor->bouncebuf; 2129 int ret; 2130 u8 sr2_written; 2131 2132 /* Check current Quad Enable bit value. */ 2133 ret = spi_nor_read_sr2(nor, sr2); 2134 if (ret) 2135 return ret; 2136 if (*sr2 & SR2_QUAD_EN_BIT7) 2137 return 0; 2138 2139 /* Update the Quad Enable bit. */ 2140 *sr2 |= SR2_QUAD_EN_BIT7; 2141 2142 ret = spi_nor_write_sr2(nor, sr2); 2143 if (ret) 2144 return ret; 2145 2146 sr2_written = *sr2; 2147 2148 /* Read back and check it. */ 2149 ret = spi_nor_read_sr2(nor, sr2); 2150 if (ret) 2151 return ret; 2152 2153 if (*sr2 != sr2_written) { 2154 dev_dbg(nor->dev, "SR2: Read back test failed\n"); 2155 return -EIO; 2156 } 2157 2158 return 0; 2159 } 2160 2161 static const struct spi_nor_manufacturer *manufacturers[] = { 2162 &spi_nor_atmel, 2163 &spi_nor_catalyst, 2164 &spi_nor_eon, 2165 &spi_nor_esmt, 2166 &spi_nor_everspin, 2167 &spi_nor_fujitsu, 2168 &spi_nor_gigadevice, 2169 &spi_nor_intel, 2170 &spi_nor_issi, 2171 &spi_nor_macronix, 2172 &spi_nor_micron, 2173 &spi_nor_st, 2174 &spi_nor_spansion, 2175 &spi_nor_sst, 2176 &spi_nor_winbond, 2177 &spi_nor_xilinx, 2178 &spi_nor_xmc, 2179 }; 2180 2181 static const struct flash_info * 2182 spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int nparts, 2183 const u8 *id) 2184 { 2185 unsigned int i; 2186 2187 for (i = 0; i < nparts; i++) { 2188 if (parts[i].id_len && 2189 !memcmp(parts[i].id, id, parts[i].id_len)) 2190 return &parts[i]; 2191 } 2192 2193 return NULL; 2194 } 2195 2196 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 2197 { 2198 const struct flash_info *info; 2199 u8 *id = nor->bouncebuf; 2200 unsigned int i; 2201 int ret; 2202 2203 if (nor->spimem) { 2204 struct spi_mem_op op = 2205 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), 2206 SPI_MEM_OP_NO_ADDR, 2207 SPI_MEM_OP_NO_DUMMY, 2208 SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); 2209 2210 ret = spi_mem_exec_op(nor->spimem, &op); 2211 } else { 2212 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, 2213 SPI_NOR_MAX_ID_LEN); 2214 } 2215 if (ret) { 2216 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); 2217 return ERR_PTR(ret); 2218 } 2219 2220 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 2221 info = spi_nor_search_part_by_id(manufacturers[i]->parts, 2222 manufacturers[i]->nparts, 2223 id); 2224 if (info) { 2225 nor->manufacturer = manufacturers[i]; 2226 return info; 2227 } 2228 } 2229 2230 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", 2231 SPI_NOR_MAX_ID_LEN, id); 2232 return ERR_PTR(-ENODEV); 2233 } 2234 2235 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 2236 size_t *retlen, u_char *buf) 2237 { 2238 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2239 ssize_t ret; 2240 2241 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 2242 2243 ret = spi_nor_lock_and_prep(nor); 2244 if (ret) 2245 return ret; 2246 2247 while (len) { 2248 loff_t addr = from; 2249 2250 addr = spi_nor_convert_addr(nor, addr); 2251 2252 ret = spi_nor_read_data(nor, addr, len, buf); 2253 if (ret == 0) { 2254 /* We shouldn't see 0-length reads */ 2255 ret = -EIO; 2256 goto read_err; 2257 } 2258 if (ret < 0) 2259 goto read_err; 2260 2261 WARN_ON(ret > len); 2262 *retlen += ret; 2263 buf += ret; 2264 from += ret; 2265 len -= ret; 2266 } 2267 ret = 0; 2268 2269 read_err: 2270 spi_nor_unlock_and_unprep(nor); 2271 return ret; 2272 } 2273 2274 /* 2275 * Write an address range to the nor chip. Data must be written in 2276 * FLASH_PAGESIZE chunks. The address range may be any size provided 2277 * it is within the physical boundaries. 2278 */ 2279 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 2280 size_t *retlen, const u_char *buf) 2281 { 2282 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2283 size_t page_offset, page_remain, i; 2284 ssize_t ret; 2285 2286 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 2287 2288 ret = spi_nor_lock_and_prep(nor); 2289 if (ret) 2290 return ret; 2291 2292 for (i = 0; i < len; ) { 2293 ssize_t written; 2294 loff_t addr = to + i; 2295 2296 /* 2297 * If page_size is a power of two, the offset can be quickly 2298 * calculated with an AND operation. On the other cases we 2299 * need to do a modulus operation (more expensive). 2300 * Power of two numbers have only one bit set and we can use 2301 * the instruction hweight32 to detect if we need to do a 2302 * modulus (do_div()) or not. 2303 */ 2304 if (hweight32(nor->page_size) == 1) { 2305 page_offset = addr & (nor->page_size - 1); 2306 } else { 2307 uint64_t aux = addr; 2308 2309 page_offset = do_div(aux, nor->page_size); 2310 } 2311 /* the size of data remaining on the first page */ 2312 page_remain = min_t(size_t, 2313 nor->page_size - page_offset, len - i); 2314 2315 addr = spi_nor_convert_addr(nor, addr); 2316 2317 ret = spi_nor_write_enable(nor); 2318 if (ret) 2319 goto write_err; 2320 2321 ret = spi_nor_write_data(nor, addr, page_remain, buf + i); 2322 if (ret < 0) 2323 goto write_err; 2324 written = ret; 2325 2326 ret = spi_nor_wait_till_ready(nor); 2327 if (ret) 2328 goto write_err; 2329 *retlen += written; 2330 i += written; 2331 } 2332 2333 write_err: 2334 spi_nor_unlock_and_unprep(nor); 2335 return ret; 2336 } 2337 2338 static int spi_nor_check(struct spi_nor *nor) 2339 { 2340 if (!nor->dev || 2341 (!nor->spimem && !nor->controller_ops) || 2342 (!nor->spimem && nor->controller_ops && 2343 (!nor->controller_ops->read || 2344 !nor->controller_ops->write || 2345 !nor->controller_ops->read_reg || 2346 !nor->controller_ops->write_reg))) { 2347 pr_err("spi-nor: please fill all the necessary fields!\n"); 2348 return -EINVAL; 2349 } 2350 2351 if (nor->spimem && nor->controller_ops) { 2352 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n"); 2353 return -EINVAL; 2354 } 2355 2356 return 0; 2357 } 2358 2359 void 2360 spi_nor_set_read_settings(struct spi_nor_read_command *read, 2361 u8 num_mode_clocks, 2362 u8 num_wait_states, 2363 u8 opcode, 2364 enum spi_nor_protocol proto) 2365 { 2366 read->num_mode_clocks = num_mode_clocks; 2367 read->num_wait_states = num_wait_states; 2368 read->opcode = opcode; 2369 read->proto = proto; 2370 } 2371 2372 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 2373 enum spi_nor_protocol proto) 2374 { 2375 pp->opcode = opcode; 2376 pp->proto = proto; 2377 } 2378 2379 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2380 { 2381 size_t i; 2382 2383 for (i = 0; i < size; i++) 2384 if (table[i][0] == (int)hwcaps) 2385 return table[i][1]; 2386 2387 return -EINVAL; 2388 } 2389 2390 int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2391 { 2392 static const int hwcaps_read2cmd[][2] = { 2393 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2394 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2395 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2396 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2397 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2398 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2399 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2400 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2401 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2402 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2403 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2404 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2405 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2406 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2407 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2408 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR }, 2409 }; 2410 2411 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2412 ARRAY_SIZE(hwcaps_read2cmd)); 2413 } 2414 2415 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2416 { 2417 static const int hwcaps_pp2cmd[][2] = { 2418 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2419 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2420 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2421 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2422 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2423 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2424 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2425 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR }, 2426 }; 2427 2428 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2429 ARRAY_SIZE(hwcaps_pp2cmd)); 2430 } 2431 2432 /** 2433 * spi_nor_spimem_check_op - check if the operation is supported 2434 * by controller 2435 *@nor: pointer to a 'struct spi_nor' 2436 *@op: pointer to op template to be checked 2437 * 2438 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2439 */ 2440 static int spi_nor_spimem_check_op(struct spi_nor *nor, 2441 struct spi_mem_op *op) 2442 { 2443 /* 2444 * First test with 4 address bytes. The opcode itself might 2445 * be a 3B addressing opcode but we don't care, because 2446 * SPI controller implementation should not check the opcode, 2447 * but just the sequence. 2448 */ 2449 op->addr.nbytes = 4; 2450 if (!spi_mem_supports_op(nor->spimem, op)) { 2451 if (nor->mtd.size > SZ_16M) 2452 return -EOPNOTSUPP; 2453 2454 /* If flash size <= 16MB, 3 address bytes are sufficient */ 2455 op->addr.nbytes = 3; 2456 if (!spi_mem_supports_op(nor->spimem, op)) 2457 return -EOPNOTSUPP; 2458 } 2459 2460 return 0; 2461 } 2462 2463 /** 2464 * spi_nor_spimem_check_readop - check if the read op is supported 2465 * by controller 2466 *@nor: pointer to a 'struct spi_nor' 2467 *@read: pointer to op template to be checked 2468 * 2469 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2470 */ 2471 static int spi_nor_spimem_check_readop(struct spi_nor *nor, 2472 const struct spi_nor_read_command *read) 2473 { 2474 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), 2475 SPI_MEM_OP_ADDR(3, 0, 0), 2476 SPI_MEM_OP_DUMMY(1, 0), 2477 SPI_MEM_OP_DATA_IN(1, NULL, 0)); 2478 2479 spi_nor_spimem_setup_op(nor, &op, read->proto); 2480 2481 /* convert the dummy cycles to the number of bytes */ 2482 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 2483 if (spi_nor_protocol_is_dtr(nor->read_proto)) 2484 op.dummy.nbytes *= 2; 2485 2486 return spi_nor_spimem_check_op(nor, &op); 2487 } 2488 2489 /** 2490 * spi_nor_spimem_check_pp - check if the page program op is supported 2491 * by controller 2492 *@nor: pointer to a 'struct spi_nor' 2493 *@pp: pointer to op template to be checked 2494 * 2495 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2496 */ 2497 static int spi_nor_spimem_check_pp(struct spi_nor *nor, 2498 const struct spi_nor_pp_command *pp) 2499 { 2500 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0), 2501 SPI_MEM_OP_ADDR(3, 0, 0), 2502 SPI_MEM_OP_NO_DUMMY, 2503 SPI_MEM_OP_DATA_OUT(1, NULL, 0)); 2504 2505 spi_nor_spimem_setup_op(nor, &op, pp->proto); 2506 2507 return spi_nor_spimem_check_op(nor, &op); 2508 } 2509 2510 /** 2511 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol 2512 * based on SPI controller capabilities 2513 * @nor: pointer to a 'struct spi_nor' 2514 * @hwcaps: pointer to resulting capabilities after adjusting 2515 * according to controller and flash's capability 2516 */ 2517 static void 2518 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) 2519 { 2520 struct spi_nor_flash_parameter *params = nor->params; 2521 unsigned int cap; 2522 2523 /* X-X-X modes are not supported yet, mask them all. */ 2524 *hwcaps &= ~SNOR_HWCAPS_X_X_X; 2525 2526 /* 2527 * If the reset line is broken, we do not want to enter a stateful 2528 * mode. 2529 */ 2530 if (nor->flags & SNOR_F_BROKEN_RESET) 2531 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR); 2532 2533 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { 2534 int rdidx, ppidx; 2535 2536 if (!(*hwcaps & BIT(cap))) 2537 continue; 2538 2539 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); 2540 if (rdidx >= 0 && 2541 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx])) 2542 *hwcaps &= ~BIT(cap); 2543 2544 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); 2545 if (ppidx < 0) 2546 continue; 2547 2548 if (spi_nor_spimem_check_pp(nor, 2549 ¶ms->page_programs[ppidx])) 2550 *hwcaps &= ~BIT(cap); 2551 } 2552 } 2553 2554 /** 2555 * spi_nor_set_erase_type() - set a SPI NOR erase type 2556 * @erase: pointer to a structure that describes a SPI NOR erase type 2557 * @size: the size of the sector/block erased by the erase type 2558 * @opcode: the SPI command op code to erase the sector/block 2559 */ 2560 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 2561 u8 opcode) 2562 { 2563 erase->size = size; 2564 erase->opcode = opcode; 2565 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 2566 erase->size_shift = ffs(erase->size) - 1; 2567 erase->size_mask = (1 << erase->size_shift) - 1; 2568 } 2569 2570 /** 2571 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map 2572 * @map: the erase map of the SPI NOR 2573 * @erase_mask: bitmask encoding erase types that can erase the entire 2574 * flash memory 2575 * @flash_size: the spi nor flash memory size 2576 */ 2577 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 2578 u8 erase_mask, u64 flash_size) 2579 { 2580 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */ 2581 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) | 2582 SNOR_LAST_REGION; 2583 map->uniform_region.size = flash_size; 2584 map->regions = &map->uniform_region; 2585 map->uniform_erase_type = erase_mask; 2586 } 2587 2588 int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 2589 const struct sfdp_parameter_header *bfpt_header, 2590 const struct sfdp_bfpt *bfpt, 2591 struct spi_nor_flash_parameter *params) 2592 { 2593 int ret; 2594 2595 if (nor->manufacturer && nor->manufacturer->fixups && 2596 nor->manufacturer->fixups->post_bfpt) { 2597 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header, 2598 bfpt, params); 2599 if (ret) 2600 return ret; 2601 } 2602 2603 if (nor->info->fixups && nor->info->fixups->post_bfpt) 2604 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt, 2605 params); 2606 2607 return 0; 2608 } 2609 2610 static int spi_nor_select_read(struct spi_nor *nor, 2611 u32 shared_hwcaps) 2612 { 2613 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2614 const struct spi_nor_read_command *read; 2615 2616 if (best_match < 0) 2617 return -EINVAL; 2618 2619 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2620 if (cmd < 0) 2621 return -EINVAL; 2622 2623 read = &nor->params->reads[cmd]; 2624 nor->read_opcode = read->opcode; 2625 nor->read_proto = read->proto; 2626 2627 /* 2628 * In the SPI NOR framework, we don't need to make the difference 2629 * between mode clock cycles and wait state clock cycles. 2630 * Indeed, the value of the mode clock cycles is used by a QSPI 2631 * flash memory to know whether it should enter or leave its 0-4-4 2632 * (Continuous Read / XIP) mode. 2633 * eXecution In Place is out of the scope of the mtd sub-system. 2634 * Hence we choose to merge both mode and wait state clock cycles 2635 * into the so called dummy clock cycles. 2636 */ 2637 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2638 return 0; 2639 } 2640 2641 static int spi_nor_select_pp(struct spi_nor *nor, 2642 u32 shared_hwcaps) 2643 { 2644 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2645 const struct spi_nor_pp_command *pp; 2646 2647 if (best_match < 0) 2648 return -EINVAL; 2649 2650 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2651 if (cmd < 0) 2652 return -EINVAL; 2653 2654 pp = &nor->params->page_programs[cmd]; 2655 nor->program_opcode = pp->opcode; 2656 nor->write_proto = pp->proto; 2657 return 0; 2658 } 2659 2660 /** 2661 * spi_nor_select_uniform_erase() - select optimum uniform erase type 2662 * @map: the erase map of the SPI NOR 2663 * @wanted_size: the erase type size to search for. Contains the value of 2664 * info->sector_size or of the "small sector" size in case 2665 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined. 2666 * 2667 * Once the optimum uniform sector erase command is found, disable all the 2668 * other. 2669 * 2670 * Return: pointer to erase type on success, NULL otherwise. 2671 */ 2672 static const struct spi_nor_erase_type * 2673 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map, 2674 const u32 wanted_size) 2675 { 2676 const struct spi_nor_erase_type *tested_erase, *erase = NULL; 2677 int i; 2678 u8 uniform_erase_type = map->uniform_erase_type; 2679 2680 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2681 if (!(uniform_erase_type & BIT(i))) 2682 continue; 2683 2684 tested_erase = &map->erase_type[i]; 2685 2686 /* 2687 * If the current erase size is the one, stop here: 2688 * we have found the right uniform Sector Erase command. 2689 */ 2690 if (tested_erase->size == wanted_size) { 2691 erase = tested_erase; 2692 break; 2693 } 2694 2695 /* 2696 * Otherwise, the current erase size is still a valid candidate. 2697 * Select the biggest valid candidate. 2698 */ 2699 if (!erase && tested_erase->size) 2700 erase = tested_erase; 2701 /* keep iterating to find the wanted_size */ 2702 } 2703 2704 if (!erase) 2705 return NULL; 2706 2707 /* Disable all other Sector Erase commands. */ 2708 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK; 2709 map->uniform_erase_type |= BIT(erase - map->erase_type); 2710 return erase; 2711 } 2712 2713 static int spi_nor_select_erase(struct spi_nor *nor) 2714 { 2715 struct spi_nor_erase_map *map = &nor->params->erase_map; 2716 const struct spi_nor_erase_type *erase = NULL; 2717 struct mtd_info *mtd = &nor->mtd; 2718 u32 wanted_size = nor->info->sector_size; 2719 int i; 2720 2721 /* 2722 * The previous implementation handling Sector Erase commands assumed 2723 * that the SPI flash memory has an uniform layout then used only one 2724 * of the supported erase sizes for all Sector Erase commands. 2725 * So to be backward compatible, the new implementation also tries to 2726 * manage the SPI flash memory as uniform with a single erase sector 2727 * size, when possible. 2728 */ 2729 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 2730 /* prefer "small sector" erase if possible */ 2731 wanted_size = 4096u; 2732 #endif 2733 2734 if (spi_nor_has_uniform_erase(nor)) { 2735 erase = spi_nor_select_uniform_erase(map, wanted_size); 2736 if (!erase) 2737 return -EINVAL; 2738 nor->erase_opcode = erase->opcode; 2739 mtd->erasesize = erase->size; 2740 return 0; 2741 } 2742 2743 /* 2744 * For non-uniform SPI flash memory, set mtd->erasesize to the 2745 * maximum erase sector size. No need to set nor->erase_opcode. 2746 */ 2747 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2748 if (map->erase_type[i].size) { 2749 erase = &map->erase_type[i]; 2750 break; 2751 } 2752 } 2753 2754 if (!erase) 2755 return -EINVAL; 2756 2757 mtd->erasesize = erase->size; 2758 return 0; 2759 } 2760 2761 static int spi_nor_default_setup(struct spi_nor *nor, 2762 const struct spi_nor_hwcaps *hwcaps) 2763 { 2764 struct spi_nor_flash_parameter *params = nor->params; 2765 u32 ignored_mask, shared_mask; 2766 int err; 2767 2768 /* 2769 * Keep only the hardware capabilities supported by both the SPI 2770 * controller and the SPI flash memory. 2771 */ 2772 shared_mask = hwcaps->mask & params->hwcaps.mask; 2773 2774 if (nor->spimem) { 2775 /* 2776 * When called from spi_nor_probe(), all caps are set and we 2777 * need to discard some of them based on what the SPI 2778 * controller actually supports (using spi_mem_supports_op()). 2779 */ 2780 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask); 2781 } else { 2782 /* 2783 * SPI n-n-n protocols are not supported when the SPI 2784 * controller directly implements the spi_nor interface. 2785 * Yet another reason to switch to spi-mem. 2786 */ 2787 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR; 2788 if (shared_mask & ignored_mask) { 2789 dev_dbg(nor->dev, 2790 "SPI n-n-n protocols are not supported.\n"); 2791 shared_mask &= ~ignored_mask; 2792 } 2793 } 2794 2795 /* Select the (Fast) Read command. */ 2796 err = spi_nor_select_read(nor, shared_mask); 2797 if (err) { 2798 dev_dbg(nor->dev, 2799 "can't select read settings supported by both the SPI controller and memory.\n"); 2800 return err; 2801 } 2802 2803 /* Select the Page Program command. */ 2804 err = spi_nor_select_pp(nor, shared_mask); 2805 if (err) { 2806 dev_dbg(nor->dev, 2807 "can't select write settings supported by both the SPI controller and memory.\n"); 2808 return err; 2809 } 2810 2811 /* Select the Sector Erase command. */ 2812 err = spi_nor_select_erase(nor); 2813 if (err) { 2814 dev_dbg(nor->dev, 2815 "can't select erase settings supported by both the SPI controller and memory.\n"); 2816 return err; 2817 } 2818 2819 return 0; 2820 } 2821 2822 static int spi_nor_setup(struct spi_nor *nor, 2823 const struct spi_nor_hwcaps *hwcaps) 2824 { 2825 if (!nor->params->setup) 2826 return 0; 2827 2828 return nor->params->setup(nor, hwcaps); 2829 } 2830 2831 /** 2832 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and 2833 * settings based on MFR register and ->default_init() hook. 2834 * @nor: pointer to a 'struct spi_nor'. 2835 */ 2836 static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 2837 { 2838 if (nor->manufacturer && nor->manufacturer->fixups && 2839 nor->manufacturer->fixups->default_init) 2840 nor->manufacturer->fixups->default_init(nor); 2841 2842 if (nor->info->fixups && nor->info->fixups->default_init) 2843 nor->info->fixups->default_init(nor); 2844 } 2845 2846 /** 2847 * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings 2848 * based on JESD216 SFDP standard. 2849 * @nor: pointer to a 'struct spi_nor'. 2850 * 2851 * The method has a roll-back mechanism: in case the SFDP parsing fails, the 2852 * legacy flash parameters and settings will be restored. 2853 */ 2854 static void spi_nor_sfdp_init_params(struct spi_nor *nor) 2855 { 2856 struct spi_nor_flash_parameter sfdp_params; 2857 2858 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params)); 2859 2860 if (spi_nor_parse_sfdp(nor, nor->params)) { 2861 memcpy(nor->params, &sfdp_params, sizeof(*nor->params)); 2862 nor->addr_width = 0; 2863 nor->flags &= ~SNOR_F_4B_OPCODES; 2864 } 2865 } 2866 2867 /** 2868 * spi_nor_info_init_params() - Initialize the flash's parameters and settings 2869 * based on nor->info data. 2870 * @nor: pointer to a 'struct spi_nor'. 2871 */ 2872 static void spi_nor_info_init_params(struct spi_nor *nor) 2873 { 2874 struct spi_nor_flash_parameter *params = nor->params; 2875 struct spi_nor_erase_map *map = ¶ms->erase_map; 2876 const struct flash_info *info = nor->info; 2877 struct device_node *np = spi_nor_get_flash_node(nor); 2878 u8 i, erase_mask; 2879 2880 /* Initialize legacy flash parameters and settings. */ 2881 params->quad_enable = spi_nor_sr2_bit1_quad_enable; 2882 params->set_4byte_addr_mode = spansion_set_4byte_addr_mode; 2883 params->setup = spi_nor_default_setup; 2884 /* Default to 16-bit Write Status (01h) Command */ 2885 nor->flags |= SNOR_F_HAS_16BIT_SR; 2886 2887 /* Set SPI NOR sizes. */ 2888 params->writesize = 1; 2889 params->size = (u64)info->sector_size * info->n_sectors; 2890 params->page_size = info->page_size; 2891 2892 if (!(info->flags & SPI_NOR_NO_FR)) { 2893 /* Default to Fast Read for DT and non-DT platform devices. */ 2894 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2895 2896 /* Mask out Fast Read if not requested at DT instantiation. */ 2897 if (np && !of_property_read_bool(np, "m25p,fast-read")) 2898 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2899 } 2900 2901 /* (Fast) Read settings. */ 2902 params->hwcaps.mask |= SNOR_HWCAPS_READ; 2903 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 2904 0, 0, SPINOR_OP_READ, 2905 SNOR_PROTO_1_1_1); 2906 2907 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) 2908 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 2909 0, 8, SPINOR_OP_READ_FAST, 2910 SNOR_PROTO_1_1_1); 2911 2912 if (info->flags & SPI_NOR_DUAL_READ) { 2913 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2914 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2915 0, 8, SPINOR_OP_READ_1_1_2, 2916 SNOR_PROTO_1_1_2); 2917 } 2918 2919 if (info->flags & SPI_NOR_QUAD_READ) { 2920 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2921 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2922 0, 8, SPINOR_OP_READ_1_1_4, 2923 SNOR_PROTO_1_1_4); 2924 } 2925 2926 if (info->flags & SPI_NOR_OCTAL_READ) { 2927 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; 2928 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], 2929 0, 8, SPINOR_OP_READ_1_1_8, 2930 SNOR_PROTO_1_1_8); 2931 } 2932 2933 if (info->flags & SPI_NOR_OCTAL_DTR_READ) { 2934 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; 2935 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], 2936 0, 20, SPINOR_OP_READ_FAST, 2937 SNOR_PROTO_8_8_8_DTR); 2938 } 2939 2940 /* Page Program settings. */ 2941 params->hwcaps.mask |= SNOR_HWCAPS_PP; 2942 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 2943 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 2944 2945 if (info->flags & SPI_NOR_OCTAL_DTR_PP) { 2946 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; 2947 /* 2948 * Since xSPI Page Program opcode is backward compatible with 2949 * Legacy SPI, use Legacy SPI opcode there as well. 2950 */ 2951 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], 2952 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); 2953 } 2954 2955 /* 2956 * Sector Erase settings. Sort Erase Types in ascending order, with the 2957 * smallest erase size starting at BIT(0). 2958 */ 2959 erase_mask = 0; 2960 i = 0; 2961 if (info->flags & SECT_4K_PMC) { 2962 erase_mask |= BIT(i); 2963 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2964 SPINOR_OP_BE_4K_PMC); 2965 i++; 2966 } else if (info->flags & SECT_4K) { 2967 erase_mask |= BIT(i); 2968 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2969 SPINOR_OP_BE_4K); 2970 i++; 2971 } 2972 erase_mask |= BIT(i); 2973 spi_nor_set_erase_type(&map->erase_type[i], info->sector_size, 2974 SPINOR_OP_SE); 2975 spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 2976 } 2977 2978 /** 2979 * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings 2980 * after SFDP has been parsed (is also called for SPI NORs that do not 2981 * support RDSFDP). 2982 * @nor: pointer to a 'struct spi_nor' 2983 * 2984 * Typically used to tweak various parameters that could not be extracted by 2985 * other means (i.e. when information provided by the SFDP/flash_info tables 2986 * are incomplete or wrong). 2987 */ 2988 static void spi_nor_post_sfdp_fixups(struct spi_nor *nor) 2989 { 2990 if (nor->manufacturer && nor->manufacturer->fixups && 2991 nor->manufacturer->fixups->post_sfdp) 2992 nor->manufacturer->fixups->post_sfdp(nor); 2993 2994 if (nor->info->fixups && nor->info->fixups->post_sfdp) 2995 nor->info->fixups->post_sfdp(nor); 2996 } 2997 2998 /** 2999 * spi_nor_late_init_params() - Late initialization of default flash parameters. 3000 * @nor: pointer to a 'struct spi_nor' 3001 * 3002 * Used to set default flash parameters and settings when the ->default_init() 3003 * hook or the SFDP parser let voids. 3004 */ 3005 static void spi_nor_late_init_params(struct spi_nor *nor) 3006 { 3007 /* 3008 * NOR protection support. When locking_ops are not provided, we pick 3009 * the default ones. 3010 */ 3011 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) 3012 nor->params->locking_ops = &spi_nor_sr_locking_ops; 3013 } 3014 3015 /** 3016 * spi_nor_init_params() - Initialize the flash's parameters and settings. 3017 * @nor: pointer to a 'struct spi_nor'. 3018 * 3019 * The flash parameters and settings are initialized based on a sequence of 3020 * calls that are ordered by priority: 3021 * 3022 * 1/ Default flash parameters initialization. The initializations are done 3023 * based on nor->info data: 3024 * spi_nor_info_init_params() 3025 * 3026 * which can be overwritten by: 3027 * 2/ Manufacturer flash parameters initialization. The initializations are 3028 * done based on MFR register, or when the decisions can not be done solely 3029 * based on MFR, by using specific flash_info tweeks, ->default_init(): 3030 * spi_nor_manufacturer_init_params() 3031 * 3032 * which can be overwritten by: 3033 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and 3034 * should be more accurate that the above. 3035 * spi_nor_sfdp_init_params() 3036 * 3037 * Please note that there is a ->post_bfpt() fixup hook that can overwrite 3038 * the flash parameters and settings immediately after parsing the Basic 3039 * Flash Parameter Table. 3040 * 3041 * which can be overwritten by: 3042 * 4/ Post SFDP flash parameters initialization. Used to tweak various 3043 * parameters that could not be extracted by other means (i.e. when 3044 * information provided by the SFDP/flash_info tables are incomplete or 3045 * wrong). 3046 * spi_nor_post_sfdp_fixups() 3047 * 3048 * 5/ Late default flash parameters initialization, used when the 3049 * ->default_init() hook or the SFDP parser do not set specific params. 3050 * spi_nor_late_init_params() 3051 */ 3052 static int spi_nor_init_params(struct spi_nor *nor) 3053 { 3054 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); 3055 if (!nor->params) 3056 return -ENOMEM; 3057 3058 spi_nor_info_init_params(nor); 3059 3060 spi_nor_manufacturer_init_params(nor); 3061 3062 if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 3063 SPI_NOR_OCTAL_READ | SPI_NOR_OCTAL_DTR_READ)) && 3064 !(nor->info->flags & SPI_NOR_SKIP_SFDP)) 3065 spi_nor_sfdp_init_params(nor); 3066 3067 spi_nor_post_sfdp_fixups(nor); 3068 3069 spi_nor_late_init_params(nor); 3070 3071 return 0; 3072 } 3073 3074 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed 3075 * @nor: pointer to a 'struct spi_nor' 3076 * @enable: whether to enable or disable Octal DTR 3077 * 3078 * Return: 0 on success, -errno otherwise. 3079 */ 3080 static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 3081 { 3082 int ret; 3083 3084 if (!nor->params->octal_dtr_enable) 3085 return 0; 3086 3087 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && 3088 nor->write_proto == SNOR_PROTO_8_8_8_DTR)) 3089 return 0; 3090 3091 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) 3092 return 0; 3093 3094 ret = nor->params->octal_dtr_enable(nor, enable); 3095 if (ret) 3096 return ret; 3097 3098 if (enable) 3099 nor->reg_proto = SNOR_PROTO_8_8_8_DTR; 3100 else 3101 nor->reg_proto = SNOR_PROTO_1_1_1; 3102 3103 return 0; 3104 } 3105 3106 /** 3107 * spi_nor_quad_enable() - enable Quad I/O if needed. 3108 * @nor: pointer to a 'struct spi_nor' 3109 * 3110 * Return: 0 on success, -errno otherwise. 3111 */ 3112 static int spi_nor_quad_enable(struct spi_nor *nor) 3113 { 3114 if (!nor->params->quad_enable) 3115 return 0; 3116 3117 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || 3118 spi_nor_get_protocol_width(nor->write_proto) == 4)) 3119 return 0; 3120 3121 return nor->params->quad_enable(nor); 3122 } 3123 3124 /** 3125 * spi_nor_try_unlock_all() - Tries to unlock the entire flash memory array. 3126 * @nor: pointer to a 'struct spi_nor'. 3127 * 3128 * Some SPI NOR flashes are write protected by default after a power-on reset 3129 * cycle, in order to avoid inadvertent writes during power-up. Backward 3130 * compatibility imposes to unlock the entire flash memory array at power-up 3131 * by default. 3132 * 3133 * Unprotecting the entire flash array will fail for boards which are hardware 3134 * write-protected. Thus any errors are ignored. 3135 */ 3136 static void spi_nor_try_unlock_all(struct spi_nor *nor) 3137 { 3138 int ret; 3139 3140 if (!(nor->flags & SNOR_F_HAS_LOCK)) 3141 return; 3142 3143 dev_dbg(nor->dev, "Unprotecting entire flash array\n"); 3144 3145 ret = spi_nor_unlock(&nor->mtd, 0, nor->params->size); 3146 if (ret) 3147 dev_dbg(nor->dev, "Failed to unlock the entire flash memory array\n"); 3148 } 3149 3150 static int spi_nor_init(struct spi_nor *nor) 3151 { 3152 int err; 3153 3154 err = spi_nor_octal_dtr_enable(nor, true); 3155 if (err) { 3156 dev_dbg(nor->dev, "octal mode not supported\n"); 3157 return err; 3158 } 3159 3160 err = spi_nor_quad_enable(nor); 3161 if (err) { 3162 dev_dbg(nor->dev, "quad mode not supported\n"); 3163 return err; 3164 } 3165 3166 /* 3167 * Some SPI NOR flashes are write protected by default after a power-on 3168 * reset cycle, in order to avoid inadvertent writes during power-up. 3169 * Backward compatibility imposes to unlock the entire flash memory 3170 * array at power-up by default. Depending on the kernel configuration 3171 * (1) do nothing, (2) always unlock the entire flash array or (3) 3172 * unlock the entire flash array only when the software write 3173 * protection bits are volatile. The latter is indicated by 3174 * SNOR_F_SWP_IS_VOLATILE. 3175 */ 3176 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) || 3177 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) && 3178 nor->flags & SNOR_F_SWP_IS_VOLATILE)) 3179 spi_nor_try_unlock_all(nor); 3180 3181 if (nor->addr_width == 4 && 3182 nor->read_proto != SNOR_PROTO_8_8_8_DTR && 3183 !(nor->flags & SNOR_F_4B_OPCODES)) { 3184 /* 3185 * If the RESET# pin isn't hooked up properly, or the system 3186 * otherwise doesn't perform a reset command in the boot 3187 * sequence, it's impossible to 100% protect against unexpected 3188 * reboots (e.g., crashes). Warn the user (or hopefully, system 3189 * designer) that this is bad. 3190 */ 3191 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, 3192 "enabling reset hack; may not recover from unexpected reboots\n"); 3193 nor->params->set_4byte_addr_mode(nor, true); 3194 } 3195 3196 return 0; 3197 } 3198 3199 static void spi_nor_soft_reset(struct spi_nor *nor) 3200 { 3201 struct spi_mem_op op; 3202 int ret; 3203 3204 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), 3205 SPI_MEM_OP_NO_DUMMY, 3206 SPI_MEM_OP_NO_ADDR, 3207 SPI_MEM_OP_NO_DATA); 3208 3209 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3210 3211 ret = spi_mem_exec_op(nor->spimem, &op); 3212 if (ret) { 3213 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3214 return; 3215 } 3216 3217 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), 3218 SPI_MEM_OP_NO_DUMMY, 3219 SPI_MEM_OP_NO_ADDR, 3220 SPI_MEM_OP_NO_DATA); 3221 3222 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3223 3224 ret = spi_mem_exec_op(nor->spimem, &op); 3225 if (ret) { 3226 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3227 return; 3228 } 3229 3230 /* 3231 * Software Reset is not instant, and the delay varies from flash to 3232 * flash. Looking at a few flashes, most range somewhere below 100 3233 * microseconds. So, sleep for a range of 200-400 us. 3234 */ 3235 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX); 3236 } 3237 3238 /* mtd suspend handler */ 3239 static int spi_nor_suspend(struct mtd_info *mtd) 3240 { 3241 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3242 int ret; 3243 3244 /* Disable octal DTR mode if we enabled it. */ 3245 ret = spi_nor_octal_dtr_enable(nor, false); 3246 if (ret) 3247 dev_err(nor->dev, "suspend() failed\n"); 3248 3249 return ret; 3250 } 3251 3252 /* mtd resume handler */ 3253 static void spi_nor_resume(struct mtd_info *mtd) 3254 { 3255 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3256 struct device *dev = nor->dev; 3257 int ret; 3258 3259 /* re-initialize the nor chip */ 3260 ret = spi_nor_init(nor); 3261 if (ret) 3262 dev_err(dev, "resume() failed\n"); 3263 } 3264 3265 void spi_nor_restore(struct spi_nor *nor) 3266 { 3267 /* restore the addressing mode */ 3268 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && 3269 nor->flags & SNOR_F_BROKEN_RESET) 3270 nor->params->set_4byte_addr_mode(nor, false); 3271 3272 if (nor->flags & SNOR_F_SOFT_RESET) 3273 spi_nor_soft_reset(nor); 3274 } 3275 EXPORT_SYMBOL_GPL(spi_nor_restore); 3276 3277 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, 3278 const char *name) 3279 { 3280 unsigned int i, j; 3281 3282 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 3283 for (j = 0; j < manufacturers[i]->nparts; j++) { 3284 if (!strcmp(name, manufacturers[i]->parts[j].name)) { 3285 nor->manufacturer = manufacturers[i]; 3286 return &manufacturers[i]->parts[j]; 3287 } 3288 } 3289 } 3290 3291 return NULL; 3292 } 3293 3294 static int spi_nor_set_addr_width(struct spi_nor *nor) 3295 { 3296 if (nor->addr_width) { 3297 /* already configured from SFDP */ 3298 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { 3299 /* 3300 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So 3301 * in this protocol an odd address width cannot be used because 3302 * then the address phase would only span a cycle and a half. 3303 * Half a cycle would be left over. We would then have to start 3304 * the dummy phase in the middle of a cycle and so too the data 3305 * phase, and we will end the transaction with half a cycle left 3306 * over. 3307 * 3308 * Force all 8D-8D-8D flashes to use an address width of 4 to 3309 * avoid this situation. 3310 */ 3311 nor->addr_width = 4; 3312 } else if (nor->info->addr_width) { 3313 nor->addr_width = nor->info->addr_width; 3314 } else { 3315 nor->addr_width = 3; 3316 } 3317 3318 if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) { 3319 /* enable 4-byte addressing if the device exceeds 16MiB */ 3320 nor->addr_width = 4; 3321 } 3322 3323 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 3324 dev_dbg(nor->dev, "address width is too large: %u\n", 3325 nor->addr_width); 3326 return -EINVAL; 3327 } 3328 3329 /* Set 4byte opcodes when possible. */ 3330 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES && 3331 !(nor->flags & SNOR_F_HAS_4BAIT)) 3332 spi_nor_set_4byte_opcodes(nor); 3333 3334 return 0; 3335 } 3336 3337 static void spi_nor_debugfs_init(struct spi_nor *nor, 3338 const struct flash_info *info) 3339 { 3340 struct mtd_info *mtd = &nor->mtd; 3341 3342 mtd->dbg.partname = info->name; 3343 mtd->dbg.partid = devm_kasprintf(nor->dev, GFP_KERNEL, "spi-nor:%*phN", 3344 info->id_len, info->id); 3345 } 3346 3347 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, 3348 const char *name) 3349 { 3350 const struct flash_info *info = NULL; 3351 3352 if (name) 3353 info = spi_nor_match_id(nor, name); 3354 /* Try to auto-detect if chip name wasn't specified or not found */ 3355 if (!info) 3356 info = spi_nor_read_id(nor); 3357 if (IS_ERR_OR_NULL(info)) 3358 return ERR_PTR(-ENOENT); 3359 3360 /* 3361 * If caller has specified name of flash model that can normally be 3362 * detected using JEDEC, let's verify it. 3363 */ 3364 if (name && info->id_len) { 3365 const struct flash_info *jinfo; 3366 3367 jinfo = spi_nor_read_id(nor); 3368 if (IS_ERR(jinfo)) { 3369 return jinfo; 3370 } else if (jinfo != info) { 3371 /* 3372 * JEDEC knows better, so overwrite platform ID. We 3373 * can't trust partitions any longer, but we'll let 3374 * mtd apply them anyway, since some partitions may be 3375 * marked read-only, and we don't want to lose that 3376 * information, even if it's not 100% accurate. 3377 */ 3378 dev_warn(nor->dev, "found %s, expected %s\n", 3379 jinfo->name, info->name); 3380 info = jinfo; 3381 } 3382 } 3383 3384 return info; 3385 } 3386 3387 int spi_nor_scan(struct spi_nor *nor, const char *name, 3388 const struct spi_nor_hwcaps *hwcaps) 3389 { 3390 const struct flash_info *info; 3391 struct device *dev = nor->dev; 3392 struct mtd_info *mtd = &nor->mtd; 3393 struct device_node *np = spi_nor_get_flash_node(nor); 3394 int ret; 3395 int i; 3396 3397 ret = spi_nor_check(nor); 3398 if (ret) 3399 return ret; 3400 3401 /* Reset SPI protocol for all commands. */ 3402 nor->reg_proto = SNOR_PROTO_1_1_1; 3403 nor->read_proto = SNOR_PROTO_1_1_1; 3404 nor->write_proto = SNOR_PROTO_1_1_1; 3405 3406 /* 3407 * We need the bounce buffer early to read/write registers when going 3408 * through the spi-mem layer (buffers have to be DMA-able). 3409 * For spi-mem drivers, we'll reallocate a new buffer if 3410 * nor->page_size turns out to be greater than PAGE_SIZE (which 3411 * shouldn't happen before long since NOR pages are usually less 3412 * than 1KB) after spi_nor_scan() returns. 3413 */ 3414 nor->bouncebuf_size = PAGE_SIZE; 3415 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 3416 GFP_KERNEL); 3417 if (!nor->bouncebuf) 3418 return -ENOMEM; 3419 3420 info = spi_nor_get_flash_info(nor, name); 3421 if (IS_ERR(info)) 3422 return PTR_ERR(info); 3423 3424 nor->info = info; 3425 3426 spi_nor_debugfs_init(nor, info); 3427 3428 mutex_init(&nor->lock); 3429 3430 /* 3431 * Make sure the XSR_RDY flag is set before calling 3432 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR 3433 * with Atmel SPI NOR. 3434 */ 3435 if (info->flags & SPI_NOR_XSR_RDY) 3436 nor->flags |= SNOR_F_READY_XSR_RDY; 3437 3438 if (info->flags & SPI_NOR_HAS_LOCK) 3439 nor->flags |= SNOR_F_HAS_LOCK; 3440 3441 mtd->_write = spi_nor_write; 3442 3443 /* Init flash parameters based on flash_info struct and SFDP */ 3444 ret = spi_nor_init_params(nor); 3445 if (ret) 3446 return ret; 3447 3448 if (!mtd->name) 3449 mtd->name = dev_name(dev); 3450 mtd->priv = nor; 3451 mtd->type = MTD_NORFLASH; 3452 mtd->writesize = nor->params->writesize; 3453 mtd->flags = MTD_CAP_NORFLASH; 3454 mtd->size = nor->params->size; 3455 mtd->_erase = spi_nor_erase; 3456 mtd->_read = spi_nor_read; 3457 mtd->_suspend = spi_nor_suspend; 3458 mtd->_resume = spi_nor_resume; 3459 3460 if (nor->params->locking_ops) { 3461 mtd->_lock = spi_nor_lock; 3462 mtd->_unlock = spi_nor_unlock; 3463 mtd->_is_locked = spi_nor_is_locked; 3464 } 3465 3466 if (info->flags & USE_FSR) 3467 nor->flags |= SNOR_F_USE_FSR; 3468 if (info->flags & SPI_NOR_HAS_TB) { 3469 nor->flags |= SNOR_F_HAS_SR_TB; 3470 if (info->flags & SPI_NOR_TB_SR_BIT6) 3471 nor->flags |= SNOR_F_HAS_SR_TB_BIT6; 3472 } 3473 3474 if (info->flags & NO_CHIP_ERASE) 3475 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 3476 if (info->flags & USE_CLSR) 3477 nor->flags |= SNOR_F_USE_CLSR; 3478 if (info->flags & SPI_NOR_SWP_IS_VOLATILE) 3479 nor->flags |= SNOR_F_SWP_IS_VOLATILE; 3480 3481 if (info->flags & SPI_NOR_4BIT_BP) { 3482 nor->flags |= SNOR_F_HAS_4BIT_BP; 3483 if (info->flags & SPI_NOR_BP3_SR_BIT6) 3484 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; 3485 } 3486 3487 if (info->flags & SPI_NOR_NO_ERASE) 3488 mtd->flags |= MTD_NO_ERASE; 3489 3490 mtd->dev.parent = dev; 3491 nor->page_size = nor->params->page_size; 3492 mtd->writebufsize = nor->page_size; 3493 3494 if (of_property_read_bool(np, "broken-flash-reset")) 3495 nor->flags |= SNOR_F_BROKEN_RESET; 3496 3497 /* 3498 * Configure the SPI memory: 3499 * - select op codes for (Fast) Read, Page Program and Sector Erase. 3500 * - set the number of dummy cycles (mode cycles + wait states). 3501 * - set the SPI protocols for register and memory accesses. 3502 */ 3503 ret = spi_nor_setup(nor, hwcaps); 3504 if (ret) 3505 return ret; 3506 3507 if (info->flags & SPI_NOR_4B_OPCODES) 3508 nor->flags |= SNOR_F_4B_OPCODES; 3509 3510 if (info->flags & SPI_NOR_IO_MODE_EN_VOLATILE) 3511 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; 3512 3513 ret = spi_nor_set_addr_width(nor); 3514 if (ret) 3515 return ret; 3516 3517 /* Send all the required SPI flash commands to initialize device */ 3518 ret = spi_nor_init(nor); 3519 if (ret) 3520 return ret; 3521 3522 dev_info(dev, "%s (%lld Kbytes)\n", info->name, 3523 (long long)mtd->size >> 10); 3524 3525 dev_dbg(dev, 3526 "mtd .name = %s, .size = 0x%llx (%lldMiB), " 3527 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 3528 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), 3529 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); 3530 3531 if (mtd->numeraseregions) 3532 for (i = 0; i < mtd->numeraseregions; i++) 3533 dev_dbg(dev, 3534 "mtd.eraseregions[%d] = { .offset = 0x%llx, " 3535 ".erasesize = 0x%.8x (%uKiB), " 3536 ".numblocks = %d }\n", 3537 i, (long long)mtd->eraseregions[i].offset, 3538 mtd->eraseregions[i].erasesize, 3539 mtd->eraseregions[i].erasesize / 1024, 3540 mtd->eraseregions[i].numblocks); 3541 return 0; 3542 } 3543 EXPORT_SYMBOL_GPL(spi_nor_scan); 3544 3545 static int spi_nor_create_read_dirmap(struct spi_nor *nor) 3546 { 3547 struct spi_mem_dirmap_info info = { 3548 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 3549 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0), 3550 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 3551 SPI_MEM_OP_DATA_IN(0, NULL, 0)), 3552 .offset = 0, 3553 .length = nor->mtd.size, 3554 }; 3555 struct spi_mem_op *op = &info.op_tmpl; 3556 3557 spi_nor_spimem_setup_op(nor, op, nor->read_proto); 3558 3559 /* convert the dummy cycles to the number of bytes */ 3560 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8; 3561 if (spi_nor_protocol_is_dtr(nor->read_proto)) 3562 op->dummy.nbytes *= 2; 3563 3564 /* 3565 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3566 * of data bytes is non-zero, the data buswidth won't be set here. So, 3567 * do it explicitly. 3568 */ 3569 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 3570 3571 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3572 &info); 3573 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc); 3574 } 3575 3576 static int spi_nor_create_write_dirmap(struct spi_nor *nor) 3577 { 3578 struct spi_mem_dirmap_info info = { 3579 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 3580 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0), 3581 SPI_MEM_OP_NO_DUMMY, 3582 SPI_MEM_OP_DATA_OUT(0, NULL, 0)), 3583 .offset = 0, 3584 .length = nor->mtd.size, 3585 }; 3586 struct spi_mem_op *op = &info.op_tmpl; 3587 3588 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 3589 op->addr.nbytes = 0; 3590 3591 spi_nor_spimem_setup_op(nor, op, nor->write_proto); 3592 3593 /* 3594 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3595 * of data bytes is non-zero, the data buswidth won't be set here. So, 3596 * do it explicitly. 3597 */ 3598 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 3599 3600 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3601 &info); 3602 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc); 3603 } 3604 3605 static int spi_nor_probe(struct spi_mem *spimem) 3606 { 3607 struct spi_device *spi = spimem->spi; 3608 struct flash_platform_data *data = dev_get_platdata(&spi->dev); 3609 struct spi_nor *nor; 3610 /* 3611 * Enable all caps by default. The core will mask them after 3612 * checking what's really supported using spi_mem_supports_op(). 3613 */ 3614 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; 3615 char *flash_name; 3616 int ret; 3617 3618 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL); 3619 if (!nor) 3620 return -ENOMEM; 3621 3622 nor->spimem = spimem; 3623 nor->dev = &spi->dev; 3624 spi_nor_set_flash_node(nor, spi->dev.of_node); 3625 3626 spi_mem_set_drvdata(spimem, nor); 3627 3628 if (data && data->name) 3629 nor->mtd.name = data->name; 3630 3631 if (!nor->mtd.name) 3632 nor->mtd.name = spi_mem_get_name(spimem); 3633 3634 /* 3635 * For some (historical?) reason many platforms provide two different 3636 * names in flash_platform_data: "name" and "type". Quite often name is 3637 * set to "m25p80" and then "type" provides a real chip name. 3638 * If that's the case, respect "type" and ignore a "name". 3639 */ 3640 if (data && data->type) 3641 flash_name = data->type; 3642 else if (!strcmp(spi->modalias, "spi-nor")) 3643 flash_name = NULL; /* auto-detect */ 3644 else 3645 flash_name = spi->modalias; 3646 3647 ret = spi_nor_scan(nor, flash_name, &hwcaps); 3648 if (ret) 3649 return ret; 3650 3651 /* 3652 * None of the existing parts have > 512B pages, but let's play safe 3653 * and add this logic so that if anyone ever adds support for such 3654 * a NOR we don't end up with buffer overflows. 3655 */ 3656 if (nor->page_size > PAGE_SIZE) { 3657 nor->bouncebuf_size = nor->page_size; 3658 devm_kfree(nor->dev, nor->bouncebuf); 3659 nor->bouncebuf = devm_kmalloc(nor->dev, 3660 nor->bouncebuf_size, 3661 GFP_KERNEL); 3662 if (!nor->bouncebuf) 3663 return -ENOMEM; 3664 } 3665 3666 ret = spi_nor_create_read_dirmap(nor); 3667 if (ret) 3668 return ret; 3669 3670 ret = spi_nor_create_write_dirmap(nor); 3671 if (ret) 3672 return ret; 3673 3674 return mtd_device_register(&nor->mtd, data ? data->parts : NULL, 3675 data ? data->nr_parts : 0); 3676 } 3677 3678 static int spi_nor_remove(struct spi_mem *spimem) 3679 { 3680 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3681 3682 spi_nor_restore(nor); 3683 3684 /* Clean up MTD stuff. */ 3685 return mtd_device_unregister(&nor->mtd); 3686 } 3687 3688 static void spi_nor_shutdown(struct spi_mem *spimem) 3689 { 3690 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3691 3692 spi_nor_restore(nor); 3693 } 3694 3695 /* 3696 * Do NOT add to this array without reading the following: 3697 * 3698 * Historically, many flash devices are bound to this driver by their name. But 3699 * since most of these flash are compatible to some extent, and their 3700 * differences can often be differentiated by the JEDEC read-ID command, we 3701 * encourage new users to add support to the spi-nor library, and simply bind 3702 * against a generic string here (e.g., "jedec,spi-nor"). 3703 * 3704 * Many flash names are kept here in this list (as well as in spi-nor.c) to 3705 * keep them available as module aliases for existing platforms. 3706 */ 3707 static const struct spi_device_id spi_nor_dev_ids[] = { 3708 /* 3709 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and 3710 * hack around the fact that the SPI core does not provide uevent 3711 * matching for .of_match_table 3712 */ 3713 {"spi-nor"}, 3714 3715 /* 3716 * Entries not used in DTs that should be safe to drop after replacing 3717 * them with "spi-nor" in platform data. 3718 */ 3719 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, 3720 3721 /* 3722 * Entries that were used in DTs without "jedec,spi-nor" fallback and 3723 * should be kept for backward compatibility. 3724 */ 3725 {"at25df321a"}, {"at25df641"}, {"at26df081a"}, 3726 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, 3727 {"mx25l25635e"},{"mx66l51235l"}, 3728 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, 3729 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, 3730 {"s25fl064k"}, 3731 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, 3732 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, 3733 {"m25p64"}, {"m25p128"}, 3734 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, 3735 {"w25q80bl"}, {"w25q128"}, {"w25q256"}, 3736 3737 /* Flashes that can't be detected using JEDEC */ 3738 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, 3739 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, 3740 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, 3741 3742 /* Everspin MRAMs (non-JEDEC) */ 3743 { "mr25h128" }, /* 128 Kib, 40 MHz */ 3744 { "mr25h256" }, /* 256 Kib, 40 MHz */ 3745 { "mr25h10" }, /* 1 Mib, 40 MHz */ 3746 { "mr25h40" }, /* 4 Mib, 40 MHz */ 3747 3748 { }, 3749 }; 3750 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids); 3751 3752 static const struct of_device_id spi_nor_of_table[] = { 3753 /* 3754 * Generic compatibility for SPI NOR that can be identified by the 3755 * JEDEC READ ID opcode (0x9F). Use this, if possible. 3756 */ 3757 { .compatible = "jedec,spi-nor" }, 3758 { /* sentinel */ }, 3759 }; 3760 MODULE_DEVICE_TABLE(of, spi_nor_of_table); 3761 3762 /* 3763 * REVISIT: many of these chips have deep power-down modes, which 3764 * should clearly be entered on suspend() to minimize power use. 3765 * And also when they're otherwise idle... 3766 */ 3767 static struct spi_mem_driver spi_nor_driver = { 3768 .spidrv = { 3769 .driver = { 3770 .name = "spi-nor", 3771 .of_match_table = spi_nor_of_table, 3772 }, 3773 .id_table = spi_nor_dev_ids, 3774 }, 3775 .probe = spi_nor_probe, 3776 .remove = spi_nor_remove, 3777 .shutdown = spi_nor_shutdown, 3778 }; 3779 module_spi_mem_driver(spi_nor_driver); 3780 3781 MODULE_LICENSE("GPL v2"); 3782 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); 3783 MODULE_AUTHOR("Mike Lavender"); 3784 MODULE_DESCRIPTION("framework for SPI NOR"); 3785