1menuconfig MTD_SPI_NOR 2 tristate "SPI-NOR device support" 3 depends on MTD 4 help 5 This is the framework for the SPI NOR which can be used by the SPI 6 device drivers and the SPI-NOR device driver. 7 8if MTD_SPI_NOR 9 10config MTD_SPI_NOR_USE_4K_SECTORS 11 bool "Use small 4096 B erase sectors" 12 default y 13 help 14 Many flash memories support erasing small (4096 B) sectors. Depending 15 on the usage this feature may provide performance gain in comparison 16 to erasing whole blocks (32/64 KiB). 17 Changing a small part of the flash's contents is usually faster with 18 small sectors. On the other hand erasing should be faster when using 19 64 KiB block instead of 16 × 4 KiB sectors. 20 21 Please note that some tools/drivers/filesystems may not work with 22 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum). 23 24config SPI_ASPEED_SMC 25 tristate "Aspeed flash controllers in SPI mode" 26 depends on ARCH_ASPEED || COMPILE_TEST 27 depends on HAS_IOMEM && OF 28 help 29 This enables support for the Firmware Memory controller (FMC) 30 in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips, 31 and support for the SPI flash memory controller (SPI) for 32 the host firmware. The implementation only supports SPI NOR. 33 34config SPI_CADENCE_QUADSPI 35 tristate "Cadence Quad SPI controller" 36 depends on OF && (ARM || ARM64 || COMPILE_TEST) 37 help 38 Enable support for the Cadence Quad SPI Flash controller. 39 40 Cadence QSPI is a specialized controller for connecting an SPI 41 Flash over 1/2/4-bit wide bus. Enable this option if you have a 42 device with a Cadence QSPI controller and want to access the 43 Flash as an MTD device. 44 45config SPI_HISI_SFC 46 tristate "Hisilicon SPI-NOR Flash Controller(SFC)" 47 depends on ARCH_HISI || COMPILE_TEST 48 depends on HAS_IOMEM 49 help 50 This enables support for hisilicon SPI-NOR flash controller. 51 52config SPI_MTK_QUADSPI 53 tristate "MediaTek Quad SPI controller" 54 depends on HAS_IOMEM 55 help 56 This enables support for the Quad SPI controller in master mode. 57 This controller does not support generic SPI. It only supports 58 SPI NOR. 59 60config SPI_NXP_SPIFI 61 tristate "NXP SPI Flash Interface (SPIFI)" 62 depends on OF && (ARCH_LPC18XX || COMPILE_TEST) 63 depends on HAS_IOMEM 64 help 65 Enable support for the NXP LPC SPI Flash Interface controller. 66 67 SPIFI is a specialized controller for connecting serial SPI 68 Flash. Enable this option if you have a device with a SPIFI 69 controller and want to access the Flash as a mtd device. 70 71config SPI_INTEL_SPI 72 tristate 73 74config SPI_INTEL_SPI_PCI 75 tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)" 76 depends on X86 && PCI 77 select SPI_INTEL_SPI 78 help 79 This enables PCI support for the Intel PCH/PCU SPI controller in 80 master mode. This controller is present in modern Intel hardware 81 and is used to hold BIOS and other persistent settings. Using 82 this driver it is possible to upgrade BIOS directly from Linux. 83 84 Say N here unless you know what you are doing. Overwriting the 85 SPI flash may render the system unbootable. 86 87 To compile this driver as a module, choose M here: the module 88 will be called intel-spi-pci. 89 90config SPI_INTEL_SPI_PLATFORM 91 tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)" 92 depends on X86 93 select SPI_INTEL_SPI 94 help 95 This enables platform support for the Intel PCH/PCU SPI 96 controller in master mode. This controller is present in modern 97 Intel hardware and is used to hold BIOS and other persistent 98 settings. Using this driver it is possible to upgrade BIOS 99 directly from Linux. 100 101 Say N here unless you know what you are doing. Overwriting the 102 SPI flash may render the system unbootable. 103 104 To compile this driver as a module, choose M here: the module 105 will be called intel-spi-platform. 106 107config SPI_STM32_QUADSPI 108 tristate "STM32 Quad SPI controller" 109 depends on ARCH_STM32 || COMPILE_TEST 110 help 111 This enables support for the STM32 Quad SPI controller. 112 We only connect the NOR to this controller. 113 114endif # MTD_SPI_NOR 115