1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #define pr_fmt(fmt) "spi-nand: " fmt 11 12 #include <linux/device.h> 13 #include <linux/jiffies.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/mtd/spinand.h> 17 #include <linux/of.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi-mem.h> 22 23 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) 24 { 25 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, 26 spinand->scratchbuf); 27 int ret; 28 29 ret = spi_mem_exec_op(spinand->spimem, &op); 30 if (ret) 31 return ret; 32 33 *val = *spinand->scratchbuf; 34 return 0; 35 } 36 37 static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) 38 { 39 struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, 40 spinand->scratchbuf); 41 42 *spinand->scratchbuf = val; 43 return spi_mem_exec_op(spinand->spimem, &op); 44 } 45 46 static int spinand_read_status(struct spinand_device *spinand, u8 *status) 47 { 48 return spinand_read_reg_op(spinand, REG_STATUS, status); 49 } 50 51 static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg) 52 { 53 struct nand_device *nand = spinand_to_nand(spinand); 54 55 if (WARN_ON(spinand->cur_target < 0 || 56 spinand->cur_target >= nand->memorg.ntargets)) 57 return -EINVAL; 58 59 *cfg = spinand->cfg_cache[spinand->cur_target]; 60 return 0; 61 } 62 63 static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg) 64 { 65 struct nand_device *nand = spinand_to_nand(spinand); 66 int ret; 67 68 if (WARN_ON(spinand->cur_target < 0 || 69 spinand->cur_target >= nand->memorg.ntargets)) 70 return -EINVAL; 71 72 if (spinand->cfg_cache[spinand->cur_target] == cfg) 73 return 0; 74 75 ret = spinand_write_reg_op(spinand, REG_CFG, cfg); 76 if (ret) 77 return ret; 78 79 spinand->cfg_cache[spinand->cur_target] = cfg; 80 return 0; 81 } 82 83 /** 84 * spinand_upd_cfg() - Update the configuration register 85 * @spinand: the spinand device 86 * @mask: the mask encoding the bits to update in the config reg 87 * @val: the new value to apply 88 * 89 * Update the configuration register. 90 * 91 * Return: 0 on success, a negative error code otherwise. 92 */ 93 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val) 94 { 95 int ret; 96 u8 cfg; 97 98 ret = spinand_get_cfg(spinand, &cfg); 99 if (ret) 100 return ret; 101 102 cfg &= ~mask; 103 cfg |= val; 104 105 return spinand_set_cfg(spinand, cfg); 106 } 107 108 /** 109 * spinand_select_target() - Select a specific NAND target/die 110 * @spinand: the spinand device 111 * @target: the target/die to select 112 * 113 * Select a new target/die. If chip only has one die, this function is a NOOP. 114 * 115 * Return: 0 on success, a negative error code otherwise. 116 */ 117 int spinand_select_target(struct spinand_device *spinand, unsigned int target) 118 { 119 struct nand_device *nand = spinand_to_nand(spinand); 120 int ret; 121 122 if (WARN_ON(target >= nand->memorg.ntargets)) 123 return -EINVAL; 124 125 if (spinand->cur_target == target) 126 return 0; 127 128 if (nand->memorg.ntargets == 1) { 129 spinand->cur_target = target; 130 return 0; 131 } 132 133 ret = spinand->select_target(spinand, target); 134 if (ret) 135 return ret; 136 137 spinand->cur_target = target; 138 return 0; 139 } 140 141 static int spinand_read_cfg(struct spinand_device *spinand) 142 { 143 struct nand_device *nand = spinand_to_nand(spinand); 144 unsigned int target; 145 int ret; 146 147 for (target = 0; target < nand->memorg.ntargets; target++) { 148 ret = spinand_select_target(spinand, target); 149 if (ret) 150 return ret; 151 152 /* 153 * We use spinand_read_reg_op() instead of spinand_get_cfg() 154 * here to bypass the config cache. 155 */ 156 ret = spinand_read_reg_op(spinand, REG_CFG, 157 &spinand->cfg_cache[target]); 158 if (ret) 159 return ret; 160 } 161 162 return 0; 163 } 164 165 static int spinand_init_cfg_cache(struct spinand_device *spinand) 166 { 167 struct nand_device *nand = spinand_to_nand(spinand); 168 struct device *dev = &spinand->spimem->spi->dev; 169 170 spinand->cfg_cache = devm_kcalloc(dev, 171 nand->memorg.ntargets, 172 sizeof(*spinand->cfg_cache), 173 GFP_KERNEL); 174 if (!spinand->cfg_cache) 175 return -ENOMEM; 176 177 return 0; 178 } 179 180 static int spinand_init_quad_enable(struct spinand_device *spinand) 181 { 182 bool enable = false; 183 184 if (!(spinand->flags & SPINAND_HAS_QE_BIT)) 185 return 0; 186 187 if (spinand->op_templates.read_cache->data.buswidth == 4 || 188 spinand->op_templates.write_cache->data.buswidth == 4 || 189 spinand->op_templates.update_cache->data.buswidth == 4) 190 enable = true; 191 192 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, 193 enable ? CFG_QUAD_ENABLE : 0); 194 } 195 196 static int spinand_ecc_enable(struct spinand_device *spinand, 197 bool enable) 198 { 199 return spinand_upd_cfg(spinand, CFG_ECC_ENABLE, 200 enable ? CFG_ECC_ENABLE : 0); 201 } 202 203 static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status) 204 { 205 struct nand_device *nand = spinand_to_nand(spinand); 206 207 if (spinand->eccinfo.get_status) 208 return spinand->eccinfo.get_status(spinand, status); 209 210 switch (status & STATUS_ECC_MASK) { 211 case STATUS_ECC_NO_BITFLIPS: 212 return 0; 213 214 case STATUS_ECC_HAS_BITFLIPS: 215 /* 216 * We have no way to know exactly how many bitflips have been 217 * fixed, so let's return the maximum possible value so that 218 * wear-leveling layers move the data immediately. 219 */ 220 return nanddev_get_ecc_conf(nand)->strength; 221 222 case STATUS_ECC_UNCOR_ERROR: 223 return -EBADMSG; 224 225 default: 226 break; 227 } 228 229 return -EINVAL; 230 } 231 232 static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section, 233 struct mtd_oob_region *region) 234 { 235 return -ERANGE; 236 } 237 238 static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section, 239 struct mtd_oob_region *region) 240 { 241 if (section) 242 return -ERANGE; 243 244 /* Reserve 2 bytes for the BBM. */ 245 region->offset = 2; 246 region->length = 62; 247 248 return 0; 249 } 250 251 static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = { 252 .ecc = spinand_noecc_ooblayout_ecc, 253 .free = spinand_noecc_ooblayout_free, 254 }; 255 256 static int spinand_ondie_ecc_init_ctx(struct nand_device *nand) 257 { 258 struct spinand_device *spinand = nand_to_spinand(nand); 259 struct mtd_info *mtd = nanddev_to_mtd(nand); 260 struct spinand_ondie_ecc_conf *engine_conf; 261 262 nand->ecc.ctx.conf.engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE; 263 nand->ecc.ctx.conf.step_size = nand->ecc.requirements.step_size; 264 nand->ecc.ctx.conf.strength = nand->ecc.requirements.strength; 265 266 engine_conf = kzalloc(sizeof(*engine_conf), GFP_KERNEL); 267 if (!engine_conf) 268 return -ENOMEM; 269 270 nand->ecc.ctx.priv = engine_conf; 271 272 if (spinand->eccinfo.ooblayout) 273 mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout); 274 else 275 mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout); 276 277 return 0; 278 } 279 280 static void spinand_ondie_ecc_cleanup_ctx(struct nand_device *nand) 281 { 282 kfree(nand->ecc.ctx.priv); 283 } 284 285 static int spinand_ondie_ecc_prepare_io_req(struct nand_device *nand, 286 struct nand_page_io_req *req) 287 { 288 struct spinand_device *spinand = nand_to_spinand(nand); 289 bool enable = (req->mode != MTD_OPS_RAW); 290 291 memset(spinand->oobbuf, 0xff, nanddev_per_page_oobsize(nand)); 292 293 /* Only enable or disable the engine */ 294 return spinand_ecc_enable(spinand, enable); 295 } 296 297 static int spinand_ondie_ecc_finish_io_req(struct nand_device *nand, 298 struct nand_page_io_req *req) 299 { 300 struct spinand_ondie_ecc_conf *engine_conf = nand->ecc.ctx.priv; 301 struct spinand_device *spinand = nand_to_spinand(nand); 302 struct mtd_info *mtd = spinand_to_mtd(spinand); 303 int ret; 304 305 if (req->mode == MTD_OPS_RAW) 306 return 0; 307 308 /* Nothing to do when finishing a page write */ 309 if (req->type == NAND_PAGE_WRITE) 310 return 0; 311 312 /* Finish a page read: check the status, report errors/bitflips */ 313 ret = spinand_check_ecc_status(spinand, engine_conf->status); 314 if (ret == -EBADMSG) 315 mtd->ecc_stats.failed++; 316 else if (ret > 0) 317 mtd->ecc_stats.corrected += ret; 318 319 return ret; 320 } 321 322 static struct nand_ecc_engine_ops spinand_ondie_ecc_engine_ops = { 323 .init_ctx = spinand_ondie_ecc_init_ctx, 324 .cleanup_ctx = spinand_ondie_ecc_cleanup_ctx, 325 .prepare_io_req = spinand_ondie_ecc_prepare_io_req, 326 .finish_io_req = spinand_ondie_ecc_finish_io_req, 327 }; 328 329 static struct nand_ecc_engine spinand_ondie_ecc_engine = { 330 .ops = &spinand_ondie_ecc_engine_ops, 331 }; 332 333 static void spinand_ondie_ecc_save_status(struct nand_device *nand, u8 status) 334 { 335 struct spinand_ondie_ecc_conf *engine_conf = nand->ecc.ctx.priv; 336 337 if (nand->ecc.ctx.conf.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE && 338 engine_conf) 339 engine_conf->status = status; 340 } 341 342 static int spinand_write_enable_op(struct spinand_device *spinand) 343 { 344 struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true); 345 346 return spi_mem_exec_op(spinand->spimem, &op); 347 } 348 349 static int spinand_load_page_op(struct spinand_device *spinand, 350 const struct nand_page_io_req *req) 351 { 352 struct nand_device *nand = spinand_to_nand(spinand); 353 unsigned int row = nanddev_pos_to_row(nand, &req->pos); 354 struct spi_mem_op op = SPINAND_PAGE_READ_OP(row); 355 356 return spi_mem_exec_op(spinand->spimem, &op); 357 } 358 359 static int spinand_read_from_cache_op(struct spinand_device *spinand, 360 const struct nand_page_io_req *req) 361 { 362 struct nand_device *nand = spinand_to_nand(spinand); 363 struct mtd_info *mtd = spinand_to_mtd(spinand); 364 struct spi_mem_dirmap_desc *rdesc; 365 unsigned int nbytes = 0; 366 void *buf = NULL; 367 u16 column = 0; 368 ssize_t ret; 369 370 if (req->datalen) { 371 buf = spinand->databuf; 372 nbytes = nanddev_page_size(nand); 373 column = 0; 374 } 375 376 if (req->ooblen) { 377 nbytes += nanddev_per_page_oobsize(nand); 378 if (!buf) { 379 buf = spinand->oobbuf; 380 column = nanddev_page_size(nand); 381 } 382 } 383 384 if (req->mode == MTD_OPS_RAW) 385 rdesc = spinand->dirmaps[req->pos.plane].rdesc; 386 else 387 rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; 388 389 while (nbytes) { 390 ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); 391 if (ret < 0) 392 return ret; 393 394 if (!ret || ret > nbytes) 395 return -EIO; 396 397 nbytes -= ret; 398 column += ret; 399 buf += ret; 400 } 401 402 if (req->datalen) 403 memcpy(req->databuf.in, spinand->databuf + req->dataoffs, 404 req->datalen); 405 406 if (req->ooblen) { 407 if (req->mode == MTD_OPS_AUTO_OOB) 408 mtd_ooblayout_get_databytes(mtd, req->oobbuf.in, 409 spinand->oobbuf, 410 req->ooboffs, 411 req->ooblen); 412 else 413 memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs, 414 req->ooblen); 415 } 416 417 return 0; 418 } 419 420 static int spinand_write_to_cache_op(struct spinand_device *spinand, 421 const struct nand_page_io_req *req) 422 { 423 struct nand_device *nand = spinand_to_nand(spinand); 424 struct mtd_info *mtd = spinand_to_mtd(spinand); 425 struct spi_mem_dirmap_desc *wdesc; 426 unsigned int nbytes, column = 0; 427 void *buf = spinand->databuf; 428 ssize_t ret; 429 430 /* 431 * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset 432 * the cache content to 0xFF (depends on vendor implementation), so we 433 * must fill the page cache entirely even if we only want to program 434 * the data portion of the page, otherwise we might corrupt the BBM or 435 * user data previously programmed in OOB area. 436 * 437 * Only reset the data buffer manually, the OOB buffer is prepared by 438 * ECC engines ->prepare_io_req() callback. 439 */ 440 nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand); 441 memset(spinand->databuf, 0xff, nanddev_page_size(nand)); 442 443 if (req->datalen) 444 memcpy(spinand->databuf + req->dataoffs, req->databuf.out, 445 req->datalen); 446 447 if (req->ooblen) { 448 if (req->mode == MTD_OPS_AUTO_OOB) 449 mtd_ooblayout_set_databytes(mtd, req->oobbuf.out, 450 spinand->oobbuf, 451 req->ooboffs, 452 req->ooblen); 453 else 454 memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out, 455 req->ooblen); 456 } 457 458 if (req->mode == MTD_OPS_RAW) 459 wdesc = spinand->dirmaps[req->pos.plane].wdesc; 460 else 461 wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; 462 463 while (nbytes) { 464 ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); 465 if (ret < 0) 466 return ret; 467 468 if (!ret || ret > nbytes) 469 return -EIO; 470 471 nbytes -= ret; 472 column += ret; 473 buf += ret; 474 } 475 476 return 0; 477 } 478 479 static int spinand_program_op(struct spinand_device *spinand, 480 const struct nand_page_io_req *req) 481 { 482 struct nand_device *nand = spinand_to_nand(spinand); 483 unsigned int row = nanddev_pos_to_row(nand, &req->pos); 484 struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row); 485 486 return spi_mem_exec_op(spinand->spimem, &op); 487 } 488 489 static int spinand_erase_op(struct spinand_device *spinand, 490 const struct nand_pos *pos) 491 { 492 struct nand_device *nand = spinand_to_nand(spinand); 493 unsigned int row = nanddev_pos_to_row(nand, pos); 494 struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row); 495 496 return spi_mem_exec_op(spinand->spimem, &op); 497 } 498 499 static int spinand_wait(struct spinand_device *spinand, 500 unsigned long initial_delay_us, 501 unsigned long poll_delay_us, 502 u8 *s) 503 { 504 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(REG_STATUS, 505 spinand->scratchbuf); 506 u8 status; 507 int ret; 508 509 ret = spi_mem_poll_status(spinand->spimem, &op, STATUS_BUSY, 0, 510 initial_delay_us, 511 poll_delay_us, 512 SPINAND_WAITRDY_TIMEOUT_MS); 513 if (ret) 514 return ret; 515 516 status = *spinand->scratchbuf; 517 if (!(status & STATUS_BUSY)) 518 goto out; 519 520 /* 521 * Extra read, just in case the STATUS_READY bit has changed 522 * since our last check 523 */ 524 ret = spinand_read_status(spinand, &status); 525 if (ret) 526 return ret; 527 528 out: 529 if (s) 530 *s = status; 531 532 return status & STATUS_BUSY ? -ETIMEDOUT : 0; 533 } 534 535 static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, 536 u8 ndummy, u8 *buf) 537 { 538 struct spi_mem_op op = SPINAND_READID_OP( 539 naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); 540 int ret; 541 542 ret = spi_mem_exec_op(spinand->spimem, &op); 543 if (!ret) 544 memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN); 545 546 return ret; 547 } 548 549 static int spinand_reset_op(struct spinand_device *spinand) 550 { 551 struct spi_mem_op op = SPINAND_RESET_OP; 552 int ret; 553 554 ret = spi_mem_exec_op(spinand->spimem, &op); 555 if (ret) 556 return ret; 557 558 return spinand_wait(spinand, 559 SPINAND_RESET_INITIAL_DELAY_US, 560 SPINAND_RESET_POLL_DELAY_US, 561 NULL); 562 } 563 564 static int spinand_lock_block(struct spinand_device *spinand, u8 lock) 565 { 566 return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); 567 } 568 569 static int spinand_read_page(struct spinand_device *spinand, 570 const struct nand_page_io_req *req) 571 { 572 struct nand_device *nand = spinand_to_nand(spinand); 573 u8 status; 574 int ret; 575 576 ret = nand_ecc_prepare_io_req(nand, (struct nand_page_io_req *)req); 577 if (ret) 578 return ret; 579 580 ret = spinand_load_page_op(spinand, req); 581 if (ret) 582 return ret; 583 584 ret = spinand_wait(spinand, 585 SPINAND_READ_INITIAL_DELAY_US, 586 SPINAND_READ_POLL_DELAY_US, 587 &status); 588 if (ret < 0) 589 return ret; 590 591 spinand_ondie_ecc_save_status(nand, status); 592 593 ret = spinand_read_from_cache_op(spinand, req); 594 if (ret) 595 return ret; 596 597 return nand_ecc_finish_io_req(nand, (struct nand_page_io_req *)req); 598 } 599 600 static int spinand_write_page(struct spinand_device *spinand, 601 const struct nand_page_io_req *req) 602 { 603 struct nand_device *nand = spinand_to_nand(spinand); 604 u8 status; 605 int ret; 606 607 ret = nand_ecc_prepare_io_req(nand, (struct nand_page_io_req *)req); 608 if (ret) 609 return ret; 610 611 ret = spinand_write_enable_op(spinand); 612 if (ret) 613 return ret; 614 615 ret = spinand_write_to_cache_op(spinand, req); 616 if (ret) 617 return ret; 618 619 ret = spinand_program_op(spinand, req); 620 if (ret) 621 return ret; 622 623 ret = spinand_wait(spinand, 624 SPINAND_WRITE_INITIAL_DELAY_US, 625 SPINAND_WRITE_POLL_DELAY_US, 626 &status); 627 if (!ret && (status & STATUS_PROG_FAILED)) 628 return -EIO; 629 630 return nand_ecc_finish_io_req(nand, (struct nand_page_io_req *)req); 631 } 632 633 static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, 634 struct mtd_oob_ops *ops) 635 { 636 struct spinand_device *spinand = mtd_to_spinand(mtd); 637 struct nand_device *nand = mtd_to_nanddev(mtd); 638 struct mtd_ecc_stats old_stats; 639 unsigned int max_bitflips = 0; 640 struct nand_io_iter iter; 641 bool disable_ecc = false; 642 bool ecc_failed = false; 643 int ret = 0; 644 645 if (ops->mode == MTD_OPS_RAW || !spinand->eccinfo.ooblayout) 646 disable_ecc = true; 647 648 mutex_lock(&spinand->lock); 649 650 old_stats = mtd->ecc_stats; 651 652 nanddev_io_for_each_page(nand, NAND_PAGE_READ, from, ops, &iter) { 653 if (disable_ecc) 654 iter.req.mode = MTD_OPS_RAW; 655 656 ret = spinand_select_target(spinand, iter.req.pos.target); 657 if (ret) 658 break; 659 660 ret = spinand_read_page(spinand, &iter.req); 661 if (ret < 0 && ret != -EBADMSG) 662 break; 663 664 if (ret == -EBADMSG) 665 ecc_failed = true; 666 else 667 max_bitflips = max_t(unsigned int, max_bitflips, ret); 668 669 ret = 0; 670 ops->retlen += iter.req.datalen; 671 ops->oobretlen += iter.req.ooblen; 672 } 673 674 if (ops->stats) { 675 ops->stats->uncorrectable_errors += 676 mtd->ecc_stats.failed - old_stats.failed; 677 ops->stats->corrected_bitflips += 678 mtd->ecc_stats.corrected - old_stats.corrected; 679 } 680 681 mutex_unlock(&spinand->lock); 682 683 if (ecc_failed && !ret) 684 ret = -EBADMSG; 685 686 return ret ? ret : max_bitflips; 687 } 688 689 static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, 690 struct mtd_oob_ops *ops) 691 { 692 struct spinand_device *spinand = mtd_to_spinand(mtd); 693 struct nand_device *nand = mtd_to_nanddev(mtd); 694 struct nand_io_iter iter; 695 bool disable_ecc = false; 696 int ret = 0; 697 698 if (ops->mode == MTD_OPS_RAW || !mtd->ooblayout) 699 disable_ecc = true; 700 701 mutex_lock(&spinand->lock); 702 703 nanddev_io_for_each_page(nand, NAND_PAGE_WRITE, to, ops, &iter) { 704 if (disable_ecc) 705 iter.req.mode = MTD_OPS_RAW; 706 707 ret = spinand_select_target(spinand, iter.req.pos.target); 708 if (ret) 709 break; 710 711 ret = spinand_write_page(spinand, &iter.req); 712 if (ret) 713 break; 714 715 ops->retlen += iter.req.datalen; 716 ops->oobretlen += iter.req.ooblen; 717 } 718 719 mutex_unlock(&spinand->lock); 720 721 return ret; 722 } 723 724 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) 725 { 726 struct spinand_device *spinand = nand_to_spinand(nand); 727 u8 marker[2] = { }; 728 struct nand_page_io_req req = { 729 .pos = *pos, 730 .ooblen = sizeof(marker), 731 .ooboffs = 0, 732 .oobbuf.in = marker, 733 .mode = MTD_OPS_RAW, 734 }; 735 736 spinand_select_target(spinand, pos->target); 737 spinand_read_page(spinand, &req); 738 if (marker[0] != 0xff || marker[1] != 0xff) 739 return true; 740 741 return false; 742 } 743 744 static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) 745 { 746 struct nand_device *nand = mtd_to_nanddev(mtd); 747 struct spinand_device *spinand = nand_to_spinand(nand); 748 struct nand_pos pos; 749 int ret; 750 751 nanddev_offs_to_pos(nand, offs, &pos); 752 mutex_lock(&spinand->lock); 753 ret = nanddev_isbad(nand, &pos); 754 mutex_unlock(&spinand->lock); 755 756 return ret; 757 } 758 759 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) 760 { 761 struct spinand_device *spinand = nand_to_spinand(nand); 762 u8 marker[2] = { }; 763 struct nand_page_io_req req = { 764 .pos = *pos, 765 .ooboffs = 0, 766 .ooblen = sizeof(marker), 767 .oobbuf.out = marker, 768 .mode = MTD_OPS_RAW, 769 }; 770 int ret; 771 772 ret = spinand_select_target(spinand, pos->target); 773 if (ret) 774 return ret; 775 776 ret = spinand_write_enable_op(spinand); 777 if (ret) 778 return ret; 779 780 return spinand_write_page(spinand, &req); 781 } 782 783 static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs) 784 { 785 struct nand_device *nand = mtd_to_nanddev(mtd); 786 struct spinand_device *spinand = nand_to_spinand(nand); 787 struct nand_pos pos; 788 int ret; 789 790 nanddev_offs_to_pos(nand, offs, &pos); 791 mutex_lock(&spinand->lock); 792 ret = nanddev_markbad(nand, &pos); 793 mutex_unlock(&spinand->lock); 794 795 return ret; 796 } 797 798 static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos) 799 { 800 struct spinand_device *spinand = nand_to_spinand(nand); 801 u8 status; 802 int ret; 803 804 ret = spinand_select_target(spinand, pos->target); 805 if (ret) 806 return ret; 807 808 ret = spinand_write_enable_op(spinand); 809 if (ret) 810 return ret; 811 812 ret = spinand_erase_op(spinand, pos); 813 if (ret) 814 return ret; 815 816 ret = spinand_wait(spinand, 817 SPINAND_ERASE_INITIAL_DELAY_US, 818 SPINAND_ERASE_POLL_DELAY_US, 819 &status); 820 821 if (!ret && (status & STATUS_ERASE_FAILED)) 822 ret = -EIO; 823 824 return ret; 825 } 826 827 static int spinand_mtd_erase(struct mtd_info *mtd, 828 struct erase_info *einfo) 829 { 830 struct spinand_device *spinand = mtd_to_spinand(mtd); 831 int ret; 832 833 mutex_lock(&spinand->lock); 834 ret = nanddev_mtd_erase(mtd, einfo); 835 mutex_unlock(&spinand->lock); 836 837 return ret; 838 } 839 840 static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs) 841 { 842 struct spinand_device *spinand = mtd_to_spinand(mtd); 843 struct nand_device *nand = mtd_to_nanddev(mtd); 844 struct nand_pos pos; 845 int ret; 846 847 nanddev_offs_to_pos(nand, offs, &pos); 848 mutex_lock(&spinand->lock); 849 ret = nanddev_isreserved(nand, &pos); 850 mutex_unlock(&spinand->lock); 851 852 return ret; 853 } 854 855 static int spinand_create_dirmap(struct spinand_device *spinand, 856 unsigned int plane) 857 { 858 struct nand_device *nand = spinand_to_nand(spinand); 859 struct spi_mem_dirmap_info info = { 860 .length = nanddev_page_size(nand) + 861 nanddev_per_page_oobsize(nand), 862 }; 863 struct spi_mem_dirmap_desc *desc; 864 865 /* The plane number is passed in MSB just above the column address */ 866 info.offset = plane << fls(nand->memorg.pagesize); 867 868 info.op_tmpl = *spinand->op_templates.update_cache; 869 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, 870 spinand->spimem, &info); 871 if (IS_ERR(desc)) 872 return PTR_ERR(desc); 873 874 spinand->dirmaps[plane].wdesc = desc; 875 876 info.op_tmpl = *spinand->op_templates.read_cache; 877 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, 878 spinand->spimem, &info); 879 if (IS_ERR(desc)) 880 return PTR_ERR(desc); 881 882 spinand->dirmaps[plane].rdesc = desc; 883 884 if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) { 885 spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc; 886 spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc; 887 888 return 0; 889 } 890 891 info.op_tmpl = *spinand->op_templates.update_cache; 892 info.op_tmpl.data.ecc = true; 893 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, 894 spinand->spimem, &info); 895 if (IS_ERR(desc)) 896 return PTR_ERR(desc); 897 898 spinand->dirmaps[plane].wdesc_ecc = desc; 899 900 info.op_tmpl = *spinand->op_templates.read_cache; 901 info.op_tmpl.data.ecc = true; 902 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, 903 spinand->spimem, &info); 904 if (IS_ERR(desc)) 905 return PTR_ERR(desc); 906 907 spinand->dirmaps[plane].rdesc_ecc = desc; 908 909 return 0; 910 } 911 912 static int spinand_create_dirmaps(struct spinand_device *spinand) 913 { 914 struct nand_device *nand = spinand_to_nand(spinand); 915 int i, ret; 916 917 spinand->dirmaps = devm_kzalloc(&spinand->spimem->spi->dev, 918 sizeof(*spinand->dirmaps) * 919 nand->memorg.planes_per_lun, 920 GFP_KERNEL); 921 if (!spinand->dirmaps) 922 return -ENOMEM; 923 924 for (i = 0; i < nand->memorg.planes_per_lun; i++) { 925 ret = spinand_create_dirmap(spinand, i); 926 if (ret) 927 return ret; 928 } 929 930 return 0; 931 } 932 933 static const struct nand_ops spinand_ops = { 934 .erase = spinand_erase, 935 .markbad = spinand_markbad, 936 .isbad = spinand_isbad, 937 }; 938 939 static const struct spinand_manufacturer *spinand_manufacturers[] = { 940 &alliancememory_spinand_manufacturer, 941 &ato_spinand_manufacturer, 942 &esmt_c8_spinand_manufacturer, 943 &gigadevice_spinand_manufacturer, 944 ¯onix_spinand_manufacturer, 945 µn_spinand_manufacturer, 946 ¶gon_spinand_manufacturer, 947 &toshiba_spinand_manufacturer, 948 &winbond_spinand_manufacturer, 949 &xtx_spinand_manufacturer, 950 }; 951 952 static int spinand_manufacturer_match(struct spinand_device *spinand, 953 enum spinand_readid_method rdid_method) 954 { 955 u8 *id = spinand->id.data; 956 unsigned int i; 957 int ret; 958 959 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { 960 const struct spinand_manufacturer *manufacturer = 961 spinand_manufacturers[i]; 962 963 if (id[0] != manufacturer->id) 964 continue; 965 966 ret = spinand_match_and_init(spinand, 967 manufacturer->chips, 968 manufacturer->nchips, 969 rdid_method); 970 if (ret < 0) 971 continue; 972 973 spinand->manufacturer = manufacturer; 974 return 0; 975 } 976 return -ENOTSUPP; 977 } 978 979 static int spinand_id_detect(struct spinand_device *spinand) 980 { 981 u8 *id = spinand->id.data; 982 int ret; 983 984 ret = spinand_read_id_op(spinand, 0, 0, id); 985 if (ret) 986 return ret; 987 ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE); 988 if (!ret) 989 return 0; 990 991 ret = spinand_read_id_op(spinand, 1, 0, id); 992 if (ret) 993 return ret; 994 ret = spinand_manufacturer_match(spinand, 995 SPINAND_READID_METHOD_OPCODE_ADDR); 996 if (!ret) 997 return 0; 998 999 ret = spinand_read_id_op(spinand, 0, 1, id); 1000 if (ret) 1001 return ret; 1002 ret = spinand_manufacturer_match(spinand, 1003 SPINAND_READID_METHOD_OPCODE_DUMMY); 1004 1005 return ret; 1006 } 1007 1008 static int spinand_manufacturer_init(struct spinand_device *spinand) 1009 { 1010 if (spinand->manufacturer->ops->init) 1011 return spinand->manufacturer->ops->init(spinand); 1012 1013 return 0; 1014 } 1015 1016 static void spinand_manufacturer_cleanup(struct spinand_device *spinand) 1017 { 1018 /* Release manufacturer private data */ 1019 if (spinand->manufacturer->ops->cleanup) 1020 return spinand->manufacturer->ops->cleanup(spinand); 1021 } 1022 1023 static const struct spi_mem_op * 1024 spinand_select_op_variant(struct spinand_device *spinand, 1025 const struct spinand_op_variants *variants) 1026 { 1027 struct nand_device *nand = spinand_to_nand(spinand); 1028 unsigned int i; 1029 1030 for (i = 0; i < variants->nops; i++) { 1031 struct spi_mem_op op = variants->ops[i]; 1032 unsigned int nbytes; 1033 int ret; 1034 1035 nbytes = nanddev_per_page_oobsize(nand) + 1036 nanddev_page_size(nand); 1037 1038 while (nbytes) { 1039 op.data.nbytes = nbytes; 1040 ret = spi_mem_adjust_op_size(spinand->spimem, &op); 1041 if (ret) 1042 break; 1043 1044 if (!spi_mem_supports_op(spinand->spimem, &op)) 1045 break; 1046 1047 nbytes -= op.data.nbytes; 1048 } 1049 1050 if (!nbytes) 1051 return &variants->ops[i]; 1052 } 1053 1054 return NULL; 1055 } 1056 1057 /** 1058 * spinand_match_and_init() - Try to find a match between a device ID and an 1059 * entry in a spinand_info table 1060 * @spinand: SPI NAND object 1061 * @table: SPI NAND device description table 1062 * @table_size: size of the device description table 1063 * @rdid_method: read id method to match 1064 * 1065 * Match between a device ID retrieved through the READ_ID command and an 1066 * entry in the SPI NAND description table. If a match is found, the spinand 1067 * object will be initialized with information provided by the matching 1068 * spinand_info entry. 1069 * 1070 * Return: 0 on success, a negative error code otherwise. 1071 */ 1072 int spinand_match_and_init(struct spinand_device *spinand, 1073 const struct spinand_info *table, 1074 unsigned int table_size, 1075 enum spinand_readid_method rdid_method) 1076 { 1077 u8 *id = spinand->id.data; 1078 struct nand_device *nand = spinand_to_nand(spinand); 1079 unsigned int i; 1080 1081 for (i = 0; i < table_size; i++) { 1082 const struct spinand_info *info = &table[i]; 1083 const struct spi_mem_op *op; 1084 1085 if (rdid_method != info->devid.method) 1086 continue; 1087 1088 if (memcmp(id + 1, info->devid.id, info->devid.len)) 1089 continue; 1090 1091 nand->memorg = table[i].memorg; 1092 nanddev_set_ecc_requirements(nand, &table[i].eccreq); 1093 spinand->eccinfo = table[i].eccinfo; 1094 spinand->flags = table[i].flags; 1095 spinand->id.len = 1 + table[i].devid.len; 1096 spinand->select_target = table[i].select_target; 1097 1098 op = spinand_select_op_variant(spinand, 1099 info->op_variants.read_cache); 1100 if (!op) 1101 return -ENOTSUPP; 1102 1103 spinand->op_templates.read_cache = op; 1104 1105 op = spinand_select_op_variant(spinand, 1106 info->op_variants.write_cache); 1107 if (!op) 1108 return -ENOTSUPP; 1109 1110 spinand->op_templates.write_cache = op; 1111 1112 op = spinand_select_op_variant(spinand, 1113 info->op_variants.update_cache); 1114 spinand->op_templates.update_cache = op; 1115 1116 return 0; 1117 } 1118 1119 return -ENOTSUPP; 1120 } 1121 1122 static int spinand_detect(struct spinand_device *spinand) 1123 { 1124 struct device *dev = &spinand->spimem->spi->dev; 1125 struct nand_device *nand = spinand_to_nand(spinand); 1126 int ret; 1127 1128 ret = spinand_reset_op(spinand); 1129 if (ret) 1130 return ret; 1131 1132 ret = spinand_id_detect(spinand); 1133 if (ret) { 1134 dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN, 1135 spinand->id.data); 1136 return ret; 1137 } 1138 1139 if (nand->memorg.ntargets > 1 && !spinand->select_target) { 1140 dev_err(dev, 1141 "SPI NANDs with more than one die must implement ->select_target()\n"); 1142 return -EINVAL; 1143 } 1144 1145 dev_info(&spinand->spimem->spi->dev, 1146 "%s SPI NAND was found.\n", spinand->manufacturer->name); 1147 dev_info(&spinand->spimem->spi->dev, 1148 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n", 1149 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10, 1150 nanddev_page_size(nand), nanddev_per_page_oobsize(nand)); 1151 1152 return 0; 1153 } 1154 1155 static int spinand_init_flash(struct spinand_device *spinand) 1156 { 1157 struct device *dev = &spinand->spimem->spi->dev; 1158 struct nand_device *nand = spinand_to_nand(spinand); 1159 int ret, i; 1160 1161 ret = spinand_read_cfg(spinand); 1162 if (ret) 1163 return ret; 1164 1165 ret = spinand_init_quad_enable(spinand); 1166 if (ret) 1167 return ret; 1168 1169 ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); 1170 if (ret) 1171 return ret; 1172 1173 ret = spinand_manufacturer_init(spinand); 1174 if (ret) { 1175 dev_err(dev, 1176 "Failed to initialize the SPI NAND chip (err = %d)\n", 1177 ret); 1178 return ret; 1179 } 1180 1181 /* After power up, all blocks are locked, so unlock them here. */ 1182 for (i = 0; i < nand->memorg.ntargets; i++) { 1183 ret = spinand_select_target(spinand, i); 1184 if (ret) 1185 break; 1186 1187 ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); 1188 if (ret) 1189 break; 1190 } 1191 1192 if (ret) 1193 spinand_manufacturer_cleanup(spinand); 1194 1195 return ret; 1196 } 1197 1198 static void spinand_mtd_resume(struct mtd_info *mtd) 1199 { 1200 struct spinand_device *spinand = mtd_to_spinand(mtd); 1201 int ret; 1202 1203 ret = spinand_reset_op(spinand); 1204 if (ret) 1205 return; 1206 1207 ret = spinand_init_flash(spinand); 1208 if (ret) 1209 return; 1210 1211 spinand_ecc_enable(spinand, false); 1212 } 1213 1214 static int spinand_init(struct spinand_device *spinand) 1215 { 1216 struct device *dev = &spinand->spimem->spi->dev; 1217 struct mtd_info *mtd = spinand_to_mtd(spinand); 1218 struct nand_device *nand = mtd_to_nanddev(mtd); 1219 int ret; 1220 1221 /* 1222 * We need a scratch buffer because the spi_mem interface requires that 1223 * buf passed in spi_mem_op->data.buf be DMA-able. 1224 */ 1225 spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL); 1226 if (!spinand->scratchbuf) 1227 return -ENOMEM; 1228 1229 ret = spinand_detect(spinand); 1230 if (ret) 1231 goto err_free_bufs; 1232 1233 /* 1234 * Use kzalloc() instead of devm_kzalloc() here, because some drivers 1235 * may use this buffer for DMA access. 1236 * Memory allocated by devm_ does not guarantee DMA-safe alignment. 1237 */ 1238 spinand->databuf = kzalloc(nanddev_page_size(nand) + 1239 nanddev_per_page_oobsize(nand), 1240 GFP_KERNEL); 1241 if (!spinand->databuf) { 1242 ret = -ENOMEM; 1243 goto err_free_bufs; 1244 } 1245 1246 spinand->oobbuf = spinand->databuf + nanddev_page_size(nand); 1247 1248 ret = spinand_init_cfg_cache(spinand); 1249 if (ret) 1250 goto err_free_bufs; 1251 1252 ret = spinand_init_flash(spinand); 1253 if (ret) 1254 goto err_free_bufs; 1255 1256 ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); 1257 if (ret) 1258 goto err_manuf_cleanup; 1259 1260 /* SPI-NAND default ECC engine is on-die */ 1261 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE; 1262 nand->ecc.ondie_engine = &spinand_ondie_ecc_engine; 1263 1264 spinand_ecc_enable(spinand, false); 1265 ret = nanddev_ecc_engine_init(nand); 1266 if (ret) 1267 goto err_cleanup_nanddev; 1268 1269 mtd->_read_oob = spinand_mtd_read; 1270 mtd->_write_oob = spinand_mtd_write; 1271 mtd->_block_isbad = spinand_mtd_block_isbad; 1272 mtd->_block_markbad = spinand_mtd_block_markbad; 1273 mtd->_block_isreserved = spinand_mtd_block_isreserved; 1274 mtd->_erase = spinand_mtd_erase; 1275 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; 1276 mtd->_resume = spinand_mtd_resume; 1277 1278 if (nand->ecc.engine) { 1279 ret = mtd_ooblayout_count_freebytes(mtd); 1280 if (ret < 0) 1281 goto err_cleanup_ecc_engine; 1282 } 1283 1284 mtd->oobavail = ret; 1285 1286 /* Propagate ECC information to mtd_info */ 1287 mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; 1288 mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; 1289 1290 ret = spinand_create_dirmaps(spinand); 1291 if (ret) { 1292 dev_err(dev, 1293 "Failed to create direct mappings for read/write operations (err = %d)\n", 1294 ret); 1295 goto err_cleanup_ecc_engine; 1296 } 1297 1298 return 0; 1299 1300 err_cleanup_ecc_engine: 1301 nanddev_ecc_engine_cleanup(nand); 1302 1303 err_cleanup_nanddev: 1304 nanddev_cleanup(nand); 1305 1306 err_manuf_cleanup: 1307 spinand_manufacturer_cleanup(spinand); 1308 1309 err_free_bufs: 1310 kfree(spinand->databuf); 1311 kfree(spinand->scratchbuf); 1312 return ret; 1313 } 1314 1315 static void spinand_cleanup(struct spinand_device *spinand) 1316 { 1317 struct nand_device *nand = spinand_to_nand(spinand); 1318 1319 nanddev_cleanup(nand); 1320 spinand_manufacturer_cleanup(spinand); 1321 kfree(spinand->databuf); 1322 kfree(spinand->scratchbuf); 1323 } 1324 1325 static int spinand_probe(struct spi_mem *mem) 1326 { 1327 struct spinand_device *spinand; 1328 struct mtd_info *mtd; 1329 int ret; 1330 1331 spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand), 1332 GFP_KERNEL); 1333 if (!spinand) 1334 return -ENOMEM; 1335 1336 spinand->spimem = mem; 1337 spi_mem_set_drvdata(mem, spinand); 1338 spinand_set_of_node(spinand, mem->spi->dev.of_node); 1339 mutex_init(&spinand->lock); 1340 mtd = spinand_to_mtd(spinand); 1341 mtd->dev.parent = &mem->spi->dev; 1342 1343 ret = spinand_init(spinand); 1344 if (ret) 1345 return ret; 1346 1347 ret = mtd_device_register(mtd, NULL, 0); 1348 if (ret) 1349 goto err_spinand_cleanup; 1350 1351 return 0; 1352 1353 err_spinand_cleanup: 1354 spinand_cleanup(spinand); 1355 1356 return ret; 1357 } 1358 1359 static int spinand_remove(struct spi_mem *mem) 1360 { 1361 struct spinand_device *spinand; 1362 struct mtd_info *mtd; 1363 int ret; 1364 1365 spinand = spi_mem_get_drvdata(mem); 1366 mtd = spinand_to_mtd(spinand); 1367 1368 ret = mtd_device_unregister(mtd); 1369 if (ret) 1370 return ret; 1371 1372 spinand_cleanup(spinand); 1373 1374 return 0; 1375 } 1376 1377 static const struct spi_device_id spinand_ids[] = { 1378 { .name = "spi-nand" }, 1379 { /* sentinel */ }, 1380 }; 1381 MODULE_DEVICE_TABLE(spi, spinand_ids); 1382 1383 #ifdef CONFIG_OF 1384 static const struct of_device_id spinand_of_ids[] = { 1385 { .compatible = "spi-nand" }, 1386 { /* sentinel */ }, 1387 }; 1388 MODULE_DEVICE_TABLE(of, spinand_of_ids); 1389 #endif 1390 1391 static struct spi_mem_driver spinand_drv = { 1392 .spidrv = { 1393 .id_table = spinand_ids, 1394 .driver = { 1395 .name = "spi-nand", 1396 .of_match_table = of_match_ptr(spinand_of_ids), 1397 }, 1398 }, 1399 .probe = spinand_probe, 1400 .remove = spinand_remove, 1401 }; 1402 module_spi_mem_driver(spinand_drv); 1403 1404 MODULE_DESCRIPTION("SPI NAND framework"); 1405 MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>"); 1406 MODULE_LICENSE("GPL v2"); 1407