1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright © 2012 John Crispin <john@phrozen.org> 5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de> 6 */ 7 8 #include <linux/mtd/rawnand.h> 9 #include <linux/of_gpio.h> 10 #include <linux/of_platform.h> 11 12 #include <lantiq_soc.h> 13 14 /* nand registers */ 15 #define EBU_ADDSEL1 0x24 16 #define EBU_NAND_CON 0xB0 17 #define EBU_NAND_WAIT 0xB4 18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */ 19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */ 20 #define EBU_NAND_ECC0 0xB8 21 #define EBU_NAND_ECC_AC 0xBC 22 23 /* 24 * nand commands 25 * The pins of the NAND chip are selected based on the address bits of the 26 * "register" read and write. There are no special registers, but an 27 * address range and the lower address bits are used to activate the 28 * correct line. For example when the bit (1 << 2) is set in the address 29 * the ALE pin will be activated. 30 */ 31 #define NAND_CMD_ALE BIT(2) /* address latch enable */ 32 #define NAND_CMD_CLE BIT(3) /* command latch enable */ 33 #define NAND_CMD_CS BIT(4) /* chip select */ 34 #define NAND_CMD_SE BIT(5) /* spare area access latch */ 35 #define NAND_CMD_WP BIT(6) /* write protect */ 36 #define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) 37 #define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) 38 #define NAND_WRITE_DATA (NAND_CMD_CS) 39 #define NAND_READ_DATA (NAND_CMD_CS) 40 41 /* we need to tel the ebu which addr we mapped the nand to */ 42 #define ADDSEL1_MASK(x) (x << 4) 43 #define ADDSEL1_REGEN 1 44 45 /* we need to tell the EBU that we have nand attached and set it up properly */ 46 #define BUSCON1_SETUP (1 << 22) 47 #define BUSCON1_BCGEN_RES (0x3 << 12) 48 #define BUSCON1_WAITWRC2 (2 << 8) 49 #define BUSCON1_WAITRDC2 (2 << 6) 50 #define BUSCON1_HOLDC1 (1 << 4) 51 #define BUSCON1_RECOVC1 (1 << 2) 52 #define BUSCON1_CMULT4 1 53 54 #define NAND_CON_CE (1 << 20) 55 #define NAND_CON_OUT_CS1 (1 << 10) 56 #define NAND_CON_IN_CS1 (1 << 8) 57 #define NAND_CON_PRE_P (1 << 7) 58 #define NAND_CON_WP_P (1 << 6) 59 #define NAND_CON_SE_P (1 << 5) 60 #define NAND_CON_CS_P (1 << 4) 61 #define NAND_CON_CSMUX (1 << 1) 62 #define NAND_CON_NANDM 1 63 64 struct xway_nand_data { 65 struct nand_chip chip; 66 unsigned long csflags; 67 void __iomem *nandaddr; 68 }; 69 70 static u8 xway_readb(struct mtd_info *mtd, int op) 71 { 72 struct nand_chip *chip = mtd_to_nand(mtd); 73 struct xway_nand_data *data = nand_get_controller_data(chip); 74 75 return readb(data->nandaddr + op); 76 } 77 78 static void xway_writeb(struct mtd_info *mtd, int op, u8 value) 79 { 80 struct nand_chip *chip = mtd_to_nand(mtd); 81 struct xway_nand_data *data = nand_get_controller_data(chip); 82 83 writeb(value, data->nandaddr + op); 84 } 85 86 static void xway_select_chip(struct nand_chip *chip, int select) 87 { 88 struct xway_nand_data *data = nand_get_controller_data(chip); 89 90 switch (select) { 91 case -1: 92 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); 93 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); 94 spin_unlock_irqrestore(&ebu_lock, data->csflags); 95 break; 96 case 0: 97 spin_lock_irqsave(&ebu_lock, data->csflags); 98 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); 99 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); 100 break; 101 default: 102 BUG(); 103 } 104 } 105 106 static void xway_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl) 107 { 108 struct mtd_info *mtd = nand_to_mtd(chip); 109 110 if (cmd == NAND_CMD_NONE) 111 return; 112 113 if (ctrl & NAND_CLE) 114 xway_writeb(mtd, NAND_WRITE_CMD, cmd); 115 else if (ctrl & NAND_ALE) 116 xway_writeb(mtd, NAND_WRITE_ADDR, cmd); 117 118 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) 119 ; 120 } 121 122 static int xway_dev_ready(struct nand_chip *chip) 123 { 124 return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; 125 } 126 127 static unsigned char xway_read_byte(struct nand_chip *chip) 128 { 129 return xway_readb(nand_to_mtd(chip), NAND_READ_DATA); 130 } 131 132 static void xway_read_buf(struct nand_chip *chip, u_char *buf, int len) 133 { 134 int i; 135 136 for (i = 0; i < len; i++) 137 buf[i] = xway_readb(nand_to_mtd(chip), NAND_WRITE_DATA); 138 } 139 140 static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len) 141 { 142 int i; 143 144 for (i = 0; i < len; i++) 145 xway_writeb(nand_to_mtd(chip), NAND_WRITE_DATA, buf[i]); 146 } 147 148 /* 149 * Probe for the NAND device. 150 */ 151 static int xway_nand_probe(struct platform_device *pdev) 152 { 153 struct xway_nand_data *data; 154 struct mtd_info *mtd; 155 struct resource *res; 156 int err; 157 u32 cs; 158 u32 cs_flag = 0; 159 160 /* Allocate memory for the device structure (and zero it) */ 161 data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), 162 GFP_KERNEL); 163 if (!data) 164 return -ENOMEM; 165 166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 167 data->nandaddr = devm_ioremap_resource(&pdev->dev, res); 168 if (IS_ERR(data->nandaddr)) 169 return PTR_ERR(data->nandaddr); 170 171 nand_set_flash_node(&data->chip, pdev->dev.of_node); 172 mtd = nand_to_mtd(&data->chip); 173 mtd->dev.parent = &pdev->dev; 174 175 data->chip.legacy.cmd_ctrl = xway_cmd_ctrl; 176 data->chip.legacy.dev_ready = xway_dev_ready; 177 data->chip.legacy.select_chip = xway_select_chip; 178 data->chip.legacy.write_buf = xway_write_buf; 179 data->chip.legacy.read_buf = xway_read_buf; 180 data->chip.legacy.read_byte = xway_read_byte; 181 data->chip.legacy.chip_delay = 30; 182 183 data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 184 data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 185 186 platform_set_drvdata(pdev, data); 187 nand_set_controller_data(&data->chip, data); 188 189 /* load our CS from the DT. Either we find a valid 1 or default to 0 */ 190 err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs); 191 if (!err && cs == 1) 192 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; 193 194 /* setup the EBU to run in NAND mode on our base addr */ 195 ltq_ebu_w32(CPHYSADDR(data->nandaddr) 196 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); 197 198 ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 199 | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 200 | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); 201 202 ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P 203 | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P 204 | cs_flag, EBU_NAND_CON); 205 206 /* Scan to find existence of the device */ 207 err = nand_scan(&data->chip, 1); 208 if (err) 209 return err; 210 211 err = mtd_device_register(mtd, NULL, 0); 212 if (err) 213 nand_cleanup(&data->chip); 214 215 return err; 216 } 217 218 /* 219 * Remove a NAND device. 220 */ 221 static int xway_nand_remove(struct platform_device *pdev) 222 { 223 struct xway_nand_data *data = platform_get_drvdata(pdev); 224 struct nand_chip *chip = &data->chip; 225 int ret; 226 227 ret = mtd_device_unregister(nand_to_mtd(chip)); 228 WARN_ON(ret); 229 nand_cleanup(chip); 230 231 return 0; 232 } 233 234 static const struct of_device_id xway_nand_match[] = { 235 { .compatible = "lantiq,nand-xway" }, 236 {}, 237 }; 238 239 static struct platform_driver xway_nand_driver = { 240 .probe = xway_nand_probe, 241 .remove = xway_nand_remove, 242 .driver = { 243 .name = "lantiq,nand-xway", 244 .of_match_table = xway_nand_match, 245 }, 246 }; 247 248 builtin_platform_driver(xway_nand_driver); 249