1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright © 2012 John Crispin <john@phrozen.org> 7 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de> 8 */ 9 10 #include <linux/mtd/rawnand.h> 11 #include <linux/of_gpio.h> 12 #include <linux/of_platform.h> 13 14 #include <lantiq_soc.h> 15 16 /* nand registers */ 17 #define EBU_ADDSEL1 0x24 18 #define EBU_NAND_CON 0xB0 19 #define EBU_NAND_WAIT 0xB4 20 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */ 21 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */ 22 #define EBU_NAND_ECC0 0xB8 23 #define EBU_NAND_ECC_AC 0xBC 24 25 /* 26 * nand commands 27 * The pins of the NAND chip are selected based on the address bits of the 28 * "register" read and write. There are no special registers, but an 29 * address range and the lower address bits are used to activate the 30 * correct line. For example when the bit (1 << 2) is set in the address 31 * the ALE pin will be activated. 32 */ 33 #define NAND_CMD_ALE BIT(2) /* address latch enable */ 34 #define NAND_CMD_CLE BIT(3) /* command latch enable */ 35 #define NAND_CMD_CS BIT(4) /* chip select */ 36 #define NAND_CMD_SE BIT(5) /* spare area access latch */ 37 #define NAND_CMD_WP BIT(6) /* write protect */ 38 #define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) 39 #define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) 40 #define NAND_WRITE_DATA (NAND_CMD_CS) 41 #define NAND_READ_DATA (NAND_CMD_CS) 42 43 /* we need to tel the ebu which addr we mapped the nand to */ 44 #define ADDSEL1_MASK(x) (x << 4) 45 #define ADDSEL1_REGEN 1 46 47 /* we need to tell the EBU that we have nand attached and set it up properly */ 48 #define BUSCON1_SETUP (1 << 22) 49 #define BUSCON1_BCGEN_RES (0x3 << 12) 50 #define BUSCON1_WAITWRC2 (2 << 8) 51 #define BUSCON1_WAITRDC2 (2 << 6) 52 #define BUSCON1_HOLDC1 (1 << 4) 53 #define BUSCON1_RECOVC1 (1 << 2) 54 #define BUSCON1_CMULT4 1 55 56 #define NAND_CON_CE (1 << 20) 57 #define NAND_CON_OUT_CS1 (1 << 10) 58 #define NAND_CON_IN_CS1 (1 << 8) 59 #define NAND_CON_PRE_P (1 << 7) 60 #define NAND_CON_WP_P (1 << 6) 61 #define NAND_CON_SE_P (1 << 5) 62 #define NAND_CON_CS_P (1 << 4) 63 #define NAND_CON_CSMUX (1 << 1) 64 #define NAND_CON_NANDM 1 65 66 struct xway_nand_data { 67 struct nand_chip chip; 68 unsigned long csflags; 69 void __iomem *nandaddr; 70 }; 71 72 static u8 xway_readb(struct mtd_info *mtd, int op) 73 { 74 struct nand_chip *chip = mtd_to_nand(mtd); 75 struct xway_nand_data *data = nand_get_controller_data(chip); 76 77 return readb(data->nandaddr + op); 78 } 79 80 static void xway_writeb(struct mtd_info *mtd, int op, u8 value) 81 { 82 struct nand_chip *chip = mtd_to_nand(mtd); 83 struct xway_nand_data *data = nand_get_controller_data(chip); 84 85 writeb(value, data->nandaddr + op); 86 } 87 88 static void xway_select_chip(struct nand_chip *chip, int select) 89 { 90 struct xway_nand_data *data = nand_get_controller_data(chip); 91 92 switch (select) { 93 case -1: 94 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); 95 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); 96 spin_unlock_irqrestore(&ebu_lock, data->csflags); 97 break; 98 case 0: 99 spin_lock_irqsave(&ebu_lock, data->csflags); 100 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); 101 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); 102 break; 103 default: 104 BUG(); 105 } 106 } 107 108 static void xway_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl) 109 { 110 struct mtd_info *mtd = nand_to_mtd(chip); 111 112 if (cmd == NAND_CMD_NONE) 113 return; 114 115 if (ctrl & NAND_CLE) 116 xway_writeb(mtd, NAND_WRITE_CMD, cmd); 117 else if (ctrl & NAND_ALE) 118 xway_writeb(mtd, NAND_WRITE_ADDR, cmd); 119 120 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) 121 ; 122 } 123 124 static int xway_dev_ready(struct nand_chip *chip) 125 { 126 return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; 127 } 128 129 static unsigned char xway_read_byte(struct nand_chip *chip) 130 { 131 return xway_readb(nand_to_mtd(chip), NAND_READ_DATA); 132 } 133 134 static void xway_read_buf(struct nand_chip *chip, u_char *buf, int len) 135 { 136 int i; 137 138 for (i = 0; i < len; i++) 139 buf[i] = xway_readb(nand_to_mtd(chip), NAND_WRITE_DATA); 140 } 141 142 static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len) 143 { 144 int i; 145 146 for (i = 0; i < len; i++) 147 xway_writeb(nand_to_mtd(chip), NAND_WRITE_DATA, buf[i]); 148 } 149 150 /* 151 * Probe for the NAND device. 152 */ 153 static int xway_nand_probe(struct platform_device *pdev) 154 { 155 struct xway_nand_data *data; 156 struct mtd_info *mtd; 157 struct resource *res; 158 int err; 159 u32 cs; 160 u32 cs_flag = 0; 161 162 /* Allocate memory for the device structure (and zero it) */ 163 data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), 164 GFP_KERNEL); 165 if (!data) 166 return -ENOMEM; 167 168 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 169 data->nandaddr = devm_ioremap_resource(&pdev->dev, res); 170 if (IS_ERR(data->nandaddr)) 171 return PTR_ERR(data->nandaddr); 172 173 nand_set_flash_node(&data->chip, pdev->dev.of_node); 174 mtd = nand_to_mtd(&data->chip); 175 mtd->dev.parent = &pdev->dev; 176 177 data->chip.legacy.cmd_ctrl = xway_cmd_ctrl; 178 data->chip.legacy.dev_ready = xway_dev_ready; 179 data->chip.legacy.select_chip = xway_select_chip; 180 data->chip.legacy.write_buf = xway_write_buf; 181 data->chip.legacy.read_buf = xway_read_buf; 182 data->chip.legacy.read_byte = xway_read_byte; 183 data->chip.legacy.chip_delay = 30; 184 185 data->chip.ecc.mode = NAND_ECC_SOFT; 186 data->chip.ecc.algo = NAND_ECC_HAMMING; 187 188 platform_set_drvdata(pdev, data); 189 nand_set_controller_data(&data->chip, data); 190 191 /* load our CS from the DT. Either we find a valid 1 or default to 0 */ 192 err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs); 193 if (!err && cs == 1) 194 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; 195 196 /* setup the EBU to run in NAND mode on our base addr */ 197 ltq_ebu_w32(CPHYSADDR(data->nandaddr) 198 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); 199 200 ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 201 | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 202 | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); 203 204 ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P 205 | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P 206 | cs_flag, EBU_NAND_CON); 207 208 /* Scan to find existence of the device */ 209 err = nand_scan(&data->chip, 1); 210 if (err) 211 return err; 212 213 err = mtd_device_register(mtd, NULL, 0); 214 if (err) 215 nand_release(&data->chip); 216 217 return err; 218 } 219 220 /* 221 * Remove a NAND device. 222 */ 223 static int xway_nand_remove(struct platform_device *pdev) 224 { 225 struct xway_nand_data *data = platform_get_drvdata(pdev); 226 227 nand_release(&data->chip); 228 229 return 0; 230 } 231 232 static const struct of_device_id xway_nand_match[] = { 233 { .compatible = "lantiq,nand-xway" }, 234 {}, 235 }; 236 237 static struct platform_driver xway_nand_driver = { 238 .probe = xway_nand_probe, 239 .remove = xway_nand_remove, 240 .driver = { 241 .name = "lantiq,nand-xway", 242 .of_match_table = xway_nand_match, 243 }, 244 }; 245 246 builtin_platform_driver(xway_nand_driver); 247