1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright © 2012 John Crispin <john@phrozen.org> 5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de> 6 */ 7 8 #include <linux/mtd/rawnand.h> 9 #include <linux/of_gpio.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 13 #include <lantiq_soc.h> 14 15 /* nand registers */ 16 #define EBU_ADDSEL1 0x24 17 #define EBU_NAND_CON 0xB0 18 #define EBU_NAND_WAIT 0xB4 19 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */ 20 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */ 21 #define EBU_NAND_ECC0 0xB8 22 #define EBU_NAND_ECC_AC 0xBC 23 24 /* 25 * nand commands 26 * The pins of the NAND chip are selected based on the address bits of the 27 * "register" read and write. There are no special registers, but an 28 * address range and the lower address bits are used to activate the 29 * correct line. For example when the bit (1 << 2) is set in the address 30 * the ALE pin will be activated. 31 */ 32 #define NAND_CMD_ALE BIT(2) /* address latch enable */ 33 #define NAND_CMD_CLE BIT(3) /* command latch enable */ 34 #define NAND_CMD_CS BIT(4) /* chip select */ 35 #define NAND_CMD_SE BIT(5) /* spare area access latch */ 36 #define NAND_CMD_WP BIT(6) /* write protect */ 37 #define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) 38 #define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) 39 #define NAND_WRITE_DATA (NAND_CMD_CS) 40 #define NAND_READ_DATA (NAND_CMD_CS) 41 42 /* we need to tel the ebu which addr we mapped the nand to */ 43 #define ADDSEL1_MASK(x) (x << 4) 44 #define ADDSEL1_REGEN 1 45 46 /* we need to tell the EBU that we have nand attached and set it up properly */ 47 #define BUSCON1_SETUP (1 << 22) 48 #define BUSCON1_BCGEN_RES (0x3 << 12) 49 #define BUSCON1_WAITWRC2 (2 << 8) 50 #define BUSCON1_WAITRDC2 (2 << 6) 51 #define BUSCON1_HOLDC1 (1 << 4) 52 #define BUSCON1_RECOVC1 (1 << 2) 53 #define BUSCON1_CMULT4 1 54 55 #define NAND_CON_CE (1 << 20) 56 #define NAND_CON_OUT_CS1 (1 << 10) 57 #define NAND_CON_IN_CS1 (1 << 8) 58 #define NAND_CON_PRE_P (1 << 7) 59 #define NAND_CON_WP_P (1 << 6) 60 #define NAND_CON_SE_P (1 << 5) 61 #define NAND_CON_CS_P (1 << 4) 62 #define NAND_CON_CSMUX (1 << 1) 63 #define NAND_CON_NANDM 1 64 65 struct xway_nand_data { 66 struct nand_controller controller; 67 struct nand_chip chip; 68 unsigned long csflags; 69 void __iomem *nandaddr; 70 }; 71 72 static u8 xway_readb(struct mtd_info *mtd, int op) 73 { 74 struct nand_chip *chip = mtd_to_nand(mtd); 75 struct xway_nand_data *data = nand_get_controller_data(chip); 76 77 return readb(data->nandaddr + op); 78 } 79 80 static void xway_writeb(struct mtd_info *mtd, int op, u8 value) 81 { 82 struct nand_chip *chip = mtd_to_nand(mtd); 83 struct xway_nand_data *data = nand_get_controller_data(chip); 84 85 writeb(value, data->nandaddr + op); 86 } 87 88 static void xway_select_chip(struct nand_chip *chip, int select) 89 { 90 struct xway_nand_data *data = nand_get_controller_data(chip); 91 92 switch (select) { 93 case -1: 94 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); 95 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); 96 spin_unlock_irqrestore(&ebu_lock, data->csflags); 97 break; 98 case 0: 99 spin_lock_irqsave(&ebu_lock, data->csflags); 100 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); 101 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); 102 break; 103 default: 104 BUG(); 105 } 106 } 107 108 static void xway_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl) 109 { 110 struct mtd_info *mtd = nand_to_mtd(chip); 111 112 if (cmd == NAND_CMD_NONE) 113 return; 114 115 if (ctrl & NAND_CLE) 116 xway_writeb(mtd, NAND_WRITE_CMD, cmd); 117 else if (ctrl & NAND_ALE) 118 xway_writeb(mtd, NAND_WRITE_ADDR, cmd); 119 120 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) 121 ; 122 } 123 124 static int xway_dev_ready(struct nand_chip *chip) 125 { 126 return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; 127 } 128 129 static unsigned char xway_read_byte(struct nand_chip *chip) 130 { 131 return xway_readb(nand_to_mtd(chip), NAND_READ_DATA); 132 } 133 134 static void xway_read_buf(struct nand_chip *chip, u_char *buf, int len) 135 { 136 int i; 137 138 for (i = 0; i < len; i++) 139 buf[i] = xway_readb(nand_to_mtd(chip), NAND_WRITE_DATA); 140 } 141 142 static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len) 143 { 144 int i; 145 146 for (i = 0; i < len; i++) 147 xway_writeb(nand_to_mtd(chip), NAND_WRITE_DATA, buf[i]); 148 } 149 150 static int xway_attach_chip(struct nand_chip *chip) 151 { 152 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 153 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) 154 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 155 156 return 0; 157 } 158 159 static const struct nand_controller_ops xway_nand_ops = { 160 .attach_chip = xway_attach_chip, 161 }; 162 163 /* 164 * Probe for the NAND device. 165 */ 166 static int xway_nand_probe(struct platform_device *pdev) 167 { 168 struct xway_nand_data *data; 169 struct mtd_info *mtd; 170 int err; 171 u32 cs; 172 u32 cs_flag = 0; 173 174 /* Allocate memory for the device structure (and zero it) */ 175 data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), 176 GFP_KERNEL); 177 if (!data) 178 return -ENOMEM; 179 180 data->nandaddr = devm_platform_ioremap_resource(pdev, 0); 181 if (IS_ERR(data->nandaddr)) 182 return PTR_ERR(data->nandaddr); 183 184 nand_set_flash_node(&data->chip, pdev->dev.of_node); 185 mtd = nand_to_mtd(&data->chip); 186 mtd->dev.parent = &pdev->dev; 187 188 data->chip.legacy.cmd_ctrl = xway_cmd_ctrl; 189 data->chip.legacy.dev_ready = xway_dev_ready; 190 data->chip.legacy.select_chip = xway_select_chip; 191 data->chip.legacy.write_buf = xway_write_buf; 192 data->chip.legacy.read_buf = xway_read_buf; 193 data->chip.legacy.read_byte = xway_read_byte; 194 data->chip.legacy.chip_delay = 30; 195 196 nand_controller_init(&data->controller); 197 data->controller.ops = &xway_nand_ops; 198 data->chip.controller = &data->controller; 199 200 platform_set_drvdata(pdev, data); 201 nand_set_controller_data(&data->chip, data); 202 203 /* load our CS from the DT. Either we find a valid 1 or default to 0 */ 204 err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs); 205 if (!err && cs == 1) 206 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; 207 208 /* setup the EBU to run in NAND mode on our base addr */ 209 ltq_ebu_w32(CPHYSADDR(data->nandaddr) 210 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); 211 212 ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 213 | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 214 | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); 215 216 ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P 217 | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P 218 | cs_flag, EBU_NAND_CON); 219 220 /* 221 * This driver assumes that the default ECC engine should be TYPE_SOFT. 222 * Set ->engine_type before registering the NAND devices in order to 223 * provide a driver specific default value. 224 */ 225 data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 226 227 /* Scan to find existence of the device */ 228 err = nand_scan(&data->chip, 1); 229 if (err) 230 return err; 231 232 err = mtd_device_register(mtd, NULL, 0); 233 if (err) 234 nand_cleanup(&data->chip); 235 236 return err; 237 } 238 239 /* 240 * Remove a NAND device. 241 */ 242 static void xway_nand_remove(struct platform_device *pdev) 243 { 244 struct xway_nand_data *data = platform_get_drvdata(pdev); 245 struct nand_chip *chip = &data->chip; 246 int ret; 247 248 ret = mtd_device_unregister(nand_to_mtd(chip)); 249 WARN_ON(ret); 250 nand_cleanup(chip); 251 } 252 253 static const struct of_device_id xway_nand_match[] = { 254 { .compatible = "lantiq,nand-xway" }, 255 {}, 256 }; 257 258 static struct platform_driver xway_nand_driver = { 259 .probe = xway_nand_probe, 260 .remove_new = xway_nand_remove, 261 .driver = { 262 .name = "lantiq,nand-xway", 263 .of_match_table = xway_nand_match, 264 }, 265 }; 266 267 builtin_platform_driver(xway_nand_driver); 268