1 /* 2 * TXx9 NAND flash memory controller driver 3 * Based on RBTX49xx patch from CELF patch archive. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * (C) Copyright TOSHIBA CORPORATION 2004-2007 10 * All Rights Reserved. 11 */ 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/delay.h> 18 #include <linux/mtd/mtd.h> 19 #include <linux/mtd/rawnand.h> 20 #include <linux/mtd/nand_ecc.h> 21 #include <linux/mtd/partitions.h> 22 #include <linux/io.h> 23 #include <linux/platform_data/txx9/ndfmc.h> 24 25 /* TXX9 NDFMC Registers */ 26 #define TXX9_NDFDTR 0x00 27 #define TXX9_NDFMCR 0x04 28 #define TXX9_NDFSR 0x08 29 #define TXX9_NDFISR 0x0c 30 #define TXX9_NDFIMR 0x10 31 #define TXX9_NDFSPR 0x14 32 #define TXX9_NDFRSTR 0x18 /* not TX4939 */ 33 34 /* NDFMCR : NDFMC Mode Control */ 35 #define TXX9_NDFMCR_WE 0x80 36 #define TXX9_NDFMCR_ECC_ALL 0x60 37 #define TXX9_NDFMCR_ECC_RESET 0x60 38 #define TXX9_NDFMCR_ECC_READ 0x40 39 #define TXX9_NDFMCR_ECC_ON 0x20 40 #define TXX9_NDFMCR_ECC_OFF 0x00 41 #define TXX9_NDFMCR_CE 0x10 42 #define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */ 43 #define TXX9_NDFMCR_ALE 0x02 44 #define TXX9_NDFMCR_CLE 0x01 45 /* TX4939 only */ 46 #define TXX9_NDFMCR_X16 0x0400 47 #define TXX9_NDFMCR_DMAREQ_MASK 0x0300 48 #define TXX9_NDFMCR_DMAREQ_NODMA 0x0000 49 #define TXX9_NDFMCR_DMAREQ_128 0x0100 50 #define TXX9_NDFMCR_DMAREQ_256 0x0200 51 #define TXX9_NDFMCR_DMAREQ_512 0x0300 52 #define TXX9_NDFMCR_CS_MASK 0x0c 53 #define TXX9_NDFMCR_CS(ch) ((ch) << 2) 54 55 /* NDFMCR : NDFMC Status */ 56 #define TXX9_NDFSR_BUSY 0x80 57 /* TX4939 only */ 58 #define TXX9_NDFSR_DMARUN 0x40 59 60 /* NDFMCR : NDFMC Reset */ 61 #define TXX9_NDFRSTR_RST 0x01 62 63 struct txx9ndfmc_priv { 64 struct platform_device *dev; 65 struct nand_chip chip; 66 int cs; 67 const char *mtdname; 68 }; 69 70 #define MAX_TXX9NDFMC_DEV 4 71 struct txx9ndfmc_drvdata { 72 struct mtd_info *mtds[MAX_TXX9NDFMC_DEV]; 73 void __iomem *base; 74 unsigned char hold; /* in gbusclock */ 75 unsigned char spw; /* in gbusclock */ 76 struct nand_controller controller; 77 }; 78 79 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd) 80 { 81 struct nand_chip *chip = mtd_to_nand(mtd); 82 struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip); 83 return txx9_priv->dev; 84 } 85 86 static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg) 87 { 88 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 89 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 90 91 return drvdata->base + (reg << plat->shift); 92 } 93 94 static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg) 95 { 96 return __raw_readl(ndregaddr(dev, reg)); 97 } 98 99 static void txx9ndfmc_write(struct platform_device *dev, 100 u32 val, unsigned int reg) 101 { 102 __raw_writel(val, ndregaddr(dev, reg)); 103 } 104 105 static uint8_t txx9ndfmc_read_byte(struct nand_chip *chip) 106 { 107 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 108 109 return txx9ndfmc_read(dev, TXX9_NDFDTR); 110 } 111 112 static void txx9ndfmc_write_buf(struct nand_chip *chip, const uint8_t *buf, 113 int len) 114 { 115 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 116 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); 117 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 118 119 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); 120 while (len--) 121 __raw_writel(*buf++, ndfdtr); 122 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); 123 } 124 125 static void txx9ndfmc_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 126 { 127 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 128 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); 129 130 while (len--) 131 *buf++ = __raw_readl(ndfdtr); 132 } 133 134 static void txx9ndfmc_cmd_ctrl(struct nand_chip *chip, int cmd, 135 unsigned int ctrl) 136 { 137 struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip); 138 struct platform_device *dev = txx9_priv->dev; 139 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 140 141 if (ctrl & NAND_CTRL_CHANGE) { 142 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 143 144 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); 145 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; 146 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; 147 /* TXX9_NDFMCR_CE bit is 0:high 1:low */ 148 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; 149 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) { 150 mcr &= ~TXX9_NDFMCR_CS_MASK; 151 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs); 152 } 153 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); 154 } 155 if (cmd != NAND_CMD_NONE) 156 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR); 157 if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) { 158 /* dummy write to update external latch */ 159 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE) 160 txx9ndfmc_write(dev, 0, TXX9_NDFDTR); 161 } 162 } 163 164 static int txx9ndfmc_dev_ready(struct nand_chip *chip) 165 { 166 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 167 168 return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY); 169 } 170 171 static int txx9ndfmc_calculate_ecc(struct nand_chip *chip, const uint8_t *dat, 172 uint8_t *ecc_code) 173 { 174 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 175 int eccbytes; 176 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 177 178 mcr &= ~TXX9_NDFMCR_ECC_ALL; 179 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 180 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR); 181 for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) { 182 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR); 183 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR); 184 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR); 185 ecc_code += 3; 186 } 187 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 188 return 0; 189 } 190 191 static int txx9ndfmc_correct_data(struct nand_chip *chip, unsigned char *buf, 192 unsigned char *read_ecc, 193 unsigned char *calc_ecc) 194 { 195 int eccsize; 196 int corrected = 0; 197 int stat; 198 199 for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) { 200 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256, 201 false); 202 if (stat < 0) 203 return stat; 204 corrected += stat; 205 buf += 256; 206 read_ecc += 3; 207 calc_ecc += 3; 208 } 209 return corrected; 210 } 211 212 static void txx9ndfmc_enable_hwecc(struct nand_chip *chip, int mode) 213 { 214 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 215 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 216 217 mcr &= ~TXX9_NDFMCR_ECC_ALL; 218 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR); 219 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 220 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR); 221 } 222 223 static void txx9ndfmc_initialize(struct platform_device *dev) 224 { 225 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 226 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 227 int tmout = 100; 228 229 if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR) 230 ; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */ 231 else { 232 /* reset NDFMC */ 233 txx9ndfmc_write(dev, 234 txx9ndfmc_read(dev, TXX9_NDFRSTR) | 235 TXX9_NDFRSTR_RST, 236 TXX9_NDFRSTR); 237 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) { 238 if (--tmout == 0) { 239 dev_err(&dev->dev, "reset failed.\n"); 240 break; 241 } 242 udelay(1); 243 } 244 } 245 /* setup Hold Time, Strobe Pulse Width */ 246 txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR); 247 txx9ndfmc_write(dev, 248 (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ? 249 TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR); 250 } 251 252 #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \ 253 DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000) 254 255 static int txx9ndfmc_attach_chip(struct nand_chip *chip) 256 { 257 struct mtd_info *mtd = nand_to_mtd(chip); 258 259 if (mtd->writesize >= 512) { 260 chip->ecc.size = 512; 261 chip->ecc.bytes = 6; 262 } else { 263 chip->ecc.size = 256; 264 chip->ecc.bytes = 3; 265 } 266 267 return 0; 268 } 269 270 static const struct nand_controller_ops txx9ndfmc_controller_ops = { 271 .attach_chip = txx9ndfmc_attach_chip, 272 }; 273 274 static int __init txx9ndfmc_probe(struct platform_device *dev) 275 { 276 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 277 int hold, spw; 278 int i; 279 struct txx9ndfmc_drvdata *drvdata; 280 unsigned long gbusclk = plat->gbus_clock; 281 struct resource *res; 282 283 drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL); 284 if (!drvdata) 285 return -ENOMEM; 286 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 287 drvdata->base = devm_ioremap_resource(&dev->dev, res); 288 if (IS_ERR(drvdata->base)) 289 return PTR_ERR(drvdata->base); 290 291 hold = plat->hold ?: 20; /* tDH */ 292 spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */ 293 294 hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold); 295 spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw); 296 if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD) 297 hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */ 298 spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */ 299 hold = clamp(hold, 1, 15); 300 drvdata->hold = hold; 301 spw = clamp(spw, 1, 15); 302 drvdata->spw = spw; 303 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", 304 (gbusclk + 500000) / 1000000, hold, spw); 305 306 nand_controller_init(&drvdata->controller); 307 drvdata->controller.ops = &txx9ndfmc_controller_ops; 308 309 platform_set_drvdata(dev, drvdata); 310 txx9ndfmc_initialize(dev); 311 312 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { 313 struct txx9ndfmc_priv *txx9_priv; 314 struct nand_chip *chip; 315 struct mtd_info *mtd; 316 317 if (!(plat->ch_mask & (1 << i))) 318 continue; 319 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv), 320 GFP_KERNEL); 321 if (!txx9_priv) 322 continue; 323 chip = &txx9_priv->chip; 324 mtd = nand_to_mtd(chip); 325 mtd->dev.parent = &dev->dev; 326 327 chip->legacy.read_byte = txx9ndfmc_read_byte; 328 chip->legacy.read_buf = txx9ndfmc_read_buf; 329 chip->legacy.write_buf = txx9ndfmc_write_buf; 330 chip->legacy.cmd_ctrl = txx9ndfmc_cmd_ctrl; 331 chip->legacy.dev_ready = txx9ndfmc_dev_ready; 332 chip->ecc.calculate = txx9ndfmc_calculate_ecc; 333 chip->ecc.correct = txx9ndfmc_correct_data; 334 chip->ecc.hwctl = txx9ndfmc_enable_hwecc; 335 chip->ecc.mode = NAND_ECC_HW; 336 chip->ecc.strength = 1; 337 chip->legacy.chip_delay = 100; 338 chip->controller = &drvdata->controller; 339 340 nand_set_controller_data(chip, txx9_priv); 341 txx9_priv->dev = dev; 342 343 if (plat->ch_mask != 1) { 344 txx9_priv->cs = i; 345 txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u", 346 dev_name(&dev->dev), i); 347 } else { 348 txx9_priv->cs = -1; 349 txx9_priv->mtdname = kstrdup(dev_name(&dev->dev), 350 GFP_KERNEL); 351 } 352 if (!txx9_priv->mtdname) { 353 kfree(txx9_priv); 354 dev_err(&dev->dev, "Unable to allocate MTD name.\n"); 355 continue; 356 } 357 if (plat->wide_mask & (1 << i)) 358 chip->options |= NAND_BUSWIDTH_16; 359 360 if (nand_scan(chip, 1)) { 361 kfree(txx9_priv->mtdname); 362 kfree(txx9_priv); 363 continue; 364 } 365 mtd->name = txx9_priv->mtdname; 366 367 mtd_device_register(mtd, NULL, 0); 368 drvdata->mtds[i] = mtd; 369 } 370 371 return 0; 372 } 373 374 static int __exit txx9ndfmc_remove(struct platform_device *dev) 375 { 376 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 377 int i; 378 379 if (!drvdata) 380 return 0; 381 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { 382 struct mtd_info *mtd = drvdata->mtds[i]; 383 struct nand_chip *chip; 384 struct txx9ndfmc_priv *txx9_priv; 385 386 if (!mtd) 387 continue; 388 chip = mtd_to_nand(mtd); 389 txx9_priv = nand_get_controller_data(chip); 390 391 nand_release(chip); 392 kfree(txx9_priv->mtdname); 393 kfree(txx9_priv); 394 } 395 return 0; 396 } 397 398 #ifdef CONFIG_PM 399 static int txx9ndfmc_resume(struct platform_device *dev) 400 { 401 if (platform_get_drvdata(dev)) 402 txx9ndfmc_initialize(dev); 403 return 0; 404 } 405 #else 406 #define txx9ndfmc_resume NULL 407 #endif 408 409 static struct platform_driver txx9ndfmc_driver = { 410 .remove = __exit_p(txx9ndfmc_remove), 411 .resume = txx9ndfmc_resume, 412 .driver = { 413 .name = "txx9ndfmc", 414 }, 415 }; 416 417 module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe); 418 419 MODULE_LICENSE("GPL"); 420 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver"); 421 MODULE_ALIAS("platform:txx9ndfmc"); 422