1 /* 2 * TXx9 NAND flash memory controller driver 3 * Based on RBTX49xx patch from CELF patch archive. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * (C) Copyright TOSHIBA CORPORATION 2004-2007 10 * All Rights Reserved. 11 */ 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/delay.h> 18 #include <linux/mtd/mtd.h> 19 #include <linux/mtd/rawnand.h> 20 #include <linux/mtd/nand_ecc.h> 21 #include <linux/mtd/partitions.h> 22 #include <linux/io.h> 23 #include <linux/platform_data/txx9/ndfmc.h> 24 25 /* TXX9 NDFMC Registers */ 26 #define TXX9_NDFDTR 0x00 27 #define TXX9_NDFMCR 0x04 28 #define TXX9_NDFSR 0x08 29 #define TXX9_NDFISR 0x0c 30 #define TXX9_NDFIMR 0x10 31 #define TXX9_NDFSPR 0x14 32 #define TXX9_NDFRSTR 0x18 /* not TX4939 */ 33 34 /* NDFMCR : NDFMC Mode Control */ 35 #define TXX9_NDFMCR_WE 0x80 36 #define TXX9_NDFMCR_ECC_ALL 0x60 37 #define TXX9_NDFMCR_ECC_RESET 0x60 38 #define TXX9_NDFMCR_ECC_READ 0x40 39 #define TXX9_NDFMCR_ECC_ON 0x20 40 #define TXX9_NDFMCR_ECC_OFF 0x00 41 #define TXX9_NDFMCR_CE 0x10 42 #define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */ 43 #define TXX9_NDFMCR_ALE 0x02 44 #define TXX9_NDFMCR_CLE 0x01 45 /* TX4939 only */ 46 #define TXX9_NDFMCR_X16 0x0400 47 #define TXX9_NDFMCR_DMAREQ_MASK 0x0300 48 #define TXX9_NDFMCR_DMAREQ_NODMA 0x0000 49 #define TXX9_NDFMCR_DMAREQ_128 0x0100 50 #define TXX9_NDFMCR_DMAREQ_256 0x0200 51 #define TXX9_NDFMCR_DMAREQ_512 0x0300 52 #define TXX9_NDFMCR_CS_MASK 0x0c 53 #define TXX9_NDFMCR_CS(ch) ((ch) << 2) 54 55 /* NDFMCR : NDFMC Status */ 56 #define TXX9_NDFSR_BUSY 0x80 57 /* TX4939 only */ 58 #define TXX9_NDFSR_DMARUN 0x40 59 60 /* NDFMCR : NDFMC Reset */ 61 #define TXX9_NDFRSTR_RST 0x01 62 63 struct txx9ndfmc_priv { 64 struct platform_device *dev; 65 struct nand_chip chip; 66 int cs; 67 const char *mtdname; 68 }; 69 70 #define MAX_TXX9NDFMC_DEV 4 71 struct txx9ndfmc_drvdata { 72 struct mtd_info *mtds[MAX_TXX9NDFMC_DEV]; 73 void __iomem *base; 74 unsigned char hold; /* in gbusclock */ 75 unsigned char spw; /* in gbusclock */ 76 struct nand_controller controller; 77 }; 78 79 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd) 80 { 81 struct nand_chip *chip = mtd_to_nand(mtd); 82 struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip); 83 return txx9_priv->dev; 84 } 85 86 static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg) 87 { 88 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 89 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 90 91 return drvdata->base + (reg << plat->shift); 92 } 93 94 static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg) 95 { 96 return __raw_readl(ndregaddr(dev, reg)); 97 } 98 99 static void txx9ndfmc_write(struct platform_device *dev, 100 u32 val, unsigned int reg) 101 { 102 __raw_writel(val, ndregaddr(dev, reg)); 103 } 104 105 static uint8_t txx9ndfmc_read_byte(struct nand_chip *chip) 106 { 107 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 108 109 return txx9ndfmc_read(dev, TXX9_NDFDTR); 110 } 111 112 static void txx9ndfmc_write_buf(struct nand_chip *chip, const uint8_t *buf, 113 int len) 114 { 115 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 116 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); 117 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 118 119 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); 120 while (len--) 121 __raw_writel(*buf++, ndfdtr); 122 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); 123 } 124 125 static void txx9ndfmc_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 126 { 127 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 128 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); 129 130 while (len--) 131 *buf++ = __raw_readl(ndfdtr); 132 } 133 134 static void txx9ndfmc_cmd_ctrl(struct nand_chip *chip, int cmd, 135 unsigned int ctrl) 136 { 137 struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip); 138 struct platform_device *dev = txx9_priv->dev; 139 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 140 141 if (ctrl & NAND_CTRL_CHANGE) { 142 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 143 144 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); 145 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; 146 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; 147 /* TXX9_NDFMCR_CE bit is 0:high 1:low */ 148 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; 149 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) { 150 mcr &= ~TXX9_NDFMCR_CS_MASK; 151 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs); 152 } 153 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); 154 } 155 if (cmd != NAND_CMD_NONE) 156 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR); 157 if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) { 158 /* dummy write to update external latch */ 159 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE) 160 txx9ndfmc_write(dev, 0, TXX9_NDFDTR); 161 } 162 mmiowb(); 163 } 164 165 static int txx9ndfmc_dev_ready(struct nand_chip *chip) 166 { 167 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 168 169 return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY); 170 } 171 172 static int txx9ndfmc_calculate_ecc(struct nand_chip *chip, const uint8_t *dat, 173 uint8_t *ecc_code) 174 { 175 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 176 int eccbytes; 177 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 178 179 mcr &= ~TXX9_NDFMCR_ECC_ALL; 180 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 181 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR); 182 for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) { 183 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR); 184 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR); 185 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR); 186 ecc_code += 3; 187 } 188 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 189 return 0; 190 } 191 192 static int txx9ndfmc_correct_data(struct nand_chip *chip, unsigned char *buf, 193 unsigned char *read_ecc, 194 unsigned char *calc_ecc) 195 { 196 int eccsize; 197 int corrected = 0; 198 int stat; 199 200 for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) { 201 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256, 202 false); 203 if (stat < 0) 204 return stat; 205 corrected += stat; 206 buf += 256; 207 read_ecc += 3; 208 calc_ecc += 3; 209 } 210 return corrected; 211 } 212 213 static void txx9ndfmc_enable_hwecc(struct nand_chip *chip, int mode) 214 { 215 struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip)); 216 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 217 218 mcr &= ~TXX9_NDFMCR_ECC_ALL; 219 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR); 220 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 221 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR); 222 } 223 224 static void txx9ndfmc_initialize(struct platform_device *dev) 225 { 226 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 227 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 228 int tmout = 100; 229 230 if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR) 231 ; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */ 232 else { 233 /* reset NDFMC */ 234 txx9ndfmc_write(dev, 235 txx9ndfmc_read(dev, TXX9_NDFRSTR) | 236 TXX9_NDFRSTR_RST, 237 TXX9_NDFRSTR); 238 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) { 239 if (--tmout == 0) { 240 dev_err(&dev->dev, "reset failed.\n"); 241 break; 242 } 243 udelay(1); 244 } 245 } 246 /* setup Hold Time, Strobe Pulse Width */ 247 txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR); 248 txx9ndfmc_write(dev, 249 (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ? 250 TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR); 251 } 252 253 #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \ 254 DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000) 255 256 static int txx9ndfmc_attach_chip(struct nand_chip *chip) 257 { 258 struct mtd_info *mtd = nand_to_mtd(chip); 259 260 if (mtd->writesize >= 512) { 261 chip->ecc.size = 512; 262 chip->ecc.bytes = 6; 263 } else { 264 chip->ecc.size = 256; 265 chip->ecc.bytes = 3; 266 } 267 268 return 0; 269 } 270 271 static const struct nand_controller_ops txx9ndfmc_controller_ops = { 272 .attach_chip = txx9ndfmc_attach_chip, 273 }; 274 275 static int __init txx9ndfmc_probe(struct platform_device *dev) 276 { 277 struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); 278 int hold, spw; 279 int i; 280 struct txx9ndfmc_drvdata *drvdata; 281 unsigned long gbusclk = plat->gbus_clock; 282 struct resource *res; 283 284 drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL); 285 if (!drvdata) 286 return -ENOMEM; 287 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 288 drvdata->base = devm_ioremap_resource(&dev->dev, res); 289 if (IS_ERR(drvdata->base)) 290 return PTR_ERR(drvdata->base); 291 292 hold = plat->hold ?: 20; /* tDH */ 293 spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */ 294 295 hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold); 296 spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw); 297 if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD) 298 hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */ 299 spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */ 300 hold = clamp(hold, 1, 15); 301 drvdata->hold = hold; 302 spw = clamp(spw, 1, 15); 303 drvdata->spw = spw; 304 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", 305 (gbusclk + 500000) / 1000000, hold, spw); 306 307 nand_controller_init(&drvdata->controller); 308 drvdata->controller.ops = &txx9ndfmc_controller_ops; 309 310 platform_set_drvdata(dev, drvdata); 311 txx9ndfmc_initialize(dev); 312 313 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { 314 struct txx9ndfmc_priv *txx9_priv; 315 struct nand_chip *chip; 316 struct mtd_info *mtd; 317 318 if (!(plat->ch_mask & (1 << i))) 319 continue; 320 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv), 321 GFP_KERNEL); 322 if (!txx9_priv) 323 continue; 324 chip = &txx9_priv->chip; 325 mtd = nand_to_mtd(chip); 326 mtd->dev.parent = &dev->dev; 327 328 chip->legacy.read_byte = txx9ndfmc_read_byte; 329 chip->legacy.read_buf = txx9ndfmc_read_buf; 330 chip->legacy.write_buf = txx9ndfmc_write_buf; 331 chip->legacy.cmd_ctrl = txx9ndfmc_cmd_ctrl; 332 chip->legacy.dev_ready = txx9ndfmc_dev_ready; 333 chip->ecc.calculate = txx9ndfmc_calculate_ecc; 334 chip->ecc.correct = txx9ndfmc_correct_data; 335 chip->ecc.hwctl = txx9ndfmc_enable_hwecc; 336 chip->ecc.mode = NAND_ECC_HW; 337 chip->ecc.strength = 1; 338 chip->legacy.chip_delay = 100; 339 chip->controller = &drvdata->controller; 340 341 nand_set_controller_data(chip, txx9_priv); 342 txx9_priv->dev = dev; 343 344 if (plat->ch_mask != 1) { 345 txx9_priv->cs = i; 346 txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u", 347 dev_name(&dev->dev), i); 348 } else { 349 txx9_priv->cs = -1; 350 txx9_priv->mtdname = kstrdup(dev_name(&dev->dev), 351 GFP_KERNEL); 352 } 353 if (!txx9_priv->mtdname) { 354 kfree(txx9_priv); 355 dev_err(&dev->dev, "Unable to allocate MTD name.\n"); 356 continue; 357 } 358 if (plat->wide_mask & (1 << i)) 359 chip->options |= NAND_BUSWIDTH_16; 360 361 if (nand_scan(chip, 1)) { 362 kfree(txx9_priv->mtdname); 363 kfree(txx9_priv); 364 continue; 365 } 366 mtd->name = txx9_priv->mtdname; 367 368 mtd_device_register(mtd, NULL, 0); 369 drvdata->mtds[i] = mtd; 370 } 371 372 return 0; 373 } 374 375 static int __exit txx9ndfmc_remove(struct platform_device *dev) 376 { 377 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 378 int i; 379 380 if (!drvdata) 381 return 0; 382 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { 383 struct mtd_info *mtd = drvdata->mtds[i]; 384 struct nand_chip *chip; 385 struct txx9ndfmc_priv *txx9_priv; 386 387 if (!mtd) 388 continue; 389 chip = mtd_to_nand(mtd); 390 txx9_priv = nand_get_controller_data(chip); 391 392 nand_release(chip); 393 kfree(txx9_priv->mtdname); 394 kfree(txx9_priv); 395 } 396 return 0; 397 } 398 399 #ifdef CONFIG_PM 400 static int txx9ndfmc_resume(struct platform_device *dev) 401 { 402 if (platform_get_drvdata(dev)) 403 txx9ndfmc_initialize(dev); 404 return 0; 405 } 406 #else 407 #define txx9ndfmc_resume NULL 408 #endif 409 410 static struct platform_driver txx9ndfmc_driver = { 411 .remove = __exit_p(txx9ndfmc_remove), 412 .resume = txx9ndfmc_resume, 413 .driver = { 414 .name = "txx9ndfmc", 415 }, 416 }; 417 418 module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe); 419 420 MODULE_LICENSE("GPL"); 421 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver"); 422 MODULE_ALIAS("platform:txx9ndfmc"); 423