1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2018
4  * Author: Christophe Kerello <christophe.kerello@st.com>
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/errno.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/of_address.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/reset.h>
22 
23 /* Bad block marker length */
24 #define FMC2_BBM_LEN			2
25 
26 /* ECC step size */
27 #define FMC2_ECC_STEP_SIZE		512
28 
29 /* BCHDSRx registers length */
30 #define FMC2_BCHDSRS_LEN		20
31 
32 /* HECCR length */
33 #define FMC2_HECCR_LEN			4
34 
35 /* Max requests done for a 8k nand page size */
36 #define FMC2_MAX_SG			16
37 
38 /* Max chip enable */
39 #define FMC2_MAX_CE			2
40 
41 /* Max ECC buffer length */
42 #define FMC2_MAX_ECC_BUF_LEN		(FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
43 
44 #define FMC2_TIMEOUT_MS			5000
45 
46 /* Timings */
47 #define FMC2_THIZ			1
48 #define FMC2_TIO			8000
49 #define FMC2_TSYNC			3000
50 #define FMC2_PCR_TIMING_MASK		0xf
51 #define FMC2_PMEM_PATT_TIMING_MASK	0xff
52 
53 /* FMC2 Controller Registers */
54 #define FMC2_BCR1			0x0
55 #define FMC2_PCR			0x80
56 #define FMC2_SR				0x84
57 #define FMC2_PMEM			0x88
58 #define FMC2_PATT			0x8c
59 #define FMC2_HECCR			0x94
60 #define FMC2_ISR			0x184
61 #define FMC2_ICR			0x188
62 #define FMC2_CSQCR			0x200
63 #define FMC2_CSQCFGR1			0x204
64 #define FMC2_CSQCFGR2			0x208
65 #define FMC2_CSQCFGR3			0x20c
66 #define FMC2_CSQAR1			0x210
67 #define FMC2_CSQAR2			0x214
68 #define FMC2_CSQIER			0x220
69 #define FMC2_CSQISR			0x224
70 #define FMC2_CSQICR			0x228
71 #define FMC2_CSQEMSR			0x230
72 #define FMC2_BCHIER			0x250
73 #define FMC2_BCHISR			0x254
74 #define FMC2_BCHICR			0x258
75 #define FMC2_BCHPBR1			0x260
76 #define FMC2_BCHPBR2			0x264
77 #define FMC2_BCHPBR3			0x268
78 #define FMC2_BCHPBR4			0x26c
79 #define FMC2_BCHDSR0			0x27c
80 #define FMC2_BCHDSR1			0x280
81 #define FMC2_BCHDSR2			0x284
82 #define FMC2_BCHDSR3			0x288
83 #define FMC2_BCHDSR4			0x28c
84 
85 /* Register: FMC2_BCR1 */
86 #define FMC2_BCR1_FMC2EN		BIT(31)
87 
88 /* Register: FMC2_PCR */
89 #define FMC2_PCR_PWAITEN		BIT(1)
90 #define FMC2_PCR_PBKEN			BIT(2)
91 #define FMC2_PCR_PWID			GENMASK(5, 4)
92 #define FMC2_PCR_PWID_BUSWIDTH_8	0
93 #define FMC2_PCR_PWID_BUSWIDTH_16	1
94 #define FMC2_PCR_ECCEN			BIT(6)
95 #define FMC2_PCR_ECCALG			BIT(8)
96 #define FMC2_PCR_TCLR			GENMASK(12, 9)
97 #define FMC2_PCR_TCLR_DEFAULT		0xf
98 #define FMC2_PCR_TAR			GENMASK(16, 13)
99 #define FMC2_PCR_TAR_DEFAULT		0xf
100 #define FMC2_PCR_ECCSS			GENMASK(19, 17)
101 #define FMC2_PCR_ECCSS_512		1
102 #define FMC2_PCR_ECCSS_2048		3
103 #define FMC2_PCR_BCHECC			BIT(24)
104 #define FMC2_PCR_WEN			BIT(25)
105 
106 /* Register: FMC2_SR */
107 #define FMC2_SR_NWRF			BIT(6)
108 
109 /* Register: FMC2_PMEM */
110 #define FMC2_PMEM_MEMSET		GENMASK(7, 0)
111 #define FMC2_PMEM_MEMWAIT		GENMASK(15, 8)
112 #define FMC2_PMEM_MEMHOLD		GENMASK(23, 16)
113 #define FMC2_PMEM_MEMHIZ		GENMASK(31, 24)
114 #define FMC2_PMEM_DEFAULT		0x0a0a0a0a
115 
116 /* Register: FMC2_PATT */
117 #define FMC2_PATT_ATTSET		GENMASK(7, 0)
118 #define FMC2_PATT_ATTWAIT		GENMASK(15, 8)
119 #define FMC2_PATT_ATTHOLD		GENMASK(23, 16)
120 #define FMC2_PATT_ATTHIZ		GENMASK(31, 24)
121 #define FMC2_PATT_DEFAULT		0x0a0a0a0a
122 
123 /* Register: FMC2_ISR */
124 #define FMC2_ISR_IHLF			BIT(1)
125 
126 /* Register: FMC2_ICR */
127 #define FMC2_ICR_CIHLF			BIT(1)
128 
129 /* Register: FMC2_CSQCR */
130 #define FMC2_CSQCR_CSQSTART		BIT(0)
131 
132 /* Register: FMC2_CSQCFGR1 */
133 #define FMC2_CSQCFGR1_CMD2EN		BIT(1)
134 #define FMC2_CSQCFGR1_DMADEN		BIT(2)
135 #define FMC2_CSQCFGR1_ACYNBR		GENMASK(6, 4)
136 #define FMC2_CSQCFGR1_CMD1		GENMASK(15, 8)
137 #define FMC2_CSQCFGR1_CMD2		GENMASK(23, 16)
138 #define FMC2_CSQCFGR1_CMD1T		BIT(24)
139 #define FMC2_CSQCFGR1_CMD2T		BIT(25)
140 
141 /* Register: FMC2_CSQCFGR2 */
142 #define FMC2_CSQCFGR2_SQSDTEN		BIT(0)
143 #define FMC2_CSQCFGR2_RCMD2EN		BIT(1)
144 #define FMC2_CSQCFGR2_DMASEN		BIT(2)
145 #define FMC2_CSQCFGR2_RCMD1		GENMASK(15, 8)
146 #define FMC2_CSQCFGR2_RCMD2		GENMASK(23, 16)
147 #define FMC2_CSQCFGR2_RCMD1T		BIT(24)
148 #define FMC2_CSQCFGR2_RCMD2T		BIT(25)
149 
150 /* Register: FMC2_CSQCFGR3 */
151 #define FMC2_CSQCFGR3_SNBR		GENMASK(13, 8)
152 #define FMC2_CSQCFGR3_AC1T		BIT(16)
153 #define FMC2_CSQCFGR3_AC2T		BIT(17)
154 #define FMC2_CSQCFGR3_AC3T		BIT(18)
155 #define FMC2_CSQCFGR3_AC4T		BIT(19)
156 #define FMC2_CSQCFGR3_AC5T		BIT(20)
157 #define FMC2_CSQCFGR3_SDT		BIT(21)
158 #define FMC2_CSQCFGR3_RAC1T		BIT(22)
159 #define FMC2_CSQCFGR3_RAC2T		BIT(23)
160 
161 /* Register: FMC2_CSQCAR1 */
162 #define FMC2_CSQCAR1_ADDC1		GENMASK(7, 0)
163 #define FMC2_CSQCAR1_ADDC2		GENMASK(15, 8)
164 #define FMC2_CSQCAR1_ADDC3		GENMASK(23, 16)
165 #define FMC2_CSQCAR1_ADDC4		GENMASK(31, 24)
166 
167 /* Register: FMC2_CSQCAR2 */
168 #define FMC2_CSQCAR2_ADDC5		GENMASK(7, 0)
169 #define FMC2_CSQCAR2_NANDCEN		GENMASK(11, 10)
170 #define FMC2_CSQCAR2_SAO		GENMASK(31, 16)
171 
172 /* Register: FMC2_CSQIER */
173 #define FMC2_CSQIER_TCIE		BIT(0)
174 
175 /* Register: FMC2_CSQICR */
176 #define FMC2_CSQICR_CLEAR_IRQ		GENMASK(4, 0)
177 
178 /* Register: FMC2_CSQEMSR */
179 #define FMC2_CSQEMSR_SEM		GENMASK(15, 0)
180 
181 /* Register: FMC2_BCHIER */
182 #define FMC2_BCHIER_DERIE		BIT(1)
183 #define FMC2_BCHIER_EPBRIE		BIT(4)
184 
185 /* Register: FMC2_BCHICR */
186 #define FMC2_BCHICR_CLEAR_IRQ		GENMASK(4, 0)
187 
188 /* Register: FMC2_BCHDSR0 */
189 #define FMC2_BCHDSR0_DUE		BIT(0)
190 #define FMC2_BCHDSR0_DEF		BIT(1)
191 #define FMC2_BCHDSR0_DEN		GENMASK(7, 4)
192 
193 /* Register: FMC2_BCHDSR1 */
194 #define FMC2_BCHDSR1_EBP1		GENMASK(12, 0)
195 #define FMC2_BCHDSR1_EBP2		GENMASK(28, 16)
196 
197 /* Register: FMC2_BCHDSR2 */
198 #define FMC2_BCHDSR2_EBP3		GENMASK(12, 0)
199 #define FMC2_BCHDSR2_EBP4		GENMASK(28, 16)
200 
201 /* Register: FMC2_BCHDSR3 */
202 #define FMC2_BCHDSR3_EBP5		GENMASK(12, 0)
203 #define FMC2_BCHDSR3_EBP6		GENMASK(28, 16)
204 
205 /* Register: FMC2_BCHDSR4 */
206 #define FMC2_BCHDSR4_EBP7		GENMASK(12, 0)
207 #define FMC2_BCHDSR4_EBP8		GENMASK(28, 16)
208 
209 enum stm32_fmc2_ecc {
210 	FMC2_ECC_HAM = 1,
211 	FMC2_ECC_BCH4 = 4,
212 	FMC2_ECC_BCH8 = 8
213 };
214 
215 enum stm32_fmc2_irq_state {
216 	FMC2_IRQ_UNKNOWN = 0,
217 	FMC2_IRQ_BCH,
218 	FMC2_IRQ_SEQ
219 };
220 
221 struct stm32_fmc2_timings {
222 	u8 tclr;
223 	u8 tar;
224 	u8 thiz;
225 	u8 twait;
226 	u8 thold_mem;
227 	u8 tset_mem;
228 	u8 thold_att;
229 	u8 tset_att;
230 };
231 
232 struct stm32_fmc2_nand {
233 	struct nand_chip chip;
234 	struct stm32_fmc2_timings timings;
235 	int ncs;
236 	int cs_used[FMC2_MAX_CE];
237 };
238 
239 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
240 {
241 	return container_of(chip, struct stm32_fmc2_nand, chip);
242 }
243 
244 struct stm32_fmc2_nfc {
245 	struct nand_controller base;
246 	struct stm32_fmc2_nand nand;
247 	struct device *dev;
248 	struct device *cdev;
249 	struct regmap *regmap;
250 	void __iomem *data_base[FMC2_MAX_CE];
251 	void __iomem *cmd_base[FMC2_MAX_CE];
252 	void __iomem *addr_base[FMC2_MAX_CE];
253 	phys_addr_t io_phys_addr;
254 	phys_addr_t data_phys_addr[FMC2_MAX_CE];
255 	struct clk *clk;
256 	u8 irq_state;
257 
258 	struct dma_chan *dma_tx_ch;
259 	struct dma_chan *dma_rx_ch;
260 	struct dma_chan *dma_ecc_ch;
261 	struct sg_table dma_data_sg;
262 	struct sg_table dma_ecc_sg;
263 	u8 *ecc_buf;
264 	int dma_ecc_len;
265 
266 	struct completion complete;
267 	struct completion dma_data_complete;
268 	struct completion dma_ecc_complete;
269 
270 	u8 cs_assigned;
271 	int cs_sel;
272 };
273 
274 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
275 {
276 	return container_of(base, struct stm32_fmc2_nfc, base);
277 }
278 
279 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
280 {
281 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
282 	struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
283 	struct stm32_fmc2_timings *timings = &nand->timings;
284 	u32 pmem, patt;
285 
286 	/* Set tclr/tar timings */
287 	regmap_update_bits(nfc->regmap, FMC2_PCR,
288 			   FMC2_PCR_TCLR | FMC2_PCR_TAR,
289 			   FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
290 			   FIELD_PREP(FMC2_PCR_TAR, timings->tar));
291 
292 	/* Set tset/twait/thold/thiz timings in common bank */
293 	pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
294 	pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
295 	pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
296 	pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
297 	regmap_write(nfc->regmap, FMC2_PMEM, pmem);
298 
299 	/* Set tset/twait/thold/thiz timings in attribut bank */
300 	patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
301 	patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
302 	patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
303 	patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
304 	regmap_write(nfc->regmap, FMC2_PATT, patt);
305 }
306 
307 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
308 {
309 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
310 	u32 pcr = 0, pcr_mask;
311 
312 	/* Configure ECC algorithm (default configuration is Hamming) */
313 	pcr_mask = FMC2_PCR_ECCALG;
314 	pcr_mask |= FMC2_PCR_BCHECC;
315 	if (chip->ecc.strength == FMC2_ECC_BCH8) {
316 		pcr |= FMC2_PCR_ECCALG;
317 		pcr |= FMC2_PCR_BCHECC;
318 	} else if (chip->ecc.strength == FMC2_ECC_BCH4) {
319 		pcr |= FMC2_PCR_ECCALG;
320 	}
321 
322 	/* Set buswidth */
323 	pcr_mask |= FMC2_PCR_PWID;
324 	if (chip->options & NAND_BUSWIDTH_16)
325 		pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
326 
327 	/* Set ECC sector size */
328 	pcr_mask |= FMC2_PCR_ECCSS;
329 	pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
330 
331 	regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
332 }
333 
334 static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
335 {
336 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
337 	struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
338 	struct dma_slave_config dma_cfg;
339 	int ret;
340 
341 	if (nand->cs_used[chipnr] == nfc->cs_sel)
342 		return 0;
343 
344 	nfc->cs_sel = nand->cs_used[chipnr];
345 	stm32_fmc2_nfc_setup(chip);
346 	stm32_fmc2_nfc_timings_init(chip);
347 
348 	if (nfc->dma_tx_ch && nfc->dma_rx_ch) {
349 		memset(&dma_cfg, 0, sizeof(dma_cfg));
350 		dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel];
351 		dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel];
352 		dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
353 		dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
354 		dma_cfg.src_maxburst = 32;
355 		dma_cfg.dst_maxburst = 32;
356 
357 		ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg);
358 		if (ret) {
359 			dev_err(nfc->dev, "tx DMA engine slave config failed\n");
360 			return ret;
361 		}
362 
363 		ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg);
364 		if (ret) {
365 			dev_err(nfc->dev, "rx DMA engine slave config failed\n");
366 			return ret;
367 		}
368 	}
369 
370 	if (nfc->dma_ecc_ch) {
371 		/*
372 		 * Hamming: we read HECCR register
373 		 * BCH4/BCH8: we read BCHDSRSx registers
374 		 */
375 		memset(&dma_cfg, 0, sizeof(dma_cfg));
376 		dma_cfg.src_addr = nfc->io_phys_addr;
377 		dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ?
378 				    FMC2_HECCR : FMC2_BCHDSR0;
379 		dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
380 
381 		ret = dmaengine_slave_config(nfc->dma_ecc_ch, &dma_cfg);
382 		if (ret) {
383 			dev_err(nfc->dev, "ECC DMA engine slave config failed\n");
384 			return ret;
385 		}
386 
387 		/* Calculate ECC length needed for one sector */
388 		nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
389 				   FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN;
390 	}
391 
392 	return 0;
393 }
394 
395 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
396 {
397 	u32 pcr;
398 
399 	pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
400 		    FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
401 
402 	regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
403 }
404 
405 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
406 {
407 	regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
408 			   enable ? FMC2_PCR_ECCEN : 0);
409 }
410 
411 static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
412 {
413 	nfc->irq_state = FMC2_IRQ_SEQ;
414 
415 	regmap_update_bits(nfc->regmap, FMC2_CSQIER,
416 			   FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE);
417 }
418 
419 static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
420 {
421 	regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0);
422 
423 	nfc->irq_state = FMC2_IRQ_UNKNOWN;
424 }
425 
426 static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
427 {
428 	regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ);
429 }
430 
431 static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode)
432 {
433 	nfc->irq_state = FMC2_IRQ_BCH;
434 
435 	if (mode == NAND_ECC_WRITE)
436 		regmap_update_bits(nfc->regmap, FMC2_BCHIER,
437 				   FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE);
438 	else
439 		regmap_update_bits(nfc->regmap, FMC2_BCHIER,
440 				   FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE);
441 }
442 
443 static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
444 {
445 	regmap_update_bits(nfc->regmap, FMC2_BCHIER,
446 			   FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, 0);
447 
448 	nfc->irq_state = FMC2_IRQ_UNKNOWN;
449 }
450 
451 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
452 {
453 	regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
454 }
455 
456 /*
457  * Enable ECC logic and reset syndrome/parity bits previously calculated
458  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
459  */
460 static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode)
461 {
462 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
463 
464 	stm32_fmc2_nfc_set_ecc(nfc, false);
465 
466 	if (chip->ecc.strength != FMC2_ECC_HAM) {
467 		regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
468 				   mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
469 
470 		reinit_completion(&nfc->complete);
471 		stm32_fmc2_nfc_clear_bch_irq(nfc);
472 		stm32_fmc2_nfc_enable_bch_irq(nfc, mode);
473 	}
474 
475 	stm32_fmc2_nfc_set_ecc(nfc, true);
476 }
477 
478 /*
479  * ECC Hamming calculation
480  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
481  * max of 1-bit)
482  */
483 static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
484 {
485 	ecc[0] = ecc_sta;
486 	ecc[1] = ecc_sta >> 8;
487 	ecc[2] = ecc_sta >> 16;
488 }
489 
490 static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data,
491 					u8 *ecc)
492 {
493 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
494 	u32 sr, heccr;
495 	int ret;
496 
497 	ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
498 				       sr & FMC2_SR_NWRF, 1,
499 				       1000 * FMC2_TIMEOUT_MS);
500 	if (ret) {
501 		dev_err(nfc->dev, "ham timeout\n");
502 		return ret;
503 	}
504 
505 	regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
506 	stm32_fmc2_nfc_ham_set_ecc(heccr, ecc);
507 	stm32_fmc2_nfc_set_ecc(nfc, false);
508 
509 	return 0;
510 }
511 
512 static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat,
513 				      u8 *read_ecc, u8 *calc_ecc)
514 {
515 	u8 bit_position = 0, b0, b1, b2;
516 	u32 byte_addr = 0, b;
517 	u32 i, shifting = 1;
518 
519 	/* Indicate which bit and byte is faulty (if any) */
520 	b0 = read_ecc[0] ^ calc_ecc[0];
521 	b1 = read_ecc[1] ^ calc_ecc[1];
522 	b2 = read_ecc[2] ^ calc_ecc[2];
523 	b = b0 | (b1 << 8) | (b2 << 16);
524 
525 	/* No errors */
526 	if (likely(!b))
527 		return 0;
528 
529 	/* Calculate bit position */
530 	for (i = 0; i < 3; i++) {
531 		switch (b % 4) {
532 		case 2:
533 			bit_position += shifting;
534 			break;
535 		case 1:
536 			break;
537 		default:
538 			return -EBADMSG;
539 		}
540 		shifting <<= 1;
541 		b >>= 2;
542 	}
543 
544 	/* Calculate byte position */
545 	shifting = 1;
546 	for (i = 0; i < 9; i++) {
547 		switch (b % 4) {
548 		case 2:
549 			byte_addr += shifting;
550 			break;
551 		case 1:
552 			break;
553 		default:
554 			return -EBADMSG;
555 		}
556 		shifting <<= 1;
557 		b >>= 2;
558 	}
559 
560 	/* Flip the bit */
561 	dat[byte_addr] ^= (1 << bit_position);
562 
563 	return 1;
564 }
565 
566 /*
567  * ECC BCH calculation and correction
568  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
569  * max of 4-bit/8-bit)
570  */
571 static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data,
572 					u8 *ecc)
573 {
574 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
575 	u32 bchpbr;
576 
577 	/* Wait until the BCH code is ready */
578 	if (!wait_for_completion_timeout(&nfc->complete,
579 					 msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
580 		dev_err(nfc->dev, "bch timeout\n");
581 		stm32_fmc2_nfc_disable_bch_irq(nfc);
582 		return -ETIMEDOUT;
583 	}
584 
585 	/* Read parity bits */
586 	regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
587 	ecc[0] = bchpbr;
588 	ecc[1] = bchpbr >> 8;
589 	ecc[2] = bchpbr >> 16;
590 	ecc[3] = bchpbr >> 24;
591 
592 	regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
593 	ecc[4] = bchpbr;
594 	ecc[5] = bchpbr >> 8;
595 	ecc[6] = bchpbr >> 16;
596 
597 	if (chip->ecc.strength == FMC2_ECC_BCH8) {
598 		ecc[7] = bchpbr >> 24;
599 
600 		regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
601 		ecc[8] = bchpbr;
602 		ecc[9] = bchpbr >> 8;
603 		ecc[10] = bchpbr >> 16;
604 		ecc[11] = bchpbr >> 24;
605 
606 		regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
607 		ecc[12] = bchpbr;
608 	}
609 
610 	stm32_fmc2_nfc_set_ecc(nfc, false);
611 
612 	return 0;
613 }
614 
615 static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
616 {
617 	u32 bchdsr0 = ecc_sta[0];
618 	u32 bchdsr1 = ecc_sta[1];
619 	u32 bchdsr2 = ecc_sta[2];
620 	u32 bchdsr3 = ecc_sta[3];
621 	u32 bchdsr4 = ecc_sta[4];
622 	u16 pos[8];
623 	int i, den;
624 	unsigned int nb_errs = 0;
625 
626 	/* No errors found */
627 	if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
628 		return 0;
629 
630 	/* Too many errors detected */
631 	if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
632 		return -EBADMSG;
633 
634 	pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
635 	pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
636 	pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
637 	pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
638 	pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
639 	pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
640 	pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
641 	pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
642 
643 	den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
644 	for (i = 0; i < den; i++) {
645 		if (pos[i] < eccsize * 8) {
646 			change_bit(pos[i], (unsigned long *)dat);
647 			nb_errs++;
648 		}
649 	}
650 
651 	return nb_errs;
652 }
653 
654 static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat,
655 				      u8 *read_ecc, u8 *calc_ecc)
656 {
657 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
658 	u32 ecc_sta[5];
659 
660 	/* Wait until the decoding error is ready */
661 	if (!wait_for_completion_timeout(&nfc->complete,
662 					 msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
663 		dev_err(nfc->dev, "bch timeout\n");
664 		stm32_fmc2_nfc_disable_bch_irq(nfc);
665 		return -ETIMEDOUT;
666 	}
667 
668 	regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
669 
670 	stm32_fmc2_nfc_set_ecc(nfc, false);
671 
672 	return stm32_fmc2_nfc_bch_decode(chip->ecc.size, dat, ecc_sta);
673 }
674 
675 static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf,
676 				    int oob_required, int page)
677 {
678 	struct mtd_info *mtd = nand_to_mtd(chip);
679 	int ret, i, s, stat, eccsize = chip->ecc.size;
680 	int eccbytes = chip->ecc.bytes;
681 	int eccsteps = chip->ecc.steps;
682 	int eccstrength = chip->ecc.strength;
683 	u8 *p = buf;
684 	u8 *ecc_calc = chip->ecc.calc_buf;
685 	u8 *ecc_code = chip->ecc.code_buf;
686 	unsigned int max_bitflips = 0;
687 
688 	ret = nand_read_page_op(chip, page, 0, NULL, 0);
689 	if (ret)
690 		return ret;
691 
692 	for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
693 	     s++, i += eccbytes, p += eccsize) {
694 		chip->ecc.hwctl(chip, NAND_ECC_READ);
695 
696 		/* Read the nand page sector (512 bytes) */
697 		ret = nand_change_read_column_op(chip, s * eccsize, p,
698 						 eccsize, false);
699 		if (ret)
700 			return ret;
701 
702 		/* Read the corresponding ECC bytes */
703 		ret = nand_change_read_column_op(chip, i, ecc_code,
704 						 eccbytes, false);
705 		if (ret)
706 			return ret;
707 
708 		/* Correct the data */
709 		stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
710 		if (stat == -EBADMSG)
711 			/* Check for empty pages with bitflips */
712 			stat = nand_check_erased_ecc_chunk(p, eccsize,
713 							   ecc_code, eccbytes,
714 							   NULL, 0,
715 							   eccstrength);
716 
717 		if (stat < 0) {
718 			mtd->ecc_stats.failed++;
719 		} else {
720 			mtd->ecc_stats.corrected += stat;
721 			max_bitflips = max_t(unsigned int, max_bitflips, stat);
722 		}
723 	}
724 
725 	/* Read oob */
726 	if (oob_required) {
727 		ret = nand_change_read_column_op(chip, mtd->writesize,
728 						 chip->oob_poi, mtd->oobsize,
729 						 false);
730 		if (ret)
731 			return ret;
732 	}
733 
734 	return max_bitflips;
735 }
736 
737 /* Sequencer read/write configuration */
738 static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
739 					int raw, bool write_data)
740 {
741 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
742 	struct mtd_info *mtd = nand_to_mtd(chip);
743 	u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
744 	/*
745 	 * cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3
746 	 * cfg[3] => csqar1, cfg[4] => csqar2
747 	 */
748 	u32 cfg[5];
749 
750 	regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
751 			   write_data ? FMC2_PCR_WEN : 0);
752 
753 	/*
754 	 * - Set Program Page/Page Read command
755 	 * - Enable DMA request data
756 	 * - Set timings
757 	 */
758 	cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
759 	if (write_data)
760 		cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
761 	else
762 		cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
763 			  FMC2_CSQCFGR1_CMD2EN |
764 			  FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
765 			  FMC2_CSQCFGR1_CMD2T;
766 
767 	/*
768 	 * - Set Random Data Input/Random Data Read command
769 	 * - Enable the sequencer to access the Spare data area
770 	 * - Enable  DMA request status decoding for read
771 	 * - Set timings
772 	 */
773 	if (write_data)
774 		cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
775 	else
776 		cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
777 			 FMC2_CSQCFGR2_RCMD2EN |
778 			 FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) |
779 			 FMC2_CSQCFGR2_RCMD1T |
780 			 FMC2_CSQCFGR2_RCMD2T;
781 	if (!raw) {
782 		cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
783 		cfg[1] |= FMC2_CSQCFGR2_SQSDTEN;
784 	}
785 
786 	/*
787 	 * - Set the number of sectors to be written
788 	 * - Set timings
789 	 */
790 	cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
791 	if (write_data) {
792 		cfg[2] |= FMC2_CSQCFGR3_RAC2T;
793 		if (chip->options & NAND_ROW_ADDR_3)
794 			cfg[2] |= FMC2_CSQCFGR3_AC5T;
795 		else
796 			cfg[2] |= FMC2_CSQCFGR3_AC4T;
797 	}
798 
799 	/*
800 	 * Set the fourth first address cycles
801 	 * Byte 1 and byte 2 => column, we start at 0x0
802 	 * Byte 3 and byte 4 => page
803 	 */
804 	cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
805 	cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
806 
807 	/*
808 	 * - Set chip enable number
809 	 * - Set ECC byte offset in the spare area
810 	 * - Calculate the number of address cycles to be issued
811 	 * - Set byte 5 of address cycle if needed
812 	 */
813 	cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
814 	if (chip->options & NAND_BUSWIDTH_16)
815 		cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
816 	else
817 		cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
818 	if (chip->options & NAND_ROW_ADDR_3) {
819 		cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
820 		cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
821 	} else {
822 		cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
823 	}
824 
825 	regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5);
826 }
827 
828 static void stm32_fmc2_nfc_dma_callback(void *arg)
829 {
830 	complete((struct completion *)arg);
831 }
832 
833 /* Read/write data from/to a page */
834 static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf,
835 			       int raw, bool write_data)
836 {
837 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
838 	struct dma_async_tx_descriptor *desc_data, *desc_ecc;
839 	struct scatterlist *sg;
840 	struct dma_chan *dma_ch = nfc->dma_rx_ch;
841 	enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
842 	enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
843 	int eccsteps = chip->ecc.steps;
844 	int eccsize = chip->ecc.size;
845 	unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS);
846 	const u8 *p = buf;
847 	int s, ret;
848 
849 	/* Configure DMA data */
850 	if (write_data) {
851 		dma_data_dir = DMA_TO_DEVICE;
852 		dma_transfer_dir = DMA_MEM_TO_DEV;
853 		dma_ch = nfc->dma_tx_ch;
854 	}
855 
856 	for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) {
857 		sg_set_buf(sg, p, eccsize);
858 		p += eccsize;
859 	}
860 
861 	ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl,
862 			 eccsteps, dma_data_dir);
863 	if (ret < 0)
864 		return ret;
865 
866 	desc_data = dmaengine_prep_slave_sg(dma_ch, nfc->dma_data_sg.sgl,
867 					    eccsteps, dma_transfer_dir,
868 					    DMA_PREP_INTERRUPT);
869 	if (!desc_data) {
870 		ret = -ENOMEM;
871 		goto err_unmap_data;
872 	}
873 
874 	reinit_completion(&nfc->dma_data_complete);
875 	reinit_completion(&nfc->complete);
876 	desc_data->callback = stm32_fmc2_nfc_dma_callback;
877 	desc_data->callback_param = &nfc->dma_data_complete;
878 	ret = dma_submit_error(dmaengine_submit(desc_data));
879 	if (ret)
880 		goto err_unmap_data;
881 
882 	dma_async_issue_pending(dma_ch);
883 
884 	if (!write_data && !raw) {
885 		/* Configure DMA ECC status */
886 		p = nfc->ecc_buf;
887 		for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) {
888 			sg_set_buf(sg, p, nfc->dma_ecc_len);
889 			p += nfc->dma_ecc_len;
890 		}
891 
892 		ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
893 				 eccsteps, dma_data_dir);
894 		if (ret < 0)
895 			goto err_unmap_data;
896 
897 		desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch,
898 						   nfc->dma_ecc_sg.sgl,
899 						   eccsteps, dma_transfer_dir,
900 						   DMA_PREP_INTERRUPT);
901 		if (!desc_ecc) {
902 			ret = -ENOMEM;
903 			goto err_unmap_ecc;
904 		}
905 
906 		reinit_completion(&nfc->dma_ecc_complete);
907 		desc_ecc->callback = stm32_fmc2_nfc_dma_callback;
908 		desc_ecc->callback_param = &nfc->dma_ecc_complete;
909 		ret = dma_submit_error(dmaengine_submit(desc_ecc));
910 		if (ret)
911 			goto err_unmap_ecc;
912 
913 		dma_async_issue_pending(nfc->dma_ecc_ch);
914 	}
915 
916 	stm32_fmc2_nfc_clear_seq_irq(nfc);
917 	stm32_fmc2_nfc_enable_seq_irq(nfc);
918 
919 	/* Start the transfer */
920 	regmap_update_bits(nfc->regmap, FMC2_CSQCR,
921 			   FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART);
922 
923 	/* Wait end of sequencer transfer */
924 	if (!wait_for_completion_timeout(&nfc->complete, timeout)) {
925 		dev_err(nfc->dev, "seq timeout\n");
926 		stm32_fmc2_nfc_disable_seq_irq(nfc);
927 		dmaengine_terminate_all(dma_ch);
928 		if (!write_data && !raw)
929 			dmaengine_terminate_all(nfc->dma_ecc_ch);
930 		ret = -ETIMEDOUT;
931 		goto err_unmap_ecc;
932 	}
933 
934 	/* Wait DMA data transfer completion */
935 	if (!wait_for_completion_timeout(&nfc->dma_data_complete, timeout)) {
936 		dev_err(nfc->dev, "data DMA timeout\n");
937 		dmaengine_terminate_all(dma_ch);
938 		ret = -ETIMEDOUT;
939 	}
940 
941 	/* Wait DMA ECC transfer completion */
942 	if (!write_data && !raw) {
943 		if (!wait_for_completion_timeout(&nfc->dma_ecc_complete,
944 						 timeout)) {
945 			dev_err(nfc->dev, "ECC DMA timeout\n");
946 			dmaengine_terminate_all(nfc->dma_ecc_ch);
947 			ret = -ETIMEDOUT;
948 		}
949 	}
950 
951 err_unmap_ecc:
952 	if (!write_data && !raw)
953 		dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
954 			     eccsteps, dma_data_dir);
955 
956 err_unmap_data:
957 	dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir);
958 
959 	return ret;
960 }
961 
962 static int stm32_fmc2_nfc_seq_write(struct nand_chip *chip, const u8 *buf,
963 				    int oob_required, int page, int raw)
964 {
965 	struct mtd_info *mtd = nand_to_mtd(chip);
966 	int ret;
967 
968 	/* Configure the sequencer */
969 	stm32_fmc2_nfc_rw_page_init(chip, page, raw, true);
970 
971 	/* Write the page */
972 	ret = stm32_fmc2_nfc_xfer(chip, buf, raw, true);
973 	if (ret)
974 		return ret;
975 
976 	/* Write oob */
977 	if (oob_required) {
978 		ret = nand_change_write_column_op(chip, mtd->writesize,
979 						  chip->oob_poi, mtd->oobsize,
980 						  false);
981 		if (ret)
982 			return ret;
983 	}
984 
985 	return nand_prog_page_end_op(chip);
986 }
987 
988 static int stm32_fmc2_nfc_seq_write_page(struct nand_chip *chip, const u8 *buf,
989 					 int oob_required, int page)
990 {
991 	int ret;
992 
993 	ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
994 	if (ret)
995 		return ret;
996 
997 	return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, false);
998 }
999 
1000 static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip,
1001 					     const u8 *buf, int oob_required,
1002 					     int page)
1003 {
1004 	int ret;
1005 
1006 	ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1007 	if (ret)
1008 		return ret;
1009 
1010 	return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, true);
1011 }
1012 
1013 /* Get a status indicating which sectors have errors */
1014 static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
1015 {
1016 	u32 csqemsr;
1017 
1018 	regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr);
1019 
1020 	return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr);
1021 }
1022 
1023 static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat,
1024 				      u8 *read_ecc, u8 *calc_ecc)
1025 {
1026 	struct mtd_info *mtd = nand_to_mtd(chip);
1027 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1028 	int eccbytes = chip->ecc.bytes;
1029 	int eccsteps = chip->ecc.steps;
1030 	int eccstrength = chip->ecc.strength;
1031 	int i, s, eccsize = chip->ecc.size;
1032 	u32 *ecc_sta = (u32 *)nfc->ecc_buf;
1033 	u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1034 	unsigned int max_bitflips = 0;
1035 
1036 	for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) {
1037 		int stat = 0;
1038 
1039 		if (eccstrength == FMC2_ECC_HAM) {
1040 			/* Ecc_sta = FMC2_HECCR */
1041 			if (sta_map & BIT(s)) {
1042 				stm32_fmc2_nfc_ham_set_ecc(*ecc_sta,
1043 							   &calc_ecc[i]);
1044 				stat = stm32_fmc2_nfc_ham_correct(chip, dat,
1045 								  &read_ecc[i],
1046 								  &calc_ecc[i]);
1047 			}
1048 			ecc_sta++;
1049 		} else {
1050 			/*
1051 			 * Ecc_sta[0] = FMC2_BCHDSR0
1052 			 * Ecc_sta[1] = FMC2_BCHDSR1
1053 			 * Ecc_sta[2] = FMC2_BCHDSR2
1054 			 * Ecc_sta[3] = FMC2_BCHDSR3
1055 			 * Ecc_sta[4] = FMC2_BCHDSR4
1056 			 */
1057 			if (sta_map & BIT(s))
1058 				stat = stm32_fmc2_nfc_bch_decode(eccsize, dat,
1059 								 ecc_sta);
1060 			ecc_sta += 5;
1061 		}
1062 
1063 		if (stat == -EBADMSG)
1064 			/* Check for empty pages with bitflips */
1065 			stat = nand_check_erased_ecc_chunk(dat, eccsize,
1066 							   &read_ecc[i],
1067 							   eccbytes,
1068 							   NULL, 0,
1069 							   eccstrength);
1070 
1071 		if (stat < 0) {
1072 			mtd->ecc_stats.failed++;
1073 		} else {
1074 			mtd->ecc_stats.corrected += stat;
1075 			max_bitflips = max_t(unsigned int, max_bitflips, stat);
1076 		}
1077 	}
1078 
1079 	return max_bitflips;
1080 }
1081 
1082 static int stm32_fmc2_nfc_seq_read_page(struct nand_chip *chip, u8 *buf,
1083 					int oob_required, int page)
1084 {
1085 	struct mtd_info *mtd = nand_to_mtd(chip);
1086 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1087 	u8 *ecc_calc = chip->ecc.calc_buf;
1088 	u8 *ecc_code = chip->ecc.code_buf;
1089 	u16 sta_map;
1090 	int ret;
1091 
1092 	ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1093 	if (ret)
1094 		return ret;
1095 
1096 	/* Configure the sequencer */
1097 	stm32_fmc2_nfc_rw_page_init(chip, page, 0, false);
1098 
1099 	/* Read the page */
1100 	ret = stm32_fmc2_nfc_xfer(chip, buf, 0, false);
1101 	if (ret)
1102 		return ret;
1103 
1104 	sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1105 
1106 	/* Check if errors happen */
1107 	if (likely(!sta_map)) {
1108 		if (oob_required)
1109 			return nand_change_read_column_op(chip, mtd->writesize,
1110 							  chip->oob_poi,
1111 							  mtd->oobsize, false);
1112 
1113 		return 0;
1114 	}
1115 
1116 	/* Read oob */
1117 	ret = nand_change_read_column_op(chip, mtd->writesize,
1118 					 chip->oob_poi, mtd->oobsize, false);
1119 	if (ret)
1120 		return ret;
1121 
1122 	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1123 					 chip->ecc.total);
1124 	if (ret)
1125 		return ret;
1126 
1127 	/* Correct data */
1128 	return chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
1129 }
1130 
1131 static int stm32_fmc2_nfc_seq_read_page_raw(struct nand_chip *chip, u8 *buf,
1132 					    int oob_required, int page)
1133 {
1134 	struct mtd_info *mtd = nand_to_mtd(chip);
1135 	int ret;
1136 
1137 	ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1138 	if (ret)
1139 		return ret;
1140 
1141 	/* Configure the sequencer */
1142 	stm32_fmc2_nfc_rw_page_init(chip, page, 1, false);
1143 
1144 	/* Read the page */
1145 	ret = stm32_fmc2_nfc_xfer(chip, buf, 1, false);
1146 	if (ret)
1147 		return ret;
1148 
1149 	/* Read oob */
1150 	if (oob_required)
1151 		return nand_change_read_column_op(chip, mtd->writesize,
1152 						  chip->oob_poi, mtd->oobsize,
1153 						  false);
1154 
1155 	return 0;
1156 }
1157 
1158 static irqreturn_t stm32_fmc2_nfc_irq(int irq, void *dev_id)
1159 {
1160 	struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id;
1161 
1162 	if (nfc->irq_state == FMC2_IRQ_SEQ)
1163 		/* Sequencer is used */
1164 		stm32_fmc2_nfc_disable_seq_irq(nfc);
1165 	else if (nfc->irq_state == FMC2_IRQ_BCH)
1166 		/* BCH is used */
1167 		stm32_fmc2_nfc_disable_bch_irq(nfc);
1168 
1169 	complete(&nfc->complete);
1170 
1171 	return IRQ_HANDLED;
1172 }
1173 
1174 static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf,
1175 				     unsigned int len, bool force_8bit)
1176 {
1177 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1178 	void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel];
1179 
1180 	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1181 		/* Reconfigure bus width to 8-bit */
1182 		stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1183 
1184 	if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1185 		if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1186 			*(u8 *)buf = readb_relaxed(io_addr_r);
1187 			buf += sizeof(u8);
1188 			len -= sizeof(u8);
1189 		}
1190 
1191 		if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1192 		    len >= sizeof(u16)) {
1193 			*(u16 *)buf = readw_relaxed(io_addr_r);
1194 			buf += sizeof(u16);
1195 			len -= sizeof(u16);
1196 		}
1197 	}
1198 
1199 	/* Buf is aligned */
1200 	while (len >= sizeof(u32)) {
1201 		*(u32 *)buf = readl_relaxed(io_addr_r);
1202 		buf += sizeof(u32);
1203 		len -= sizeof(u32);
1204 	}
1205 
1206 	/* Read remaining bytes */
1207 	if (len >= sizeof(u16)) {
1208 		*(u16 *)buf = readw_relaxed(io_addr_r);
1209 		buf += sizeof(u16);
1210 		len -= sizeof(u16);
1211 	}
1212 
1213 	if (len)
1214 		*(u8 *)buf = readb_relaxed(io_addr_r);
1215 
1216 	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1217 		/* Reconfigure bus width to 16-bit */
1218 		stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1219 }
1220 
1221 static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf,
1222 				      unsigned int len, bool force_8bit)
1223 {
1224 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1225 	void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel];
1226 
1227 	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1228 		/* Reconfigure bus width to 8-bit */
1229 		stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1230 
1231 	if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1232 		if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1233 			writeb_relaxed(*(u8 *)buf, io_addr_w);
1234 			buf += sizeof(u8);
1235 			len -= sizeof(u8);
1236 		}
1237 
1238 		if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1239 		    len >= sizeof(u16)) {
1240 			writew_relaxed(*(u16 *)buf, io_addr_w);
1241 			buf += sizeof(u16);
1242 			len -= sizeof(u16);
1243 		}
1244 	}
1245 
1246 	/* Buf is aligned */
1247 	while (len >= sizeof(u32)) {
1248 		writel_relaxed(*(u32 *)buf, io_addr_w);
1249 		buf += sizeof(u32);
1250 		len -= sizeof(u32);
1251 	}
1252 
1253 	/* Write remaining bytes */
1254 	if (len >= sizeof(u16)) {
1255 		writew_relaxed(*(u16 *)buf, io_addr_w);
1256 		buf += sizeof(u16);
1257 		len -= sizeof(u16);
1258 	}
1259 
1260 	if (len)
1261 		writeb_relaxed(*(u8 *)buf, io_addr_w);
1262 
1263 	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1264 		/* Reconfigure bus width to 16-bit */
1265 		stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1266 }
1267 
1268 static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip,
1269 				  unsigned long timeout_ms)
1270 {
1271 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1272 	const struct nand_sdr_timings *timings;
1273 	u32 isr, sr;
1274 
1275 	/* Check if there is no pending requests to the NAND flash */
1276 	if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
1277 				     sr & FMC2_SR_NWRF, 1,
1278 				     1000 * FMC2_TIMEOUT_MS))
1279 		dev_warn(nfc->dev, "Waitrdy timeout\n");
1280 
1281 	/* Wait tWB before R/B# signal is low */
1282 	timings = nand_get_sdr_timings(nand_get_interface_config(chip));
1283 	ndelay(PSEC_TO_NSEC(timings->tWB_max));
1284 
1285 	/* R/B# signal is low, clear high level flag */
1286 	regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
1287 
1288 	/* Wait R/B# signal is high */
1289 	return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
1290 					isr & FMC2_ISR_IHLF, 5,
1291 					1000 * FMC2_TIMEOUT_MS);
1292 }
1293 
1294 static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
1295 				  const struct nand_operation *op,
1296 				  bool check_only)
1297 {
1298 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1299 	const struct nand_op_instr *instr = NULL;
1300 	unsigned int op_id, i, timeout;
1301 	int ret;
1302 
1303 	if (check_only)
1304 		return 0;
1305 
1306 	ret = stm32_fmc2_nfc_select_chip(chip, op->cs);
1307 	if (ret)
1308 		return ret;
1309 
1310 	for (op_id = 0; op_id < op->ninstrs; op_id++) {
1311 		instr = &op->instrs[op_id];
1312 
1313 		switch (instr->type) {
1314 		case NAND_OP_CMD_INSTR:
1315 			writeb_relaxed(instr->ctx.cmd.opcode,
1316 				       nfc->cmd_base[nfc->cs_sel]);
1317 			break;
1318 
1319 		case NAND_OP_ADDR_INSTR:
1320 			for (i = 0; i < instr->ctx.addr.naddrs; i++)
1321 				writeb_relaxed(instr->ctx.addr.addrs[i],
1322 					       nfc->addr_base[nfc->cs_sel]);
1323 			break;
1324 
1325 		case NAND_OP_DATA_IN_INSTR:
1326 			stm32_fmc2_nfc_read_data(chip, instr->ctx.data.buf.in,
1327 						 instr->ctx.data.len,
1328 						 instr->ctx.data.force_8bit);
1329 			break;
1330 
1331 		case NAND_OP_DATA_OUT_INSTR:
1332 			stm32_fmc2_nfc_write_data(chip, instr->ctx.data.buf.out,
1333 						  instr->ctx.data.len,
1334 						  instr->ctx.data.force_8bit);
1335 			break;
1336 
1337 		case NAND_OP_WAITRDY_INSTR:
1338 			timeout = instr->ctx.waitrdy.timeout_ms;
1339 			ret = stm32_fmc2_nfc_waitrdy(chip, timeout);
1340 			break;
1341 		}
1342 	}
1343 
1344 	return ret;
1345 }
1346 
1347 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
1348 {
1349 	u32 pcr;
1350 
1351 	regmap_read(nfc->regmap, FMC2_PCR, &pcr);
1352 
1353 	/* Set CS used to undefined */
1354 	nfc->cs_sel = -1;
1355 
1356 	/* Enable wait feature and nand flash memory bank */
1357 	pcr |= FMC2_PCR_PWAITEN;
1358 	pcr |= FMC2_PCR_PBKEN;
1359 
1360 	/* Set buswidth to 8 bits mode for identification */
1361 	pcr &= ~FMC2_PCR_PWID;
1362 
1363 	/* ECC logic is disabled */
1364 	pcr &= ~FMC2_PCR_ECCEN;
1365 
1366 	/* Default mode */
1367 	pcr &= ~FMC2_PCR_ECCALG;
1368 	pcr &= ~FMC2_PCR_BCHECC;
1369 	pcr &= ~FMC2_PCR_WEN;
1370 
1371 	/* Set default ECC sector size */
1372 	pcr &= ~FMC2_PCR_ECCSS;
1373 	pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
1374 
1375 	/* Set default tclr/tar timings */
1376 	pcr &= ~FMC2_PCR_TCLR;
1377 	pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
1378 	pcr &= ~FMC2_PCR_TAR;
1379 	pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
1380 
1381 	/* Enable FMC2 controller */
1382 	if (nfc->dev == nfc->cdev)
1383 		regmap_update_bits(nfc->regmap, FMC2_BCR1,
1384 				   FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1385 
1386 	regmap_write(nfc->regmap, FMC2_PCR, pcr);
1387 	regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
1388 	regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
1389 }
1390 
1391 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
1392 					const struct nand_sdr_timings *sdrt)
1393 {
1394 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1395 	struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
1396 	struct stm32_fmc2_timings *tims = &nand->timings;
1397 	unsigned long hclk = clk_get_rate(nfc->clk);
1398 	unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
1399 	unsigned long timing, tar, tclr, thiz, twait;
1400 	unsigned long tset_mem, tset_att, thold_mem, thold_att;
1401 
1402 	tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
1403 	timing = DIV_ROUND_UP(tar, hclkp) - 1;
1404 	tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1405 
1406 	tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
1407 	timing = DIV_ROUND_UP(tclr, hclkp) - 1;
1408 	tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1409 
1410 	tims->thiz = FMC2_THIZ;
1411 	thiz = (tims->thiz + 1) * hclkp;
1412 
1413 	/*
1414 	 * tWAIT > tRP
1415 	 * tWAIT > tWP
1416 	 * tWAIT > tREA + tIO
1417 	 */
1418 	twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
1419 	twait = max_t(unsigned long, twait, sdrt->tWP_min);
1420 	twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
1421 	timing = DIV_ROUND_UP(twait, hclkp);
1422 	tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1423 
1424 	/*
1425 	 * tSETUP_MEM > tCS - tWAIT
1426 	 * tSETUP_MEM > tALS - tWAIT
1427 	 * tSETUP_MEM > tDS - (tWAIT - tHIZ)
1428 	 */
1429 	tset_mem = hclkp;
1430 	if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
1431 		tset_mem = sdrt->tCS_min - twait;
1432 	if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
1433 		tset_mem = sdrt->tALS_min - twait;
1434 	if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1435 	    (tset_mem < sdrt->tDS_min - (twait - thiz)))
1436 		tset_mem = sdrt->tDS_min - (twait - thiz);
1437 	timing = DIV_ROUND_UP(tset_mem, hclkp);
1438 	tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1439 
1440 	/*
1441 	 * tHOLD_MEM > tCH
1442 	 * tHOLD_MEM > tREH - tSETUP_MEM
1443 	 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
1444 	 */
1445 	thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
1446 	if (sdrt->tREH_min > tset_mem &&
1447 	    (thold_mem < sdrt->tREH_min - tset_mem))
1448 		thold_mem = sdrt->tREH_min - tset_mem;
1449 	if ((sdrt->tRC_min > tset_mem + twait) &&
1450 	    (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
1451 		thold_mem = sdrt->tRC_min - (tset_mem + twait);
1452 	if ((sdrt->tWC_min > tset_mem + twait) &&
1453 	    (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
1454 		thold_mem = sdrt->tWC_min - (tset_mem + twait);
1455 	timing = DIV_ROUND_UP(thold_mem, hclkp);
1456 	tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1457 
1458 	/*
1459 	 * tSETUP_ATT > tCS - tWAIT
1460 	 * tSETUP_ATT > tCLS - tWAIT
1461 	 * tSETUP_ATT > tALS - tWAIT
1462 	 * tSETUP_ATT > tRHW - tHOLD_MEM
1463 	 * tSETUP_ATT > tDS - (tWAIT - tHIZ)
1464 	 */
1465 	tset_att = hclkp;
1466 	if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
1467 		tset_att = sdrt->tCS_min - twait;
1468 	if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
1469 		tset_att = sdrt->tCLS_min - twait;
1470 	if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
1471 		tset_att = sdrt->tALS_min - twait;
1472 	if (sdrt->tRHW_min > thold_mem &&
1473 	    (tset_att < sdrt->tRHW_min - thold_mem))
1474 		tset_att = sdrt->tRHW_min - thold_mem;
1475 	if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1476 	    (tset_att < sdrt->tDS_min - (twait - thiz)))
1477 		tset_att = sdrt->tDS_min - (twait - thiz);
1478 	timing = DIV_ROUND_UP(tset_att, hclkp);
1479 	tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1480 
1481 	/*
1482 	 * tHOLD_ATT > tALH
1483 	 * tHOLD_ATT > tCH
1484 	 * tHOLD_ATT > tCLH
1485 	 * tHOLD_ATT > tCOH
1486 	 * tHOLD_ATT > tDH
1487 	 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
1488 	 * tHOLD_ATT > tADL - tSETUP_MEM
1489 	 * tHOLD_ATT > tWH - tSETUP_MEM
1490 	 * tHOLD_ATT > tWHR - tSETUP_MEM
1491 	 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
1492 	 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
1493 	 */
1494 	thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
1495 	thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
1496 	thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
1497 	thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
1498 	thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
1499 	if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
1500 	    (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
1501 		thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
1502 	if (sdrt->tADL_min > tset_mem &&
1503 	    (thold_att < sdrt->tADL_min - tset_mem))
1504 		thold_att = sdrt->tADL_min - tset_mem;
1505 	if (sdrt->tWH_min > tset_mem &&
1506 	    (thold_att < sdrt->tWH_min - tset_mem))
1507 		thold_att = sdrt->tWH_min - tset_mem;
1508 	if (sdrt->tWHR_min > tset_mem &&
1509 	    (thold_att < sdrt->tWHR_min - tset_mem))
1510 		thold_att = sdrt->tWHR_min - tset_mem;
1511 	if ((sdrt->tRC_min > tset_att + twait) &&
1512 	    (thold_att < sdrt->tRC_min - (tset_att + twait)))
1513 		thold_att = sdrt->tRC_min - (tset_att + twait);
1514 	if ((sdrt->tWC_min > tset_att + twait) &&
1515 	    (thold_att < sdrt->tWC_min - (tset_att + twait)))
1516 		thold_att = sdrt->tWC_min - (tset_att + twait);
1517 	timing = DIV_ROUND_UP(thold_att, hclkp);
1518 	tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1519 }
1520 
1521 static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr,
1522 					  const struct nand_interface_config *conf)
1523 {
1524 	const struct nand_sdr_timings *sdrt;
1525 
1526 	sdrt = nand_get_sdr_timings(conf);
1527 	if (IS_ERR(sdrt))
1528 		return PTR_ERR(sdrt);
1529 
1530 	if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
1531 		return 0;
1532 
1533 	stm32_fmc2_nfc_calc_timings(chip, sdrt);
1534 	stm32_fmc2_nfc_timings_init(chip);
1535 
1536 	return 0;
1537 }
1538 
1539 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
1540 {
1541 	int ret = 0;
1542 
1543 	nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx");
1544 	if (IS_ERR(nfc->dma_tx_ch)) {
1545 		ret = PTR_ERR(nfc->dma_tx_ch);
1546 		if (ret != -ENODEV && ret != -EPROBE_DEFER)
1547 			dev_err(nfc->dev,
1548 				"failed to request tx DMA channel: %d\n", ret);
1549 		nfc->dma_tx_ch = NULL;
1550 		goto err_dma;
1551 	}
1552 
1553 	nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx");
1554 	if (IS_ERR(nfc->dma_rx_ch)) {
1555 		ret = PTR_ERR(nfc->dma_rx_ch);
1556 		if (ret != -ENODEV && ret != -EPROBE_DEFER)
1557 			dev_err(nfc->dev,
1558 				"failed to request rx DMA channel: %d\n", ret);
1559 		nfc->dma_rx_ch = NULL;
1560 		goto err_dma;
1561 	}
1562 
1563 	nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc");
1564 	if (IS_ERR(nfc->dma_ecc_ch)) {
1565 		ret = PTR_ERR(nfc->dma_ecc_ch);
1566 		if (ret != -ENODEV && ret != -EPROBE_DEFER)
1567 			dev_err(nfc->dev,
1568 				"failed to request ecc DMA channel: %d\n", ret);
1569 		nfc->dma_ecc_ch = NULL;
1570 		goto err_dma;
1571 	}
1572 
1573 	ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
1574 	if (ret)
1575 		return ret;
1576 
1577 	/* Allocate a buffer to store ECC status registers */
1578 	nfc->ecc_buf = devm_kzalloc(nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL);
1579 	if (!nfc->ecc_buf)
1580 		return -ENOMEM;
1581 
1582 	ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
1583 	if (ret)
1584 		return ret;
1585 
1586 	init_completion(&nfc->dma_data_complete);
1587 	init_completion(&nfc->dma_ecc_complete);
1588 
1589 	return 0;
1590 
1591 err_dma:
1592 	if (ret == -ENODEV) {
1593 		dev_warn(nfc->dev,
1594 			 "DMAs not defined in the DT, polling mode is used\n");
1595 		ret = 0;
1596 	}
1597 
1598 	return ret;
1599 }
1600 
1601 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
1602 {
1603 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1604 
1605 	/*
1606 	 * Specific callbacks to read/write a page depending on
1607 	 * the mode (polling/sequencer) and the algo used (Hamming, BCH).
1608 	 */
1609 	if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) {
1610 		/* DMA => use sequencer mode callbacks */
1611 		chip->ecc.correct = stm32_fmc2_nfc_seq_correct;
1612 		chip->ecc.write_page = stm32_fmc2_nfc_seq_write_page;
1613 		chip->ecc.read_page = stm32_fmc2_nfc_seq_read_page;
1614 		chip->ecc.write_page_raw = stm32_fmc2_nfc_seq_write_page_raw;
1615 		chip->ecc.read_page_raw = stm32_fmc2_nfc_seq_read_page_raw;
1616 	} else {
1617 		/* No DMA => use polling mode callbacks */
1618 		chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
1619 		if (chip->ecc.strength == FMC2_ECC_HAM) {
1620 			/* Hamming is used */
1621 			chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
1622 			chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
1623 			chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
1624 		} else {
1625 			/* BCH is used */
1626 			chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
1627 			chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
1628 			chip->ecc.read_page = stm32_fmc2_nfc_read_page;
1629 		}
1630 	}
1631 
1632 	/* Specific configurations depending on the algo used */
1633 	if (chip->ecc.strength == FMC2_ECC_HAM)
1634 		chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
1635 	else if (chip->ecc.strength == FMC2_ECC_BCH8)
1636 		chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
1637 	else
1638 		chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
1639 }
1640 
1641 static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1642 					struct mtd_oob_region *oobregion)
1643 {
1644 	struct nand_chip *chip = mtd_to_nand(mtd);
1645 	struct nand_ecc_ctrl *ecc = &chip->ecc;
1646 
1647 	if (section)
1648 		return -ERANGE;
1649 
1650 	oobregion->length = ecc->total;
1651 	oobregion->offset = FMC2_BBM_LEN;
1652 
1653 	return 0;
1654 }
1655 
1656 static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1657 					 struct mtd_oob_region *oobregion)
1658 {
1659 	struct nand_chip *chip = mtd_to_nand(mtd);
1660 	struct nand_ecc_ctrl *ecc = &chip->ecc;
1661 
1662 	if (section)
1663 		return -ERANGE;
1664 
1665 	oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN;
1666 	oobregion->offset = ecc->total + FMC2_BBM_LEN;
1667 
1668 	return 0;
1669 }
1670 
1671 static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = {
1672 	.ecc = stm32_fmc2_nfc_ooblayout_ecc,
1673 	.free = stm32_fmc2_nfc_ooblayout_free,
1674 };
1675 
1676 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
1677 {
1678 	/* Hamming */
1679 	if (strength == FMC2_ECC_HAM)
1680 		return 4;
1681 
1682 	/* BCH8 */
1683 	if (strength == FMC2_ECC_BCH8)
1684 		return 14;
1685 
1686 	/* BCH4 */
1687 	return 8;
1688 }
1689 
1690 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
1691 		     FMC2_ECC_STEP_SIZE,
1692 		     FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
1693 
1694 static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
1695 {
1696 	struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1697 	struct mtd_info *mtd = nand_to_mtd(chip);
1698 	int ret;
1699 
1700 	/*
1701 	 * Only NAND_ECC_ENGINE_TYPE_ON_HOST mode is actually supported
1702 	 * Hamming => ecc.strength = 1
1703 	 * BCH4 => ecc.strength = 4
1704 	 * BCH8 => ecc.strength = 8
1705 	 * ECC sector size = 512
1706 	 */
1707 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
1708 		dev_err(nfc->dev,
1709 			"nand_ecc_engine_type is not well defined in the DT\n");
1710 		return -EINVAL;
1711 	}
1712 
1713 	/* Default ECC settings in case they are not set in the device tree */
1714 	if (!chip->ecc.size)
1715 		chip->ecc.size = FMC2_ECC_STEP_SIZE;
1716 
1717 	if (!chip->ecc.strength)
1718 		chip->ecc.strength = FMC2_ECC_BCH8;
1719 
1720 	ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
1721 				   mtd->oobsize - FMC2_BBM_LEN);
1722 	if (ret) {
1723 		dev_err(nfc->dev, "no valid ECC settings set\n");
1724 		return ret;
1725 	}
1726 
1727 	if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
1728 		dev_err(nfc->dev, "nand page size is not supported\n");
1729 		return -EINVAL;
1730 	}
1731 
1732 	if (chip->bbt_options & NAND_BBT_USE_FLASH)
1733 		chip->bbt_options |= NAND_BBT_NO_OOB;
1734 
1735 	stm32_fmc2_nfc_nand_callbacks_setup(chip);
1736 
1737 	mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
1738 
1739 	stm32_fmc2_nfc_setup(chip);
1740 
1741 	return 0;
1742 }
1743 
1744 static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
1745 	.attach_chip = stm32_fmc2_nfc_attach_chip,
1746 	.exec_op = stm32_fmc2_nfc_exec_op,
1747 	.setup_interface = stm32_fmc2_nfc_setup_interface,
1748 };
1749 
1750 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
1751 				      struct device_node *dn)
1752 {
1753 	struct stm32_fmc2_nand *nand = &nfc->nand;
1754 	u32 cs;
1755 	int ret, i;
1756 
1757 	if (!of_get_property(dn, "reg", &nand->ncs))
1758 		return -EINVAL;
1759 
1760 	nand->ncs /= sizeof(u32);
1761 	if (!nand->ncs) {
1762 		dev_err(nfc->dev, "invalid reg property size\n");
1763 		return -EINVAL;
1764 	}
1765 
1766 	for (i = 0; i < nand->ncs; i++) {
1767 		ret = of_property_read_u32_index(dn, "reg", i, &cs);
1768 		if (ret) {
1769 			dev_err(nfc->dev, "could not retrieve reg property: %d\n",
1770 				ret);
1771 			return ret;
1772 		}
1773 
1774 		if (cs >= FMC2_MAX_CE) {
1775 			dev_err(nfc->dev, "invalid reg value: %d\n", cs);
1776 			return -EINVAL;
1777 		}
1778 
1779 		if (nfc->cs_assigned & BIT(cs)) {
1780 			dev_err(nfc->dev, "cs already assigned: %d\n", cs);
1781 			return -EINVAL;
1782 		}
1783 
1784 		nfc->cs_assigned |= BIT(cs);
1785 		nand->cs_used[i] = cs;
1786 	}
1787 
1788 	nand_set_flash_node(&nand->chip, dn);
1789 
1790 	return 0;
1791 }
1792 
1793 static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
1794 {
1795 	struct device_node *dn = nfc->dev->of_node;
1796 	struct device_node *child;
1797 	int nchips = of_get_child_count(dn);
1798 	int ret = 0;
1799 
1800 	if (!nchips) {
1801 		dev_err(nfc->dev, "NAND chip not defined\n");
1802 		return -EINVAL;
1803 	}
1804 
1805 	if (nchips > 1) {
1806 		dev_err(nfc->dev, "too many NAND chips defined\n");
1807 		return -EINVAL;
1808 	}
1809 
1810 	for_each_child_of_node(dn, child) {
1811 		ret = stm32_fmc2_nfc_parse_child(nfc, child);
1812 		if (ret < 0) {
1813 			of_node_put(child);
1814 			return ret;
1815 		}
1816 	}
1817 
1818 	return ret;
1819 }
1820 
1821 static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc)
1822 {
1823 	struct device *dev = nfc->dev;
1824 	bool ebi_found = false;
1825 
1826 	if (dev->parent && of_device_is_compatible(dev->parent->of_node,
1827 						   "st,stm32mp1-fmc2-ebi"))
1828 		ebi_found = true;
1829 
1830 	if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) {
1831 		if (ebi_found) {
1832 			nfc->cdev = dev->parent;
1833 
1834 			return 0;
1835 		}
1836 
1837 		return -EINVAL;
1838 	}
1839 
1840 	if (ebi_found)
1841 		return -EINVAL;
1842 
1843 	nfc->cdev = dev;
1844 
1845 	return 0;
1846 }
1847 
1848 static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
1849 {
1850 	struct device *dev = &pdev->dev;
1851 	struct reset_control *rstc;
1852 	struct stm32_fmc2_nfc *nfc;
1853 	struct stm32_fmc2_nand *nand;
1854 	struct resource *res;
1855 	struct mtd_info *mtd;
1856 	struct nand_chip *chip;
1857 	struct resource cres;
1858 	int chip_cs, mem_region, ret, irq;
1859 	int start_region = 0;
1860 
1861 	nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1862 	if (!nfc)
1863 		return -ENOMEM;
1864 
1865 	nfc->dev = dev;
1866 	nand_controller_init(&nfc->base);
1867 	nfc->base.ops = &stm32_fmc2_nfc_controller_ops;
1868 
1869 	ret = stm32_fmc2_nfc_set_cdev(nfc);
1870 	if (ret)
1871 		return ret;
1872 
1873 	ret = stm32_fmc2_nfc_parse_dt(nfc);
1874 	if (ret)
1875 		return ret;
1876 
1877 	ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres);
1878 	if (ret)
1879 		return ret;
1880 
1881 	nfc->io_phys_addr = cres.start;
1882 
1883 	nfc->regmap = device_node_to_regmap(nfc->cdev->of_node);
1884 	if (IS_ERR(nfc->regmap))
1885 		return PTR_ERR(nfc->regmap);
1886 
1887 	if (nfc->dev == nfc->cdev)
1888 		start_region = 1;
1889 
1890 	for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
1891 	     chip_cs++, mem_region += 3) {
1892 		if (!(nfc->cs_assigned & BIT(chip_cs)))
1893 			continue;
1894 
1895 		res = platform_get_resource(pdev, IORESOURCE_MEM, mem_region);
1896 		nfc->data_base[chip_cs] = devm_ioremap_resource(dev, res);
1897 		if (IS_ERR(nfc->data_base[chip_cs]))
1898 			return PTR_ERR(nfc->data_base[chip_cs]);
1899 
1900 		nfc->data_phys_addr[chip_cs] = res->start;
1901 
1902 		res = platform_get_resource(pdev, IORESOURCE_MEM,
1903 					    mem_region + 1);
1904 		nfc->cmd_base[chip_cs] = devm_ioremap_resource(dev, res);
1905 		if (IS_ERR(nfc->cmd_base[chip_cs]))
1906 			return PTR_ERR(nfc->cmd_base[chip_cs]);
1907 
1908 		res = platform_get_resource(pdev, IORESOURCE_MEM,
1909 					    mem_region + 2);
1910 		nfc->addr_base[chip_cs] = devm_ioremap_resource(dev, res);
1911 		if (IS_ERR(nfc->addr_base[chip_cs]))
1912 			return PTR_ERR(nfc->addr_base[chip_cs]);
1913 	}
1914 
1915 	irq = platform_get_irq(pdev, 0);
1916 	if (irq < 0)
1917 		return irq;
1918 
1919 	ret = devm_request_irq(dev, irq, stm32_fmc2_nfc_irq, 0,
1920 			       dev_name(dev), nfc);
1921 	if (ret) {
1922 		dev_err(dev, "failed to request irq\n");
1923 		return ret;
1924 	}
1925 
1926 	init_completion(&nfc->complete);
1927 
1928 	nfc->clk = devm_clk_get(nfc->cdev, NULL);
1929 	if (IS_ERR(nfc->clk))
1930 		return PTR_ERR(nfc->clk);
1931 
1932 	ret = clk_prepare_enable(nfc->clk);
1933 	if (ret) {
1934 		dev_err(dev, "can not enable the clock\n");
1935 		return ret;
1936 	}
1937 
1938 	rstc = devm_reset_control_get(dev, NULL);
1939 	if (IS_ERR(rstc)) {
1940 		ret = PTR_ERR(rstc);
1941 		if (ret == -EPROBE_DEFER)
1942 			goto err_clk_disable;
1943 	} else {
1944 		reset_control_assert(rstc);
1945 		reset_control_deassert(rstc);
1946 	}
1947 
1948 	ret = stm32_fmc2_nfc_dma_setup(nfc);
1949 	if (ret)
1950 		goto err_release_dma;
1951 
1952 	stm32_fmc2_nfc_init(nfc);
1953 
1954 	nand = &nfc->nand;
1955 	chip = &nand->chip;
1956 	mtd = nand_to_mtd(chip);
1957 	mtd->dev.parent = dev;
1958 
1959 	chip->controller = &nfc->base;
1960 	chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1961 			 NAND_USES_DMA;
1962 
1963 	/* Scan to find existence of the device */
1964 	ret = nand_scan(chip, nand->ncs);
1965 	if (ret)
1966 		goto err_release_dma;
1967 
1968 	ret = mtd_device_register(mtd, NULL, 0);
1969 	if (ret)
1970 		goto err_nand_cleanup;
1971 
1972 	platform_set_drvdata(pdev, nfc);
1973 
1974 	return 0;
1975 
1976 err_nand_cleanup:
1977 	nand_cleanup(chip);
1978 
1979 err_release_dma:
1980 	if (nfc->dma_ecc_ch)
1981 		dma_release_channel(nfc->dma_ecc_ch);
1982 	if (nfc->dma_tx_ch)
1983 		dma_release_channel(nfc->dma_tx_ch);
1984 	if (nfc->dma_rx_ch)
1985 		dma_release_channel(nfc->dma_rx_ch);
1986 
1987 	sg_free_table(&nfc->dma_data_sg);
1988 	sg_free_table(&nfc->dma_ecc_sg);
1989 
1990 err_clk_disable:
1991 	clk_disable_unprepare(nfc->clk);
1992 
1993 	return ret;
1994 }
1995 
1996 static int stm32_fmc2_nfc_remove(struct platform_device *pdev)
1997 {
1998 	struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev);
1999 	struct stm32_fmc2_nand *nand = &nfc->nand;
2000 	struct nand_chip *chip = &nand->chip;
2001 	int ret;
2002 
2003 	ret = mtd_device_unregister(nand_to_mtd(chip));
2004 	WARN_ON(ret);
2005 	nand_cleanup(chip);
2006 
2007 	if (nfc->dma_ecc_ch)
2008 		dma_release_channel(nfc->dma_ecc_ch);
2009 	if (nfc->dma_tx_ch)
2010 		dma_release_channel(nfc->dma_tx_ch);
2011 	if (nfc->dma_rx_ch)
2012 		dma_release_channel(nfc->dma_rx_ch);
2013 
2014 	sg_free_table(&nfc->dma_data_sg);
2015 	sg_free_table(&nfc->dma_ecc_sg);
2016 
2017 	clk_disable_unprepare(nfc->clk);
2018 
2019 	return 0;
2020 }
2021 
2022 static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev)
2023 {
2024 	struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2025 
2026 	clk_disable_unprepare(nfc->clk);
2027 
2028 	pinctrl_pm_select_sleep_state(dev);
2029 
2030 	return 0;
2031 }
2032 
2033 static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev)
2034 {
2035 	struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2036 	struct stm32_fmc2_nand *nand = &nfc->nand;
2037 	int chip_cs, ret;
2038 
2039 	pinctrl_pm_select_default_state(dev);
2040 
2041 	ret = clk_prepare_enable(nfc->clk);
2042 	if (ret) {
2043 		dev_err(dev, "can not enable the clock\n");
2044 		return ret;
2045 	}
2046 
2047 	stm32_fmc2_nfc_init(nfc);
2048 
2049 	for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
2050 		if (!(nfc->cs_assigned & BIT(chip_cs)))
2051 			continue;
2052 
2053 		nand_reset(&nand->chip, chip_cs);
2054 	}
2055 
2056 	return 0;
2057 }
2058 
2059 static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend,
2060 			 stm32_fmc2_nfc_resume);
2061 
2062 static const struct of_device_id stm32_fmc2_nfc_match[] = {
2063 	{.compatible = "st,stm32mp15-fmc2"},
2064 	{.compatible = "st,stm32mp1-fmc2-nfc"},
2065 	{}
2066 };
2067 MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match);
2068 
2069 static struct platform_driver stm32_fmc2_nfc_driver = {
2070 	.probe	= stm32_fmc2_nfc_probe,
2071 	.remove	= stm32_fmc2_nfc_remove,
2072 	.driver	= {
2073 		.name = "stm32_fmc2_nfc",
2074 		.of_match_table = stm32_fmc2_nfc_match,
2075 		.pm = &stm32_fmc2_nfc_pm_ops,
2076 	},
2077 };
2078 module_platform_driver(stm32_fmc2_nfc_driver);
2079 
2080 MODULE_ALIAS("platform:stm32_fmc2_nfc");
2081 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
2082 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 NFC driver");
2083 MODULE_LICENSE("GPL v2");
2084