1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2018 4 * Author: Christophe Kerello <christophe.kerello@st.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/dmaengine.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/errno.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/mtd/rawnand.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 20 /* Bad block marker length */ 21 #define FMC2_BBM_LEN 2 22 23 /* ECC step size */ 24 #define FMC2_ECC_STEP_SIZE 512 25 26 /* BCHDSRx registers length */ 27 #define FMC2_BCHDSRS_LEN 20 28 29 /* HECCR length */ 30 #define FMC2_HECCR_LEN 4 31 32 /* Max requests done for a 8k nand page size */ 33 #define FMC2_MAX_SG 16 34 35 /* Max chip enable */ 36 #define FMC2_MAX_CE 2 37 38 /* Max ECC buffer length */ 39 #define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG) 40 41 #define FMC2_TIMEOUT_MS 5000 42 43 /* Timings */ 44 #define FMC2_THIZ 1 45 #define FMC2_TIO 8000 46 #define FMC2_TSYNC 3000 47 #define FMC2_PCR_TIMING_MASK 0xf 48 #define FMC2_PMEM_PATT_TIMING_MASK 0xff 49 50 /* FMC2 Controller Registers */ 51 #define FMC2_BCR1 0x0 52 #define FMC2_PCR 0x80 53 #define FMC2_SR 0x84 54 #define FMC2_PMEM 0x88 55 #define FMC2_PATT 0x8c 56 #define FMC2_HECCR 0x94 57 #define FMC2_ISR 0x184 58 #define FMC2_ICR 0x188 59 #define FMC2_CSQCR 0x200 60 #define FMC2_CSQCFGR1 0x204 61 #define FMC2_CSQCFGR2 0x208 62 #define FMC2_CSQCFGR3 0x20c 63 #define FMC2_CSQAR1 0x210 64 #define FMC2_CSQAR2 0x214 65 #define FMC2_CSQIER 0x220 66 #define FMC2_CSQISR 0x224 67 #define FMC2_CSQICR 0x228 68 #define FMC2_CSQEMSR 0x230 69 #define FMC2_BCHIER 0x250 70 #define FMC2_BCHISR 0x254 71 #define FMC2_BCHICR 0x258 72 #define FMC2_BCHPBR1 0x260 73 #define FMC2_BCHPBR2 0x264 74 #define FMC2_BCHPBR3 0x268 75 #define FMC2_BCHPBR4 0x26c 76 #define FMC2_BCHDSR0 0x27c 77 #define FMC2_BCHDSR1 0x280 78 #define FMC2_BCHDSR2 0x284 79 #define FMC2_BCHDSR3 0x288 80 #define FMC2_BCHDSR4 0x28c 81 82 /* Register: FMC2_BCR1 */ 83 #define FMC2_BCR1_FMC2EN BIT(31) 84 85 /* Register: FMC2_PCR */ 86 #define FMC2_PCR_PWAITEN BIT(1) 87 #define FMC2_PCR_PBKEN BIT(2) 88 #define FMC2_PCR_PWID GENMASK(5, 4) 89 #define FMC2_PCR_PWID_BUSWIDTH_8 0 90 #define FMC2_PCR_PWID_BUSWIDTH_16 1 91 #define FMC2_PCR_ECCEN BIT(6) 92 #define FMC2_PCR_ECCALG BIT(8) 93 #define FMC2_PCR_TCLR GENMASK(12, 9) 94 #define FMC2_PCR_TCLR_DEFAULT 0xf 95 #define FMC2_PCR_TAR GENMASK(16, 13) 96 #define FMC2_PCR_TAR_DEFAULT 0xf 97 #define FMC2_PCR_ECCSS GENMASK(19, 17) 98 #define FMC2_PCR_ECCSS_512 1 99 #define FMC2_PCR_ECCSS_2048 3 100 #define FMC2_PCR_BCHECC BIT(24) 101 #define FMC2_PCR_WEN BIT(25) 102 103 /* Register: FMC2_SR */ 104 #define FMC2_SR_NWRF BIT(6) 105 106 /* Register: FMC2_PMEM */ 107 #define FMC2_PMEM_MEMSET GENMASK(7, 0) 108 #define FMC2_PMEM_MEMWAIT GENMASK(15, 8) 109 #define FMC2_PMEM_MEMHOLD GENMASK(23, 16) 110 #define FMC2_PMEM_MEMHIZ GENMASK(31, 24) 111 #define FMC2_PMEM_DEFAULT 0x0a0a0a0a 112 113 /* Register: FMC2_PATT */ 114 #define FMC2_PATT_ATTSET GENMASK(7, 0) 115 #define FMC2_PATT_ATTWAIT GENMASK(15, 8) 116 #define FMC2_PATT_ATTHOLD GENMASK(23, 16) 117 #define FMC2_PATT_ATTHIZ GENMASK(31, 24) 118 #define FMC2_PATT_DEFAULT 0x0a0a0a0a 119 120 /* Register: FMC2_ISR */ 121 #define FMC2_ISR_IHLF BIT(1) 122 123 /* Register: FMC2_ICR */ 124 #define FMC2_ICR_CIHLF BIT(1) 125 126 /* Register: FMC2_CSQCR */ 127 #define FMC2_CSQCR_CSQSTART BIT(0) 128 129 /* Register: FMC2_CSQCFGR1 */ 130 #define FMC2_CSQCFGR1_CMD2EN BIT(1) 131 #define FMC2_CSQCFGR1_DMADEN BIT(2) 132 #define FMC2_CSQCFGR1_ACYNBR GENMASK(6, 4) 133 #define FMC2_CSQCFGR1_CMD1 GENMASK(15, 8) 134 #define FMC2_CSQCFGR1_CMD2 GENMASK(23, 16) 135 #define FMC2_CSQCFGR1_CMD1T BIT(24) 136 #define FMC2_CSQCFGR1_CMD2T BIT(25) 137 138 /* Register: FMC2_CSQCFGR2 */ 139 #define FMC2_CSQCFGR2_SQSDTEN BIT(0) 140 #define FMC2_CSQCFGR2_RCMD2EN BIT(1) 141 #define FMC2_CSQCFGR2_DMASEN BIT(2) 142 #define FMC2_CSQCFGR2_RCMD1 GENMASK(15, 8) 143 #define FMC2_CSQCFGR2_RCMD2 GENMASK(23, 16) 144 #define FMC2_CSQCFGR2_RCMD1T BIT(24) 145 #define FMC2_CSQCFGR2_RCMD2T BIT(25) 146 147 /* Register: FMC2_CSQCFGR3 */ 148 #define FMC2_CSQCFGR3_SNBR GENMASK(13, 8) 149 #define FMC2_CSQCFGR3_AC1T BIT(16) 150 #define FMC2_CSQCFGR3_AC2T BIT(17) 151 #define FMC2_CSQCFGR3_AC3T BIT(18) 152 #define FMC2_CSQCFGR3_AC4T BIT(19) 153 #define FMC2_CSQCFGR3_AC5T BIT(20) 154 #define FMC2_CSQCFGR3_SDT BIT(21) 155 #define FMC2_CSQCFGR3_RAC1T BIT(22) 156 #define FMC2_CSQCFGR3_RAC2T BIT(23) 157 158 /* Register: FMC2_CSQCAR1 */ 159 #define FMC2_CSQCAR1_ADDC1 GENMASK(7, 0) 160 #define FMC2_CSQCAR1_ADDC2 GENMASK(15, 8) 161 #define FMC2_CSQCAR1_ADDC3 GENMASK(23, 16) 162 #define FMC2_CSQCAR1_ADDC4 GENMASK(31, 24) 163 164 /* Register: FMC2_CSQCAR2 */ 165 #define FMC2_CSQCAR2_ADDC5 GENMASK(7, 0) 166 #define FMC2_CSQCAR2_NANDCEN GENMASK(11, 10) 167 #define FMC2_CSQCAR2_SAO GENMASK(31, 16) 168 169 /* Register: FMC2_CSQIER */ 170 #define FMC2_CSQIER_TCIE BIT(0) 171 172 /* Register: FMC2_CSQICR */ 173 #define FMC2_CSQICR_CLEAR_IRQ GENMASK(4, 0) 174 175 /* Register: FMC2_CSQEMSR */ 176 #define FMC2_CSQEMSR_SEM GENMASK(15, 0) 177 178 /* Register: FMC2_BCHIER */ 179 #define FMC2_BCHIER_DERIE BIT(1) 180 #define FMC2_BCHIER_EPBRIE BIT(4) 181 182 /* Register: FMC2_BCHICR */ 183 #define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0) 184 185 /* Register: FMC2_BCHDSR0 */ 186 #define FMC2_BCHDSR0_DUE BIT(0) 187 #define FMC2_BCHDSR0_DEF BIT(1) 188 #define FMC2_BCHDSR0_DEN GENMASK(7, 4) 189 190 /* Register: FMC2_BCHDSR1 */ 191 #define FMC2_BCHDSR1_EBP1 GENMASK(12, 0) 192 #define FMC2_BCHDSR1_EBP2 GENMASK(28, 16) 193 194 /* Register: FMC2_BCHDSR2 */ 195 #define FMC2_BCHDSR2_EBP3 GENMASK(12, 0) 196 #define FMC2_BCHDSR2_EBP4 GENMASK(28, 16) 197 198 /* Register: FMC2_BCHDSR3 */ 199 #define FMC2_BCHDSR3_EBP5 GENMASK(12, 0) 200 #define FMC2_BCHDSR3_EBP6 GENMASK(28, 16) 201 202 /* Register: FMC2_BCHDSR4 */ 203 #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) 204 #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) 205 206 enum stm32_fmc2_ecc { 207 FMC2_ECC_HAM = 1, 208 FMC2_ECC_BCH4 = 4, 209 FMC2_ECC_BCH8 = 8 210 }; 211 212 enum stm32_fmc2_irq_state { 213 FMC2_IRQ_UNKNOWN = 0, 214 FMC2_IRQ_BCH, 215 FMC2_IRQ_SEQ 216 }; 217 218 struct stm32_fmc2_timings { 219 u8 tclr; 220 u8 tar; 221 u8 thiz; 222 u8 twait; 223 u8 thold_mem; 224 u8 tset_mem; 225 u8 thold_att; 226 u8 tset_att; 227 }; 228 229 struct stm32_fmc2_nand { 230 struct nand_chip chip; 231 struct stm32_fmc2_timings timings; 232 int ncs; 233 int cs_used[FMC2_MAX_CE]; 234 }; 235 236 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) 237 { 238 return container_of(chip, struct stm32_fmc2_nand, chip); 239 } 240 241 struct stm32_fmc2_nfc { 242 struct nand_controller base; 243 struct stm32_fmc2_nand nand; 244 struct device *dev; 245 void __iomem *io_base; 246 void __iomem *data_base[FMC2_MAX_CE]; 247 void __iomem *cmd_base[FMC2_MAX_CE]; 248 void __iomem *addr_base[FMC2_MAX_CE]; 249 phys_addr_t io_phys_addr; 250 phys_addr_t data_phys_addr[FMC2_MAX_CE]; 251 struct clk *clk; 252 u8 irq_state; 253 254 struct dma_chan *dma_tx_ch; 255 struct dma_chan *dma_rx_ch; 256 struct dma_chan *dma_ecc_ch; 257 struct sg_table dma_data_sg; 258 struct sg_table dma_ecc_sg; 259 u8 *ecc_buf; 260 int dma_ecc_len; 261 262 struct completion complete; 263 struct completion dma_data_complete; 264 struct completion dma_ecc_complete; 265 266 u8 cs_assigned; 267 int cs_sel; 268 }; 269 270 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base) 271 { 272 return container_of(base, struct stm32_fmc2_nfc, base); 273 } 274 275 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip) 276 { 277 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 278 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 279 struct stm32_fmc2_timings *timings = &nand->timings; 280 u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR); 281 u32 pmem, patt; 282 283 /* Set tclr/tar timings */ 284 pcr &= ~FMC2_PCR_TCLR; 285 pcr |= FIELD_PREP(FMC2_PCR_TCLR, timings->tclr); 286 pcr &= ~FMC2_PCR_TAR; 287 pcr |= FIELD_PREP(FMC2_PCR_TAR, timings->tar); 288 289 /* Set tset/twait/thold/thiz timings in common bank */ 290 pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem); 291 pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait); 292 pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem); 293 pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz); 294 295 /* Set tset/twait/thold/thiz timings in attribut bank */ 296 patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att); 297 patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait); 298 patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att); 299 patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz); 300 301 writel_relaxed(pcr, nfc->io_base + FMC2_PCR); 302 writel_relaxed(pmem, nfc->io_base + FMC2_PMEM); 303 writel_relaxed(patt, nfc->io_base + FMC2_PATT); 304 } 305 306 static void stm32_fmc2_nfc_setup(struct nand_chip *chip) 307 { 308 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 309 u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR); 310 311 /* Configure ECC algorithm (default configuration is Hamming) */ 312 pcr &= ~FMC2_PCR_ECCALG; 313 pcr &= ~FMC2_PCR_BCHECC; 314 if (chip->ecc.strength == FMC2_ECC_BCH8) { 315 pcr |= FMC2_PCR_ECCALG; 316 pcr |= FMC2_PCR_BCHECC; 317 } else if (chip->ecc.strength == FMC2_ECC_BCH4) { 318 pcr |= FMC2_PCR_ECCALG; 319 } 320 321 /* Set buswidth */ 322 pcr &= ~FMC2_PCR_PWID; 323 if (chip->options & NAND_BUSWIDTH_16) 324 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16); 325 326 /* Set ECC sector size */ 327 pcr &= ~FMC2_PCR_ECCSS; 328 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512); 329 330 writel_relaxed(pcr, nfc->io_base + FMC2_PCR); 331 } 332 333 static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr) 334 { 335 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 336 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 337 struct dma_slave_config dma_cfg; 338 int ret; 339 340 if (nand->cs_used[chipnr] == nfc->cs_sel) 341 return 0; 342 343 nfc->cs_sel = nand->cs_used[chipnr]; 344 stm32_fmc2_nfc_setup(chip); 345 stm32_fmc2_nfc_timings_init(chip); 346 347 if (nfc->dma_tx_ch && nfc->dma_rx_ch) { 348 memset(&dma_cfg, 0, sizeof(dma_cfg)); 349 dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel]; 350 dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel]; 351 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 352 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 353 dma_cfg.src_maxburst = 32; 354 dma_cfg.dst_maxburst = 32; 355 356 ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg); 357 if (ret) { 358 dev_err(nfc->dev, "tx DMA engine slave config failed\n"); 359 return ret; 360 } 361 362 ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg); 363 if (ret) { 364 dev_err(nfc->dev, "rx DMA engine slave config failed\n"); 365 return ret; 366 } 367 } 368 369 if (nfc->dma_ecc_ch) { 370 /* 371 * Hamming: we read HECCR register 372 * BCH4/BCH8: we read BCHDSRSx registers 373 */ 374 memset(&dma_cfg, 0, sizeof(dma_cfg)); 375 dma_cfg.src_addr = nfc->io_phys_addr; 376 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ? 377 FMC2_HECCR : FMC2_BCHDSR0; 378 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 379 380 ret = dmaengine_slave_config(nfc->dma_ecc_ch, &dma_cfg); 381 if (ret) { 382 dev_err(nfc->dev, "ECC DMA engine slave config failed\n"); 383 return ret; 384 } 385 386 /* Calculate ECC length needed for one sector */ 387 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ? 388 FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN; 389 } 390 391 return 0; 392 } 393 394 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set) 395 { 396 u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR); 397 398 pcr &= ~FMC2_PCR_PWID; 399 if (set) 400 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16); 401 writel_relaxed(pcr, nfc->io_base + FMC2_PCR); 402 } 403 404 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable) 405 { 406 u32 pcr = readl(nfc->io_base + FMC2_PCR); 407 408 pcr &= ~FMC2_PCR_ECCEN; 409 if (enable) 410 pcr |= FMC2_PCR_ECCEN; 411 writel(pcr, nfc->io_base + FMC2_PCR); 412 } 413 414 static inline void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc) 415 { 416 u32 csqier = readl_relaxed(nfc->io_base + FMC2_CSQIER); 417 418 csqier |= FMC2_CSQIER_TCIE; 419 420 nfc->irq_state = FMC2_IRQ_SEQ; 421 422 writel_relaxed(csqier, nfc->io_base + FMC2_CSQIER); 423 } 424 425 static inline void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc) 426 { 427 u32 csqier = readl_relaxed(nfc->io_base + FMC2_CSQIER); 428 429 csqier &= ~FMC2_CSQIER_TCIE; 430 431 writel_relaxed(csqier, nfc->io_base + FMC2_CSQIER); 432 433 nfc->irq_state = FMC2_IRQ_UNKNOWN; 434 } 435 436 static inline void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc) 437 { 438 writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, nfc->io_base + FMC2_CSQICR); 439 } 440 441 static inline void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, 442 int mode) 443 { 444 u32 bchier = readl_relaxed(nfc->io_base + FMC2_BCHIER); 445 446 if (mode == NAND_ECC_WRITE) 447 bchier |= FMC2_BCHIER_EPBRIE; 448 else 449 bchier |= FMC2_BCHIER_DERIE; 450 451 nfc->irq_state = FMC2_IRQ_BCH; 452 453 writel_relaxed(bchier, nfc->io_base + FMC2_BCHIER); 454 } 455 456 static inline void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc) 457 { 458 u32 bchier = readl_relaxed(nfc->io_base + FMC2_BCHIER); 459 460 bchier &= ~FMC2_BCHIER_DERIE; 461 bchier &= ~FMC2_BCHIER_EPBRIE; 462 463 writel_relaxed(bchier, nfc->io_base + FMC2_BCHIER); 464 465 nfc->irq_state = FMC2_IRQ_UNKNOWN; 466 } 467 468 static inline void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc) 469 { 470 writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR); 471 } 472 473 /* 474 * Enable ECC logic and reset syndrome/parity bits previously calculated 475 * Syndrome/parity bits is cleared by setting the ECCEN bit to 0 476 */ 477 static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode) 478 { 479 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 480 481 stm32_fmc2_nfc_set_ecc(nfc, false); 482 483 if (chip->ecc.strength != FMC2_ECC_HAM) { 484 u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR); 485 486 if (mode == NAND_ECC_WRITE) 487 pcr |= FMC2_PCR_WEN; 488 else 489 pcr &= ~FMC2_PCR_WEN; 490 writel_relaxed(pcr, nfc->io_base + FMC2_PCR); 491 492 reinit_completion(&nfc->complete); 493 stm32_fmc2_nfc_clear_bch_irq(nfc); 494 stm32_fmc2_nfc_enable_bch_irq(nfc, mode); 495 } 496 497 stm32_fmc2_nfc_set_ecc(nfc, true); 498 } 499 500 /* 501 * ECC Hamming calculation 502 * ECC is 3 bytes for 512 bytes of data (supports error correction up to 503 * max of 1-bit) 504 */ 505 static inline void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc) 506 { 507 ecc[0] = ecc_sta; 508 ecc[1] = ecc_sta >> 8; 509 ecc[2] = ecc_sta >> 16; 510 } 511 512 static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data, 513 u8 *ecc) 514 { 515 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 516 u32 sr, heccr; 517 int ret; 518 519 ret = readl_relaxed_poll_timeout(nfc->io_base + FMC2_SR, 520 sr, sr & FMC2_SR_NWRF, 1, 521 1000 * FMC2_TIMEOUT_MS); 522 if (ret) { 523 dev_err(nfc->dev, "ham timeout\n"); 524 return ret; 525 } 526 527 heccr = readl_relaxed(nfc->io_base + FMC2_HECCR); 528 stm32_fmc2_nfc_ham_set_ecc(heccr, ecc); 529 stm32_fmc2_nfc_set_ecc(nfc, false); 530 531 return 0; 532 } 533 534 static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat, 535 u8 *read_ecc, u8 *calc_ecc) 536 { 537 u8 bit_position = 0, b0, b1, b2; 538 u32 byte_addr = 0, b; 539 u32 i, shifting = 1; 540 541 /* Indicate which bit and byte is faulty (if any) */ 542 b0 = read_ecc[0] ^ calc_ecc[0]; 543 b1 = read_ecc[1] ^ calc_ecc[1]; 544 b2 = read_ecc[2] ^ calc_ecc[2]; 545 b = b0 | (b1 << 8) | (b2 << 16); 546 547 /* No errors */ 548 if (likely(!b)) 549 return 0; 550 551 /* Calculate bit position */ 552 for (i = 0; i < 3; i++) { 553 switch (b % 4) { 554 case 2: 555 bit_position += shifting; 556 case 1: 557 break; 558 default: 559 return -EBADMSG; 560 } 561 shifting <<= 1; 562 b >>= 2; 563 } 564 565 /* Calculate byte position */ 566 shifting = 1; 567 for (i = 0; i < 9; i++) { 568 switch (b % 4) { 569 case 2: 570 byte_addr += shifting; 571 case 1: 572 break; 573 default: 574 return -EBADMSG; 575 } 576 shifting <<= 1; 577 b >>= 2; 578 } 579 580 /* Flip the bit */ 581 dat[byte_addr] ^= (1 << bit_position); 582 583 return 1; 584 } 585 586 /* 587 * ECC BCH calculation and correction 588 * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to 589 * max of 4-bit/8-bit) 590 */ 591 static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data, 592 u8 *ecc) 593 { 594 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 595 u32 bchpbr; 596 597 /* Wait until the BCH code is ready */ 598 if (!wait_for_completion_timeout(&nfc->complete, 599 msecs_to_jiffies(FMC2_TIMEOUT_MS))) { 600 dev_err(nfc->dev, "bch timeout\n"); 601 stm32_fmc2_nfc_disable_bch_irq(nfc); 602 return -ETIMEDOUT; 603 } 604 605 /* Read parity bits */ 606 bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR1); 607 ecc[0] = bchpbr; 608 ecc[1] = bchpbr >> 8; 609 ecc[2] = bchpbr >> 16; 610 ecc[3] = bchpbr >> 24; 611 612 bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR2); 613 ecc[4] = bchpbr; 614 ecc[5] = bchpbr >> 8; 615 ecc[6] = bchpbr >> 16; 616 617 if (chip->ecc.strength == FMC2_ECC_BCH8) { 618 ecc[7] = bchpbr >> 24; 619 620 bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR3); 621 ecc[8] = bchpbr; 622 ecc[9] = bchpbr >> 8; 623 ecc[10] = bchpbr >> 16; 624 ecc[11] = bchpbr >> 24; 625 626 bchpbr = readl_relaxed(nfc->io_base + FMC2_BCHPBR4); 627 ecc[12] = bchpbr; 628 } 629 630 stm32_fmc2_nfc_set_ecc(nfc, false); 631 632 return 0; 633 } 634 635 static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta) 636 { 637 u32 bchdsr0 = ecc_sta[0]; 638 u32 bchdsr1 = ecc_sta[1]; 639 u32 bchdsr2 = ecc_sta[2]; 640 u32 bchdsr3 = ecc_sta[3]; 641 u32 bchdsr4 = ecc_sta[4]; 642 u16 pos[8]; 643 int i, den; 644 unsigned int nb_errs = 0; 645 646 /* No errors found */ 647 if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF))) 648 return 0; 649 650 /* Too many errors detected */ 651 if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE)) 652 return -EBADMSG; 653 654 pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1); 655 pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1); 656 pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2); 657 pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2); 658 pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3); 659 pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3); 660 pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4); 661 pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4); 662 663 den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0); 664 for (i = 0; i < den; i++) { 665 if (pos[i] < eccsize * 8) { 666 change_bit(pos[i], (unsigned long *)dat); 667 nb_errs++; 668 } 669 } 670 671 return nb_errs; 672 } 673 674 static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat, 675 u8 *read_ecc, u8 *calc_ecc) 676 { 677 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 678 u32 ecc_sta[5]; 679 680 /* Wait until the decoding error is ready */ 681 if (!wait_for_completion_timeout(&nfc->complete, 682 msecs_to_jiffies(FMC2_TIMEOUT_MS))) { 683 dev_err(nfc->dev, "bch timeout\n"); 684 stm32_fmc2_nfc_disable_bch_irq(nfc); 685 return -ETIMEDOUT; 686 } 687 688 ecc_sta[0] = readl_relaxed(nfc->io_base + FMC2_BCHDSR0); 689 ecc_sta[1] = readl_relaxed(nfc->io_base + FMC2_BCHDSR1); 690 ecc_sta[2] = readl_relaxed(nfc->io_base + FMC2_BCHDSR2); 691 ecc_sta[3] = readl_relaxed(nfc->io_base + FMC2_BCHDSR3); 692 ecc_sta[4] = readl_relaxed(nfc->io_base + FMC2_BCHDSR4); 693 694 stm32_fmc2_nfc_set_ecc(nfc, false); 695 696 return stm32_fmc2_nfc_bch_decode(chip->ecc.size, dat, ecc_sta); 697 } 698 699 static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf, 700 int oob_required, int page) 701 { 702 struct mtd_info *mtd = nand_to_mtd(chip); 703 int ret, i, s, stat, eccsize = chip->ecc.size; 704 int eccbytes = chip->ecc.bytes; 705 int eccsteps = chip->ecc.steps; 706 int eccstrength = chip->ecc.strength; 707 u8 *p = buf; 708 u8 *ecc_calc = chip->ecc.calc_buf; 709 u8 *ecc_code = chip->ecc.code_buf; 710 unsigned int max_bitflips = 0; 711 712 ret = nand_read_page_op(chip, page, 0, NULL, 0); 713 if (ret) 714 return ret; 715 716 for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps; 717 s++, i += eccbytes, p += eccsize) { 718 chip->ecc.hwctl(chip, NAND_ECC_READ); 719 720 /* Read the nand page sector (512 bytes) */ 721 ret = nand_change_read_column_op(chip, s * eccsize, p, 722 eccsize, false); 723 if (ret) 724 return ret; 725 726 /* Read the corresponding ECC bytes */ 727 ret = nand_change_read_column_op(chip, i, ecc_code, 728 eccbytes, false); 729 if (ret) 730 return ret; 731 732 /* Correct the data */ 733 stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc); 734 if (stat == -EBADMSG) 735 /* Check for empty pages with bitflips */ 736 stat = nand_check_erased_ecc_chunk(p, eccsize, 737 ecc_code, eccbytes, 738 NULL, 0, 739 eccstrength); 740 741 if (stat < 0) { 742 mtd->ecc_stats.failed++; 743 } else { 744 mtd->ecc_stats.corrected += stat; 745 max_bitflips = max_t(unsigned int, max_bitflips, stat); 746 } 747 } 748 749 /* Read oob */ 750 if (oob_required) { 751 ret = nand_change_read_column_op(chip, mtd->writesize, 752 chip->oob_poi, mtd->oobsize, 753 false); 754 if (ret) 755 return ret; 756 } 757 758 return max_bitflips; 759 } 760 761 /* Sequencer read/write configuration */ 762 static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page, 763 int raw, bool write_data) 764 { 765 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 766 struct mtd_info *mtd = nand_to_mtd(chip); 767 u32 csqcfgr1, csqcfgr2, csqcfgr3; 768 u32 csqar1, csqar2; 769 u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN; 770 u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR); 771 772 if (write_data) 773 pcr |= FMC2_PCR_WEN; 774 else 775 pcr &= ~FMC2_PCR_WEN; 776 writel_relaxed(pcr, nfc->io_base + FMC2_PCR); 777 778 /* 779 * - Set Program Page/Page Read command 780 * - Enable DMA request data 781 * - Set timings 782 */ 783 csqcfgr1 = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T; 784 if (write_data) 785 csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN); 786 else 787 csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) | 788 FMC2_CSQCFGR1_CMD2EN | 789 FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) | 790 FMC2_CSQCFGR1_CMD2T; 791 792 /* 793 * - Set Random Data Input/Random Data Read command 794 * - Enable the sequencer to access the Spare data area 795 * - Enable DMA request status decoding for read 796 * - Set timings 797 */ 798 if (write_data) 799 csqcfgr2 = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN); 800 else 801 csqcfgr2 = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) | 802 FMC2_CSQCFGR2_RCMD2EN | 803 FIELD_PREP(FMC2_CSQCFGR2_RCMD2, 804 NAND_CMD_RNDOUTSTART) | 805 FMC2_CSQCFGR2_RCMD1T | 806 FMC2_CSQCFGR2_RCMD2T; 807 if (!raw) { 808 csqcfgr2 |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN; 809 csqcfgr2 |= FMC2_CSQCFGR2_SQSDTEN; 810 } 811 812 /* 813 * - Set the number of sectors to be written 814 * - Set timings 815 */ 816 csqcfgr3 = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1); 817 if (write_data) { 818 csqcfgr3 |= FMC2_CSQCFGR3_RAC2T; 819 if (chip->options & NAND_ROW_ADDR_3) 820 csqcfgr3 |= FMC2_CSQCFGR3_AC5T; 821 else 822 csqcfgr3 |= FMC2_CSQCFGR3_AC4T; 823 } 824 825 /* 826 * Set the fourth first address cycles 827 * Byte 1 and byte 2 => column, we start at 0x0 828 * Byte 3 and byte 4 => page 829 */ 830 csqar1 = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page); 831 csqar1 |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8); 832 833 /* 834 * - Set chip enable number 835 * - Set ECC byte offset in the spare area 836 * - Calculate the number of address cycles to be issued 837 * - Set byte 5 of address cycle if needed 838 */ 839 csqar2 = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel); 840 if (chip->options & NAND_BUSWIDTH_16) 841 csqar2 |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1); 842 else 843 csqar2 |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset); 844 if (chip->options & NAND_ROW_ADDR_3) { 845 csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5); 846 csqar2 |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16); 847 } else { 848 csqcfgr1 |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4); 849 } 850 851 writel_relaxed(csqcfgr1, nfc->io_base + FMC2_CSQCFGR1); 852 writel_relaxed(csqcfgr2, nfc->io_base + FMC2_CSQCFGR2); 853 writel_relaxed(csqcfgr3, nfc->io_base + FMC2_CSQCFGR3); 854 writel_relaxed(csqar1, nfc->io_base + FMC2_CSQAR1); 855 writel_relaxed(csqar2, nfc->io_base + FMC2_CSQAR2); 856 } 857 858 static void stm32_fmc2_nfc_dma_callback(void *arg) 859 { 860 complete((struct completion *)arg); 861 } 862 863 /* Read/write data from/to a page */ 864 static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf, 865 int raw, bool write_data) 866 { 867 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 868 struct dma_async_tx_descriptor *desc_data, *desc_ecc; 869 struct scatterlist *sg; 870 struct dma_chan *dma_ch = nfc->dma_rx_ch; 871 enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE; 872 enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM; 873 u32 csqcr = readl_relaxed(nfc->io_base + FMC2_CSQCR); 874 int eccsteps = chip->ecc.steps; 875 int eccsize = chip->ecc.size; 876 unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS); 877 const u8 *p = buf; 878 int s, ret; 879 880 /* Configure DMA data */ 881 if (write_data) { 882 dma_data_dir = DMA_TO_DEVICE; 883 dma_transfer_dir = DMA_MEM_TO_DEV; 884 dma_ch = nfc->dma_tx_ch; 885 } 886 887 for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) { 888 sg_set_buf(sg, p, eccsize); 889 p += eccsize; 890 } 891 892 ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl, 893 eccsteps, dma_data_dir); 894 if (ret < 0) 895 return ret; 896 897 desc_data = dmaengine_prep_slave_sg(dma_ch, nfc->dma_data_sg.sgl, 898 eccsteps, dma_transfer_dir, 899 DMA_PREP_INTERRUPT); 900 if (!desc_data) { 901 ret = -ENOMEM; 902 goto err_unmap_data; 903 } 904 905 reinit_completion(&nfc->dma_data_complete); 906 reinit_completion(&nfc->complete); 907 desc_data->callback = stm32_fmc2_nfc_dma_callback; 908 desc_data->callback_param = &nfc->dma_data_complete; 909 ret = dma_submit_error(dmaengine_submit(desc_data)); 910 if (ret) 911 goto err_unmap_data; 912 913 dma_async_issue_pending(dma_ch); 914 915 if (!write_data && !raw) { 916 /* Configure DMA ECC status */ 917 p = nfc->ecc_buf; 918 for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) { 919 sg_set_buf(sg, p, nfc->dma_ecc_len); 920 p += nfc->dma_ecc_len; 921 } 922 923 ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl, 924 eccsteps, dma_data_dir); 925 if (ret < 0) 926 goto err_unmap_data; 927 928 desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch, 929 nfc->dma_ecc_sg.sgl, 930 eccsteps, dma_transfer_dir, 931 DMA_PREP_INTERRUPT); 932 if (!desc_ecc) { 933 ret = -ENOMEM; 934 goto err_unmap_ecc; 935 } 936 937 reinit_completion(&nfc->dma_ecc_complete); 938 desc_ecc->callback = stm32_fmc2_nfc_dma_callback; 939 desc_ecc->callback_param = &nfc->dma_ecc_complete; 940 ret = dma_submit_error(dmaengine_submit(desc_ecc)); 941 if (ret) 942 goto err_unmap_ecc; 943 944 dma_async_issue_pending(nfc->dma_ecc_ch); 945 } 946 947 stm32_fmc2_nfc_clear_seq_irq(nfc); 948 stm32_fmc2_nfc_enable_seq_irq(nfc); 949 950 /* Start the transfer */ 951 csqcr |= FMC2_CSQCR_CSQSTART; 952 writel_relaxed(csqcr, nfc->io_base + FMC2_CSQCR); 953 954 /* Wait end of sequencer transfer */ 955 if (!wait_for_completion_timeout(&nfc->complete, timeout)) { 956 dev_err(nfc->dev, "seq timeout\n"); 957 stm32_fmc2_nfc_disable_seq_irq(nfc); 958 dmaengine_terminate_all(dma_ch); 959 if (!write_data && !raw) 960 dmaengine_terminate_all(nfc->dma_ecc_ch); 961 ret = -ETIMEDOUT; 962 goto err_unmap_ecc; 963 } 964 965 /* Wait DMA data transfer completion */ 966 if (!wait_for_completion_timeout(&nfc->dma_data_complete, timeout)) { 967 dev_err(nfc->dev, "data DMA timeout\n"); 968 dmaengine_terminate_all(dma_ch); 969 ret = -ETIMEDOUT; 970 } 971 972 /* Wait DMA ECC transfer completion */ 973 if (!write_data && !raw) { 974 if (!wait_for_completion_timeout(&nfc->dma_ecc_complete, 975 timeout)) { 976 dev_err(nfc->dev, "ECC DMA timeout\n"); 977 dmaengine_terminate_all(nfc->dma_ecc_ch); 978 ret = -ETIMEDOUT; 979 } 980 } 981 982 err_unmap_ecc: 983 if (!write_data && !raw) 984 dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl, 985 eccsteps, dma_data_dir); 986 987 err_unmap_data: 988 dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir); 989 990 return ret; 991 } 992 993 static int stm32_fmc2_nfc_seq_write(struct nand_chip *chip, const u8 *buf, 994 int oob_required, int page, int raw) 995 { 996 struct mtd_info *mtd = nand_to_mtd(chip); 997 int ret; 998 999 /* Configure the sequencer */ 1000 stm32_fmc2_nfc_rw_page_init(chip, page, raw, true); 1001 1002 /* Write the page */ 1003 ret = stm32_fmc2_nfc_xfer(chip, buf, raw, true); 1004 if (ret) 1005 return ret; 1006 1007 /* Write oob */ 1008 if (oob_required) { 1009 ret = nand_change_write_column_op(chip, mtd->writesize, 1010 chip->oob_poi, mtd->oobsize, 1011 false); 1012 if (ret) 1013 return ret; 1014 } 1015 1016 return nand_prog_page_end_op(chip); 1017 } 1018 1019 static int stm32_fmc2_nfc_seq_write_page(struct nand_chip *chip, const u8 *buf, 1020 int oob_required, int page) 1021 { 1022 int ret; 1023 1024 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1025 if (ret) 1026 return ret; 1027 1028 return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, false); 1029 } 1030 1031 static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip, 1032 const u8 *buf, int oob_required, 1033 int page) 1034 { 1035 int ret; 1036 1037 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1038 if (ret) 1039 return ret; 1040 1041 return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, true); 1042 } 1043 1044 /* Get a status indicating which sectors have errors */ 1045 static inline u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc) 1046 { 1047 u32 csqemsr = readl_relaxed(nfc->io_base + FMC2_CSQEMSR); 1048 1049 return csqemsr & FMC2_CSQEMSR_SEM; 1050 } 1051 1052 static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat, 1053 u8 *read_ecc, u8 *calc_ecc) 1054 { 1055 struct mtd_info *mtd = nand_to_mtd(chip); 1056 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1057 int eccbytes = chip->ecc.bytes; 1058 int eccsteps = chip->ecc.steps; 1059 int eccstrength = chip->ecc.strength; 1060 int i, s, eccsize = chip->ecc.size; 1061 u32 *ecc_sta = (u32 *)nfc->ecc_buf; 1062 u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc); 1063 unsigned int max_bitflips = 0; 1064 1065 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) { 1066 int stat = 0; 1067 1068 if (eccstrength == FMC2_ECC_HAM) { 1069 /* Ecc_sta = FMC2_HECCR */ 1070 if (sta_map & BIT(s)) { 1071 stm32_fmc2_nfc_ham_set_ecc(*ecc_sta, 1072 &calc_ecc[i]); 1073 stat = stm32_fmc2_nfc_ham_correct(chip, dat, 1074 &read_ecc[i], 1075 &calc_ecc[i]); 1076 } 1077 ecc_sta++; 1078 } else { 1079 /* 1080 * Ecc_sta[0] = FMC2_BCHDSR0 1081 * Ecc_sta[1] = FMC2_BCHDSR1 1082 * Ecc_sta[2] = FMC2_BCHDSR2 1083 * Ecc_sta[3] = FMC2_BCHDSR3 1084 * Ecc_sta[4] = FMC2_BCHDSR4 1085 */ 1086 if (sta_map & BIT(s)) 1087 stat = stm32_fmc2_nfc_bch_decode(eccsize, dat, 1088 ecc_sta); 1089 ecc_sta += 5; 1090 } 1091 1092 if (stat == -EBADMSG) 1093 /* Check for empty pages with bitflips */ 1094 stat = nand_check_erased_ecc_chunk(dat, eccsize, 1095 &read_ecc[i], 1096 eccbytes, 1097 NULL, 0, 1098 eccstrength); 1099 1100 if (stat < 0) { 1101 mtd->ecc_stats.failed++; 1102 } else { 1103 mtd->ecc_stats.corrected += stat; 1104 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1105 } 1106 } 1107 1108 return max_bitflips; 1109 } 1110 1111 static int stm32_fmc2_nfc_seq_read_page(struct nand_chip *chip, u8 *buf, 1112 int oob_required, int page) 1113 { 1114 struct mtd_info *mtd = nand_to_mtd(chip); 1115 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1116 u8 *ecc_calc = chip->ecc.calc_buf; 1117 u8 *ecc_code = chip->ecc.code_buf; 1118 u16 sta_map; 1119 int ret; 1120 1121 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1122 if (ret) 1123 return ret; 1124 1125 /* Configure the sequencer */ 1126 stm32_fmc2_nfc_rw_page_init(chip, page, 0, false); 1127 1128 /* Read the page */ 1129 ret = stm32_fmc2_nfc_xfer(chip, buf, 0, false); 1130 if (ret) 1131 return ret; 1132 1133 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc); 1134 1135 /* Check if errors happen */ 1136 if (likely(!sta_map)) { 1137 if (oob_required) 1138 return nand_change_read_column_op(chip, mtd->writesize, 1139 chip->oob_poi, 1140 mtd->oobsize, false); 1141 1142 return 0; 1143 } 1144 1145 /* Read oob */ 1146 ret = nand_change_read_column_op(chip, mtd->writesize, 1147 chip->oob_poi, mtd->oobsize, false); 1148 if (ret) 1149 return ret; 1150 1151 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 1152 chip->ecc.total); 1153 if (ret) 1154 return ret; 1155 1156 /* Correct data */ 1157 return chip->ecc.correct(chip, buf, ecc_code, ecc_calc); 1158 } 1159 1160 static int stm32_fmc2_nfc_seq_read_page_raw(struct nand_chip *chip, u8 *buf, 1161 int oob_required, int page) 1162 { 1163 struct mtd_info *mtd = nand_to_mtd(chip); 1164 int ret; 1165 1166 ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs); 1167 if (ret) 1168 return ret; 1169 1170 /* Configure the sequencer */ 1171 stm32_fmc2_nfc_rw_page_init(chip, page, 1, false); 1172 1173 /* Read the page */ 1174 ret = stm32_fmc2_nfc_xfer(chip, buf, 1, false); 1175 if (ret) 1176 return ret; 1177 1178 /* Read oob */ 1179 if (oob_required) 1180 return nand_change_read_column_op(chip, mtd->writesize, 1181 chip->oob_poi, mtd->oobsize, 1182 false); 1183 1184 return 0; 1185 } 1186 1187 static irqreturn_t stm32_fmc2_nfc_irq(int irq, void *dev_id) 1188 { 1189 struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id; 1190 1191 if (nfc->irq_state == FMC2_IRQ_SEQ) 1192 /* Sequencer is used */ 1193 stm32_fmc2_nfc_disable_seq_irq(nfc); 1194 else if (nfc->irq_state == FMC2_IRQ_BCH) 1195 /* BCH is used */ 1196 stm32_fmc2_nfc_disable_bch_irq(nfc); 1197 1198 complete(&nfc->complete); 1199 1200 return IRQ_HANDLED; 1201 } 1202 1203 static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf, 1204 unsigned int len, bool force_8bit) 1205 { 1206 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1207 void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel]; 1208 1209 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1210 /* Reconfigure bus width to 8-bit */ 1211 stm32_fmc2_nfc_set_buswidth_16(nfc, false); 1212 1213 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) { 1214 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) { 1215 *(u8 *)buf = readb_relaxed(io_addr_r); 1216 buf += sizeof(u8); 1217 len -= sizeof(u8); 1218 } 1219 1220 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 1221 len >= sizeof(u16)) { 1222 *(u16 *)buf = readw_relaxed(io_addr_r); 1223 buf += sizeof(u16); 1224 len -= sizeof(u16); 1225 } 1226 } 1227 1228 /* Buf is aligned */ 1229 while (len >= sizeof(u32)) { 1230 *(u32 *)buf = readl_relaxed(io_addr_r); 1231 buf += sizeof(u32); 1232 len -= sizeof(u32); 1233 } 1234 1235 /* Read remaining bytes */ 1236 if (len >= sizeof(u16)) { 1237 *(u16 *)buf = readw_relaxed(io_addr_r); 1238 buf += sizeof(u16); 1239 len -= sizeof(u16); 1240 } 1241 1242 if (len) 1243 *(u8 *)buf = readb_relaxed(io_addr_r); 1244 1245 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1246 /* Reconfigure bus width to 16-bit */ 1247 stm32_fmc2_nfc_set_buswidth_16(nfc, true); 1248 } 1249 1250 static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf, 1251 unsigned int len, bool force_8bit) 1252 { 1253 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1254 void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel]; 1255 1256 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1257 /* Reconfigure bus width to 8-bit */ 1258 stm32_fmc2_nfc_set_buswidth_16(nfc, false); 1259 1260 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) { 1261 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) { 1262 writeb_relaxed(*(u8 *)buf, io_addr_w); 1263 buf += sizeof(u8); 1264 len -= sizeof(u8); 1265 } 1266 1267 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 1268 len >= sizeof(u16)) { 1269 writew_relaxed(*(u16 *)buf, io_addr_w); 1270 buf += sizeof(u16); 1271 len -= sizeof(u16); 1272 } 1273 } 1274 1275 /* Buf is aligned */ 1276 while (len >= sizeof(u32)) { 1277 writel_relaxed(*(u32 *)buf, io_addr_w); 1278 buf += sizeof(u32); 1279 len -= sizeof(u32); 1280 } 1281 1282 /* Write remaining bytes */ 1283 if (len >= sizeof(u16)) { 1284 writew_relaxed(*(u16 *)buf, io_addr_w); 1285 buf += sizeof(u16); 1286 len -= sizeof(u16); 1287 } 1288 1289 if (len) 1290 writeb_relaxed(*(u8 *)buf, io_addr_w); 1291 1292 if (force_8bit && chip->options & NAND_BUSWIDTH_16) 1293 /* Reconfigure bus width to 16-bit */ 1294 stm32_fmc2_nfc_set_buswidth_16(nfc, true); 1295 } 1296 1297 static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip, 1298 unsigned long timeout_ms) 1299 { 1300 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1301 const struct nand_sdr_timings *timings; 1302 u32 isr, sr; 1303 1304 /* Check if there is no pending requests to the NAND flash */ 1305 if (readl_relaxed_poll_timeout_atomic(nfc->io_base + FMC2_SR, sr, 1306 sr & FMC2_SR_NWRF, 1, 1307 1000 * FMC2_TIMEOUT_MS)) 1308 dev_warn(nfc->dev, "Waitrdy timeout\n"); 1309 1310 /* Wait tWB before R/B# signal is low */ 1311 timings = nand_get_sdr_timings(&chip->data_interface); 1312 ndelay(PSEC_TO_NSEC(timings->tWB_max)); 1313 1314 /* R/B# signal is low, clear high level flag */ 1315 writel_relaxed(FMC2_ICR_CIHLF, nfc->io_base + FMC2_ICR); 1316 1317 /* Wait R/B# signal is high */ 1318 return readl_relaxed_poll_timeout_atomic(nfc->io_base + FMC2_ISR, 1319 isr, isr & FMC2_ISR_IHLF, 1320 5, 1000 * timeout_ms); 1321 } 1322 1323 static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip, 1324 const struct nand_operation *op, 1325 bool check_only) 1326 { 1327 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1328 const struct nand_op_instr *instr = NULL; 1329 unsigned int op_id, i, timeout; 1330 int ret; 1331 1332 if (check_only) 1333 return 0; 1334 1335 ret = stm32_fmc2_nfc_select_chip(chip, op->cs); 1336 if (ret) 1337 return ret; 1338 1339 for (op_id = 0; op_id < op->ninstrs; op_id++) { 1340 instr = &op->instrs[op_id]; 1341 1342 switch (instr->type) { 1343 case NAND_OP_CMD_INSTR: 1344 writeb_relaxed(instr->ctx.cmd.opcode, 1345 nfc->cmd_base[nfc->cs_sel]); 1346 break; 1347 1348 case NAND_OP_ADDR_INSTR: 1349 for (i = 0; i < instr->ctx.addr.naddrs; i++) 1350 writeb_relaxed(instr->ctx.addr.addrs[i], 1351 nfc->addr_base[nfc->cs_sel]); 1352 break; 1353 1354 case NAND_OP_DATA_IN_INSTR: 1355 stm32_fmc2_nfc_read_data(chip, instr->ctx.data.buf.in, 1356 instr->ctx.data.len, 1357 instr->ctx.data.force_8bit); 1358 break; 1359 1360 case NAND_OP_DATA_OUT_INSTR: 1361 stm32_fmc2_nfc_write_data(chip, instr->ctx.data.buf.out, 1362 instr->ctx.data.len, 1363 instr->ctx.data.force_8bit); 1364 break; 1365 1366 case NAND_OP_WAITRDY_INSTR: 1367 timeout = instr->ctx.waitrdy.timeout_ms; 1368 ret = stm32_fmc2_nfc_waitrdy(chip, timeout); 1369 break; 1370 } 1371 } 1372 1373 return ret; 1374 } 1375 1376 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc) 1377 { 1378 u32 pcr = readl_relaxed(nfc->io_base + FMC2_PCR); 1379 u32 bcr1 = readl_relaxed(nfc->io_base + FMC2_BCR1); 1380 1381 /* Set CS used to undefined */ 1382 nfc->cs_sel = -1; 1383 1384 /* Enable wait feature and nand flash memory bank */ 1385 pcr |= FMC2_PCR_PWAITEN; 1386 pcr |= FMC2_PCR_PBKEN; 1387 1388 /* Set buswidth to 8 bits mode for identification */ 1389 pcr &= ~FMC2_PCR_PWID; 1390 1391 /* ECC logic is disabled */ 1392 pcr &= ~FMC2_PCR_ECCEN; 1393 1394 /* Default mode */ 1395 pcr &= ~FMC2_PCR_ECCALG; 1396 pcr &= ~FMC2_PCR_BCHECC; 1397 pcr &= ~FMC2_PCR_WEN; 1398 1399 /* Set default ECC sector size */ 1400 pcr &= ~FMC2_PCR_ECCSS; 1401 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048); 1402 1403 /* Set default tclr/tar timings */ 1404 pcr &= ~FMC2_PCR_TCLR; 1405 pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT); 1406 pcr &= ~FMC2_PCR_TAR; 1407 pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); 1408 1409 /* Enable FMC2 controller */ 1410 bcr1 |= FMC2_BCR1_FMC2EN; 1411 1412 writel_relaxed(bcr1, nfc->io_base + FMC2_BCR1); 1413 writel_relaxed(pcr, nfc->io_base + FMC2_PCR); 1414 writel_relaxed(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM); 1415 writel_relaxed(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT); 1416 } 1417 1418 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip, 1419 const struct nand_sdr_timings *sdrt) 1420 { 1421 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1422 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 1423 struct stm32_fmc2_timings *tims = &nand->timings; 1424 unsigned long hclk = clk_get_rate(nfc->clk); 1425 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); 1426 unsigned long timing, tar, tclr, thiz, twait; 1427 unsigned long tset_mem, tset_att, thold_mem, thold_att; 1428 1429 tar = max_t(unsigned long, hclkp, sdrt->tAR_min); 1430 timing = DIV_ROUND_UP(tar, hclkp) - 1; 1431 tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); 1432 1433 tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min); 1434 timing = DIV_ROUND_UP(tclr, hclkp) - 1; 1435 tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); 1436 1437 tims->thiz = FMC2_THIZ; 1438 thiz = (tims->thiz + 1) * hclkp; 1439 1440 /* 1441 * tWAIT > tRP 1442 * tWAIT > tWP 1443 * tWAIT > tREA + tIO 1444 */ 1445 twait = max_t(unsigned long, hclkp, sdrt->tRP_min); 1446 twait = max_t(unsigned long, twait, sdrt->tWP_min); 1447 twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO); 1448 timing = DIV_ROUND_UP(twait, hclkp); 1449 tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1450 1451 /* 1452 * tSETUP_MEM > tCS - tWAIT 1453 * tSETUP_MEM > tALS - tWAIT 1454 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 1455 */ 1456 tset_mem = hclkp; 1457 if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait)) 1458 tset_mem = sdrt->tCS_min - twait; 1459 if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait)) 1460 tset_mem = sdrt->tALS_min - twait; 1461 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 1462 (tset_mem < sdrt->tDS_min - (twait - thiz))) 1463 tset_mem = sdrt->tDS_min - (twait - thiz); 1464 timing = DIV_ROUND_UP(tset_mem, hclkp); 1465 tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1466 1467 /* 1468 * tHOLD_MEM > tCH 1469 * tHOLD_MEM > tREH - tSETUP_MEM 1470 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 1471 */ 1472 thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min); 1473 if (sdrt->tREH_min > tset_mem && 1474 (thold_mem < sdrt->tREH_min - tset_mem)) 1475 thold_mem = sdrt->tREH_min - tset_mem; 1476 if ((sdrt->tRC_min > tset_mem + twait) && 1477 (thold_mem < sdrt->tRC_min - (tset_mem + twait))) 1478 thold_mem = sdrt->tRC_min - (tset_mem + twait); 1479 if ((sdrt->tWC_min > tset_mem + twait) && 1480 (thold_mem < sdrt->tWC_min - (tset_mem + twait))) 1481 thold_mem = sdrt->tWC_min - (tset_mem + twait); 1482 timing = DIV_ROUND_UP(thold_mem, hclkp); 1483 tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1484 1485 /* 1486 * tSETUP_ATT > tCS - tWAIT 1487 * tSETUP_ATT > tCLS - tWAIT 1488 * tSETUP_ATT > tALS - tWAIT 1489 * tSETUP_ATT > tRHW - tHOLD_MEM 1490 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 1491 */ 1492 tset_att = hclkp; 1493 if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait)) 1494 tset_att = sdrt->tCS_min - twait; 1495 if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait)) 1496 tset_att = sdrt->tCLS_min - twait; 1497 if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait)) 1498 tset_att = sdrt->tALS_min - twait; 1499 if (sdrt->tRHW_min > thold_mem && 1500 (tset_att < sdrt->tRHW_min - thold_mem)) 1501 tset_att = sdrt->tRHW_min - thold_mem; 1502 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 1503 (tset_att < sdrt->tDS_min - (twait - thiz))) 1504 tset_att = sdrt->tDS_min - (twait - thiz); 1505 timing = DIV_ROUND_UP(tset_att, hclkp); 1506 tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1507 1508 /* 1509 * tHOLD_ATT > tALH 1510 * tHOLD_ATT > tCH 1511 * tHOLD_ATT > tCLH 1512 * tHOLD_ATT > tCOH 1513 * tHOLD_ATT > tDH 1514 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 1515 * tHOLD_ATT > tADL - tSETUP_MEM 1516 * tHOLD_ATT > tWH - tSETUP_MEM 1517 * tHOLD_ATT > tWHR - tSETUP_MEM 1518 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 1519 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 1520 */ 1521 thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min); 1522 thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min); 1523 thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min); 1524 thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min); 1525 thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min); 1526 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && 1527 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) 1528 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; 1529 if (sdrt->tADL_min > tset_mem && 1530 (thold_att < sdrt->tADL_min - tset_mem)) 1531 thold_att = sdrt->tADL_min - tset_mem; 1532 if (sdrt->tWH_min > tset_mem && 1533 (thold_att < sdrt->tWH_min - tset_mem)) 1534 thold_att = sdrt->tWH_min - tset_mem; 1535 if (sdrt->tWHR_min > tset_mem && 1536 (thold_att < sdrt->tWHR_min - tset_mem)) 1537 thold_att = sdrt->tWHR_min - tset_mem; 1538 if ((sdrt->tRC_min > tset_att + twait) && 1539 (thold_att < sdrt->tRC_min - (tset_att + twait))) 1540 thold_att = sdrt->tRC_min - (tset_att + twait); 1541 if ((sdrt->tWC_min > tset_att + twait) && 1542 (thold_att < sdrt->tWC_min - (tset_att + twait))) 1543 thold_att = sdrt->tWC_min - (tset_att + twait); 1544 timing = DIV_ROUND_UP(thold_att, hclkp); 1545 tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 1546 } 1547 1548 static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, 1549 const struct nand_data_interface *conf) 1550 { 1551 const struct nand_sdr_timings *sdrt; 1552 1553 sdrt = nand_get_sdr_timings(conf); 1554 if (IS_ERR(sdrt)) 1555 return PTR_ERR(sdrt); 1556 1557 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 1558 return 0; 1559 1560 stm32_fmc2_nfc_calc_timings(chip, sdrt); 1561 stm32_fmc2_nfc_timings_init(chip); 1562 1563 return 0; 1564 } 1565 1566 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) 1567 { 1568 int ret = 0; 1569 1570 nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx"); 1571 if (IS_ERR(nfc->dma_tx_ch)) { 1572 ret = PTR_ERR(nfc->dma_tx_ch); 1573 if (ret != -ENODEV) 1574 dev_err(nfc->dev, 1575 "failed to request tx DMA channel: %d\n", ret); 1576 nfc->dma_tx_ch = NULL; 1577 goto err_dma; 1578 } 1579 1580 nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx"); 1581 if (IS_ERR(nfc->dma_rx_ch)) { 1582 ret = PTR_ERR(nfc->dma_rx_ch); 1583 if (ret != -ENODEV) 1584 dev_err(nfc->dev, 1585 "failed to request rx DMA channel: %d\n", ret); 1586 nfc->dma_rx_ch = NULL; 1587 goto err_dma; 1588 } 1589 1590 nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc"); 1591 if (IS_ERR(nfc->dma_ecc_ch)) { 1592 ret = PTR_ERR(nfc->dma_ecc_ch); 1593 if (ret != -ENODEV) 1594 dev_err(nfc->dev, 1595 "failed to request ecc DMA channel: %d\n", ret); 1596 nfc->dma_ecc_ch = NULL; 1597 goto err_dma; 1598 } 1599 1600 ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL); 1601 if (ret) 1602 return ret; 1603 1604 /* Allocate a buffer to store ECC status registers */ 1605 nfc->ecc_buf = devm_kzalloc(nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL); 1606 if (!nfc->ecc_buf) 1607 return -ENOMEM; 1608 1609 ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL); 1610 if (ret) 1611 return ret; 1612 1613 init_completion(&nfc->dma_data_complete); 1614 init_completion(&nfc->dma_ecc_complete); 1615 1616 return 0; 1617 1618 err_dma: 1619 if (ret == -ENODEV) { 1620 dev_warn(nfc->dev, 1621 "DMAs not defined in the DT, polling mode is used\n"); 1622 ret = 0; 1623 } 1624 1625 return ret; 1626 } 1627 1628 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip) 1629 { 1630 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1631 1632 /* 1633 * Specific callbacks to read/write a page depending on 1634 * the mode (polling/sequencer) and the algo used (Hamming, BCH). 1635 */ 1636 if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) { 1637 /* DMA => use sequencer mode callbacks */ 1638 chip->ecc.correct = stm32_fmc2_nfc_seq_correct; 1639 chip->ecc.write_page = stm32_fmc2_nfc_seq_write_page; 1640 chip->ecc.read_page = stm32_fmc2_nfc_seq_read_page; 1641 chip->ecc.write_page_raw = stm32_fmc2_nfc_seq_write_page_raw; 1642 chip->ecc.read_page_raw = stm32_fmc2_nfc_seq_read_page_raw; 1643 } else { 1644 /* No DMA => use polling mode callbacks */ 1645 chip->ecc.hwctl = stm32_fmc2_nfc_hwctl; 1646 if (chip->ecc.strength == FMC2_ECC_HAM) { 1647 /* Hamming is used */ 1648 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate; 1649 chip->ecc.correct = stm32_fmc2_nfc_ham_correct; 1650 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK; 1651 } else { 1652 /* BCH is used */ 1653 chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate; 1654 chip->ecc.correct = stm32_fmc2_nfc_bch_correct; 1655 chip->ecc.read_page = stm32_fmc2_nfc_read_page; 1656 } 1657 } 1658 1659 /* Specific configurations depending on the algo used */ 1660 if (chip->ecc.strength == FMC2_ECC_HAM) 1661 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3; 1662 else if (chip->ecc.strength == FMC2_ECC_BCH8) 1663 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13; 1664 else 1665 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7; 1666 } 1667 1668 static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, 1669 struct mtd_oob_region *oobregion) 1670 { 1671 struct nand_chip *chip = mtd_to_nand(mtd); 1672 struct nand_ecc_ctrl *ecc = &chip->ecc; 1673 1674 if (section) 1675 return -ERANGE; 1676 1677 oobregion->length = ecc->total; 1678 oobregion->offset = FMC2_BBM_LEN; 1679 1680 return 0; 1681 } 1682 1683 static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section, 1684 struct mtd_oob_region *oobregion) 1685 { 1686 struct nand_chip *chip = mtd_to_nand(mtd); 1687 struct nand_ecc_ctrl *ecc = &chip->ecc; 1688 1689 if (section) 1690 return -ERANGE; 1691 1692 oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN; 1693 oobregion->offset = ecc->total + FMC2_BBM_LEN; 1694 1695 return 0; 1696 } 1697 1698 static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = { 1699 .ecc = stm32_fmc2_nfc_ooblayout_ecc, 1700 .free = stm32_fmc2_nfc_ooblayout_free, 1701 }; 1702 1703 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength) 1704 { 1705 /* Hamming */ 1706 if (strength == FMC2_ECC_HAM) 1707 return 4; 1708 1709 /* BCH8 */ 1710 if (strength == FMC2_ECC_BCH8) 1711 return 14; 1712 1713 /* BCH4 */ 1714 return 8; 1715 } 1716 1717 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes, 1718 FMC2_ECC_STEP_SIZE, 1719 FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8); 1720 1721 static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip) 1722 { 1723 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 1724 struct mtd_info *mtd = nand_to_mtd(chip); 1725 int ret; 1726 1727 /* 1728 * Only NAND_ECC_HW mode is actually supported 1729 * Hamming => ecc.strength = 1 1730 * BCH4 => ecc.strength = 4 1731 * BCH8 => ecc.strength = 8 1732 * ECC sector size = 512 1733 */ 1734 if (chip->ecc.mode != NAND_ECC_HW) { 1735 dev_err(nfc->dev, "nand_ecc_mode is not well defined in the DT\n"); 1736 return -EINVAL; 1737 } 1738 1739 ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps, 1740 mtd->oobsize - FMC2_BBM_LEN); 1741 if (ret) { 1742 dev_err(nfc->dev, "no valid ECC settings set\n"); 1743 return ret; 1744 } 1745 1746 if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) { 1747 dev_err(nfc->dev, "nand page size is not supported\n"); 1748 return -EINVAL; 1749 } 1750 1751 if (chip->bbt_options & NAND_BBT_USE_FLASH) 1752 chip->bbt_options |= NAND_BBT_NO_OOB; 1753 1754 stm32_fmc2_nfc_nand_callbacks_setup(chip); 1755 1756 mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops); 1757 1758 if (chip->options & NAND_BUSWIDTH_16) 1759 stm32_fmc2_nfc_set_buswidth_16(nfc, true); 1760 1761 return 0; 1762 } 1763 1764 static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = { 1765 .attach_chip = stm32_fmc2_nfc_attach_chip, 1766 .exec_op = stm32_fmc2_nfc_exec_op, 1767 .setup_data_interface = stm32_fmc2_nfc_setup_interface, 1768 }; 1769 1770 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, 1771 struct device_node *dn) 1772 { 1773 struct stm32_fmc2_nand *nand = &nfc->nand; 1774 u32 cs; 1775 int ret, i; 1776 1777 if (!of_get_property(dn, "reg", &nand->ncs)) 1778 return -EINVAL; 1779 1780 nand->ncs /= sizeof(u32); 1781 if (!nand->ncs) { 1782 dev_err(nfc->dev, "invalid reg property size\n"); 1783 return -EINVAL; 1784 } 1785 1786 for (i = 0; i < nand->ncs; i++) { 1787 ret = of_property_read_u32_index(dn, "reg", i, &cs); 1788 if (ret) { 1789 dev_err(nfc->dev, "could not retrieve reg property: %d\n", 1790 ret); 1791 return ret; 1792 } 1793 1794 if (cs > FMC2_MAX_CE) { 1795 dev_err(nfc->dev, "invalid reg value: %d\n", cs); 1796 return -EINVAL; 1797 } 1798 1799 if (nfc->cs_assigned & BIT(cs)) { 1800 dev_err(nfc->dev, "cs already assigned: %d\n", cs); 1801 return -EINVAL; 1802 } 1803 1804 nfc->cs_assigned |= BIT(cs); 1805 nand->cs_used[i] = cs; 1806 } 1807 1808 nand_set_flash_node(&nand->chip, dn); 1809 1810 return 0; 1811 } 1812 1813 static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc) 1814 { 1815 struct device_node *dn = nfc->dev->of_node; 1816 struct device_node *child; 1817 int nchips = of_get_child_count(dn); 1818 int ret = 0; 1819 1820 if (!nchips) { 1821 dev_err(nfc->dev, "NAND chip not defined\n"); 1822 return -EINVAL; 1823 } 1824 1825 if (nchips > 1) { 1826 dev_err(nfc->dev, "too many NAND chips defined\n"); 1827 return -EINVAL; 1828 } 1829 1830 for_each_child_of_node(dn, child) { 1831 ret = stm32_fmc2_nfc_parse_child(nfc, child); 1832 if (ret < 0) { 1833 of_node_put(child); 1834 return ret; 1835 } 1836 } 1837 1838 return ret; 1839 } 1840 1841 static int stm32_fmc2_nfc_probe(struct platform_device *pdev) 1842 { 1843 struct device *dev = &pdev->dev; 1844 struct reset_control *rstc; 1845 struct stm32_fmc2_nfc *nfc; 1846 struct stm32_fmc2_nand *nand; 1847 struct resource *res; 1848 struct mtd_info *mtd; 1849 struct nand_chip *chip; 1850 int chip_cs, mem_region, ret, irq; 1851 1852 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1853 if (!nfc) 1854 return -ENOMEM; 1855 1856 nfc->dev = dev; 1857 nand_controller_init(&nfc->base); 1858 nfc->base.ops = &stm32_fmc2_nfc_controller_ops; 1859 1860 ret = stm32_fmc2_nfc_parse_dt(nfc); 1861 if (ret) 1862 return ret; 1863 1864 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1865 nfc->io_base = devm_ioremap_resource(dev, res); 1866 if (IS_ERR(nfc->io_base)) 1867 return PTR_ERR(nfc->io_base); 1868 1869 nfc->io_phys_addr = res->start; 1870 1871 for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE; 1872 chip_cs++, mem_region += 3) { 1873 if (!(nfc->cs_assigned & BIT(chip_cs))) 1874 continue; 1875 1876 res = platform_get_resource(pdev, IORESOURCE_MEM, mem_region); 1877 nfc->data_base[chip_cs] = devm_ioremap_resource(dev, res); 1878 if (IS_ERR(nfc->data_base[chip_cs])) 1879 return PTR_ERR(nfc->data_base[chip_cs]); 1880 1881 nfc->data_phys_addr[chip_cs] = res->start; 1882 1883 res = platform_get_resource(pdev, IORESOURCE_MEM, 1884 mem_region + 1); 1885 nfc->cmd_base[chip_cs] = devm_ioremap_resource(dev, res); 1886 if (IS_ERR(nfc->cmd_base[chip_cs])) 1887 return PTR_ERR(nfc->cmd_base[chip_cs]); 1888 1889 res = platform_get_resource(pdev, IORESOURCE_MEM, 1890 mem_region + 2); 1891 nfc->addr_base[chip_cs] = devm_ioremap_resource(dev, res); 1892 if (IS_ERR(nfc->addr_base[chip_cs])) 1893 return PTR_ERR(nfc->addr_base[chip_cs]); 1894 } 1895 1896 irq = platform_get_irq(pdev, 0); 1897 if (irq < 0) 1898 return irq; 1899 1900 ret = devm_request_irq(dev, irq, stm32_fmc2_nfc_irq, 0, 1901 dev_name(dev), nfc); 1902 if (ret) { 1903 dev_err(dev, "failed to request irq\n"); 1904 return ret; 1905 } 1906 1907 init_completion(&nfc->complete); 1908 1909 nfc->clk = devm_clk_get(dev, NULL); 1910 if (IS_ERR(nfc->clk)) 1911 return PTR_ERR(nfc->clk); 1912 1913 ret = clk_prepare_enable(nfc->clk); 1914 if (ret) { 1915 dev_err(dev, "can not enable the clock\n"); 1916 return ret; 1917 } 1918 1919 rstc = devm_reset_control_get(dev, NULL); 1920 if (IS_ERR(rstc)) { 1921 ret = PTR_ERR(rstc); 1922 if (ret == -EPROBE_DEFER) 1923 goto err_clk_disable; 1924 } else { 1925 reset_control_assert(rstc); 1926 reset_control_deassert(rstc); 1927 } 1928 1929 ret = stm32_fmc2_nfc_dma_setup(nfc); 1930 if (ret) 1931 goto err_release_dma; 1932 1933 stm32_fmc2_nfc_init(nfc); 1934 1935 nand = &nfc->nand; 1936 chip = &nand->chip; 1937 mtd = nand_to_mtd(chip); 1938 mtd->dev.parent = dev; 1939 1940 chip->controller = &nfc->base; 1941 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | 1942 NAND_USES_DMA; 1943 1944 /* Default ECC settings */ 1945 chip->ecc.mode = NAND_ECC_HW; 1946 chip->ecc.size = FMC2_ECC_STEP_SIZE; 1947 chip->ecc.strength = FMC2_ECC_BCH8; 1948 1949 /* Scan to find existence of the device */ 1950 ret = nand_scan(chip, nand->ncs); 1951 if (ret) 1952 goto err_release_dma; 1953 1954 ret = mtd_device_register(mtd, NULL, 0); 1955 if (ret) 1956 goto err_nand_cleanup; 1957 1958 platform_set_drvdata(pdev, nfc); 1959 1960 return 0; 1961 1962 err_nand_cleanup: 1963 nand_cleanup(chip); 1964 1965 err_release_dma: 1966 if (nfc->dma_ecc_ch) 1967 dma_release_channel(nfc->dma_ecc_ch); 1968 if (nfc->dma_tx_ch) 1969 dma_release_channel(nfc->dma_tx_ch); 1970 if (nfc->dma_rx_ch) 1971 dma_release_channel(nfc->dma_rx_ch); 1972 1973 sg_free_table(&nfc->dma_data_sg); 1974 sg_free_table(&nfc->dma_ecc_sg); 1975 1976 err_clk_disable: 1977 clk_disable_unprepare(nfc->clk); 1978 1979 return ret; 1980 } 1981 1982 static int stm32_fmc2_nfc_remove(struct platform_device *pdev) 1983 { 1984 struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev); 1985 struct stm32_fmc2_nand *nand = &nfc->nand; 1986 struct nand_chip *chip = &nand->chip; 1987 int ret; 1988 1989 ret = mtd_device_unregister(nand_to_mtd(chip)); 1990 WARN_ON(ret); 1991 nand_cleanup(chip); 1992 1993 if (nfc->dma_ecc_ch) 1994 dma_release_channel(nfc->dma_ecc_ch); 1995 if (nfc->dma_tx_ch) 1996 dma_release_channel(nfc->dma_tx_ch); 1997 if (nfc->dma_rx_ch) 1998 dma_release_channel(nfc->dma_rx_ch); 1999 2000 sg_free_table(&nfc->dma_data_sg); 2001 sg_free_table(&nfc->dma_ecc_sg); 2002 2003 clk_disable_unprepare(nfc->clk); 2004 2005 return 0; 2006 } 2007 2008 static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev) 2009 { 2010 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev); 2011 2012 clk_disable_unprepare(nfc->clk); 2013 2014 pinctrl_pm_select_sleep_state(dev); 2015 2016 return 0; 2017 } 2018 2019 static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev) 2020 { 2021 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev); 2022 struct stm32_fmc2_nand *nand = &nfc->nand; 2023 int chip_cs, ret; 2024 2025 pinctrl_pm_select_default_state(dev); 2026 2027 ret = clk_prepare_enable(nfc->clk); 2028 if (ret) { 2029 dev_err(dev, "can not enable the clock\n"); 2030 return ret; 2031 } 2032 2033 stm32_fmc2_nfc_init(nfc); 2034 2035 for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) { 2036 if (!(nfc->cs_assigned & BIT(chip_cs))) 2037 continue; 2038 2039 nand_reset(&nand->chip, chip_cs); 2040 } 2041 2042 return 0; 2043 } 2044 2045 static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend, 2046 stm32_fmc2_nfc_resume); 2047 2048 static const struct of_device_id stm32_fmc2_nfc_match[] = { 2049 {.compatible = "st,stm32mp15-fmc2"}, 2050 {} 2051 }; 2052 MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match); 2053 2054 static struct platform_driver stm32_fmc2_nfc_driver = { 2055 .probe = stm32_fmc2_nfc_probe, 2056 .remove = stm32_fmc2_nfc_remove, 2057 .driver = { 2058 .name = "stm32_fmc2_nfc", 2059 .of_match_table = stm32_fmc2_nfc_match, 2060 .pm = &stm32_fmc2_nfc_pm_ops, 2061 }, 2062 }; 2063 module_platform_driver(stm32_fmc2_nfc_driver); 2064 2065 MODULE_ALIAS("platform:stm32_fmc2_nfc"); 2066 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>"); 2067 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 NFC driver"); 2068 MODULE_LICENSE("GPL v2"); 2069