1 /* 2 * Copyright © 2008 Ilya Yanok, Emcraft Systems 3 * 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/mtd/mtd.h> 14 #include <linux/mtd/rawnand.h> 15 #include <linux/mtd/partitions.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/io.h> 19 20 #define FPGA_NAND_CMD_MASK (0x7 << 28) 21 #define FPGA_NAND_CMD_COMMAND (0x0 << 28) 22 #define FPGA_NAND_CMD_ADDR (0x1 << 28) 23 #define FPGA_NAND_CMD_READ (0x2 << 28) 24 #define FPGA_NAND_CMD_WRITE (0x3 << 28) 25 #define FPGA_NAND_BUSY (0x1 << 15) 26 #define FPGA_NAND_ENABLE (0x1 << 31) 27 #define FPGA_NAND_DATA_SHIFT 16 28 29 struct socrates_nand_host { 30 struct nand_chip nand_chip; 31 void __iomem *io_base; 32 struct device *dev; 33 }; 34 35 /** 36 * socrates_nand_write_buf - write buffer to chip 37 * @this: NAND chip object 38 * @buf: data buffer 39 * @len: number of bytes to write 40 */ 41 static void socrates_nand_write_buf(struct nand_chip *this, const uint8_t *buf, 42 int len) 43 { 44 int i; 45 struct socrates_nand_host *host = nand_get_controller_data(this); 46 47 for (i = 0; i < len; i++) { 48 out_be32(host->io_base, FPGA_NAND_ENABLE | 49 FPGA_NAND_CMD_WRITE | 50 (buf[i] << FPGA_NAND_DATA_SHIFT)); 51 } 52 } 53 54 /** 55 * socrates_nand_read_buf - read chip data into buffer 56 * @this: NAND chip object 57 * @buf: buffer to store date 58 * @len: number of bytes to read 59 */ 60 static void socrates_nand_read_buf(struct nand_chip *this, uint8_t *buf, 61 int len) 62 { 63 int i; 64 struct socrates_nand_host *host = nand_get_controller_data(this); 65 uint32_t val; 66 67 val = FPGA_NAND_ENABLE | FPGA_NAND_CMD_READ; 68 69 out_be32(host->io_base, val); 70 for (i = 0; i < len; i++) { 71 buf[i] = (in_be32(host->io_base) >> 72 FPGA_NAND_DATA_SHIFT) & 0xff; 73 } 74 } 75 76 /** 77 * socrates_nand_read_byte - read one byte from the chip 78 * @mtd: MTD device structure 79 */ 80 static uint8_t socrates_nand_read_byte(struct nand_chip *this) 81 { 82 uint8_t byte; 83 socrates_nand_read_buf(this, &byte, sizeof(byte)); 84 return byte; 85 } 86 87 /* 88 * Hardware specific access to control-lines 89 */ 90 static void socrates_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd, 91 unsigned int ctrl) 92 { 93 struct socrates_nand_host *host = nand_get_controller_data(nand_chip); 94 uint32_t val; 95 96 if (cmd == NAND_CMD_NONE) 97 return; 98 99 if (ctrl & NAND_CLE) 100 val = FPGA_NAND_CMD_COMMAND; 101 else 102 val = FPGA_NAND_CMD_ADDR; 103 104 if (ctrl & NAND_NCE) 105 val |= FPGA_NAND_ENABLE; 106 107 val |= (cmd & 0xff) << FPGA_NAND_DATA_SHIFT; 108 109 out_be32(host->io_base, val); 110 } 111 112 /* 113 * Read the Device Ready pin. 114 */ 115 static int socrates_nand_device_ready(struct nand_chip *nand_chip) 116 { 117 struct socrates_nand_host *host = nand_get_controller_data(nand_chip); 118 119 if (in_be32(host->io_base) & FPGA_NAND_BUSY) 120 return 0; /* busy */ 121 return 1; 122 } 123 124 /* 125 * Probe for the NAND device. 126 */ 127 static int socrates_nand_probe(struct platform_device *ofdev) 128 { 129 struct socrates_nand_host *host; 130 struct mtd_info *mtd; 131 struct nand_chip *nand_chip; 132 int res; 133 134 /* Allocate memory for the device structure (and zero it) */ 135 host = devm_kzalloc(&ofdev->dev, sizeof(*host), GFP_KERNEL); 136 if (!host) 137 return -ENOMEM; 138 139 host->io_base = of_iomap(ofdev->dev.of_node, 0); 140 if (host->io_base == NULL) { 141 dev_err(&ofdev->dev, "ioremap failed\n"); 142 return -EIO; 143 } 144 145 nand_chip = &host->nand_chip; 146 mtd = nand_to_mtd(nand_chip); 147 host->dev = &ofdev->dev; 148 149 /* link the private data structures */ 150 nand_set_controller_data(nand_chip, host); 151 nand_set_flash_node(nand_chip, ofdev->dev.of_node); 152 mtd->name = "socrates_nand"; 153 mtd->dev.parent = &ofdev->dev; 154 155 nand_chip->legacy.cmd_ctrl = socrates_nand_cmd_ctrl; 156 nand_chip->legacy.read_byte = socrates_nand_read_byte; 157 nand_chip->legacy.write_buf = socrates_nand_write_buf; 158 nand_chip->legacy.read_buf = socrates_nand_read_buf; 159 nand_chip->legacy.dev_ready = socrates_nand_device_ready; 160 161 nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */ 162 nand_chip->ecc.algo = NAND_ECC_HAMMING; 163 164 /* TODO: I have no idea what real delay is. */ 165 nand_chip->legacy.chip_delay = 20; /* 20us command delay time */ 166 167 dev_set_drvdata(&ofdev->dev, host); 168 169 res = nand_scan(nand_chip, 1); 170 if (res) 171 goto out; 172 173 res = mtd_device_register(mtd, NULL, 0); 174 if (!res) 175 return res; 176 177 nand_release(nand_chip); 178 179 out: 180 iounmap(host->io_base); 181 return res; 182 } 183 184 /* 185 * Remove a NAND device. 186 */ 187 static int socrates_nand_remove(struct platform_device *ofdev) 188 { 189 struct socrates_nand_host *host = dev_get_drvdata(&ofdev->dev); 190 191 nand_release(&host->nand_chip); 192 193 iounmap(host->io_base); 194 195 return 0; 196 } 197 198 static const struct of_device_id socrates_nand_match[] = 199 { 200 { 201 .compatible = "abb,socrates-nand", 202 }, 203 {}, 204 }; 205 206 MODULE_DEVICE_TABLE(of, socrates_nand_match); 207 208 static struct platform_driver socrates_nand_driver = { 209 .driver = { 210 .name = "socrates_nand", 211 .of_match_table = socrates_nand_match, 212 }, 213 .probe = socrates_nand_probe, 214 .remove = socrates_nand_remove, 215 }; 216 217 module_platform_driver(socrates_nand_driver); 218 219 MODULE_LICENSE("GPL"); 220 MODULE_AUTHOR("Ilya Yanok"); 221 MODULE_DESCRIPTION("NAND driver for Socrates board"); 222