1 /* 2 * Copyright © 2004-2008 Simtec Electronics 3 * http://armlinux.simtec.co.uk/ 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * Samsung S3C2410/S3C2440/S3C2412 NAND driver 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #define pr_fmt(fmt) "nand-s3c2410: " fmt 24 25 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG 26 #define DEBUG 27 #endif 28 29 #include <linux/module.h> 30 #include <linux/types.h> 31 #include <linux/kernel.h> 32 #include <linux/string.h> 33 #include <linux/io.h> 34 #include <linux/ioport.h> 35 #include <linux/platform_device.h> 36 #include <linux/delay.h> 37 #include <linux/err.h> 38 #include <linux/slab.h> 39 #include <linux/clk.h> 40 #include <linux/cpufreq.h> 41 #include <linux/of.h> 42 #include <linux/of_device.h> 43 44 #include <linux/mtd/mtd.h> 45 #include <linux/mtd/rawnand.h> 46 #include <linux/mtd/nand_ecc.h> 47 #include <linux/mtd/partitions.h> 48 49 #include <linux/platform_data/mtd-nand-s3c2410.h> 50 51 #define S3C2410_NFREG(x) (x) 52 53 #define S3C2410_NFCONF S3C2410_NFREG(0x00) 54 #define S3C2410_NFCMD S3C2410_NFREG(0x04) 55 #define S3C2410_NFADDR S3C2410_NFREG(0x08) 56 #define S3C2410_NFDATA S3C2410_NFREG(0x0C) 57 #define S3C2410_NFSTAT S3C2410_NFREG(0x10) 58 #define S3C2410_NFECC S3C2410_NFREG(0x14) 59 #define S3C2440_NFCONT S3C2410_NFREG(0x04) 60 #define S3C2440_NFCMD S3C2410_NFREG(0x08) 61 #define S3C2440_NFADDR S3C2410_NFREG(0x0C) 62 #define S3C2440_NFDATA S3C2410_NFREG(0x10) 63 #define S3C2440_NFSTAT S3C2410_NFREG(0x20) 64 #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) 65 #define S3C2412_NFSTAT S3C2410_NFREG(0x28) 66 #define S3C2412_NFMECC0 S3C2410_NFREG(0x34) 67 #define S3C2410_NFCONF_EN (1<<15) 68 #define S3C2410_NFCONF_INITECC (1<<12) 69 #define S3C2410_NFCONF_nFCE (1<<11) 70 #define S3C2410_NFCONF_TACLS(x) ((x)<<8) 71 #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) 72 #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) 73 #define S3C2410_NFSTAT_BUSY (1<<0) 74 #define S3C2440_NFCONF_TACLS(x) ((x)<<12) 75 #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) 76 #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) 77 #define S3C2440_NFCONT_INITECC (1<<4) 78 #define S3C2440_NFCONT_nFCE (1<<1) 79 #define S3C2440_NFCONT_ENABLE (1<<0) 80 #define S3C2440_NFSTAT_READY (1<<0) 81 #define S3C2412_NFCONF_NANDBOOT (1<<31) 82 #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) 83 #define S3C2412_NFCONT_nFCE0 (1<<1) 84 #define S3C2412_NFSTAT_READY (1<<0) 85 86 /* new oob placement block for use with hardware ecc generation 87 */ 88 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section, 89 struct mtd_oob_region *oobregion) 90 { 91 if (section) 92 return -ERANGE; 93 94 oobregion->offset = 0; 95 oobregion->length = 3; 96 97 return 0; 98 } 99 100 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section, 101 struct mtd_oob_region *oobregion) 102 { 103 if (section) 104 return -ERANGE; 105 106 oobregion->offset = 8; 107 oobregion->length = 8; 108 109 return 0; 110 } 111 112 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = { 113 .ecc = s3c2410_ooblayout_ecc, 114 .free = s3c2410_ooblayout_free, 115 }; 116 117 /* controller and mtd information */ 118 119 struct s3c2410_nand_info; 120 121 /** 122 * struct s3c2410_nand_mtd - driver MTD structure 123 * @mtd: The MTD instance to pass to the MTD layer. 124 * @chip: The NAND chip information. 125 * @set: The platform information supplied for this set of NAND chips. 126 * @info: Link back to the hardware information. 127 */ 128 struct s3c2410_nand_mtd { 129 struct nand_chip chip; 130 struct s3c2410_nand_set *set; 131 struct s3c2410_nand_info *info; 132 }; 133 134 enum s3c_cpu_type { 135 TYPE_S3C2410, 136 TYPE_S3C2412, 137 TYPE_S3C2440, 138 }; 139 140 enum s3c_nand_clk_state { 141 CLOCK_DISABLE = 0, 142 CLOCK_ENABLE, 143 CLOCK_SUSPEND, 144 }; 145 146 /* overview of the s3c2410 nand state */ 147 148 /** 149 * struct s3c2410_nand_info - NAND controller state. 150 * @mtds: An array of MTD instances on this controoler. 151 * @platform: The platform data for this board. 152 * @device: The platform device we bound to. 153 * @clk: The clock resource for this controller. 154 * @regs: The area mapped for the hardware registers. 155 * @sel_reg: Pointer to the register controlling the NAND selection. 156 * @sel_bit: The bit in @sel_reg to select the NAND chip. 157 * @mtd_count: The number of MTDs created from this controller. 158 * @save_sel: The contents of @sel_reg to be saved over suspend. 159 * @clk_rate: The clock rate from @clk. 160 * @clk_state: The current clock state. 161 * @cpu_type: The exact type of this controller. 162 */ 163 struct s3c2410_nand_info { 164 /* mtd info */ 165 struct nand_hw_control controller; 166 struct s3c2410_nand_mtd *mtds; 167 struct s3c2410_platform_nand *platform; 168 169 /* device info */ 170 struct device *device; 171 struct clk *clk; 172 void __iomem *regs; 173 void __iomem *sel_reg; 174 int sel_bit; 175 int mtd_count; 176 unsigned long save_sel; 177 unsigned long clk_rate; 178 enum s3c_nand_clk_state clk_state; 179 180 enum s3c_cpu_type cpu_type; 181 182 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 183 struct notifier_block freq_transition; 184 #endif 185 }; 186 187 struct s3c24XX_nand_devtype_data { 188 enum s3c_cpu_type type; 189 }; 190 191 static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = { 192 .type = TYPE_S3C2410, 193 }; 194 195 static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = { 196 .type = TYPE_S3C2412, 197 }; 198 199 static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = { 200 .type = TYPE_S3C2440, 201 }; 202 203 /* conversion functions */ 204 205 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) 206 { 207 return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd, 208 chip); 209 } 210 211 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) 212 { 213 return s3c2410_nand_mtd_toours(mtd)->info; 214 } 215 216 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) 217 { 218 return platform_get_drvdata(dev); 219 } 220 221 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) 222 { 223 return dev_get_platdata(&dev->dev); 224 } 225 226 static inline int allow_clk_suspend(struct s3c2410_nand_info *info) 227 { 228 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP 229 return 1; 230 #else 231 return 0; 232 #endif 233 } 234 235 /** 236 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. 237 * @info: The controller instance. 238 * @new_state: State to which clock should be set. 239 */ 240 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, 241 enum s3c_nand_clk_state new_state) 242 { 243 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) 244 return; 245 246 if (info->clk_state == CLOCK_ENABLE) { 247 if (new_state != CLOCK_ENABLE) 248 clk_disable_unprepare(info->clk); 249 } else { 250 if (new_state == CLOCK_ENABLE) 251 clk_prepare_enable(info->clk); 252 } 253 254 info->clk_state = new_state; 255 } 256 257 /* timing calculations */ 258 259 #define NS_IN_KHZ 1000000 260 261 /** 262 * s3c_nand_calc_rate - calculate timing data. 263 * @wanted: The cycle time in nanoseconds. 264 * @clk: The clock rate in kHz. 265 * @max: The maximum divider value. 266 * 267 * Calculate the timing value from the given parameters. 268 */ 269 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) 270 { 271 int result; 272 273 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); 274 275 pr_debug("result %d from %ld, %d\n", result, clk, wanted); 276 277 if (result > max) { 278 pr_err("%d ns is too big for current clock rate %ld\n", 279 wanted, clk); 280 return -1; 281 } 282 283 if (result < 1) 284 result = 1; 285 286 return result; 287 } 288 289 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) 290 291 /* controller setup */ 292 293 /** 294 * s3c2410_nand_setrate - setup controller timing information. 295 * @info: The controller instance. 296 * 297 * Given the information supplied by the platform, calculate and set 298 * the necessary timing registers in the hardware to generate the 299 * necessary timing cycles to the hardware. 300 */ 301 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) 302 { 303 struct s3c2410_platform_nand *plat = info->platform; 304 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; 305 int tacls, twrph0, twrph1; 306 unsigned long clkrate = clk_get_rate(info->clk); 307 unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); 308 unsigned long flags; 309 310 /* calculate the timing information for the controller */ 311 312 info->clk_rate = clkrate; 313 clkrate /= 1000; /* turn clock into kHz for ease of use */ 314 315 if (plat != NULL) { 316 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); 317 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); 318 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); 319 } else { 320 /* default timings */ 321 tacls = tacls_max; 322 twrph0 = 8; 323 twrph1 = 8; 324 } 325 326 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { 327 dev_err(info->device, "cannot get suitable timings\n"); 328 return -EINVAL; 329 } 330 331 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", 332 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), 333 twrph1, to_ns(twrph1, clkrate)); 334 335 switch (info->cpu_type) { 336 case TYPE_S3C2410: 337 mask = (S3C2410_NFCONF_TACLS(3) | 338 S3C2410_NFCONF_TWRPH0(7) | 339 S3C2410_NFCONF_TWRPH1(7)); 340 set = S3C2410_NFCONF_EN; 341 set |= S3C2410_NFCONF_TACLS(tacls - 1); 342 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); 343 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); 344 break; 345 346 case TYPE_S3C2440: 347 case TYPE_S3C2412: 348 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | 349 S3C2440_NFCONF_TWRPH0(7) | 350 S3C2440_NFCONF_TWRPH1(7)); 351 352 set = S3C2440_NFCONF_TACLS(tacls - 1); 353 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); 354 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); 355 break; 356 357 default: 358 BUG(); 359 } 360 361 local_irq_save(flags); 362 363 cfg = readl(info->regs + S3C2410_NFCONF); 364 cfg &= ~mask; 365 cfg |= set; 366 writel(cfg, info->regs + S3C2410_NFCONF); 367 368 local_irq_restore(flags); 369 370 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); 371 372 return 0; 373 } 374 375 /** 376 * s3c2410_nand_inithw - basic hardware initialisation 377 * @info: The hardware state. 378 * 379 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() 380 * to setup the hardware access speeds and set the controller to be enabled. 381 */ 382 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) 383 { 384 int ret; 385 386 ret = s3c2410_nand_setrate(info); 387 if (ret < 0) 388 return ret; 389 390 switch (info->cpu_type) { 391 case TYPE_S3C2410: 392 default: 393 break; 394 395 case TYPE_S3C2440: 396 case TYPE_S3C2412: 397 /* enable the controller and de-assert nFCE */ 398 399 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); 400 } 401 402 return 0; 403 } 404 405 /** 406 * s3c2410_nand_select_chip - select the given nand chip 407 * @mtd: The MTD instance for this chip. 408 * @chip: The chip number. 409 * 410 * This is called by the MTD layer to either select a given chip for the 411 * @mtd instance, or to indicate that the access has finished and the 412 * chip can be de-selected. 413 * 414 * The routine ensures that the nFCE line is correctly setup, and any 415 * platform specific selection code is called to route nFCE to the specific 416 * chip. 417 */ 418 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) 419 { 420 struct s3c2410_nand_info *info; 421 struct s3c2410_nand_mtd *nmtd; 422 struct nand_chip *this = mtd_to_nand(mtd); 423 unsigned long cur; 424 425 nmtd = nand_get_controller_data(this); 426 info = nmtd->info; 427 428 if (chip != -1) 429 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 430 431 cur = readl(info->sel_reg); 432 433 if (chip == -1) { 434 cur |= info->sel_bit; 435 } else { 436 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { 437 dev_err(info->device, "invalid chip %d\n", chip); 438 return; 439 } 440 441 if (info->platform != NULL) { 442 if (info->platform->select_chip != NULL) 443 (info->platform->select_chip) (nmtd->set, chip); 444 } 445 446 cur &= ~info->sel_bit; 447 } 448 449 writel(cur, info->sel_reg); 450 451 if (chip == -1) 452 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 453 } 454 455 /* s3c2410_nand_hwcontrol 456 * 457 * Issue command and address cycles to the chip 458 */ 459 460 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, 461 unsigned int ctrl) 462 { 463 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 464 465 if (cmd == NAND_CMD_NONE) 466 return; 467 468 if (ctrl & NAND_CLE) 469 writeb(cmd, info->regs + S3C2410_NFCMD); 470 else 471 writeb(cmd, info->regs + S3C2410_NFADDR); 472 } 473 474 /* command and control functions */ 475 476 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, 477 unsigned int ctrl) 478 { 479 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 480 481 if (cmd == NAND_CMD_NONE) 482 return; 483 484 if (ctrl & NAND_CLE) 485 writeb(cmd, info->regs + S3C2440_NFCMD); 486 else 487 writeb(cmd, info->regs + S3C2440_NFADDR); 488 } 489 490 /* s3c2410_nand_devready() 491 * 492 * returns 0 if the nand is busy, 1 if it is ready 493 */ 494 495 static int s3c2410_nand_devready(struct mtd_info *mtd) 496 { 497 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 498 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; 499 } 500 501 static int s3c2440_nand_devready(struct mtd_info *mtd) 502 { 503 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 504 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; 505 } 506 507 static int s3c2412_nand_devready(struct mtd_info *mtd) 508 { 509 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 510 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; 511 } 512 513 /* ECC handling functions */ 514 515 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, 516 u_char *read_ecc, u_char *calc_ecc) 517 { 518 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 519 unsigned int diff0, diff1, diff2; 520 unsigned int bit, byte; 521 522 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); 523 524 diff0 = read_ecc[0] ^ calc_ecc[0]; 525 diff1 = read_ecc[1] ^ calc_ecc[1]; 526 diff2 = read_ecc[2] ^ calc_ecc[2]; 527 528 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", 529 __func__, 3, read_ecc, 3, calc_ecc, 530 diff0, diff1, diff2); 531 532 if (diff0 == 0 && diff1 == 0 && diff2 == 0) 533 return 0; /* ECC is ok */ 534 535 /* sometimes people do not think about using the ECC, so check 536 * to see if we have an 0xff,0xff,0xff read ECC and then ignore 537 * the error, on the assumption that this is an un-eccd page. 538 */ 539 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff 540 && info->platform->ignore_unset_ecc) 541 return 0; 542 543 /* Can we correct this ECC (ie, one row and column change). 544 * Note, this is similar to the 256 error code on smartmedia */ 545 546 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && 547 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && 548 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { 549 /* calculate the bit position of the error */ 550 551 bit = ((diff2 >> 3) & 1) | 552 ((diff2 >> 4) & 2) | 553 ((diff2 >> 5) & 4); 554 555 /* calculate the byte position of the error */ 556 557 byte = ((diff2 << 7) & 0x100) | 558 ((diff1 << 0) & 0x80) | 559 ((diff1 << 1) & 0x40) | 560 ((diff1 << 2) & 0x20) | 561 ((diff1 << 3) & 0x10) | 562 ((diff0 >> 4) & 0x08) | 563 ((diff0 >> 3) & 0x04) | 564 ((diff0 >> 2) & 0x02) | 565 ((diff0 >> 1) & 0x01); 566 567 dev_dbg(info->device, "correcting error bit %d, byte %d\n", 568 bit, byte); 569 570 dat[byte] ^= (1 << bit); 571 return 1; 572 } 573 574 /* if there is only one bit difference in the ECC, then 575 * one of only a row or column parity has changed, which 576 * means the error is most probably in the ECC itself */ 577 578 diff0 |= (diff1 << 8); 579 diff0 |= (diff2 << 16); 580 581 /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */ 582 if ((diff0 & (diff0 - 1)) == 0) 583 return 1; 584 585 return -1; 586 } 587 588 /* ECC functions 589 * 590 * These allow the s3c2410 and s3c2440 to use the controller's ECC 591 * generator block to ECC the data as it passes through] 592 */ 593 594 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) 595 { 596 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 597 unsigned long ctrl; 598 599 ctrl = readl(info->regs + S3C2410_NFCONF); 600 ctrl |= S3C2410_NFCONF_INITECC; 601 writel(ctrl, info->regs + S3C2410_NFCONF); 602 } 603 604 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) 605 { 606 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 607 unsigned long ctrl; 608 609 ctrl = readl(info->regs + S3C2440_NFCONT); 610 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, 611 info->regs + S3C2440_NFCONT); 612 } 613 614 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) 615 { 616 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 617 unsigned long ctrl; 618 619 ctrl = readl(info->regs + S3C2440_NFCONT); 620 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); 621 } 622 623 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, 624 u_char *ecc_code) 625 { 626 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 627 628 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); 629 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); 630 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); 631 632 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); 633 634 return 0; 635 } 636 637 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, 638 u_char *ecc_code) 639 { 640 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 641 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); 642 643 ecc_code[0] = ecc; 644 ecc_code[1] = ecc >> 8; 645 ecc_code[2] = ecc >> 16; 646 647 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); 648 649 return 0; 650 } 651 652 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, 653 u_char *ecc_code) 654 { 655 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 656 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); 657 658 ecc_code[0] = ecc; 659 ecc_code[1] = ecc >> 8; 660 ecc_code[2] = ecc >> 16; 661 662 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); 663 664 return 0; 665 } 666 667 /* over-ride the standard functions for a little more speed. We can 668 * use read/write block to move the data buffers to/from the controller 669 */ 670 671 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 672 { 673 struct nand_chip *this = mtd_to_nand(mtd); 674 readsb(this->IO_ADDR_R, buf, len); 675 } 676 677 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 678 { 679 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 680 681 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); 682 683 /* cleanup if we've got less than a word to do */ 684 if (len & 3) { 685 buf += len & ~3; 686 687 for (; len & 3; len--) 688 *buf++ = readb(info->regs + S3C2440_NFDATA); 689 } 690 } 691 692 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, 693 int len) 694 { 695 struct nand_chip *this = mtd_to_nand(mtd); 696 writesb(this->IO_ADDR_W, buf, len); 697 } 698 699 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, 700 int len) 701 { 702 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 703 704 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); 705 706 /* cleanup any fractional write */ 707 if (len & 3) { 708 buf += len & ~3; 709 710 for (; len & 3; len--, buf++) 711 writeb(*buf, info->regs + S3C2440_NFDATA); 712 } 713 } 714 715 /* cpufreq driver support */ 716 717 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ 718 719 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, 720 unsigned long val, void *data) 721 { 722 struct s3c2410_nand_info *info; 723 unsigned long newclk; 724 725 info = container_of(nb, struct s3c2410_nand_info, freq_transition); 726 newclk = clk_get_rate(info->clk); 727 728 if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || 729 (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { 730 s3c2410_nand_setrate(info); 731 } 732 733 return 0; 734 } 735 736 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) 737 { 738 info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; 739 740 return cpufreq_register_notifier(&info->freq_transition, 741 CPUFREQ_TRANSITION_NOTIFIER); 742 } 743 744 static inline void 745 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) 746 { 747 cpufreq_unregister_notifier(&info->freq_transition, 748 CPUFREQ_TRANSITION_NOTIFIER); 749 } 750 751 #else 752 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) 753 { 754 return 0; 755 } 756 757 static inline void 758 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) 759 { 760 } 761 #endif 762 763 /* device management functions */ 764 765 static int s3c24xx_nand_remove(struct platform_device *pdev) 766 { 767 struct s3c2410_nand_info *info = to_nand_info(pdev); 768 769 if (info == NULL) 770 return 0; 771 772 s3c2410_nand_cpufreq_deregister(info); 773 774 /* Release all our mtds and their partitions, then go through 775 * freeing the resources used 776 */ 777 778 if (info->mtds != NULL) { 779 struct s3c2410_nand_mtd *ptr = info->mtds; 780 int mtdno; 781 782 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { 783 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); 784 nand_release(nand_to_mtd(&ptr->chip)); 785 } 786 } 787 788 /* free the common resources */ 789 790 if (!IS_ERR(info->clk)) 791 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); 792 793 return 0; 794 } 795 796 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, 797 struct s3c2410_nand_mtd *mtd, 798 struct s3c2410_nand_set *set) 799 { 800 if (set) { 801 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip); 802 803 mtdinfo->name = set->name; 804 805 return mtd_device_parse_register(mtdinfo, NULL, NULL, 806 set->partitions, set->nr_partitions); 807 } 808 809 return -ENODEV; 810 } 811 812 static int s3c2410_nand_setup_data_interface(struct mtd_info *mtd, int csline, 813 const struct nand_data_interface *conf) 814 { 815 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 816 struct s3c2410_platform_nand *pdata = info->platform; 817 const struct nand_sdr_timings *timings; 818 int tacls; 819 820 timings = nand_get_sdr_timings(conf); 821 if (IS_ERR(timings)) 822 return -ENOTSUPP; 823 824 tacls = timings->tCLS_min - timings->tWP_min; 825 if (tacls < 0) 826 tacls = 0; 827 828 pdata->tacls = DIV_ROUND_UP(tacls, 1000); 829 pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000); 830 pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000); 831 832 return s3c2410_nand_setrate(info); 833 } 834 835 /** 836 * s3c2410_nand_init_chip - initialise a single instance of an chip 837 * @info: The base NAND controller the chip is on. 838 * @nmtd: The new controller MTD instance to fill in. 839 * @set: The information passed from the board specific platform data. 840 * 841 * Initialise the given @nmtd from the information in @info and @set. This 842 * readies the structure for use with the MTD layer functions by ensuring 843 * all pointers are setup and the necessary control routines selected. 844 */ 845 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, 846 struct s3c2410_nand_mtd *nmtd, 847 struct s3c2410_nand_set *set) 848 { 849 struct device_node *np = info->device->of_node; 850 struct nand_chip *chip = &nmtd->chip; 851 void __iomem *regs = info->regs; 852 853 nand_set_flash_node(chip, set->of_node); 854 855 chip->write_buf = s3c2410_nand_write_buf; 856 chip->read_buf = s3c2410_nand_read_buf; 857 chip->select_chip = s3c2410_nand_select_chip; 858 chip->chip_delay = 50; 859 nand_set_controller_data(chip, nmtd); 860 chip->options = set->options; 861 chip->controller = &info->controller; 862 863 /* 864 * let's keep behavior unchanged for legacy boards booting via pdata and 865 * auto-detect timings only when booting with a device tree. 866 */ 867 if (np) 868 chip->setup_data_interface = s3c2410_nand_setup_data_interface; 869 870 switch (info->cpu_type) { 871 case TYPE_S3C2410: 872 chip->IO_ADDR_W = regs + S3C2410_NFDATA; 873 info->sel_reg = regs + S3C2410_NFCONF; 874 info->sel_bit = S3C2410_NFCONF_nFCE; 875 chip->cmd_ctrl = s3c2410_nand_hwcontrol; 876 chip->dev_ready = s3c2410_nand_devready; 877 break; 878 879 case TYPE_S3C2440: 880 chip->IO_ADDR_W = regs + S3C2440_NFDATA; 881 info->sel_reg = regs + S3C2440_NFCONT; 882 info->sel_bit = S3C2440_NFCONT_nFCE; 883 chip->cmd_ctrl = s3c2440_nand_hwcontrol; 884 chip->dev_ready = s3c2440_nand_devready; 885 chip->read_buf = s3c2440_nand_read_buf; 886 chip->write_buf = s3c2440_nand_write_buf; 887 break; 888 889 case TYPE_S3C2412: 890 chip->IO_ADDR_W = regs + S3C2440_NFDATA; 891 info->sel_reg = regs + S3C2440_NFCONT; 892 info->sel_bit = S3C2412_NFCONT_nFCE0; 893 chip->cmd_ctrl = s3c2440_nand_hwcontrol; 894 chip->dev_ready = s3c2412_nand_devready; 895 896 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) 897 dev_info(info->device, "System booted from NAND\n"); 898 899 break; 900 } 901 902 chip->IO_ADDR_R = chip->IO_ADDR_W; 903 904 nmtd->info = info; 905 nmtd->set = set; 906 907 chip->ecc.mode = info->platform->ecc_mode; 908 909 /* 910 * If you use u-boot BBT creation code, specifying this flag will 911 * let the kernel fish out the BBT from the NAND. 912 */ 913 if (set->flash_bbt) 914 chip->bbt_options |= NAND_BBT_USE_FLASH; 915 } 916 917 /** 918 * s3c2410_nand_update_chip - post probe update 919 * @info: The controller instance. 920 * @nmtd: The driver version of the MTD instance. 921 * 922 * This routine is called after the chip probe has successfully completed 923 * and the relevant per-chip information updated. This call ensure that 924 * we update the internal state accordingly. 925 * 926 * The internal state is currently limited to the ECC state information. 927 */ 928 static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info, 929 struct s3c2410_nand_mtd *nmtd) 930 { 931 struct nand_chip *chip = &nmtd->chip; 932 933 switch (chip->ecc.mode) { 934 935 case NAND_ECC_NONE: 936 dev_info(info->device, "ECC disabled\n"); 937 break; 938 939 case NAND_ECC_SOFT: 940 /* 941 * This driver expects Hamming based ECC when ecc_mode is set 942 * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to 943 * avoid adding an extra ecc_algo field to 944 * s3c2410_platform_nand. 945 */ 946 chip->ecc.algo = NAND_ECC_HAMMING; 947 dev_info(info->device, "soft ECC\n"); 948 break; 949 950 case NAND_ECC_HW: 951 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 952 chip->ecc.correct = s3c2410_nand_correct_data; 953 chip->ecc.strength = 1; 954 955 switch (info->cpu_type) { 956 case TYPE_S3C2410: 957 chip->ecc.hwctl = s3c2410_nand_enable_hwecc; 958 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 959 break; 960 961 case TYPE_S3C2412: 962 chip->ecc.hwctl = s3c2412_nand_enable_hwecc; 963 chip->ecc.calculate = s3c2412_nand_calculate_ecc; 964 break; 965 966 case TYPE_S3C2440: 967 chip->ecc.hwctl = s3c2440_nand_enable_hwecc; 968 chip->ecc.calculate = s3c2440_nand_calculate_ecc; 969 break; 970 } 971 972 dev_dbg(info->device, "chip %p => page shift %d\n", 973 chip, chip->page_shift); 974 975 /* change the behaviour depending on whether we are using 976 * the large or small page nand device */ 977 if (chip->page_shift > 10) { 978 chip->ecc.size = 256; 979 chip->ecc.bytes = 3; 980 } else { 981 chip->ecc.size = 512; 982 chip->ecc.bytes = 3; 983 mtd_set_ooblayout(nand_to_mtd(chip), 984 &s3c2410_ooblayout_ops); 985 } 986 987 dev_info(info->device, "hardware ECC\n"); 988 break; 989 990 default: 991 dev_err(info->device, "invalid ECC mode!\n"); 992 return -EINVAL; 993 } 994 995 if (chip->bbt_options & NAND_BBT_USE_FLASH) 996 chip->options |= NAND_SKIP_BBTSCAN; 997 998 return 0; 999 } 1000 1001 static const struct of_device_id s3c24xx_nand_dt_ids[] = { 1002 { 1003 .compatible = "samsung,s3c2410-nand", 1004 .data = &s3c2410_nand_devtype_data, 1005 }, { 1006 /* also compatible with s3c6400 */ 1007 .compatible = "samsung,s3c2412-nand", 1008 .data = &s3c2412_nand_devtype_data, 1009 }, { 1010 .compatible = "samsung,s3c2440-nand", 1011 .data = &s3c2440_nand_devtype_data, 1012 }, 1013 { /* sentinel */ } 1014 }; 1015 MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids); 1016 1017 static int s3c24xx_nand_probe_dt(struct platform_device *pdev) 1018 { 1019 const struct s3c24XX_nand_devtype_data *devtype_data; 1020 struct s3c2410_platform_nand *pdata; 1021 struct s3c2410_nand_info *info = platform_get_drvdata(pdev); 1022 struct device_node *np = pdev->dev.of_node, *child; 1023 struct s3c2410_nand_set *sets; 1024 1025 devtype_data = of_device_get_match_data(&pdev->dev); 1026 if (!devtype_data) 1027 return -ENODEV; 1028 1029 info->cpu_type = devtype_data->type; 1030 1031 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1032 if (!pdata) 1033 return -ENOMEM; 1034 1035 pdev->dev.platform_data = pdata; 1036 1037 pdata->nr_sets = of_get_child_count(np); 1038 if (!pdata->nr_sets) 1039 return 0; 1040 1041 sets = devm_kcalloc(&pdev->dev, pdata->nr_sets, sizeof(*sets), 1042 GFP_KERNEL); 1043 if (!sets) 1044 return -ENOMEM; 1045 1046 pdata->sets = sets; 1047 1048 for_each_available_child_of_node(np, child) { 1049 sets->name = (char *)child->name; 1050 sets->of_node = child; 1051 sets->nr_chips = 1; 1052 1053 of_node_get(child); 1054 1055 sets++; 1056 } 1057 1058 return 0; 1059 } 1060 1061 static int s3c24xx_nand_probe_pdata(struct platform_device *pdev) 1062 { 1063 struct s3c2410_nand_info *info = platform_get_drvdata(pdev); 1064 1065 info->cpu_type = platform_get_device_id(pdev)->driver_data; 1066 1067 return 0; 1068 } 1069 1070 /* s3c24xx_nand_probe 1071 * 1072 * called by device layer when it finds a device matching 1073 * one our driver can handled. This code checks to see if 1074 * it can allocate all necessary resources then calls the 1075 * nand layer to look for devices 1076 */ 1077 static int s3c24xx_nand_probe(struct platform_device *pdev) 1078 { 1079 struct s3c2410_platform_nand *plat; 1080 struct s3c2410_nand_info *info; 1081 struct s3c2410_nand_mtd *nmtd; 1082 struct s3c2410_nand_set *sets; 1083 struct resource *res; 1084 int err = 0; 1085 int size; 1086 int nr_sets; 1087 int setno; 1088 1089 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1090 if (info == NULL) { 1091 err = -ENOMEM; 1092 goto exit_error; 1093 } 1094 1095 platform_set_drvdata(pdev, info); 1096 1097 nand_hw_control_init(&info->controller); 1098 1099 /* get the clock source and enable it */ 1100 1101 info->clk = devm_clk_get(&pdev->dev, "nand"); 1102 if (IS_ERR(info->clk)) { 1103 dev_err(&pdev->dev, "failed to get clock\n"); 1104 err = -ENOENT; 1105 goto exit_error; 1106 } 1107 1108 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 1109 1110 if (pdev->dev.of_node) 1111 err = s3c24xx_nand_probe_dt(pdev); 1112 else 1113 err = s3c24xx_nand_probe_pdata(pdev); 1114 1115 if (err) 1116 goto exit_error; 1117 1118 plat = to_nand_plat(pdev); 1119 1120 /* allocate and map the resource */ 1121 1122 /* currently we assume we have the one resource */ 1123 res = pdev->resource; 1124 size = resource_size(res); 1125 1126 info->device = &pdev->dev; 1127 info->platform = plat; 1128 1129 info->regs = devm_ioremap_resource(&pdev->dev, res); 1130 if (IS_ERR(info->regs)) { 1131 err = PTR_ERR(info->regs); 1132 goto exit_error; 1133 } 1134 1135 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); 1136 1137 sets = (plat != NULL) ? plat->sets : NULL; 1138 nr_sets = (plat != NULL) ? plat->nr_sets : 1; 1139 1140 info->mtd_count = nr_sets; 1141 1142 /* allocate our information */ 1143 1144 size = nr_sets * sizeof(*info->mtds); 1145 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); 1146 if (info->mtds == NULL) { 1147 err = -ENOMEM; 1148 goto exit_error; 1149 } 1150 1151 /* initialise all possible chips */ 1152 1153 nmtd = info->mtds; 1154 1155 for (setno = 0; setno < nr_sets; setno++, nmtd++) { 1156 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip); 1157 1158 pr_debug("initialising set %d (%p, info %p)\n", 1159 setno, nmtd, info); 1160 1161 mtd->dev.parent = &pdev->dev; 1162 s3c2410_nand_init_chip(info, nmtd, sets); 1163 1164 err = nand_scan_ident(mtd, (sets) ? sets->nr_chips : 1, NULL); 1165 if (err) 1166 goto exit_error; 1167 1168 err = s3c2410_nand_update_chip(info, nmtd); 1169 if (err < 0) 1170 goto exit_error; 1171 1172 err = nand_scan_tail(mtd); 1173 if (err) 1174 goto exit_error; 1175 1176 s3c2410_nand_add_partition(info, nmtd, sets); 1177 1178 if (sets != NULL) 1179 sets++; 1180 } 1181 1182 /* initialise the hardware */ 1183 err = s3c2410_nand_inithw(info); 1184 if (err != 0) 1185 goto exit_error; 1186 1187 err = s3c2410_nand_cpufreq_register(info); 1188 if (err < 0) { 1189 dev_err(&pdev->dev, "failed to init cpufreq support\n"); 1190 goto exit_error; 1191 } 1192 1193 if (allow_clk_suspend(info)) { 1194 dev_info(&pdev->dev, "clock idle support enabled\n"); 1195 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 1196 } 1197 1198 return 0; 1199 1200 exit_error: 1201 s3c24xx_nand_remove(pdev); 1202 1203 if (err == 0) 1204 err = -EINVAL; 1205 return err; 1206 } 1207 1208 /* PM Support */ 1209 #ifdef CONFIG_PM 1210 1211 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) 1212 { 1213 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 1214 1215 if (info) { 1216 info->save_sel = readl(info->sel_reg); 1217 1218 /* For the moment, we must ensure nFCE is high during 1219 * the time we are suspended. This really should be 1220 * handled by suspending the MTDs we are using, but 1221 * that is currently not the case. */ 1222 1223 writel(info->save_sel | info->sel_bit, info->sel_reg); 1224 1225 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int s3c24xx_nand_resume(struct platform_device *dev) 1232 { 1233 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 1234 unsigned long sel; 1235 1236 if (info) { 1237 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 1238 s3c2410_nand_inithw(info); 1239 1240 /* Restore the state of the nFCE line. */ 1241 1242 sel = readl(info->sel_reg); 1243 sel &= ~info->sel_bit; 1244 sel |= info->save_sel & info->sel_bit; 1245 writel(sel, info->sel_reg); 1246 1247 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 1248 } 1249 1250 return 0; 1251 } 1252 1253 #else 1254 #define s3c24xx_nand_suspend NULL 1255 #define s3c24xx_nand_resume NULL 1256 #endif 1257 1258 /* driver device registration */ 1259 1260 static const struct platform_device_id s3c24xx_driver_ids[] = { 1261 { 1262 .name = "s3c2410-nand", 1263 .driver_data = TYPE_S3C2410, 1264 }, { 1265 .name = "s3c2440-nand", 1266 .driver_data = TYPE_S3C2440, 1267 }, { 1268 .name = "s3c2412-nand", 1269 .driver_data = TYPE_S3C2412, 1270 }, { 1271 .name = "s3c6400-nand", 1272 .driver_data = TYPE_S3C2412, /* compatible with 2412 */ 1273 }, 1274 { } 1275 }; 1276 1277 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 1278 1279 static struct platform_driver s3c24xx_nand_driver = { 1280 .probe = s3c24xx_nand_probe, 1281 .remove = s3c24xx_nand_remove, 1282 .suspend = s3c24xx_nand_suspend, 1283 .resume = s3c24xx_nand_resume, 1284 .id_table = s3c24xx_driver_ids, 1285 .driver = { 1286 .name = "s3c24xx-nand", 1287 .of_match_table = s3c24xx_nand_dt_ids, 1288 }, 1289 }; 1290 1291 module_platform_driver(s3c24xx_nand_driver); 1292 1293 MODULE_LICENSE("GPL"); 1294 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 1295 MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); 1296