1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright © 2004-2008 Simtec Electronics 4 * http://armlinux.simtec.co.uk/ 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver 8 */ 9 10 #define pr_fmt(fmt) "nand-s3c2410: " fmt 11 12 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG 13 #define DEBUG 14 #endif 15 16 #include <linux/module.h> 17 #include <linux/types.h> 18 #include <linux/kernel.h> 19 #include <linux/string.h> 20 #include <linux/io.h> 21 #include <linux/ioport.h> 22 #include <linux/platform_device.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/slab.h> 26 #include <linux/clk.h> 27 #include <linux/cpufreq.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 31 #include <linux/mtd/mtd.h> 32 #include <linux/mtd/rawnand.h> 33 #include <linux/mtd/partitions.h> 34 35 #include <linux/platform_data/mtd-nand-s3c2410.h> 36 37 #define S3C2410_NFREG(x) (x) 38 39 #define S3C2410_NFCONF S3C2410_NFREG(0x00) 40 #define S3C2410_NFCMD S3C2410_NFREG(0x04) 41 #define S3C2410_NFADDR S3C2410_NFREG(0x08) 42 #define S3C2410_NFDATA S3C2410_NFREG(0x0C) 43 #define S3C2410_NFSTAT S3C2410_NFREG(0x10) 44 #define S3C2410_NFECC S3C2410_NFREG(0x14) 45 #define S3C2440_NFCONT S3C2410_NFREG(0x04) 46 #define S3C2440_NFCMD S3C2410_NFREG(0x08) 47 #define S3C2440_NFADDR S3C2410_NFREG(0x0C) 48 #define S3C2440_NFDATA S3C2410_NFREG(0x10) 49 #define S3C2440_NFSTAT S3C2410_NFREG(0x20) 50 #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) 51 #define S3C2412_NFSTAT S3C2410_NFREG(0x28) 52 #define S3C2412_NFMECC0 S3C2410_NFREG(0x34) 53 #define S3C2410_NFCONF_EN (1<<15) 54 #define S3C2410_NFCONF_INITECC (1<<12) 55 #define S3C2410_NFCONF_nFCE (1<<11) 56 #define S3C2410_NFCONF_TACLS(x) ((x)<<8) 57 #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) 58 #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) 59 #define S3C2410_NFSTAT_BUSY (1<<0) 60 #define S3C2440_NFCONF_TACLS(x) ((x)<<12) 61 #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) 62 #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) 63 #define S3C2440_NFCONT_INITECC (1<<4) 64 #define S3C2440_NFCONT_nFCE (1<<1) 65 #define S3C2440_NFCONT_ENABLE (1<<0) 66 #define S3C2440_NFSTAT_READY (1<<0) 67 #define S3C2412_NFCONF_NANDBOOT (1<<31) 68 #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) 69 #define S3C2412_NFCONT_nFCE0 (1<<1) 70 #define S3C2412_NFSTAT_READY (1<<0) 71 72 /* new oob placement block for use with hardware ecc generation 73 */ 74 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section, 75 struct mtd_oob_region *oobregion) 76 { 77 if (section) 78 return -ERANGE; 79 80 oobregion->offset = 0; 81 oobregion->length = 3; 82 83 return 0; 84 } 85 86 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section, 87 struct mtd_oob_region *oobregion) 88 { 89 if (section) 90 return -ERANGE; 91 92 oobregion->offset = 8; 93 oobregion->length = 8; 94 95 return 0; 96 } 97 98 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = { 99 .ecc = s3c2410_ooblayout_ecc, 100 .free = s3c2410_ooblayout_free, 101 }; 102 103 /* controller and mtd information */ 104 105 struct s3c2410_nand_info; 106 107 /** 108 * struct s3c2410_nand_mtd - driver MTD structure 109 * @mtd: The MTD instance to pass to the MTD layer. 110 * @chip: The NAND chip information. 111 * @set: The platform information supplied for this set of NAND chips. 112 * @info: Link back to the hardware information. 113 */ 114 struct s3c2410_nand_mtd { 115 struct nand_chip chip; 116 struct s3c2410_nand_set *set; 117 struct s3c2410_nand_info *info; 118 }; 119 120 enum s3c_cpu_type { 121 TYPE_S3C2410, 122 TYPE_S3C2412, 123 TYPE_S3C2440, 124 }; 125 126 enum s3c_nand_clk_state { 127 CLOCK_DISABLE = 0, 128 CLOCK_ENABLE, 129 CLOCK_SUSPEND, 130 }; 131 132 /* overview of the s3c2410 nand state */ 133 134 /** 135 * struct s3c2410_nand_info - NAND controller state. 136 * @controller: Base controller structure. 137 * @mtds: An array of MTD instances on this controller. 138 * @platform: The platform data for this board. 139 * @device: The platform device we bound to. 140 * @clk: The clock resource for this controller. 141 * @regs: The area mapped for the hardware registers. 142 * @sel_reg: Pointer to the register controlling the NAND selection. 143 * @sel_bit: The bit in @sel_reg to select the NAND chip. 144 * @mtd_count: The number of MTDs created from this controller. 145 * @save_sel: The contents of @sel_reg to be saved over suspend. 146 * @clk_rate: The clock rate from @clk. 147 * @clk_state: The current clock state. 148 * @cpu_type: The exact type of this controller. 149 * @freq_transition: CPUFreq notifier block 150 */ 151 struct s3c2410_nand_info { 152 /* mtd info */ 153 struct nand_controller controller; 154 struct s3c2410_nand_mtd *mtds; 155 struct s3c2410_platform_nand *platform; 156 157 /* device info */ 158 struct device *device; 159 struct clk *clk; 160 void __iomem *regs; 161 void __iomem *sel_reg; 162 int sel_bit; 163 int mtd_count; 164 unsigned long save_sel; 165 unsigned long clk_rate; 166 enum s3c_nand_clk_state clk_state; 167 168 enum s3c_cpu_type cpu_type; 169 }; 170 171 struct s3c24XX_nand_devtype_data { 172 enum s3c_cpu_type type; 173 }; 174 175 static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = { 176 .type = TYPE_S3C2410, 177 }; 178 179 static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = { 180 .type = TYPE_S3C2412, 181 }; 182 183 static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = { 184 .type = TYPE_S3C2440, 185 }; 186 187 /* conversion functions */ 188 189 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) 190 { 191 return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd, 192 chip); 193 } 194 195 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) 196 { 197 return s3c2410_nand_mtd_toours(mtd)->info; 198 } 199 200 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) 201 { 202 return platform_get_drvdata(dev); 203 } 204 205 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) 206 { 207 return dev_get_platdata(&dev->dev); 208 } 209 210 static inline int allow_clk_suspend(struct s3c2410_nand_info *info) 211 { 212 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP 213 return 1; 214 #else 215 return 0; 216 #endif 217 } 218 219 /** 220 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. 221 * @info: The controller instance. 222 * @new_state: State to which clock should be set. 223 */ 224 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, 225 enum s3c_nand_clk_state new_state) 226 { 227 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) 228 return; 229 230 if (info->clk_state == CLOCK_ENABLE) { 231 if (new_state != CLOCK_ENABLE) 232 clk_disable_unprepare(info->clk); 233 } else { 234 if (new_state == CLOCK_ENABLE) 235 clk_prepare_enable(info->clk); 236 } 237 238 info->clk_state = new_state; 239 } 240 241 /* timing calculations */ 242 243 #define NS_IN_KHZ 1000000 244 245 /** 246 * s3c_nand_calc_rate - calculate timing data. 247 * @wanted: The cycle time in nanoseconds. 248 * @clk: The clock rate in kHz. 249 * @max: The maximum divider value. 250 * 251 * Calculate the timing value from the given parameters. 252 */ 253 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) 254 { 255 int result; 256 257 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); 258 259 pr_debug("result %d from %ld, %d\n", result, clk, wanted); 260 261 if (result > max) { 262 pr_err("%d ns is too big for current clock rate %ld\n", 263 wanted, clk); 264 return -1; 265 } 266 267 if (result < 1) 268 result = 1; 269 270 return result; 271 } 272 273 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) 274 275 /* controller setup */ 276 277 /** 278 * s3c2410_nand_setrate - setup controller timing information. 279 * @info: The controller instance. 280 * 281 * Given the information supplied by the platform, calculate and set 282 * the necessary timing registers in the hardware to generate the 283 * necessary timing cycles to the hardware. 284 */ 285 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) 286 { 287 struct s3c2410_platform_nand *plat = info->platform; 288 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; 289 int tacls, twrph0, twrph1; 290 unsigned long clkrate = clk_get_rate(info->clk); 291 unsigned long set, cfg, mask; 292 unsigned long flags; 293 294 /* calculate the timing information for the controller */ 295 296 info->clk_rate = clkrate; 297 clkrate /= 1000; /* turn clock into kHz for ease of use */ 298 299 if (plat != NULL) { 300 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); 301 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); 302 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); 303 } else { 304 /* default timings */ 305 tacls = tacls_max; 306 twrph0 = 8; 307 twrph1 = 8; 308 } 309 310 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { 311 dev_err(info->device, "cannot get suitable timings\n"); 312 return -EINVAL; 313 } 314 315 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", 316 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), 317 twrph1, to_ns(twrph1, clkrate)); 318 319 switch (info->cpu_type) { 320 case TYPE_S3C2410: 321 mask = (S3C2410_NFCONF_TACLS(3) | 322 S3C2410_NFCONF_TWRPH0(7) | 323 S3C2410_NFCONF_TWRPH1(7)); 324 set = S3C2410_NFCONF_EN; 325 set |= S3C2410_NFCONF_TACLS(tacls - 1); 326 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); 327 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); 328 break; 329 330 case TYPE_S3C2440: 331 case TYPE_S3C2412: 332 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | 333 S3C2440_NFCONF_TWRPH0(7) | 334 S3C2440_NFCONF_TWRPH1(7)); 335 336 set = S3C2440_NFCONF_TACLS(tacls - 1); 337 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); 338 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); 339 break; 340 341 default: 342 BUG(); 343 } 344 345 local_irq_save(flags); 346 347 cfg = readl(info->regs + S3C2410_NFCONF); 348 cfg &= ~mask; 349 cfg |= set; 350 writel(cfg, info->regs + S3C2410_NFCONF); 351 352 local_irq_restore(flags); 353 354 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); 355 356 return 0; 357 } 358 359 /** 360 * s3c2410_nand_inithw - basic hardware initialisation 361 * @info: The hardware state. 362 * 363 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() 364 * to setup the hardware access speeds and set the controller to be enabled. 365 */ 366 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) 367 { 368 int ret; 369 370 ret = s3c2410_nand_setrate(info); 371 if (ret < 0) 372 return ret; 373 374 switch (info->cpu_type) { 375 case TYPE_S3C2410: 376 default: 377 break; 378 379 case TYPE_S3C2440: 380 case TYPE_S3C2412: 381 /* enable the controller and de-assert nFCE */ 382 383 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); 384 } 385 386 return 0; 387 } 388 389 /** 390 * s3c2410_nand_select_chip - select the given nand chip 391 * @this: NAND chip object. 392 * @chip: The chip number. 393 * 394 * This is called by the MTD layer to either select a given chip for the 395 * @mtd instance, or to indicate that the access has finished and the 396 * chip can be de-selected. 397 * 398 * The routine ensures that the nFCE line is correctly setup, and any 399 * platform specific selection code is called to route nFCE to the specific 400 * chip. 401 */ 402 static void s3c2410_nand_select_chip(struct nand_chip *this, int chip) 403 { 404 struct s3c2410_nand_info *info; 405 struct s3c2410_nand_mtd *nmtd; 406 unsigned long cur; 407 408 nmtd = nand_get_controller_data(this); 409 info = nmtd->info; 410 411 if (chip != -1) 412 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 413 414 cur = readl(info->sel_reg); 415 416 if (chip == -1) { 417 cur |= info->sel_bit; 418 } else { 419 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { 420 dev_err(info->device, "invalid chip %d\n", chip); 421 return; 422 } 423 424 if (info->platform != NULL) { 425 if (info->platform->select_chip != NULL) 426 (info->platform->select_chip) (nmtd->set, chip); 427 } 428 429 cur &= ~info->sel_bit; 430 } 431 432 writel(cur, info->sel_reg); 433 434 if (chip == -1) 435 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 436 } 437 438 /* s3c2410_nand_hwcontrol 439 * 440 * Issue command and address cycles to the chip 441 */ 442 443 static void s3c2410_nand_hwcontrol(struct nand_chip *chip, int cmd, 444 unsigned int ctrl) 445 { 446 struct mtd_info *mtd = nand_to_mtd(chip); 447 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 448 449 if (cmd == NAND_CMD_NONE) 450 return; 451 452 if (ctrl & NAND_CLE) 453 writeb(cmd, info->regs + S3C2410_NFCMD); 454 else 455 writeb(cmd, info->regs + S3C2410_NFADDR); 456 } 457 458 /* command and control functions */ 459 460 static void s3c2440_nand_hwcontrol(struct nand_chip *chip, int cmd, 461 unsigned int ctrl) 462 { 463 struct mtd_info *mtd = nand_to_mtd(chip); 464 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 465 466 if (cmd == NAND_CMD_NONE) 467 return; 468 469 if (ctrl & NAND_CLE) 470 writeb(cmd, info->regs + S3C2440_NFCMD); 471 else 472 writeb(cmd, info->regs + S3C2440_NFADDR); 473 } 474 475 /* s3c2410_nand_devready() 476 * 477 * returns 0 if the nand is busy, 1 if it is ready 478 */ 479 480 static int s3c2410_nand_devready(struct nand_chip *chip) 481 { 482 struct mtd_info *mtd = nand_to_mtd(chip); 483 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 484 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; 485 } 486 487 static int s3c2440_nand_devready(struct nand_chip *chip) 488 { 489 struct mtd_info *mtd = nand_to_mtd(chip); 490 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 491 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; 492 } 493 494 static int s3c2412_nand_devready(struct nand_chip *chip) 495 { 496 struct mtd_info *mtd = nand_to_mtd(chip); 497 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 498 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; 499 } 500 501 /* ECC handling functions */ 502 503 static int s3c2410_nand_correct_data(struct nand_chip *chip, u_char *dat, 504 u_char *read_ecc, u_char *calc_ecc) 505 { 506 struct mtd_info *mtd = nand_to_mtd(chip); 507 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 508 unsigned int diff0, diff1, diff2; 509 unsigned int bit, byte; 510 511 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); 512 513 diff0 = read_ecc[0] ^ calc_ecc[0]; 514 diff1 = read_ecc[1] ^ calc_ecc[1]; 515 diff2 = read_ecc[2] ^ calc_ecc[2]; 516 517 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", 518 __func__, 3, read_ecc, 3, calc_ecc, 519 diff0, diff1, diff2); 520 521 if (diff0 == 0 && diff1 == 0 && diff2 == 0) 522 return 0; /* ECC is ok */ 523 524 /* sometimes people do not think about using the ECC, so check 525 * to see if we have an 0xff,0xff,0xff read ECC and then ignore 526 * the error, on the assumption that this is an un-eccd page. 527 */ 528 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff 529 && info->platform->ignore_unset_ecc) 530 return 0; 531 532 /* Can we correct this ECC (ie, one row and column change). 533 * Note, this is similar to the 256 error code on smartmedia */ 534 535 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && 536 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && 537 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { 538 /* calculate the bit position of the error */ 539 540 bit = ((diff2 >> 3) & 1) | 541 ((diff2 >> 4) & 2) | 542 ((diff2 >> 5) & 4); 543 544 /* calculate the byte position of the error */ 545 546 byte = ((diff2 << 7) & 0x100) | 547 ((diff1 << 0) & 0x80) | 548 ((diff1 << 1) & 0x40) | 549 ((diff1 << 2) & 0x20) | 550 ((diff1 << 3) & 0x10) | 551 ((diff0 >> 4) & 0x08) | 552 ((diff0 >> 3) & 0x04) | 553 ((diff0 >> 2) & 0x02) | 554 ((diff0 >> 1) & 0x01); 555 556 dev_dbg(info->device, "correcting error bit %d, byte %d\n", 557 bit, byte); 558 559 dat[byte] ^= (1 << bit); 560 return 1; 561 } 562 563 /* if there is only one bit difference in the ECC, then 564 * one of only a row or column parity has changed, which 565 * means the error is most probably in the ECC itself */ 566 567 diff0 |= (diff1 << 8); 568 diff0 |= (diff2 << 16); 569 570 /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */ 571 if ((diff0 & (diff0 - 1)) == 0) 572 return 1; 573 574 return -1; 575 } 576 577 /* ECC functions 578 * 579 * These allow the s3c2410 and s3c2440 to use the controller's ECC 580 * generator block to ECC the data as it passes through] 581 */ 582 583 static void s3c2410_nand_enable_hwecc(struct nand_chip *chip, int mode) 584 { 585 struct s3c2410_nand_info *info; 586 unsigned long ctrl; 587 588 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip)); 589 ctrl = readl(info->regs + S3C2410_NFCONF); 590 ctrl |= S3C2410_NFCONF_INITECC; 591 writel(ctrl, info->regs + S3C2410_NFCONF); 592 } 593 594 static void s3c2412_nand_enable_hwecc(struct nand_chip *chip, int mode) 595 { 596 struct s3c2410_nand_info *info; 597 unsigned long ctrl; 598 599 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip)); 600 ctrl = readl(info->regs + S3C2440_NFCONT); 601 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, 602 info->regs + S3C2440_NFCONT); 603 } 604 605 static void s3c2440_nand_enable_hwecc(struct nand_chip *chip, int mode) 606 { 607 struct s3c2410_nand_info *info; 608 unsigned long ctrl; 609 610 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip)); 611 ctrl = readl(info->regs + S3C2440_NFCONT); 612 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); 613 } 614 615 static int s3c2410_nand_calculate_ecc(struct nand_chip *chip, 616 const u_char *dat, u_char *ecc_code) 617 { 618 struct mtd_info *mtd = nand_to_mtd(chip); 619 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 620 621 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); 622 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); 623 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); 624 625 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); 626 627 return 0; 628 } 629 630 static int s3c2412_nand_calculate_ecc(struct nand_chip *chip, 631 const u_char *dat, u_char *ecc_code) 632 { 633 struct mtd_info *mtd = nand_to_mtd(chip); 634 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 635 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); 636 637 ecc_code[0] = ecc; 638 ecc_code[1] = ecc >> 8; 639 ecc_code[2] = ecc >> 16; 640 641 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); 642 643 return 0; 644 } 645 646 static int s3c2440_nand_calculate_ecc(struct nand_chip *chip, 647 const u_char *dat, u_char *ecc_code) 648 { 649 struct mtd_info *mtd = nand_to_mtd(chip); 650 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 651 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); 652 653 ecc_code[0] = ecc; 654 ecc_code[1] = ecc >> 8; 655 ecc_code[2] = ecc >> 16; 656 657 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); 658 659 return 0; 660 } 661 662 /* over-ride the standard functions for a little more speed. We can 663 * use read/write block to move the data buffers to/from the controller 664 */ 665 666 static void s3c2410_nand_read_buf(struct nand_chip *this, u_char *buf, int len) 667 { 668 readsb(this->legacy.IO_ADDR_R, buf, len); 669 } 670 671 static void s3c2440_nand_read_buf(struct nand_chip *this, u_char *buf, int len) 672 { 673 struct mtd_info *mtd = nand_to_mtd(this); 674 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 675 676 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); 677 678 /* cleanup if we've got less than a word to do */ 679 if (len & 3) { 680 buf += len & ~3; 681 682 for (; len & 3; len--) 683 *buf++ = readb(info->regs + S3C2440_NFDATA); 684 } 685 } 686 687 static void s3c2410_nand_write_buf(struct nand_chip *this, const u_char *buf, 688 int len) 689 { 690 writesb(this->legacy.IO_ADDR_W, buf, len); 691 } 692 693 static void s3c2440_nand_write_buf(struct nand_chip *this, const u_char *buf, 694 int len) 695 { 696 struct mtd_info *mtd = nand_to_mtd(this); 697 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 698 699 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); 700 701 /* cleanup any fractional write */ 702 if (len & 3) { 703 buf += len & ~3; 704 705 for (; len & 3; len--, buf++) 706 writeb(*buf, info->regs + S3C2440_NFDATA); 707 } 708 } 709 710 /* device management functions */ 711 712 static int s3c24xx_nand_remove(struct platform_device *pdev) 713 { 714 struct s3c2410_nand_info *info = to_nand_info(pdev); 715 716 if (info == NULL) 717 return 0; 718 719 /* Release all our mtds and their partitions, then go through 720 * freeing the resources used 721 */ 722 723 if (info->mtds != NULL) { 724 struct s3c2410_nand_mtd *ptr = info->mtds; 725 int mtdno; 726 727 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { 728 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); 729 WARN_ON(mtd_device_unregister(nand_to_mtd(&ptr->chip))); 730 nand_cleanup(&ptr->chip); 731 } 732 } 733 734 /* free the common resources */ 735 736 if (!IS_ERR(info->clk)) 737 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); 738 739 return 0; 740 } 741 742 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, 743 struct s3c2410_nand_mtd *mtd, 744 struct s3c2410_nand_set *set) 745 { 746 if (set) { 747 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip); 748 749 mtdinfo->name = set->name; 750 751 return mtd_device_register(mtdinfo, set->partitions, 752 set->nr_partitions); 753 } 754 755 return -ENODEV; 756 } 757 758 static int s3c2410_nand_setup_interface(struct nand_chip *chip, int csline, 759 const struct nand_interface_config *conf) 760 { 761 struct mtd_info *mtd = nand_to_mtd(chip); 762 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 763 struct s3c2410_platform_nand *pdata = info->platform; 764 const struct nand_sdr_timings *timings; 765 int tacls; 766 767 timings = nand_get_sdr_timings(conf); 768 if (IS_ERR(timings)) 769 return -ENOTSUPP; 770 771 tacls = timings->tCLS_min - timings->tWP_min; 772 if (tacls < 0) 773 tacls = 0; 774 775 pdata->tacls = DIV_ROUND_UP(tacls, 1000); 776 pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000); 777 pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000); 778 779 return s3c2410_nand_setrate(info); 780 } 781 782 /** 783 * s3c2410_nand_init_chip - initialise a single instance of an chip 784 * @info: The base NAND controller the chip is on. 785 * @nmtd: The new controller MTD instance to fill in. 786 * @set: The information passed from the board specific platform data. 787 * 788 * Initialise the given @nmtd from the information in @info and @set. This 789 * readies the structure for use with the MTD layer functions by ensuring 790 * all pointers are setup and the necessary control routines selected. 791 */ 792 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, 793 struct s3c2410_nand_mtd *nmtd, 794 struct s3c2410_nand_set *set) 795 { 796 struct device_node *np = info->device->of_node; 797 struct nand_chip *chip = &nmtd->chip; 798 void __iomem *regs = info->regs; 799 800 nand_set_flash_node(chip, set->of_node); 801 802 chip->legacy.write_buf = s3c2410_nand_write_buf; 803 chip->legacy.read_buf = s3c2410_nand_read_buf; 804 chip->legacy.select_chip = s3c2410_nand_select_chip; 805 chip->legacy.chip_delay = 50; 806 nand_set_controller_data(chip, nmtd); 807 chip->options = set->options; 808 chip->controller = &info->controller; 809 810 /* 811 * let's keep behavior unchanged for legacy boards booting via pdata and 812 * auto-detect timings only when booting with a device tree. 813 */ 814 if (!np) 815 chip->options |= NAND_KEEP_TIMINGS; 816 817 switch (info->cpu_type) { 818 case TYPE_S3C2410: 819 chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA; 820 info->sel_reg = regs + S3C2410_NFCONF; 821 info->sel_bit = S3C2410_NFCONF_nFCE; 822 chip->legacy.cmd_ctrl = s3c2410_nand_hwcontrol; 823 chip->legacy.dev_ready = s3c2410_nand_devready; 824 break; 825 826 case TYPE_S3C2440: 827 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA; 828 info->sel_reg = regs + S3C2440_NFCONT; 829 info->sel_bit = S3C2440_NFCONT_nFCE; 830 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol; 831 chip->legacy.dev_ready = s3c2440_nand_devready; 832 chip->legacy.read_buf = s3c2440_nand_read_buf; 833 chip->legacy.write_buf = s3c2440_nand_write_buf; 834 break; 835 836 case TYPE_S3C2412: 837 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA; 838 info->sel_reg = regs + S3C2440_NFCONT; 839 info->sel_bit = S3C2412_NFCONT_nFCE0; 840 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol; 841 chip->legacy.dev_ready = s3c2412_nand_devready; 842 843 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) 844 dev_info(info->device, "System booted from NAND\n"); 845 846 break; 847 } 848 849 chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W; 850 851 nmtd->info = info; 852 nmtd->set = set; 853 854 chip->ecc.engine_type = info->platform->engine_type; 855 856 /* 857 * If you use u-boot BBT creation code, specifying this flag will 858 * let the kernel fish out the BBT from the NAND. 859 */ 860 if (set->flash_bbt) 861 chip->bbt_options |= NAND_BBT_USE_FLASH; 862 } 863 864 /** 865 * s3c2410_nand_attach_chip - Init the ECC engine after NAND scan 866 * @chip: The NAND chip 867 * 868 * This hook is called by the core after the identification of the NAND chip, 869 * once the relevant per-chip information is up to date.. This call ensure that 870 * we update the internal state accordingly. 871 * 872 * The internal state is currently limited to the ECC state information. 873 */ 874 static int s3c2410_nand_attach_chip(struct nand_chip *chip) 875 { 876 struct mtd_info *mtd = nand_to_mtd(chip); 877 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 878 879 switch (chip->ecc.engine_type) { 880 881 case NAND_ECC_ENGINE_TYPE_NONE: 882 dev_info(info->device, "ECC disabled\n"); 883 break; 884 885 case NAND_ECC_ENGINE_TYPE_SOFT: 886 /* 887 * This driver expects Hamming based ECC when engine_type is set 888 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to 889 * NAND_ECC_ALGO_HAMMING to avoid adding an extra ecc_algo field 890 * to s3c2410_platform_nand. 891 */ 892 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 893 dev_info(info->device, "soft ECC\n"); 894 break; 895 896 case NAND_ECC_ENGINE_TYPE_ON_HOST: 897 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 898 chip->ecc.correct = s3c2410_nand_correct_data; 899 chip->ecc.strength = 1; 900 901 switch (info->cpu_type) { 902 case TYPE_S3C2410: 903 chip->ecc.hwctl = s3c2410_nand_enable_hwecc; 904 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 905 break; 906 907 case TYPE_S3C2412: 908 chip->ecc.hwctl = s3c2412_nand_enable_hwecc; 909 chip->ecc.calculate = s3c2412_nand_calculate_ecc; 910 break; 911 912 case TYPE_S3C2440: 913 chip->ecc.hwctl = s3c2440_nand_enable_hwecc; 914 chip->ecc.calculate = s3c2440_nand_calculate_ecc; 915 break; 916 } 917 918 dev_dbg(info->device, "chip %p => page shift %d\n", 919 chip, chip->page_shift); 920 921 /* change the behaviour depending on whether we are using 922 * the large or small page nand device */ 923 if (chip->page_shift > 10) { 924 chip->ecc.size = 256; 925 chip->ecc.bytes = 3; 926 } else { 927 chip->ecc.size = 512; 928 chip->ecc.bytes = 3; 929 mtd_set_ooblayout(nand_to_mtd(chip), 930 &s3c2410_ooblayout_ops); 931 } 932 933 dev_info(info->device, "hardware ECC\n"); 934 break; 935 936 default: 937 dev_err(info->device, "invalid ECC mode!\n"); 938 return -EINVAL; 939 } 940 941 if (chip->bbt_options & NAND_BBT_USE_FLASH) 942 chip->options |= NAND_SKIP_BBTSCAN; 943 944 return 0; 945 } 946 947 static const struct nand_controller_ops s3c24xx_nand_controller_ops = { 948 .attach_chip = s3c2410_nand_attach_chip, 949 .setup_interface = s3c2410_nand_setup_interface, 950 }; 951 952 static const struct of_device_id s3c24xx_nand_dt_ids[] = { 953 { 954 .compatible = "samsung,s3c2410-nand", 955 .data = &s3c2410_nand_devtype_data, 956 }, { 957 /* also compatible with s3c6400 */ 958 .compatible = "samsung,s3c2412-nand", 959 .data = &s3c2412_nand_devtype_data, 960 }, { 961 .compatible = "samsung,s3c2440-nand", 962 .data = &s3c2440_nand_devtype_data, 963 }, 964 { /* sentinel */ } 965 }; 966 MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids); 967 968 static int s3c24xx_nand_probe_dt(struct platform_device *pdev) 969 { 970 const struct s3c24XX_nand_devtype_data *devtype_data; 971 struct s3c2410_platform_nand *pdata; 972 struct s3c2410_nand_info *info = platform_get_drvdata(pdev); 973 struct device_node *np = pdev->dev.of_node, *child; 974 struct s3c2410_nand_set *sets; 975 976 devtype_data = of_device_get_match_data(&pdev->dev); 977 if (!devtype_data) 978 return -ENODEV; 979 980 info->cpu_type = devtype_data->type; 981 982 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 983 if (!pdata) 984 return -ENOMEM; 985 986 pdev->dev.platform_data = pdata; 987 988 pdata->nr_sets = of_get_child_count(np); 989 if (!pdata->nr_sets) 990 return 0; 991 992 sets = devm_kcalloc(&pdev->dev, pdata->nr_sets, sizeof(*sets), 993 GFP_KERNEL); 994 if (!sets) 995 return -ENOMEM; 996 997 pdata->sets = sets; 998 999 for_each_available_child_of_node(np, child) { 1000 sets->name = (char *)child->name; 1001 sets->of_node = child; 1002 sets->nr_chips = 1; 1003 1004 of_node_get(child); 1005 1006 sets++; 1007 } 1008 1009 return 0; 1010 } 1011 1012 static int s3c24xx_nand_probe_pdata(struct platform_device *pdev) 1013 { 1014 struct s3c2410_nand_info *info = platform_get_drvdata(pdev); 1015 1016 info->cpu_type = platform_get_device_id(pdev)->driver_data; 1017 1018 return 0; 1019 } 1020 1021 /* s3c24xx_nand_probe 1022 * 1023 * called by device layer when it finds a device matching 1024 * one our driver can handled. This code checks to see if 1025 * it can allocate all necessary resources then calls the 1026 * nand layer to look for devices 1027 */ 1028 static int s3c24xx_nand_probe(struct platform_device *pdev) 1029 { 1030 struct s3c2410_platform_nand *plat; 1031 struct s3c2410_nand_info *info; 1032 struct s3c2410_nand_mtd *nmtd; 1033 struct s3c2410_nand_set *sets; 1034 struct resource *res; 1035 int err = 0; 1036 int size; 1037 int nr_sets; 1038 int setno; 1039 1040 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1041 if (info == NULL) { 1042 err = -ENOMEM; 1043 goto exit_error; 1044 } 1045 1046 platform_set_drvdata(pdev, info); 1047 1048 nand_controller_init(&info->controller); 1049 info->controller.ops = &s3c24xx_nand_controller_ops; 1050 1051 /* get the clock source and enable it */ 1052 1053 info->clk = devm_clk_get(&pdev->dev, "nand"); 1054 if (IS_ERR(info->clk)) { 1055 dev_err(&pdev->dev, "failed to get clock\n"); 1056 err = -ENOENT; 1057 goto exit_error; 1058 } 1059 1060 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 1061 1062 if (pdev->dev.of_node) 1063 err = s3c24xx_nand_probe_dt(pdev); 1064 else 1065 err = s3c24xx_nand_probe_pdata(pdev); 1066 1067 if (err) 1068 goto exit_error; 1069 1070 plat = to_nand_plat(pdev); 1071 1072 /* allocate and map the resource */ 1073 1074 /* currently we assume we have the one resource */ 1075 res = pdev->resource; 1076 size = resource_size(res); 1077 1078 info->device = &pdev->dev; 1079 info->platform = plat; 1080 1081 info->regs = devm_ioremap_resource(&pdev->dev, res); 1082 if (IS_ERR(info->regs)) { 1083 err = PTR_ERR(info->regs); 1084 goto exit_error; 1085 } 1086 1087 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); 1088 1089 if (!plat->sets || plat->nr_sets < 1) { 1090 err = -EINVAL; 1091 goto exit_error; 1092 } 1093 1094 sets = plat->sets; 1095 nr_sets = plat->nr_sets; 1096 1097 info->mtd_count = nr_sets; 1098 1099 /* allocate our information */ 1100 1101 size = nr_sets * sizeof(*info->mtds); 1102 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); 1103 if (info->mtds == NULL) { 1104 err = -ENOMEM; 1105 goto exit_error; 1106 } 1107 1108 /* initialise all possible chips */ 1109 1110 nmtd = info->mtds; 1111 1112 for (setno = 0; setno < nr_sets; setno++, nmtd++, sets++) { 1113 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip); 1114 1115 pr_debug("initialising set %d (%p, info %p)\n", 1116 setno, nmtd, info); 1117 1118 mtd->dev.parent = &pdev->dev; 1119 s3c2410_nand_init_chip(info, nmtd, sets); 1120 1121 err = nand_scan(&nmtd->chip, sets ? sets->nr_chips : 1); 1122 if (err) 1123 goto exit_error; 1124 1125 s3c2410_nand_add_partition(info, nmtd, sets); 1126 } 1127 1128 /* initialise the hardware */ 1129 err = s3c2410_nand_inithw(info); 1130 if (err != 0) 1131 goto exit_error; 1132 1133 if (allow_clk_suspend(info)) { 1134 dev_info(&pdev->dev, "clock idle support enabled\n"); 1135 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 1136 } 1137 1138 return 0; 1139 1140 exit_error: 1141 s3c24xx_nand_remove(pdev); 1142 1143 if (err == 0) 1144 err = -EINVAL; 1145 return err; 1146 } 1147 1148 /* PM Support */ 1149 #ifdef CONFIG_PM 1150 1151 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) 1152 { 1153 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 1154 1155 if (info) { 1156 info->save_sel = readl(info->sel_reg); 1157 1158 /* For the moment, we must ensure nFCE is high during 1159 * the time we are suspended. This really should be 1160 * handled by suspending the MTDs we are using, but 1161 * that is currently not the case. */ 1162 1163 writel(info->save_sel | info->sel_bit, info->sel_reg); 1164 1165 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); 1166 } 1167 1168 return 0; 1169 } 1170 1171 static int s3c24xx_nand_resume(struct platform_device *dev) 1172 { 1173 struct s3c2410_nand_info *info = platform_get_drvdata(dev); 1174 unsigned long sel; 1175 1176 if (info) { 1177 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); 1178 s3c2410_nand_inithw(info); 1179 1180 /* Restore the state of the nFCE line. */ 1181 1182 sel = readl(info->sel_reg); 1183 sel &= ~info->sel_bit; 1184 sel |= info->save_sel & info->sel_bit; 1185 writel(sel, info->sel_reg); 1186 1187 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); 1188 } 1189 1190 return 0; 1191 } 1192 1193 #else 1194 #define s3c24xx_nand_suspend NULL 1195 #define s3c24xx_nand_resume NULL 1196 #endif 1197 1198 /* driver device registration */ 1199 1200 static const struct platform_device_id s3c24xx_driver_ids[] = { 1201 { 1202 .name = "s3c2410-nand", 1203 .driver_data = TYPE_S3C2410, 1204 }, { 1205 .name = "s3c2440-nand", 1206 .driver_data = TYPE_S3C2440, 1207 }, { 1208 .name = "s3c2412-nand", 1209 .driver_data = TYPE_S3C2412, 1210 }, { 1211 .name = "s3c6400-nand", 1212 .driver_data = TYPE_S3C2412, /* compatible with 2412 */ 1213 }, 1214 { } 1215 }; 1216 1217 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 1218 1219 static struct platform_driver s3c24xx_nand_driver = { 1220 .probe = s3c24xx_nand_probe, 1221 .remove = s3c24xx_nand_remove, 1222 .suspend = s3c24xx_nand_suspend, 1223 .resume = s3c24xx_nand_resume, 1224 .id_table = s3c24xx_driver_ids, 1225 .driver = { 1226 .name = "s3c24xx-nand", 1227 .of_match_table = s3c24xx_nand_dt_ids, 1228 }, 1229 }; 1230 1231 module_platform_driver(s3c24xx_nand_driver); 1232 1233 MODULE_LICENSE("GPL"); 1234 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 1235 MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); 1236