1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright © 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver
8 */
9
10 #define pr_fmt(fmt) "nand-s3c2410: " fmt
11
12 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
13 #define DEBUG
14 #endif
15
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/io.h>
21 #include <linux/ioport.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/cpufreq.h>
28 #include <linux/of.h>
29
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/rawnand.h>
32 #include <linux/mtd/partitions.h>
33
34 #include <linux/platform_data/mtd-nand-s3c2410.h>
35
36 #define S3C2410_NFREG(x) (x)
37
38 #define S3C2410_NFCONF S3C2410_NFREG(0x00)
39 #define S3C2410_NFCMD S3C2410_NFREG(0x04)
40 #define S3C2410_NFADDR S3C2410_NFREG(0x08)
41 #define S3C2410_NFDATA S3C2410_NFREG(0x0C)
42 #define S3C2410_NFSTAT S3C2410_NFREG(0x10)
43 #define S3C2410_NFECC S3C2410_NFREG(0x14)
44 #define S3C2440_NFCONT S3C2410_NFREG(0x04)
45 #define S3C2440_NFCMD S3C2410_NFREG(0x08)
46 #define S3C2440_NFADDR S3C2410_NFREG(0x0C)
47 #define S3C2440_NFDATA S3C2410_NFREG(0x10)
48 #define S3C2440_NFSTAT S3C2410_NFREG(0x20)
49 #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
50 #define S3C2412_NFSTAT S3C2410_NFREG(0x28)
51 #define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
52 #define S3C2410_NFCONF_EN (1<<15)
53 #define S3C2410_NFCONF_INITECC (1<<12)
54 #define S3C2410_NFCONF_nFCE (1<<11)
55 #define S3C2410_NFCONF_TACLS(x) ((x)<<8)
56 #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
57 #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
58 #define S3C2410_NFSTAT_BUSY (1<<0)
59 #define S3C2440_NFCONF_TACLS(x) ((x)<<12)
60 #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
61 #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
62 #define S3C2440_NFCONT_INITECC (1<<4)
63 #define S3C2440_NFCONT_nFCE (1<<1)
64 #define S3C2440_NFCONT_ENABLE (1<<0)
65 #define S3C2440_NFSTAT_READY (1<<0)
66 #define S3C2412_NFCONF_NANDBOOT (1<<31)
67 #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
68 #define S3C2412_NFCONT_nFCE0 (1<<1)
69 #define S3C2412_NFSTAT_READY (1<<0)
70
71 /* new oob placement block for use with hardware ecc generation
72 */
s3c2410_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)73 static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
74 struct mtd_oob_region *oobregion)
75 {
76 if (section)
77 return -ERANGE;
78
79 oobregion->offset = 0;
80 oobregion->length = 3;
81
82 return 0;
83 }
84
s3c2410_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)85 static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
86 struct mtd_oob_region *oobregion)
87 {
88 if (section)
89 return -ERANGE;
90
91 oobregion->offset = 8;
92 oobregion->length = 8;
93
94 return 0;
95 }
96
97 static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
98 .ecc = s3c2410_ooblayout_ecc,
99 .free = s3c2410_ooblayout_free,
100 };
101
102 /* controller and mtd information */
103
104 struct s3c2410_nand_info;
105
106 /**
107 * struct s3c2410_nand_mtd - driver MTD structure
108 * @mtd: The MTD instance to pass to the MTD layer.
109 * @chip: The NAND chip information.
110 * @set: The platform information supplied for this set of NAND chips.
111 * @info: Link back to the hardware information.
112 */
113 struct s3c2410_nand_mtd {
114 struct nand_chip chip;
115 struct s3c2410_nand_set *set;
116 struct s3c2410_nand_info *info;
117 };
118
119 enum s3c_cpu_type {
120 TYPE_S3C2410,
121 TYPE_S3C2412,
122 TYPE_S3C2440,
123 };
124
125 enum s3c_nand_clk_state {
126 CLOCK_DISABLE = 0,
127 CLOCK_ENABLE,
128 CLOCK_SUSPEND,
129 };
130
131 /* overview of the s3c2410 nand state */
132
133 /**
134 * struct s3c2410_nand_info - NAND controller state.
135 * @controller: Base controller structure.
136 * @mtds: An array of MTD instances on this controller.
137 * @platform: The platform data for this board.
138 * @device: The platform device we bound to.
139 * @clk: The clock resource for this controller.
140 * @regs: The area mapped for the hardware registers.
141 * @sel_reg: Pointer to the register controlling the NAND selection.
142 * @sel_bit: The bit in @sel_reg to select the NAND chip.
143 * @mtd_count: The number of MTDs created from this controller.
144 * @save_sel: The contents of @sel_reg to be saved over suspend.
145 * @clk_rate: The clock rate from @clk.
146 * @clk_state: The current clock state.
147 * @cpu_type: The exact type of this controller.
148 * @freq_transition: CPUFreq notifier block
149 */
150 struct s3c2410_nand_info {
151 /* mtd info */
152 struct nand_controller controller;
153 struct s3c2410_nand_mtd *mtds;
154 struct s3c2410_platform_nand *platform;
155
156 /* device info */
157 struct device *device;
158 struct clk *clk;
159 void __iomem *regs;
160 void __iomem *sel_reg;
161 int sel_bit;
162 int mtd_count;
163 unsigned long save_sel;
164 unsigned long clk_rate;
165 enum s3c_nand_clk_state clk_state;
166
167 enum s3c_cpu_type cpu_type;
168 };
169
170 struct s3c24XX_nand_devtype_data {
171 enum s3c_cpu_type type;
172 };
173
174 static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = {
175 .type = TYPE_S3C2410,
176 };
177
178 static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = {
179 .type = TYPE_S3C2412,
180 };
181
182 static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = {
183 .type = TYPE_S3C2440,
184 };
185
186 /* conversion functions */
187
s3c2410_nand_mtd_toours(struct mtd_info * mtd)188 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
189 {
190 return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
191 chip);
192 }
193
s3c2410_nand_mtd_toinfo(struct mtd_info * mtd)194 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
195 {
196 return s3c2410_nand_mtd_toours(mtd)->info;
197 }
198
to_nand_info(struct platform_device * dev)199 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
200 {
201 return platform_get_drvdata(dev);
202 }
203
to_nand_plat(struct platform_device * dev)204 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
205 {
206 return dev_get_platdata(&dev->dev);
207 }
208
allow_clk_suspend(struct s3c2410_nand_info * info)209 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
210 {
211 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
212 return 1;
213 #else
214 return 0;
215 #endif
216 }
217
218 /**
219 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
220 * @info: The controller instance.
221 * @new_state: State to which clock should be set.
222 */
s3c2410_nand_clk_set_state(struct s3c2410_nand_info * info,enum s3c_nand_clk_state new_state)223 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
224 enum s3c_nand_clk_state new_state)
225 {
226 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
227 return;
228
229 if (info->clk_state == CLOCK_ENABLE) {
230 if (new_state != CLOCK_ENABLE)
231 clk_disable_unprepare(info->clk);
232 } else {
233 if (new_state == CLOCK_ENABLE)
234 clk_prepare_enable(info->clk);
235 }
236
237 info->clk_state = new_state;
238 }
239
240 /* timing calculations */
241
242 #define NS_IN_KHZ 1000000
243
244 /**
245 * s3c_nand_calc_rate - calculate timing data.
246 * @wanted: The cycle time in nanoseconds.
247 * @clk: The clock rate in kHz.
248 * @max: The maximum divider value.
249 *
250 * Calculate the timing value from the given parameters.
251 */
s3c_nand_calc_rate(int wanted,unsigned long clk,int max)252 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
253 {
254 int result;
255
256 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
257
258 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
259
260 if (result > max) {
261 pr_err("%d ns is too big for current clock rate %ld\n",
262 wanted, clk);
263 return -1;
264 }
265
266 if (result < 1)
267 result = 1;
268
269 return result;
270 }
271
272 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
273
274 /* controller setup */
275
276 /**
277 * s3c2410_nand_setrate - setup controller timing information.
278 * @info: The controller instance.
279 *
280 * Given the information supplied by the platform, calculate and set
281 * the necessary timing registers in the hardware to generate the
282 * necessary timing cycles to the hardware.
283 */
s3c2410_nand_setrate(struct s3c2410_nand_info * info)284 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
285 {
286 struct s3c2410_platform_nand *plat = info->platform;
287 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
288 int tacls, twrph0, twrph1;
289 unsigned long clkrate = clk_get_rate(info->clk);
290 unsigned long set, cfg, mask;
291 unsigned long flags;
292
293 /* calculate the timing information for the controller */
294
295 info->clk_rate = clkrate;
296 clkrate /= 1000; /* turn clock into kHz for ease of use */
297
298 if (plat != NULL) {
299 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
300 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
301 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
302 } else {
303 /* default timings */
304 tacls = tacls_max;
305 twrph0 = 8;
306 twrph1 = 8;
307 }
308
309 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
310 dev_err(info->device, "cannot get suitable timings\n");
311 return -EINVAL;
312 }
313
314 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
315 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
316 twrph1, to_ns(twrph1, clkrate));
317
318 switch (info->cpu_type) {
319 case TYPE_S3C2410:
320 mask = (S3C2410_NFCONF_TACLS(3) |
321 S3C2410_NFCONF_TWRPH0(7) |
322 S3C2410_NFCONF_TWRPH1(7));
323 set = S3C2410_NFCONF_EN;
324 set |= S3C2410_NFCONF_TACLS(tacls - 1);
325 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
326 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
327 break;
328
329 case TYPE_S3C2440:
330 case TYPE_S3C2412:
331 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
332 S3C2440_NFCONF_TWRPH0(7) |
333 S3C2440_NFCONF_TWRPH1(7));
334
335 set = S3C2440_NFCONF_TACLS(tacls - 1);
336 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
337 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
338 break;
339
340 default:
341 BUG();
342 }
343
344 local_irq_save(flags);
345
346 cfg = readl(info->regs + S3C2410_NFCONF);
347 cfg &= ~mask;
348 cfg |= set;
349 writel(cfg, info->regs + S3C2410_NFCONF);
350
351 local_irq_restore(flags);
352
353 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
354
355 return 0;
356 }
357
358 /**
359 * s3c2410_nand_inithw - basic hardware initialisation
360 * @info: The hardware state.
361 *
362 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
363 * to setup the hardware access speeds and set the controller to be enabled.
364 */
s3c2410_nand_inithw(struct s3c2410_nand_info * info)365 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
366 {
367 int ret;
368
369 ret = s3c2410_nand_setrate(info);
370 if (ret < 0)
371 return ret;
372
373 switch (info->cpu_type) {
374 case TYPE_S3C2410:
375 default:
376 break;
377
378 case TYPE_S3C2440:
379 case TYPE_S3C2412:
380 /* enable the controller and de-assert nFCE */
381
382 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
383 }
384
385 return 0;
386 }
387
388 /**
389 * s3c2410_nand_select_chip - select the given nand chip
390 * @this: NAND chip object.
391 * @chip: The chip number.
392 *
393 * This is called by the MTD layer to either select a given chip for the
394 * @mtd instance, or to indicate that the access has finished and the
395 * chip can be de-selected.
396 *
397 * The routine ensures that the nFCE line is correctly setup, and any
398 * platform specific selection code is called to route nFCE to the specific
399 * chip.
400 */
s3c2410_nand_select_chip(struct nand_chip * this,int chip)401 static void s3c2410_nand_select_chip(struct nand_chip *this, int chip)
402 {
403 struct s3c2410_nand_info *info;
404 struct s3c2410_nand_mtd *nmtd;
405 unsigned long cur;
406
407 nmtd = nand_get_controller_data(this);
408 info = nmtd->info;
409
410 if (chip != -1)
411 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
412
413 cur = readl(info->sel_reg);
414
415 if (chip == -1) {
416 cur |= info->sel_bit;
417 } else {
418 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
419 dev_err(info->device, "invalid chip %d\n", chip);
420 return;
421 }
422
423 if (info->platform != NULL) {
424 if (info->platform->select_chip != NULL)
425 (info->platform->select_chip) (nmtd->set, chip);
426 }
427
428 cur &= ~info->sel_bit;
429 }
430
431 writel(cur, info->sel_reg);
432
433 if (chip == -1)
434 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
435 }
436
437 /* s3c2410_nand_hwcontrol
438 *
439 * Issue command and address cycles to the chip
440 */
441
s3c2410_nand_hwcontrol(struct nand_chip * chip,int cmd,unsigned int ctrl)442 static void s3c2410_nand_hwcontrol(struct nand_chip *chip, int cmd,
443 unsigned int ctrl)
444 {
445 struct mtd_info *mtd = nand_to_mtd(chip);
446 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
447
448 if (cmd == NAND_CMD_NONE)
449 return;
450
451 if (ctrl & NAND_CLE)
452 writeb(cmd, info->regs + S3C2410_NFCMD);
453 else
454 writeb(cmd, info->regs + S3C2410_NFADDR);
455 }
456
457 /* command and control functions */
458
s3c2440_nand_hwcontrol(struct nand_chip * chip,int cmd,unsigned int ctrl)459 static void s3c2440_nand_hwcontrol(struct nand_chip *chip, int cmd,
460 unsigned int ctrl)
461 {
462 struct mtd_info *mtd = nand_to_mtd(chip);
463 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
464
465 if (cmd == NAND_CMD_NONE)
466 return;
467
468 if (ctrl & NAND_CLE)
469 writeb(cmd, info->regs + S3C2440_NFCMD);
470 else
471 writeb(cmd, info->regs + S3C2440_NFADDR);
472 }
473
474 /* s3c2410_nand_devready()
475 *
476 * returns 0 if the nand is busy, 1 if it is ready
477 */
478
s3c2410_nand_devready(struct nand_chip * chip)479 static int s3c2410_nand_devready(struct nand_chip *chip)
480 {
481 struct mtd_info *mtd = nand_to_mtd(chip);
482 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
483 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
484 }
485
s3c2440_nand_devready(struct nand_chip * chip)486 static int s3c2440_nand_devready(struct nand_chip *chip)
487 {
488 struct mtd_info *mtd = nand_to_mtd(chip);
489 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
490 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
491 }
492
s3c2412_nand_devready(struct nand_chip * chip)493 static int s3c2412_nand_devready(struct nand_chip *chip)
494 {
495 struct mtd_info *mtd = nand_to_mtd(chip);
496 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
497 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
498 }
499
500 /* ECC handling functions */
501
s3c2410_nand_correct_data(struct nand_chip * chip,u_char * dat,u_char * read_ecc,u_char * calc_ecc)502 static int s3c2410_nand_correct_data(struct nand_chip *chip, u_char *dat,
503 u_char *read_ecc, u_char *calc_ecc)
504 {
505 struct mtd_info *mtd = nand_to_mtd(chip);
506 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
507 unsigned int diff0, diff1, diff2;
508 unsigned int bit, byte;
509
510 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
511
512 diff0 = read_ecc[0] ^ calc_ecc[0];
513 diff1 = read_ecc[1] ^ calc_ecc[1];
514 diff2 = read_ecc[2] ^ calc_ecc[2];
515
516 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
517 __func__, 3, read_ecc, 3, calc_ecc,
518 diff0, diff1, diff2);
519
520 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
521 return 0; /* ECC is ok */
522
523 /* sometimes people do not think about using the ECC, so check
524 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
525 * the error, on the assumption that this is an un-eccd page.
526 */
527 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
528 && info->platform->ignore_unset_ecc)
529 return 0;
530
531 /* Can we correct this ECC (ie, one row and column change).
532 * Note, this is similar to the 256 error code on smartmedia */
533
534 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
535 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
536 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
537 /* calculate the bit position of the error */
538
539 bit = ((diff2 >> 3) & 1) |
540 ((diff2 >> 4) & 2) |
541 ((diff2 >> 5) & 4);
542
543 /* calculate the byte position of the error */
544
545 byte = ((diff2 << 7) & 0x100) |
546 ((diff1 << 0) & 0x80) |
547 ((diff1 << 1) & 0x40) |
548 ((diff1 << 2) & 0x20) |
549 ((diff1 << 3) & 0x10) |
550 ((diff0 >> 4) & 0x08) |
551 ((diff0 >> 3) & 0x04) |
552 ((diff0 >> 2) & 0x02) |
553 ((diff0 >> 1) & 0x01);
554
555 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
556 bit, byte);
557
558 dat[byte] ^= (1 << bit);
559 return 1;
560 }
561
562 /* if there is only one bit difference in the ECC, then
563 * one of only a row or column parity has changed, which
564 * means the error is most probably in the ECC itself */
565
566 diff0 |= (diff1 << 8);
567 diff0 |= (diff2 << 16);
568
569 /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */
570 if ((diff0 & (diff0 - 1)) == 0)
571 return 1;
572
573 return -1;
574 }
575
576 /* ECC functions
577 *
578 * These allow the s3c2410 and s3c2440 to use the controller's ECC
579 * generator block to ECC the data as it passes through]
580 */
581
s3c2410_nand_enable_hwecc(struct nand_chip * chip,int mode)582 static void s3c2410_nand_enable_hwecc(struct nand_chip *chip, int mode)
583 {
584 struct s3c2410_nand_info *info;
585 unsigned long ctrl;
586
587 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
588 ctrl = readl(info->regs + S3C2410_NFCONF);
589 ctrl |= S3C2410_NFCONF_INITECC;
590 writel(ctrl, info->regs + S3C2410_NFCONF);
591 }
592
s3c2412_nand_enable_hwecc(struct nand_chip * chip,int mode)593 static void s3c2412_nand_enable_hwecc(struct nand_chip *chip, int mode)
594 {
595 struct s3c2410_nand_info *info;
596 unsigned long ctrl;
597
598 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
599 ctrl = readl(info->regs + S3C2440_NFCONT);
600 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
601 info->regs + S3C2440_NFCONT);
602 }
603
s3c2440_nand_enable_hwecc(struct nand_chip * chip,int mode)604 static void s3c2440_nand_enable_hwecc(struct nand_chip *chip, int mode)
605 {
606 struct s3c2410_nand_info *info;
607 unsigned long ctrl;
608
609 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
610 ctrl = readl(info->regs + S3C2440_NFCONT);
611 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
612 }
613
s3c2410_nand_calculate_ecc(struct nand_chip * chip,const u_char * dat,u_char * ecc_code)614 static int s3c2410_nand_calculate_ecc(struct nand_chip *chip,
615 const u_char *dat, u_char *ecc_code)
616 {
617 struct mtd_info *mtd = nand_to_mtd(chip);
618 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
619
620 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
621 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
622 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
623
624 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
625
626 return 0;
627 }
628
s3c2412_nand_calculate_ecc(struct nand_chip * chip,const u_char * dat,u_char * ecc_code)629 static int s3c2412_nand_calculate_ecc(struct nand_chip *chip,
630 const u_char *dat, u_char *ecc_code)
631 {
632 struct mtd_info *mtd = nand_to_mtd(chip);
633 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
634 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
635
636 ecc_code[0] = ecc;
637 ecc_code[1] = ecc >> 8;
638 ecc_code[2] = ecc >> 16;
639
640 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
641
642 return 0;
643 }
644
s3c2440_nand_calculate_ecc(struct nand_chip * chip,const u_char * dat,u_char * ecc_code)645 static int s3c2440_nand_calculate_ecc(struct nand_chip *chip,
646 const u_char *dat, u_char *ecc_code)
647 {
648 struct mtd_info *mtd = nand_to_mtd(chip);
649 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
650 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
651
652 ecc_code[0] = ecc;
653 ecc_code[1] = ecc >> 8;
654 ecc_code[2] = ecc >> 16;
655
656 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
657
658 return 0;
659 }
660
661 /* over-ride the standard functions for a little more speed. We can
662 * use read/write block to move the data buffers to/from the controller
663 */
664
s3c2410_nand_read_buf(struct nand_chip * this,u_char * buf,int len)665 static void s3c2410_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
666 {
667 readsb(this->legacy.IO_ADDR_R, buf, len);
668 }
669
s3c2440_nand_read_buf(struct nand_chip * this,u_char * buf,int len)670 static void s3c2440_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
671 {
672 struct mtd_info *mtd = nand_to_mtd(this);
673 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
674
675 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
676
677 /* cleanup if we've got less than a word to do */
678 if (len & 3) {
679 buf += len & ~3;
680
681 for (; len & 3; len--)
682 *buf++ = readb(info->regs + S3C2440_NFDATA);
683 }
684 }
685
s3c2410_nand_write_buf(struct nand_chip * this,const u_char * buf,int len)686 static void s3c2410_nand_write_buf(struct nand_chip *this, const u_char *buf,
687 int len)
688 {
689 writesb(this->legacy.IO_ADDR_W, buf, len);
690 }
691
s3c2440_nand_write_buf(struct nand_chip * this,const u_char * buf,int len)692 static void s3c2440_nand_write_buf(struct nand_chip *this, const u_char *buf,
693 int len)
694 {
695 struct mtd_info *mtd = nand_to_mtd(this);
696 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
697
698 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
699
700 /* cleanup any fractional write */
701 if (len & 3) {
702 buf += len & ~3;
703
704 for (; len & 3; len--, buf++)
705 writeb(*buf, info->regs + S3C2440_NFDATA);
706 }
707 }
708
709 /* device management functions */
710
s3c24xx_nand_remove(struct platform_device * pdev)711 static void s3c24xx_nand_remove(struct platform_device *pdev)
712 {
713 struct s3c2410_nand_info *info = to_nand_info(pdev);
714
715 if (info == NULL)
716 return;
717
718 /* Release all our mtds and their partitions, then go through
719 * freeing the resources used
720 */
721
722 if (info->mtds != NULL) {
723 struct s3c2410_nand_mtd *ptr = info->mtds;
724 int mtdno;
725
726 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
727 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
728 WARN_ON(mtd_device_unregister(nand_to_mtd(&ptr->chip)));
729 nand_cleanup(&ptr->chip);
730 }
731 }
732
733 /* free the common resources */
734
735 if (!IS_ERR(info->clk))
736 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
737 }
738
s3c2410_nand_add_partition(struct s3c2410_nand_info * info,struct s3c2410_nand_mtd * mtd,struct s3c2410_nand_set * set)739 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
740 struct s3c2410_nand_mtd *mtd,
741 struct s3c2410_nand_set *set)
742 {
743 if (set) {
744 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
745
746 mtdinfo->name = set->name;
747
748 return mtd_device_register(mtdinfo, set->partitions,
749 set->nr_partitions);
750 }
751
752 return -ENODEV;
753 }
754
s3c2410_nand_setup_interface(struct nand_chip * chip,int csline,const struct nand_interface_config * conf)755 static int s3c2410_nand_setup_interface(struct nand_chip *chip, int csline,
756 const struct nand_interface_config *conf)
757 {
758 struct mtd_info *mtd = nand_to_mtd(chip);
759 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
760 struct s3c2410_platform_nand *pdata = info->platform;
761 const struct nand_sdr_timings *timings;
762 int tacls;
763
764 timings = nand_get_sdr_timings(conf);
765 if (IS_ERR(timings))
766 return -ENOTSUPP;
767
768 tacls = timings->tCLS_min - timings->tWP_min;
769 if (tacls < 0)
770 tacls = 0;
771
772 pdata->tacls = DIV_ROUND_UP(tacls, 1000);
773 pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000);
774 pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000);
775
776 return s3c2410_nand_setrate(info);
777 }
778
779 /**
780 * s3c2410_nand_init_chip - initialise a single instance of an chip
781 * @info: The base NAND controller the chip is on.
782 * @nmtd: The new controller MTD instance to fill in.
783 * @set: The information passed from the board specific platform data.
784 *
785 * Initialise the given @nmtd from the information in @info and @set. This
786 * readies the structure for use with the MTD layer functions by ensuring
787 * all pointers are setup and the necessary control routines selected.
788 */
s3c2410_nand_init_chip(struct s3c2410_nand_info * info,struct s3c2410_nand_mtd * nmtd,struct s3c2410_nand_set * set)789 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
790 struct s3c2410_nand_mtd *nmtd,
791 struct s3c2410_nand_set *set)
792 {
793 struct device_node *np = info->device->of_node;
794 struct nand_chip *chip = &nmtd->chip;
795 void __iomem *regs = info->regs;
796
797 nand_set_flash_node(chip, set->of_node);
798
799 chip->legacy.write_buf = s3c2410_nand_write_buf;
800 chip->legacy.read_buf = s3c2410_nand_read_buf;
801 chip->legacy.select_chip = s3c2410_nand_select_chip;
802 chip->legacy.chip_delay = 50;
803 nand_set_controller_data(chip, nmtd);
804 chip->options = set->options;
805 chip->controller = &info->controller;
806
807 /*
808 * let's keep behavior unchanged for legacy boards booting via pdata and
809 * auto-detect timings only when booting with a device tree.
810 */
811 if (!np)
812 chip->options |= NAND_KEEP_TIMINGS;
813
814 switch (info->cpu_type) {
815 case TYPE_S3C2410:
816 chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA;
817 info->sel_reg = regs + S3C2410_NFCONF;
818 info->sel_bit = S3C2410_NFCONF_nFCE;
819 chip->legacy.cmd_ctrl = s3c2410_nand_hwcontrol;
820 chip->legacy.dev_ready = s3c2410_nand_devready;
821 break;
822
823 case TYPE_S3C2440:
824 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
825 info->sel_reg = regs + S3C2440_NFCONT;
826 info->sel_bit = S3C2440_NFCONT_nFCE;
827 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
828 chip->legacy.dev_ready = s3c2440_nand_devready;
829 chip->legacy.read_buf = s3c2440_nand_read_buf;
830 chip->legacy.write_buf = s3c2440_nand_write_buf;
831 break;
832
833 case TYPE_S3C2412:
834 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
835 info->sel_reg = regs + S3C2440_NFCONT;
836 info->sel_bit = S3C2412_NFCONT_nFCE0;
837 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
838 chip->legacy.dev_ready = s3c2412_nand_devready;
839
840 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
841 dev_info(info->device, "System booted from NAND\n");
842
843 break;
844 }
845
846 chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W;
847
848 nmtd->info = info;
849 nmtd->set = set;
850
851 chip->ecc.engine_type = info->platform->engine_type;
852
853 /*
854 * If you use u-boot BBT creation code, specifying this flag will
855 * let the kernel fish out the BBT from the NAND.
856 */
857 if (set->flash_bbt)
858 chip->bbt_options |= NAND_BBT_USE_FLASH;
859 }
860
861 /**
862 * s3c2410_nand_attach_chip - Init the ECC engine after NAND scan
863 * @chip: The NAND chip
864 *
865 * This hook is called by the core after the identification of the NAND chip,
866 * once the relevant per-chip information is up to date.. This call ensure that
867 * we update the internal state accordingly.
868 *
869 * The internal state is currently limited to the ECC state information.
870 */
s3c2410_nand_attach_chip(struct nand_chip * chip)871 static int s3c2410_nand_attach_chip(struct nand_chip *chip)
872 {
873 struct mtd_info *mtd = nand_to_mtd(chip);
874 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
875
876 switch (chip->ecc.engine_type) {
877
878 case NAND_ECC_ENGINE_TYPE_NONE:
879 dev_info(info->device, "ECC disabled\n");
880 break;
881
882 case NAND_ECC_ENGINE_TYPE_SOFT:
883 /*
884 * This driver expects Hamming based ECC when engine_type is set
885 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to
886 * NAND_ECC_ALGO_HAMMING to avoid adding an extra ecc_algo field
887 * to s3c2410_platform_nand.
888 */
889 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
890 dev_info(info->device, "soft ECC\n");
891 break;
892
893 case NAND_ECC_ENGINE_TYPE_ON_HOST:
894 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
895 chip->ecc.correct = s3c2410_nand_correct_data;
896 chip->ecc.strength = 1;
897
898 switch (info->cpu_type) {
899 case TYPE_S3C2410:
900 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
901 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
902 break;
903
904 case TYPE_S3C2412:
905 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
906 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
907 break;
908
909 case TYPE_S3C2440:
910 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
911 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
912 break;
913 }
914
915 dev_dbg(info->device, "chip %p => page shift %d\n",
916 chip, chip->page_shift);
917
918 /* change the behaviour depending on whether we are using
919 * the large or small page nand device */
920 if (chip->page_shift > 10) {
921 chip->ecc.size = 256;
922 chip->ecc.bytes = 3;
923 } else {
924 chip->ecc.size = 512;
925 chip->ecc.bytes = 3;
926 mtd_set_ooblayout(nand_to_mtd(chip),
927 &s3c2410_ooblayout_ops);
928 }
929
930 dev_info(info->device, "hardware ECC\n");
931 break;
932
933 default:
934 dev_err(info->device, "invalid ECC mode!\n");
935 return -EINVAL;
936 }
937
938 if (chip->bbt_options & NAND_BBT_USE_FLASH)
939 chip->options |= NAND_SKIP_BBTSCAN;
940
941 return 0;
942 }
943
944 static const struct nand_controller_ops s3c24xx_nand_controller_ops = {
945 .attach_chip = s3c2410_nand_attach_chip,
946 .setup_interface = s3c2410_nand_setup_interface,
947 };
948
949 static const struct of_device_id s3c24xx_nand_dt_ids[] = {
950 {
951 .compatible = "samsung,s3c2410-nand",
952 .data = &s3c2410_nand_devtype_data,
953 }, {
954 /* also compatible with s3c6400 */
955 .compatible = "samsung,s3c2412-nand",
956 .data = &s3c2412_nand_devtype_data,
957 }, {
958 .compatible = "samsung,s3c2440-nand",
959 .data = &s3c2440_nand_devtype_data,
960 },
961 { /* sentinel */ }
962 };
963 MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids);
964
s3c24xx_nand_probe_dt(struct platform_device * pdev)965 static int s3c24xx_nand_probe_dt(struct platform_device *pdev)
966 {
967 const struct s3c24XX_nand_devtype_data *devtype_data;
968 struct s3c2410_platform_nand *pdata;
969 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
970 struct device_node *np = pdev->dev.of_node, *child;
971 struct s3c2410_nand_set *sets;
972
973 devtype_data = of_device_get_match_data(&pdev->dev);
974 if (!devtype_data)
975 return -ENODEV;
976
977 info->cpu_type = devtype_data->type;
978
979 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
980 if (!pdata)
981 return -ENOMEM;
982
983 pdev->dev.platform_data = pdata;
984
985 pdata->nr_sets = of_get_child_count(np);
986 if (!pdata->nr_sets)
987 return 0;
988
989 sets = devm_kcalloc(&pdev->dev, pdata->nr_sets, sizeof(*sets),
990 GFP_KERNEL);
991 if (!sets)
992 return -ENOMEM;
993
994 pdata->sets = sets;
995
996 for_each_available_child_of_node(np, child) {
997 sets->name = (char *)child->name;
998 sets->of_node = child;
999 sets->nr_chips = 1;
1000
1001 of_node_get(child);
1002
1003 sets++;
1004 }
1005
1006 return 0;
1007 }
1008
s3c24xx_nand_probe_pdata(struct platform_device * pdev)1009 static int s3c24xx_nand_probe_pdata(struct platform_device *pdev)
1010 {
1011 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1012
1013 info->cpu_type = platform_get_device_id(pdev)->driver_data;
1014
1015 return 0;
1016 }
1017
1018 /* s3c24xx_nand_probe
1019 *
1020 * called by device layer when it finds a device matching
1021 * one our driver can handled. This code checks to see if
1022 * it can allocate all necessary resources then calls the
1023 * nand layer to look for devices
1024 */
s3c24xx_nand_probe(struct platform_device * pdev)1025 static int s3c24xx_nand_probe(struct platform_device *pdev)
1026 {
1027 struct s3c2410_platform_nand *plat;
1028 struct s3c2410_nand_info *info;
1029 struct s3c2410_nand_mtd *nmtd;
1030 struct s3c2410_nand_set *sets;
1031 struct resource *res;
1032 int err = 0;
1033 int size;
1034 int nr_sets;
1035 int setno;
1036
1037 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1038 if (info == NULL) {
1039 err = -ENOMEM;
1040 goto exit_error;
1041 }
1042
1043 platform_set_drvdata(pdev, info);
1044
1045 nand_controller_init(&info->controller);
1046 info->controller.ops = &s3c24xx_nand_controller_ops;
1047
1048 /* get the clock source and enable it */
1049
1050 info->clk = devm_clk_get(&pdev->dev, "nand");
1051 if (IS_ERR(info->clk)) {
1052 dev_err(&pdev->dev, "failed to get clock\n");
1053 err = -ENOENT;
1054 goto exit_error;
1055 }
1056
1057 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1058
1059 if (pdev->dev.of_node)
1060 err = s3c24xx_nand_probe_dt(pdev);
1061 else
1062 err = s3c24xx_nand_probe_pdata(pdev);
1063
1064 if (err)
1065 goto exit_error;
1066
1067 plat = to_nand_plat(pdev);
1068
1069 /* allocate and map the resource */
1070
1071 /* currently we assume we have the one resource */
1072 res = pdev->resource;
1073 size = resource_size(res);
1074
1075 info->device = &pdev->dev;
1076 info->platform = plat;
1077
1078 info->regs = devm_ioremap_resource(&pdev->dev, res);
1079 if (IS_ERR(info->regs)) {
1080 err = PTR_ERR(info->regs);
1081 goto exit_error;
1082 }
1083
1084 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1085
1086 if (!plat->sets || plat->nr_sets < 1) {
1087 err = -EINVAL;
1088 goto exit_error;
1089 }
1090
1091 sets = plat->sets;
1092 nr_sets = plat->nr_sets;
1093
1094 info->mtd_count = nr_sets;
1095
1096 /* allocate our information */
1097
1098 size = nr_sets * sizeof(*info->mtds);
1099 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1100 if (info->mtds == NULL) {
1101 err = -ENOMEM;
1102 goto exit_error;
1103 }
1104
1105 /* initialise all possible chips */
1106
1107 nmtd = info->mtds;
1108
1109 for (setno = 0; setno < nr_sets; setno++, nmtd++, sets++) {
1110 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
1111
1112 pr_debug("initialising set %d (%p, info %p)\n",
1113 setno, nmtd, info);
1114
1115 mtd->dev.parent = &pdev->dev;
1116 s3c2410_nand_init_chip(info, nmtd, sets);
1117
1118 err = nand_scan(&nmtd->chip, sets ? sets->nr_chips : 1);
1119 if (err)
1120 goto exit_error;
1121
1122 s3c2410_nand_add_partition(info, nmtd, sets);
1123 }
1124
1125 /* initialise the hardware */
1126 err = s3c2410_nand_inithw(info);
1127 if (err != 0)
1128 goto exit_error;
1129
1130 if (allow_clk_suspend(info)) {
1131 dev_info(&pdev->dev, "clock idle support enabled\n");
1132 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1133 }
1134
1135 return 0;
1136
1137 exit_error:
1138 s3c24xx_nand_remove(pdev);
1139
1140 if (err == 0)
1141 err = -EINVAL;
1142 return err;
1143 }
1144
1145 /* PM Support */
1146 #ifdef CONFIG_PM
1147
s3c24xx_nand_suspend(struct platform_device * dev,pm_message_t pm)1148 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1149 {
1150 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1151
1152 if (info) {
1153 info->save_sel = readl(info->sel_reg);
1154
1155 /* For the moment, we must ensure nFCE is high during
1156 * the time we are suspended. This really should be
1157 * handled by suspending the MTDs we are using, but
1158 * that is currently not the case. */
1159
1160 writel(info->save_sel | info->sel_bit, info->sel_reg);
1161
1162 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1163 }
1164
1165 return 0;
1166 }
1167
s3c24xx_nand_resume(struct platform_device * dev)1168 static int s3c24xx_nand_resume(struct platform_device *dev)
1169 {
1170 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1171 unsigned long sel;
1172
1173 if (info) {
1174 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1175 s3c2410_nand_inithw(info);
1176
1177 /* Restore the state of the nFCE line. */
1178
1179 sel = readl(info->sel_reg);
1180 sel &= ~info->sel_bit;
1181 sel |= info->save_sel & info->sel_bit;
1182 writel(sel, info->sel_reg);
1183
1184 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1185 }
1186
1187 return 0;
1188 }
1189
1190 #else
1191 #define s3c24xx_nand_suspend NULL
1192 #define s3c24xx_nand_resume NULL
1193 #endif
1194
1195 /* driver device registration */
1196
1197 static const struct platform_device_id s3c24xx_driver_ids[] = {
1198 {
1199 .name = "s3c2410-nand",
1200 .driver_data = TYPE_S3C2410,
1201 }, {
1202 .name = "s3c2440-nand",
1203 .driver_data = TYPE_S3C2440,
1204 }, {
1205 .name = "s3c2412-nand",
1206 .driver_data = TYPE_S3C2412,
1207 }, {
1208 .name = "s3c6400-nand",
1209 .driver_data = TYPE_S3C2412, /* compatible with 2412 */
1210 },
1211 { }
1212 };
1213
1214 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1215
1216 static struct platform_driver s3c24xx_nand_driver = {
1217 .probe = s3c24xx_nand_probe,
1218 .remove_new = s3c24xx_nand_remove,
1219 .suspend = s3c24xx_nand_suspend,
1220 .resume = s3c24xx_nand_resume,
1221 .id_table = s3c24xx_driver_ids,
1222 .driver = {
1223 .name = "s3c24xx-nand",
1224 .of_match_table = s3c24xx_nand_dt_ids,
1225 },
1226 };
1227
1228 module_platform_driver(s3c24xx_nand_driver);
1229
1230 MODULE_LICENSE("GPL");
1231 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1232 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
1233