xref: /openbmc/linux/drivers/mtd/nand/raw/pasemi_nand.c (revision 0ad53fe3)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2006-2007 PA Semi, Inc
4  *
5  * Author: Egor Martovetsky <egor@pasemi.com>
6  * Maintained by: Olof Johansson <olof@lixom.net>
7  *
8  * Driver for the PWRficient onchip NAND flash interface
9  */
10 
11 #undef DEBUG
12 
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/pci.h>
22 
23 #include <asm/io.h>
24 
25 #define LBICTRL_LPCCTL_NR		0x00004000
26 #define CLE_PIN_CTL			15
27 #define ALE_PIN_CTL			14
28 
29 static unsigned int lpcctl;
30 static struct mtd_info *pasemi_nand_mtd;
31 static struct nand_controller controller;
32 static const char driver_name[] = "pasemi-nand";
33 
34 static void pasemi_read_buf(struct nand_chip *chip, u_char *buf, int len)
35 {
36 	while (len > 0x800) {
37 		memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800);
38 		buf += 0x800;
39 		len -= 0x800;
40 	}
41 	memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len);
42 }
43 
44 static void pasemi_write_buf(struct nand_chip *chip, const u_char *buf,
45 			     int len)
46 {
47 	while (len > 0x800) {
48 		memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800);
49 		buf += 0x800;
50 		len -= 0x800;
51 	}
52 	memcpy_toio(chip->legacy.IO_ADDR_R, buf, len);
53 }
54 
55 static void pasemi_hwcontrol(struct nand_chip *chip, int cmd,
56 			     unsigned int ctrl)
57 {
58 	if (cmd == NAND_CMD_NONE)
59 		return;
60 
61 	if (ctrl & NAND_CLE)
62 		out_8(chip->legacy.IO_ADDR_W + (1 << CLE_PIN_CTL), cmd);
63 	else
64 		out_8(chip->legacy.IO_ADDR_W + (1 << ALE_PIN_CTL), cmd);
65 
66 	/* Push out posted writes */
67 	eieio();
68 	inl(lpcctl);
69 }
70 
71 static int pasemi_device_ready(struct nand_chip *chip)
72 {
73 	return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR);
74 }
75 
76 static int pasemi_attach_chip(struct nand_chip *chip)
77 {
78 	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
79 
80 	if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
81 		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
82 
83 	return 0;
84 }
85 
86 static const struct nand_controller_ops pasemi_ops = {
87 	.attach_chip = pasemi_attach_chip,
88 };
89 
90 static int pasemi_nand_probe(struct platform_device *ofdev)
91 {
92 	struct device *dev = &ofdev->dev;
93 	struct pci_dev *pdev;
94 	struct device_node *np = dev->of_node;
95 	struct resource res;
96 	struct nand_chip *chip;
97 	int err = 0;
98 
99 	err = of_address_to_resource(np, 0, &res);
100 
101 	if (err)
102 		return -EINVAL;
103 
104 	/* We only support one device at the moment */
105 	if (pasemi_nand_mtd)
106 		return -ENODEV;
107 
108 	dev_dbg(dev, "pasemi_nand at %pR\n", &res);
109 
110 	/* Allocate memory for MTD device structure and private data */
111 	chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
112 	if (!chip) {
113 		err = -ENOMEM;
114 		goto out;
115 	}
116 
117 	controller.ops = &pasemi_ops;
118 	nand_controller_init(&controller);
119 	chip->controller = &controller;
120 
121 	pasemi_nand_mtd = nand_to_mtd(chip);
122 
123 	/* Link the private data with the MTD structure */
124 	pasemi_nand_mtd->dev.parent = dev;
125 
126 	chip->legacy.IO_ADDR_R = of_iomap(np, 0);
127 	chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
128 
129 	if (!chip->legacy.IO_ADDR_R) {
130 		err = -EIO;
131 		goto out_mtd;
132 	}
133 
134 	pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa008, NULL);
135 	if (!pdev) {
136 		err = -ENODEV;
137 		goto out_ior;
138 	}
139 
140 	lpcctl = pci_resource_start(pdev, 0);
141 	pci_dev_put(pdev);
142 
143 	if (!request_region(lpcctl, 4, driver_name)) {
144 		err = -EBUSY;
145 		goto out_ior;
146 	}
147 
148 	chip->legacy.cmd_ctrl = pasemi_hwcontrol;
149 	chip->legacy.dev_ready = pasemi_device_ready;
150 	chip->legacy.read_buf = pasemi_read_buf;
151 	chip->legacy.write_buf = pasemi_write_buf;
152 	chip->legacy.chip_delay = 0;
153 
154 	/* Enable the following for a flash based bad block table */
155 	chip->bbt_options = NAND_BBT_USE_FLASH;
156 
157 	/* Scan to find existence of the device */
158 	err = nand_scan(chip, 1);
159 	if (err)
160 		goto out_lpc;
161 
162 	if (mtd_device_register(pasemi_nand_mtd, NULL, 0)) {
163 		dev_err(dev, "Unable to register MTD device\n");
164 		err = -ENODEV;
165 		goto out_cleanup_nand;
166 	}
167 
168 	dev_info(dev, "PA Semi NAND flash at %pR, control at I/O %x\n", &res,
169 		 lpcctl);
170 
171 	return 0;
172 
173  out_cleanup_nand:
174 	nand_cleanup(chip);
175  out_lpc:
176 	release_region(lpcctl, 4);
177  out_ior:
178 	iounmap(chip->legacy.IO_ADDR_R);
179  out_mtd:
180 	kfree(chip);
181  out:
182 	return err;
183 }
184 
185 static int pasemi_nand_remove(struct platform_device *ofdev)
186 {
187 	struct nand_chip *chip;
188 	int ret;
189 
190 	if (!pasemi_nand_mtd)
191 		return 0;
192 
193 	chip = mtd_to_nand(pasemi_nand_mtd);
194 
195 	/* Release resources, unregister device */
196 	ret = mtd_device_unregister(pasemi_nand_mtd);
197 	WARN_ON(ret);
198 	nand_cleanup(chip);
199 
200 	release_region(lpcctl, 4);
201 
202 	iounmap(chip->legacy.IO_ADDR_R);
203 
204 	/* Free the MTD device structure */
205 	kfree(chip);
206 
207 	pasemi_nand_mtd = NULL;
208 
209 	return 0;
210 }
211 
212 static const struct of_device_id pasemi_nand_match[] =
213 {
214 	{
215 		.compatible   = "pasemi,localbus-nand",
216 	},
217 	{},
218 };
219 
220 MODULE_DEVICE_TABLE(of, pasemi_nand_match);
221 
222 static struct platform_driver pasemi_nand_driver =
223 {
224 	.driver = {
225 		.name = driver_name,
226 		.of_match_table = pasemi_nand_match,
227 	},
228 	.probe		= pasemi_nand_probe,
229 	.remove		= pasemi_nand_remove,
230 };
231 
232 module_platform_driver(pasemi_nand_driver);
233 
234 MODULE_LICENSE("GPL");
235 MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>");
236 MODULE_DESCRIPTION("NAND flash interface driver for PA Semi PWRficient");
237