1 /* 2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> 3 * Copyright © 2004 Micron Technology Inc. 4 * Copyright © 2004 David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/platform_device.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/jiffies.h> 19 #include <linux/sched.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/rawnand.h> 22 #include <linux/mtd/partitions.h> 23 #include <linux/omap-dma.h> 24 #include <linux/io.h> 25 #include <linux/slab.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 29 #include <linux/mtd/nand_bch.h> 30 #include <linux/platform_data/elm.h> 31 32 #include <linux/omap-gpmc.h> 33 #include <linux/platform_data/mtd-nand-omap2.h> 34 35 #define DRIVER_NAME "omap2-nand" 36 #define OMAP_NAND_TIMEOUT_MS 5000 37 38 #define NAND_Ecc_P1e (1 << 0) 39 #define NAND_Ecc_P2e (1 << 1) 40 #define NAND_Ecc_P4e (1 << 2) 41 #define NAND_Ecc_P8e (1 << 3) 42 #define NAND_Ecc_P16e (1 << 4) 43 #define NAND_Ecc_P32e (1 << 5) 44 #define NAND_Ecc_P64e (1 << 6) 45 #define NAND_Ecc_P128e (1 << 7) 46 #define NAND_Ecc_P256e (1 << 8) 47 #define NAND_Ecc_P512e (1 << 9) 48 #define NAND_Ecc_P1024e (1 << 10) 49 #define NAND_Ecc_P2048e (1 << 11) 50 51 #define NAND_Ecc_P1o (1 << 16) 52 #define NAND_Ecc_P2o (1 << 17) 53 #define NAND_Ecc_P4o (1 << 18) 54 #define NAND_Ecc_P8o (1 << 19) 55 #define NAND_Ecc_P16o (1 << 20) 56 #define NAND_Ecc_P32o (1 << 21) 57 #define NAND_Ecc_P64o (1 << 22) 58 #define NAND_Ecc_P128o (1 << 23) 59 #define NAND_Ecc_P256o (1 << 24) 60 #define NAND_Ecc_P512o (1 << 25) 61 #define NAND_Ecc_P1024o (1 << 26) 62 #define NAND_Ecc_P2048o (1 << 27) 63 64 #define TF(value) (value ? 1 : 0) 65 66 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) 67 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) 68 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) 69 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) 70 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) 71 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) 72 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) 73 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) 74 75 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) 76 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) 77 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) 78 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) 79 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) 80 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) 81 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) 82 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) 83 84 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) 85 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) 86 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) 87 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) 88 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) 89 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) 90 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) 91 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) 92 93 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) 94 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) 95 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) 96 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) 97 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) 98 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) 99 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) 100 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) 101 102 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) 103 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) 104 105 #define PREFETCH_CONFIG1_CS_SHIFT 24 106 #define ECC_CONFIG_CS_SHIFT 1 107 #define CS_MASK 0x7 108 #define ENABLE_PREFETCH (0x1 << 7) 109 #define DMA_MPU_MODE_SHIFT 2 110 #define ECCSIZE0_SHIFT 12 111 #define ECCSIZE1_SHIFT 22 112 #define ECC1RESULTSIZE 0x1 113 #define ECCCLEAR 0x100 114 #define ECC1 0x1 115 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 116 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) 117 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) 118 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) 119 #define STATUS_BUFF_EMPTY 0x00000001 120 121 #define SECTOR_BYTES 512 122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ 123 #define BCH4_BIT_PAD 4 124 125 /* GPMC ecc engine settings for read */ 126 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ 127 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ 128 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ 129 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ 130 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ 131 132 /* GPMC ecc engine settings for write */ 133 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ 134 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ 135 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ 136 137 #define BADBLOCK_MARKER_LENGTH 2 138 139 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55, 140 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78, 141 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93, 142 0x07, 0x0e}; 143 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, 144 0xac, 0x6b, 0xff, 0x99, 0x7b}; 145 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; 146 147 /* Shared among all NAND instances to synchronize access to the ECC Engine */ 148 static struct nand_hw_control omap_gpmc_controller = { 149 .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock), 150 .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq), 151 }; 152 153 struct omap_nand_info { 154 struct nand_chip nand; 155 struct platform_device *pdev; 156 157 int gpmc_cs; 158 bool dev_ready; 159 enum nand_io xfer_type; 160 int devsize; 161 enum omap_ecc ecc_opt; 162 struct device_node *elm_of_node; 163 164 unsigned long phys_base; 165 struct completion comp; 166 struct dma_chan *dma; 167 int gpmc_irq_fifo; 168 int gpmc_irq_count; 169 enum { 170 OMAP_NAND_IO_READ = 0, /* read */ 171 OMAP_NAND_IO_WRITE, /* write */ 172 } iomode; 173 u_char *buf; 174 int buf_len; 175 /* Interface to GPMC */ 176 struct gpmc_nand_regs reg; 177 struct gpmc_nand_ops *ops; 178 bool flash_bbt; 179 /* fields specific for BCHx_HW ECC scheme */ 180 struct device *elm_dev; 181 /* NAND ready gpio */ 182 struct gpio_desc *ready_gpiod; 183 }; 184 185 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd) 186 { 187 return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand); 188 } 189 190 /** 191 * omap_prefetch_enable - configures and starts prefetch transfer 192 * @cs: cs (chip select) number 193 * @fifo_th: fifo threshold to be used for read/ write 194 * @dma_mode: dma mode enable (1) or disable (0) 195 * @u32_count: number of bytes to be transferred 196 * @is_write: prefetch read(0) or write post(1) mode 197 */ 198 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, 199 unsigned int u32_count, int is_write, struct omap_nand_info *info) 200 { 201 u32 val; 202 203 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) 204 return -1; 205 206 if (readl(info->reg.gpmc_prefetch_control)) 207 return -EBUSY; 208 209 /* Set the amount of bytes to be prefetched */ 210 writel(u32_count, info->reg.gpmc_prefetch_config2); 211 212 /* Set dma/mpu mode, the prefetch read / post write and 213 * enable the engine. Set which cs is has requested for. 214 */ 215 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | 216 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | 217 (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1)); 218 writel(val, info->reg.gpmc_prefetch_config1); 219 220 /* Start the prefetch engine */ 221 writel(0x1, info->reg.gpmc_prefetch_control); 222 223 return 0; 224 } 225 226 /** 227 * omap_prefetch_reset - disables and stops the prefetch engine 228 */ 229 static int omap_prefetch_reset(int cs, struct omap_nand_info *info) 230 { 231 u32 config1; 232 233 /* check if the same module/cs is trying to reset */ 234 config1 = readl(info->reg.gpmc_prefetch_config1); 235 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) 236 return -EINVAL; 237 238 /* Stop the PFPW engine */ 239 writel(0x0, info->reg.gpmc_prefetch_control); 240 241 /* Reset/disable the PFPW engine */ 242 writel(0x0, info->reg.gpmc_prefetch_config1); 243 244 return 0; 245 } 246 247 /** 248 * omap_hwcontrol - hardware specific access to control-lines 249 * @mtd: MTD device structure 250 * @cmd: command to device 251 * @ctrl: 252 * NAND_NCE: bit 0 -> don't care 253 * NAND_CLE: bit 1 -> Command Latch 254 * NAND_ALE: bit 2 -> Address Latch 255 * 256 * NOTE: boards may use different bits for these!! 257 */ 258 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) 259 { 260 struct omap_nand_info *info = mtd_to_omap(mtd); 261 262 if (cmd != NAND_CMD_NONE) { 263 if (ctrl & NAND_CLE) 264 writeb(cmd, info->reg.gpmc_nand_command); 265 266 else if (ctrl & NAND_ALE) 267 writeb(cmd, info->reg.gpmc_nand_address); 268 269 else /* NAND_NCE */ 270 writeb(cmd, info->reg.gpmc_nand_data); 271 } 272 } 273 274 /** 275 * omap_read_buf8 - read data from NAND controller into buffer 276 * @mtd: MTD device structure 277 * @buf: buffer to store date 278 * @len: number of bytes to read 279 */ 280 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) 281 { 282 struct nand_chip *nand = mtd_to_nand(mtd); 283 284 ioread8_rep(nand->IO_ADDR_R, buf, len); 285 } 286 287 /** 288 * omap_write_buf8 - write buffer to NAND controller 289 * @mtd: MTD device structure 290 * @buf: data buffer 291 * @len: number of bytes to write 292 */ 293 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) 294 { 295 struct omap_nand_info *info = mtd_to_omap(mtd); 296 u_char *p = (u_char *)buf; 297 bool status; 298 299 while (len--) { 300 iowrite8(*p++, info->nand.IO_ADDR_W); 301 /* wait until buffer is available for write */ 302 do { 303 status = info->ops->nand_writebuffer_empty(); 304 } while (!status); 305 } 306 } 307 308 /** 309 * omap_read_buf16 - read data from NAND controller into buffer 310 * @mtd: MTD device structure 311 * @buf: buffer to store date 312 * @len: number of bytes to read 313 */ 314 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) 315 { 316 struct nand_chip *nand = mtd_to_nand(mtd); 317 318 ioread16_rep(nand->IO_ADDR_R, buf, len / 2); 319 } 320 321 /** 322 * omap_write_buf16 - write buffer to NAND controller 323 * @mtd: MTD device structure 324 * @buf: data buffer 325 * @len: number of bytes to write 326 */ 327 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) 328 { 329 struct omap_nand_info *info = mtd_to_omap(mtd); 330 u16 *p = (u16 *) buf; 331 bool status; 332 /* FIXME try bursts of writesw() or DMA ... */ 333 len >>= 1; 334 335 while (len--) { 336 iowrite16(*p++, info->nand.IO_ADDR_W); 337 /* wait until buffer is available for write */ 338 do { 339 status = info->ops->nand_writebuffer_empty(); 340 } while (!status); 341 } 342 } 343 344 /** 345 * omap_read_buf_pref - read data from NAND controller into buffer 346 * @mtd: MTD device structure 347 * @buf: buffer to store date 348 * @len: number of bytes to read 349 */ 350 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) 351 { 352 struct omap_nand_info *info = mtd_to_omap(mtd); 353 uint32_t r_count = 0; 354 int ret = 0; 355 u32 *p = (u32 *)buf; 356 357 /* take care of subpage reads */ 358 if (len % 4) { 359 if (info->nand.options & NAND_BUSWIDTH_16) 360 omap_read_buf16(mtd, buf, len % 4); 361 else 362 omap_read_buf8(mtd, buf, len % 4); 363 p = (u32 *) (buf + len % 4); 364 len -= len % 4; 365 } 366 367 /* configure and start prefetch transfer */ 368 ret = omap_prefetch_enable(info->gpmc_cs, 369 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); 370 if (ret) { 371 /* PFPW engine is busy, use cpu copy method */ 372 if (info->nand.options & NAND_BUSWIDTH_16) 373 omap_read_buf16(mtd, (u_char *)p, len); 374 else 375 omap_read_buf8(mtd, (u_char *)p, len); 376 } else { 377 do { 378 r_count = readl(info->reg.gpmc_prefetch_status); 379 r_count = PREFETCH_STATUS_FIFO_CNT(r_count); 380 r_count = r_count >> 2; 381 ioread32_rep(info->nand.IO_ADDR_R, p, r_count); 382 p += r_count; 383 len -= r_count << 2; 384 } while (len); 385 /* disable and stop the PFPW engine */ 386 omap_prefetch_reset(info->gpmc_cs, info); 387 } 388 } 389 390 /** 391 * omap_write_buf_pref - write buffer to NAND controller 392 * @mtd: MTD device structure 393 * @buf: data buffer 394 * @len: number of bytes to write 395 */ 396 static void omap_write_buf_pref(struct mtd_info *mtd, 397 const u_char *buf, int len) 398 { 399 struct omap_nand_info *info = mtd_to_omap(mtd); 400 uint32_t w_count = 0; 401 int i = 0, ret = 0; 402 u16 *p = (u16 *)buf; 403 unsigned long tim, limit; 404 u32 val; 405 406 /* take care of subpage writes */ 407 if (len % 2 != 0) { 408 writeb(*buf, info->nand.IO_ADDR_W); 409 p = (u16 *)(buf + 1); 410 len--; 411 } 412 413 /* configure and start prefetch transfer */ 414 ret = omap_prefetch_enable(info->gpmc_cs, 415 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); 416 if (ret) { 417 /* PFPW engine is busy, use cpu copy method */ 418 if (info->nand.options & NAND_BUSWIDTH_16) 419 omap_write_buf16(mtd, (u_char *)p, len); 420 else 421 omap_write_buf8(mtd, (u_char *)p, len); 422 } else { 423 while (len) { 424 w_count = readl(info->reg.gpmc_prefetch_status); 425 w_count = PREFETCH_STATUS_FIFO_CNT(w_count); 426 w_count = w_count >> 1; 427 for (i = 0; (i < w_count) && len; i++, len -= 2) 428 iowrite16(*p++, info->nand.IO_ADDR_W); 429 } 430 /* wait for data to flushed-out before reset the prefetch */ 431 tim = 0; 432 limit = (loops_per_jiffy * 433 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 434 do { 435 cpu_relax(); 436 val = readl(info->reg.gpmc_prefetch_status); 437 val = PREFETCH_STATUS_COUNT(val); 438 } while (val && (tim++ < limit)); 439 440 /* disable and stop the PFPW engine */ 441 omap_prefetch_reset(info->gpmc_cs, info); 442 } 443 } 444 445 /* 446 * omap_nand_dma_callback: callback on the completion of dma transfer 447 * @data: pointer to completion data structure 448 */ 449 static void omap_nand_dma_callback(void *data) 450 { 451 complete((struct completion *) data); 452 } 453 454 /* 455 * omap_nand_dma_transfer: configure and start dma transfer 456 * @mtd: MTD device structure 457 * @addr: virtual address in RAM of source/destination 458 * @len: number of data bytes to be transferred 459 * @is_write: flag for read/write operation 460 */ 461 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, 462 unsigned int len, int is_write) 463 { 464 struct omap_nand_info *info = mtd_to_omap(mtd); 465 struct dma_async_tx_descriptor *tx; 466 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : 467 DMA_FROM_DEVICE; 468 struct scatterlist sg; 469 unsigned long tim, limit; 470 unsigned n; 471 int ret; 472 u32 val; 473 474 if (!virt_addr_valid(addr)) 475 goto out_copy; 476 477 sg_init_one(&sg, addr, len); 478 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); 479 if (n == 0) { 480 dev_err(&info->pdev->dev, 481 "Couldn't DMA map a %d byte buffer\n", len); 482 goto out_copy; 483 } 484 485 tx = dmaengine_prep_slave_sg(info->dma, &sg, n, 486 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 487 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 488 if (!tx) 489 goto out_copy_unmap; 490 491 tx->callback = omap_nand_dma_callback; 492 tx->callback_param = &info->comp; 493 dmaengine_submit(tx); 494 495 init_completion(&info->comp); 496 497 /* setup and start DMA using dma_addr */ 498 dma_async_issue_pending(info->dma); 499 500 /* configure and start prefetch transfer */ 501 ret = omap_prefetch_enable(info->gpmc_cs, 502 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); 503 if (ret) 504 /* PFPW engine is busy, use cpu copy method */ 505 goto out_copy_unmap; 506 507 wait_for_completion(&info->comp); 508 tim = 0; 509 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 510 511 do { 512 cpu_relax(); 513 val = readl(info->reg.gpmc_prefetch_status); 514 val = PREFETCH_STATUS_COUNT(val); 515 } while (val && (tim++ < limit)); 516 517 /* disable and stop the PFPW engine */ 518 omap_prefetch_reset(info->gpmc_cs, info); 519 520 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); 521 return 0; 522 523 out_copy_unmap: 524 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); 525 out_copy: 526 if (info->nand.options & NAND_BUSWIDTH_16) 527 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) 528 : omap_write_buf16(mtd, (u_char *) addr, len); 529 else 530 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) 531 : omap_write_buf8(mtd, (u_char *) addr, len); 532 return 0; 533 } 534 535 /** 536 * omap_read_buf_dma_pref - read data from NAND controller into buffer 537 * @mtd: MTD device structure 538 * @buf: buffer to store date 539 * @len: number of bytes to read 540 */ 541 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) 542 { 543 if (len <= mtd->oobsize) 544 omap_read_buf_pref(mtd, buf, len); 545 else 546 /* start transfer in DMA mode */ 547 omap_nand_dma_transfer(mtd, buf, len, 0x0); 548 } 549 550 /** 551 * omap_write_buf_dma_pref - write buffer to NAND controller 552 * @mtd: MTD device structure 553 * @buf: data buffer 554 * @len: number of bytes to write 555 */ 556 static void omap_write_buf_dma_pref(struct mtd_info *mtd, 557 const u_char *buf, int len) 558 { 559 if (len <= mtd->oobsize) 560 omap_write_buf_pref(mtd, buf, len); 561 else 562 /* start transfer in DMA mode */ 563 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); 564 } 565 566 /* 567 * omap_nand_irq - GPMC irq handler 568 * @this_irq: gpmc irq number 569 * @dev: omap_nand_info structure pointer is passed here 570 */ 571 static irqreturn_t omap_nand_irq(int this_irq, void *dev) 572 { 573 struct omap_nand_info *info = (struct omap_nand_info *) dev; 574 u32 bytes; 575 576 bytes = readl(info->reg.gpmc_prefetch_status); 577 bytes = PREFETCH_STATUS_FIFO_CNT(bytes); 578 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ 579 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ 580 if (this_irq == info->gpmc_irq_count) 581 goto done; 582 583 if (info->buf_len && (info->buf_len < bytes)) 584 bytes = info->buf_len; 585 else if (!info->buf_len) 586 bytes = 0; 587 iowrite32_rep(info->nand.IO_ADDR_W, 588 (u32 *)info->buf, bytes >> 2); 589 info->buf = info->buf + bytes; 590 info->buf_len -= bytes; 591 592 } else { 593 ioread32_rep(info->nand.IO_ADDR_R, 594 (u32 *)info->buf, bytes >> 2); 595 info->buf = info->buf + bytes; 596 597 if (this_irq == info->gpmc_irq_count) 598 goto done; 599 } 600 601 return IRQ_HANDLED; 602 603 done: 604 complete(&info->comp); 605 606 disable_irq_nosync(info->gpmc_irq_fifo); 607 disable_irq_nosync(info->gpmc_irq_count); 608 609 return IRQ_HANDLED; 610 } 611 612 /* 613 * omap_read_buf_irq_pref - read data from NAND controller into buffer 614 * @mtd: MTD device structure 615 * @buf: buffer to store date 616 * @len: number of bytes to read 617 */ 618 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) 619 { 620 struct omap_nand_info *info = mtd_to_omap(mtd); 621 int ret = 0; 622 623 if (len <= mtd->oobsize) { 624 omap_read_buf_pref(mtd, buf, len); 625 return; 626 } 627 628 info->iomode = OMAP_NAND_IO_READ; 629 info->buf = buf; 630 init_completion(&info->comp); 631 632 /* configure and start prefetch transfer */ 633 ret = omap_prefetch_enable(info->gpmc_cs, 634 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); 635 if (ret) 636 /* PFPW engine is busy, use cpu copy method */ 637 goto out_copy; 638 639 info->buf_len = len; 640 641 enable_irq(info->gpmc_irq_count); 642 enable_irq(info->gpmc_irq_fifo); 643 644 /* waiting for read to complete */ 645 wait_for_completion(&info->comp); 646 647 /* disable and stop the PFPW engine */ 648 omap_prefetch_reset(info->gpmc_cs, info); 649 return; 650 651 out_copy: 652 if (info->nand.options & NAND_BUSWIDTH_16) 653 omap_read_buf16(mtd, buf, len); 654 else 655 omap_read_buf8(mtd, buf, len); 656 } 657 658 /* 659 * omap_write_buf_irq_pref - write buffer to NAND controller 660 * @mtd: MTD device structure 661 * @buf: data buffer 662 * @len: number of bytes to write 663 */ 664 static void omap_write_buf_irq_pref(struct mtd_info *mtd, 665 const u_char *buf, int len) 666 { 667 struct omap_nand_info *info = mtd_to_omap(mtd); 668 int ret = 0; 669 unsigned long tim, limit; 670 u32 val; 671 672 if (len <= mtd->oobsize) { 673 omap_write_buf_pref(mtd, buf, len); 674 return; 675 } 676 677 info->iomode = OMAP_NAND_IO_WRITE; 678 info->buf = (u_char *) buf; 679 init_completion(&info->comp); 680 681 /* configure and start prefetch transfer : size=24 */ 682 ret = omap_prefetch_enable(info->gpmc_cs, 683 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); 684 if (ret) 685 /* PFPW engine is busy, use cpu copy method */ 686 goto out_copy; 687 688 info->buf_len = len; 689 690 enable_irq(info->gpmc_irq_count); 691 enable_irq(info->gpmc_irq_fifo); 692 693 /* waiting for write to complete */ 694 wait_for_completion(&info->comp); 695 696 /* wait for data to flushed-out before reset the prefetch */ 697 tim = 0; 698 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 699 do { 700 val = readl(info->reg.gpmc_prefetch_status); 701 val = PREFETCH_STATUS_COUNT(val); 702 cpu_relax(); 703 } while (val && (tim++ < limit)); 704 705 /* disable and stop the PFPW engine */ 706 omap_prefetch_reset(info->gpmc_cs, info); 707 return; 708 709 out_copy: 710 if (info->nand.options & NAND_BUSWIDTH_16) 711 omap_write_buf16(mtd, buf, len); 712 else 713 omap_write_buf8(mtd, buf, len); 714 } 715 716 /** 717 * gen_true_ecc - This function will generate true ECC value 718 * @ecc_buf: buffer to store ecc code 719 * 720 * This generated true ECC value can be used when correcting 721 * data read from NAND flash memory core 722 */ 723 static void gen_true_ecc(u8 *ecc_buf) 724 { 725 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | 726 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); 727 728 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | 729 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); 730 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | 731 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); 732 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | 733 P1e(tmp) | P2048o(tmp) | P2048e(tmp)); 734 } 735 736 /** 737 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data 738 * @ecc_data1: ecc code from nand spare area 739 * @ecc_data2: ecc code from hardware register obtained from hardware ecc 740 * @page_data: page data 741 * 742 * This function compares two ECC's and indicates if there is an error. 743 * If the error can be corrected it will be corrected to the buffer. 744 * If there is no error, %0 is returned. If there is an error but it 745 * was corrected, %1 is returned. Otherwise, %-1 is returned. 746 */ 747 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ 748 u8 *ecc_data2, /* read from register */ 749 u8 *page_data) 750 { 751 uint i; 752 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; 753 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; 754 u8 ecc_bit[24]; 755 u8 ecc_sum = 0; 756 u8 find_bit = 0; 757 uint find_byte = 0; 758 int isEccFF; 759 760 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); 761 762 gen_true_ecc(ecc_data1); 763 gen_true_ecc(ecc_data2); 764 765 for (i = 0; i <= 2; i++) { 766 *(ecc_data1 + i) = ~(*(ecc_data1 + i)); 767 *(ecc_data2 + i) = ~(*(ecc_data2 + i)); 768 } 769 770 for (i = 0; i < 8; i++) { 771 tmp0_bit[i] = *ecc_data1 % 2; 772 *ecc_data1 = *ecc_data1 / 2; 773 } 774 775 for (i = 0; i < 8; i++) { 776 tmp1_bit[i] = *(ecc_data1 + 1) % 2; 777 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; 778 } 779 780 for (i = 0; i < 8; i++) { 781 tmp2_bit[i] = *(ecc_data1 + 2) % 2; 782 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; 783 } 784 785 for (i = 0; i < 8; i++) { 786 comp0_bit[i] = *ecc_data2 % 2; 787 *ecc_data2 = *ecc_data2 / 2; 788 } 789 790 for (i = 0; i < 8; i++) { 791 comp1_bit[i] = *(ecc_data2 + 1) % 2; 792 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; 793 } 794 795 for (i = 0; i < 8; i++) { 796 comp2_bit[i] = *(ecc_data2 + 2) % 2; 797 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; 798 } 799 800 for (i = 0; i < 6; i++) 801 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; 802 803 for (i = 0; i < 8; i++) 804 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; 805 806 for (i = 0; i < 8; i++) 807 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; 808 809 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; 810 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; 811 812 for (i = 0; i < 24; i++) 813 ecc_sum += ecc_bit[i]; 814 815 switch (ecc_sum) { 816 case 0: 817 /* Not reached because this function is not called if 818 * ECC values are equal 819 */ 820 return 0; 821 822 case 1: 823 /* Uncorrectable error */ 824 pr_debug("ECC UNCORRECTED_ERROR 1\n"); 825 return -EBADMSG; 826 827 case 11: 828 /* UN-Correctable error */ 829 pr_debug("ECC UNCORRECTED_ERROR B\n"); 830 return -EBADMSG; 831 832 case 12: 833 /* Correctable error */ 834 find_byte = (ecc_bit[23] << 8) + 835 (ecc_bit[21] << 7) + 836 (ecc_bit[19] << 6) + 837 (ecc_bit[17] << 5) + 838 (ecc_bit[15] << 4) + 839 (ecc_bit[13] << 3) + 840 (ecc_bit[11] << 2) + 841 (ecc_bit[9] << 1) + 842 ecc_bit[7]; 843 844 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; 845 846 pr_debug("Correcting single bit ECC error at offset: " 847 "%d, bit: %d\n", find_byte, find_bit); 848 849 page_data[find_byte] ^= (1 << find_bit); 850 851 return 1; 852 default: 853 if (isEccFF) { 854 if (ecc_data2[0] == 0 && 855 ecc_data2[1] == 0 && 856 ecc_data2[2] == 0) 857 return 0; 858 } 859 pr_debug("UNCORRECTED_ERROR default\n"); 860 return -EBADMSG; 861 } 862 } 863 864 /** 865 * omap_correct_data - Compares the ECC read with HW generated ECC 866 * @mtd: MTD device structure 867 * @dat: page data 868 * @read_ecc: ecc read from nand flash 869 * @calc_ecc: ecc read from HW ECC registers 870 * 871 * Compares the ecc read from nand spare area with ECC registers values 872 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error 873 * detection and correction. If there are no errors, %0 is returned. If 874 * there were errors and all of the errors were corrected, the number of 875 * corrected errors is returned. If uncorrectable errors exist, %-1 is 876 * returned. 877 */ 878 static int omap_correct_data(struct mtd_info *mtd, u_char *dat, 879 u_char *read_ecc, u_char *calc_ecc) 880 { 881 struct omap_nand_info *info = mtd_to_omap(mtd); 882 int blockCnt = 0, i = 0, ret = 0; 883 int stat = 0; 884 885 /* Ex NAND_ECC_HW12_2048 */ 886 if ((info->nand.ecc.mode == NAND_ECC_HW) && 887 (info->nand.ecc.size == 2048)) 888 blockCnt = 4; 889 else 890 blockCnt = 1; 891 892 for (i = 0; i < blockCnt; i++) { 893 if (memcmp(read_ecc, calc_ecc, 3) != 0) { 894 ret = omap_compare_ecc(read_ecc, calc_ecc, dat); 895 if (ret < 0) 896 return ret; 897 /* keep track of the number of corrected errors */ 898 stat += ret; 899 } 900 read_ecc += 3; 901 calc_ecc += 3; 902 dat += 512; 903 } 904 return stat; 905 } 906 907 /** 908 * omap_calcuate_ecc - Generate non-inverted ECC bytes. 909 * @mtd: MTD device structure 910 * @dat: The pointer to data on which ecc is computed 911 * @ecc_code: The ecc_code buffer 912 * 913 * Using noninverted ECC can be considered ugly since writing a blank 914 * page ie. padding will clear the ECC bytes. This is no problem as long 915 * nobody is trying to write data on the seemingly unused page. Reading 916 * an erased page will produce an ECC mismatch between generated and read 917 * ECC bytes that has to be dealt with separately. 918 */ 919 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, 920 u_char *ecc_code) 921 { 922 struct omap_nand_info *info = mtd_to_omap(mtd); 923 u32 val; 924 925 val = readl(info->reg.gpmc_ecc_config); 926 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) 927 return -EINVAL; 928 929 /* read ecc result */ 930 val = readl(info->reg.gpmc_ecc1_result); 931 *ecc_code++ = val; /* P128e, ..., P1e */ 932 *ecc_code++ = val >> 16; /* P128o, ..., P1o */ 933 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ 934 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); 935 936 return 0; 937 } 938 939 /** 940 * omap_enable_hwecc - This function enables the hardware ecc functionality 941 * @mtd: MTD device structure 942 * @mode: Read/Write mode 943 */ 944 static void omap_enable_hwecc(struct mtd_info *mtd, int mode) 945 { 946 struct omap_nand_info *info = mtd_to_omap(mtd); 947 struct nand_chip *chip = mtd_to_nand(mtd); 948 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; 949 u32 val; 950 951 /* clear ecc and enable bits */ 952 val = ECCCLEAR | ECC1; 953 writel(val, info->reg.gpmc_ecc_control); 954 955 /* program ecc and result sizes */ 956 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | 957 ECC1RESULTSIZE); 958 writel(val, info->reg.gpmc_ecc_size_config); 959 960 switch (mode) { 961 case NAND_ECC_READ: 962 case NAND_ECC_WRITE: 963 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); 964 break; 965 case NAND_ECC_READSYN: 966 writel(ECCCLEAR, info->reg.gpmc_ecc_control); 967 break; 968 default: 969 dev_info(&info->pdev->dev, 970 "error: unrecognized Mode[%d]!\n", mode); 971 break; 972 } 973 974 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ 975 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); 976 writel(val, info->reg.gpmc_ecc_config); 977 } 978 979 /** 980 * omap_wait - wait until the command is done 981 * @mtd: MTD device structure 982 * @chip: NAND Chip structure 983 * 984 * Wait function is called during Program and erase operations and 985 * the way it is called from MTD layer, we should wait till the NAND 986 * chip is ready after the programming/erase operation has completed. 987 * 988 * Erase can take up to 400ms and program up to 20ms according to 989 * general NAND and SmartMedia specs 990 */ 991 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) 992 { 993 struct nand_chip *this = mtd_to_nand(mtd); 994 struct omap_nand_info *info = mtd_to_omap(mtd); 995 unsigned long timeo = jiffies; 996 int status, state = this->state; 997 998 if (state == FL_ERASING) 999 timeo += msecs_to_jiffies(400); 1000 else 1001 timeo += msecs_to_jiffies(20); 1002 1003 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); 1004 while (time_before(jiffies, timeo)) { 1005 status = readb(info->reg.gpmc_nand_data); 1006 if (status & NAND_STATUS_READY) 1007 break; 1008 cond_resched(); 1009 } 1010 1011 status = readb(info->reg.gpmc_nand_data); 1012 return status; 1013 } 1014 1015 /** 1016 * omap_dev_ready - checks the NAND Ready GPIO line 1017 * @mtd: MTD device structure 1018 * 1019 * Returns true if ready and false if busy. 1020 */ 1021 static int omap_dev_ready(struct mtd_info *mtd) 1022 { 1023 struct omap_nand_info *info = mtd_to_omap(mtd); 1024 1025 return gpiod_get_value(info->ready_gpiod); 1026 } 1027 1028 /** 1029 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation 1030 * @mtd: MTD device structure 1031 * @mode: Read/Write mode 1032 * 1033 * When using BCH with SW correction (i.e. no ELM), sector size is set 1034 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode 1035 * for both reading and writing with: 1036 * eccsize0 = 0 (no additional protected byte in spare area) 1037 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) 1038 */ 1039 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) 1040 { 1041 unsigned int bch_type; 1042 unsigned int dev_width, nsectors; 1043 struct omap_nand_info *info = mtd_to_omap(mtd); 1044 enum omap_ecc ecc_opt = info->ecc_opt; 1045 struct nand_chip *chip = mtd_to_nand(mtd); 1046 u32 val, wr_mode; 1047 unsigned int ecc_size1, ecc_size0; 1048 1049 /* GPMC configurations for calculating ECC */ 1050 switch (ecc_opt) { 1051 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: 1052 bch_type = 0; 1053 nsectors = 1; 1054 wr_mode = BCH_WRAPMODE_6; 1055 ecc_size0 = BCH_ECC_SIZE0; 1056 ecc_size1 = BCH_ECC_SIZE1; 1057 break; 1058 case OMAP_ECC_BCH4_CODE_HW: 1059 bch_type = 0; 1060 nsectors = chip->ecc.steps; 1061 if (mode == NAND_ECC_READ) { 1062 wr_mode = BCH_WRAPMODE_1; 1063 ecc_size0 = BCH4R_ECC_SIZE0; 1064 ecc_size1 = BCH4R_ECC_SIZE1; 1065 } else { 1066 wr_mode = BCH_WRAPMODE_6; 1067 ecc_size0 = BCH_ECC_SIZE0; 1068 ecc_size1 = BCH_ECC_SIZE1; 1069 } 1070 break; 1071 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: 1072 bch_type = 1; 1073 nsectors = 1; 1074 wr_mode = BCH_WRAPMODE_6; 1075 ecc_size0 = BCH_ECC_SIZE0; 1076 ecc_size1 = BCH_ECC_SIZE1; 1077 break; 1078 case OMAP_ECC_BCH8_CODE_HW: 1079 bch_type = 1; 1080 nsectors = chip->ecc.steps; 1081 if (mode == NAND_ECC_READ) { 1082 wr_mode = BCH_WRAPMODE_1; 1083 ecc_size0 = BCH8R_ECC_SIZE0; 1084 ecc_size1 = BCH8R_ECC_SIZE1; 1085 } else { 1086 wr_mode = BCH_WRAPMODE_6; 1087 ecc_size0 = BCH_ECC_SIZE0; 1088 ecc_size1 = BCH_ECC_SIZE1; 1089 } 1090 break; 1091 case OMAP_ECC_BCH16_CODE_HW: 1092 bch_type = 0x2; 1093 nsectors = chip->ecc.steps; 1094 if (mode == NAND_ECC_READ) { 1095 wr_mode = 0x01; 1096 ecc_size0 = 52; /* ECC bits in nibbles per sector */ 1097 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ 1098 } else { 1099 wr_mode = 0x01; 1100 ecc_size0 = 0; /* extra bits in nibbles per sector */ 1101 ecc_size1 = 52; /* OOB bits in nibbles per sector */ 1102 } 1103 break; 1104 default: 1105 return; 1106 } 1107 1108 writel(ECC1, info->reg.gpmc_ecc_control); 1109 1110 /* Configure ecc size for BCH */ 1111 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); 1112 writel(val, info->reg.gpmc_ecc_size_config); 1113 1114 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; 1115 1116 /* BCH configuration */ 1117 val = ((1 << 16) | /* enable BCH */ 1118 (bch_type << 12) | /* BCH4/BCH8/BCH16 */ 1119 (wr_mode << 8) | /* wrap mode */ 1120 (dev_width << 7) | /* bus width */ 1121 (((nsectors-1) & 0x7) << 4) | /* number of sectors */ 1122 (info->gpmc_cs << 1) | /* ECC CS */ 1123 (0x1)); /* enable ECC */ 1124 1125 writel(val, info->reg.gpmc_ecc_config); 1126 1127 /* Clear ecc and enable bits */ 1128 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); 1129 } 1130 1131 static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f}; 1132 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 1133 0x97, 0x79, 0xe5, 0x24, 0xb5}; 1134 1135 /** 1136 * _omap_calculate_ecc_bch - Generate ECC bytes for one sector 1137 * @mtd: MTD device structure 1138 * @dat: The pointer to data on which ecc is computed 1139 * @ecc_code: The ecc_code buffer 1140 * @i: The sector number (for a multi sector page) 1141 * 1142 * Support calculating of BCH4/8/16 ECC vectors for one sector 1143 * within a page. Sector number is in @i. 1144 */ 1145 static int _omap_calculate_ecc_bch(struct mtd_info *mtd, 1146 const u_char *dat, u_char *ecc_calc, int i) 1147 { 1148 struct omap_nand_info *info = mtd_to_omap(mtd); 1149 int eccbytes = info->nand.ecc.bytes; 1150 struct gpmc_nand_regs *gpmc_regs = &info->reg; 1151 u8 *ecc_code; 1152 unsigned long bch_val1, bch_val2, bch_val3, bch_val4; 1153 u32 val; 1154 int j; 1155 1156 ecc_code = ecc_calc; 1157 switch (info->ecc_opt) { 1158 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: 1159 case OMAP_ECC_BCH8_CODE_HW: 1160 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); 1161 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); 1162 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]); 1163 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]); 1164 *ecc_code++ = (bch_val4 & 0xFF); 1165 *ecc_code++ = ((bch_val3 >> 24) & 0xFF); 1166 *ecc_code++ = ((bch_val3 >> 16) & 0xFF); 1167 *ecc_code++ = ((bch_val3 >> 8) & 0xFF); 1168 *ecc_code++ = (bch_val3 & 0xFF); 1169 *ecc_code++ = ((bch_val2 >> 24) & 0xFF); 1170 *ecc_code++ = ((bch_val2 >> 16) & 0xFF); 1171 *ecc_code++ = ((bch_val2 >> 8) & 0xFF); 1172 *ecc_code++ = (bch_val2 & 0xFF); 1173 *ecc_code++ = ((bch_val1 >> 24) & 0xFF); 1174 *ecc_code++ = ((bch_val1 >> 16) & 0xFF); 1175 *ecc_code++ = ((bch_val1 >> 8) & 0xFF); 1176 *ecc_code++ = (bch_val1 & 0xFF); 1177 break; 1178 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: 1179 case OMAP_ECC_BCH4_CODE_HW: 1180 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); 1181 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); 1182 *ecc_code++ = ((bch_val2 >> 12) & 0xFF); 1183 *ecc_code++ = ((bch_val2 >> 4) & 0xFF); 1184 *ecc_code++ = ((bch_val2 & 0xF) << 4) | 1185 ((bch_val1 >> 28) & 0xF); 1186 *ecc_code++ = ((bch_val1 >> 20) & 0xFF); 1187 *ecc_code++ = ((bch_val1 >> 12) & 0xFF); 1188 *ecc_code++ = ((bch_val1 >> 4) & 0xFF); 1189 *ecc_code++ = ((bch_val1 & 0xF) << 4); 1190 break; 1191 case OMAP_ECC_BCH16_CODE_HW: 1192 val = readl(gpmc_regs->gpmc_bch_result6[i]); 1193 ecc_code[0] = ((val >> 8) & 0xFF); 1194 ecc_code[1] = ((val >> 0) & 0xFF); 1195 val = readl(gpmc_regs->gpmc_bch_result5[i]); 1196 ecc_code[2] = ((val >> 24) & 0xFF); 1197 ecc_code[3] = ((val >> 16) & 0xFF); 1198 ecc_code[4] = ((val >> 8) & 0xFF); 1199 ecc_code[5] = ((val >> 0) & 0xFF); 1200 val = readl(gpmc_regs->gpmc_bch_result4[i]); 1201 ecc_code[6] = ((val >> 24) & 0xFF); 1202 ecc_code[7] = ((val >> 16) & 0xFF); 1203 ecc_code[8] = ((val >> 8) & 0xFF); 1204 ecc_code[9] = ((val >> 0) & 0xFF); 1205 val = readl(gpmc_regs->gpmc_bch_result3[i]); 1206 ecc_code[10] = ((val >> 24) & 0xFF); 1207 ecc_code[11] = ((val >> 16) & 0xFF); 1208 ecc_code[12] = ((val >> 8) & 0xFF); 1209 ecc_code[13] = ((val >> 0) & 0xFF); 1210 val = readl(gpmc_regs->gpmc_bch_result2[i]); 1211 ecc_code[14] = ((val >> 24) & 0xFF); 1212 ecc_code[15] = ((val >> 16) & 0xFF); 1213 ecc_code[16] = ((val >> 8) & 0xFF); 1214 ecc_code[17] = ((val >> 0) & 0xFF); 1215 val = readl(gpmc_regs->gpmc_bch_result1[i]); 1216 ecc_code[18] = ((val >> 24) & 0xFF); 1217 ecc_code[19] = ((val >> 16) & 0xFF); 1218 ecc_code[20] = ((val >> 8) & 0xFF); 1219 ecc_code[21] = ((val >> 0) & 0xFF); 1220 val = readl(gpmc_regs->gpmc_bch_result0[i]); 1221 ecc_code[22] = ((val >> 24) & 0xFF); 1222 ecc_code[23] = ((val >> 16) & 0xFF); 1223 ecc_code[24] = ((val >> 8) & 0xFF); 1224 ecc_code[25] = ((val >> 0) & 0xFF); 1225 break; 1226 default: 1227 return -EINVAL; 1228 } 1229 1230 /* ECC scheme specific syndrome customizations */ 1231 switch (info->ecc_opt) { 1232 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: 1233 /* Add constant polynomial to remainder, so that 1234 * ECC of blank pages results in 0x0 on reading back 1235 */ 1236 for (j = 0; j < eccbytes; j++) 1237 ecc_calc[j] ^= bch4_polynomial[j]; 1238 break; 1239 case OMAP_ECC_BCH4_CODE_HW: 1240 /* Set 8th ECC byte as 0x0 for ROM compatibility */ 1241 ecc_calc[eccbytes - 1] = 0x0; 1242 break; 1243 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: 1244 /* Add constant polynomial to remainder, so that 1245 * ECC of blank pages results in 0x0 on reading back 1246 */ 1247 for (j = 0; j < eccbytes; j++) 1248 ecc_calc[j] ^= bch8_polynomial[j]; 1249 break; 1250 case OMAP_ECC_BCH8_CODE_HW: 1251 /* Set 14th ECC byte as 0x0 for ROM compatibility */ 1252 ecc_calc[eccbytes - 1] = 0x0; 1253 break; 1254 case OMAP_ECC_BCH16_CODE_HW: 1255 break; 1256 default: 1257 return -EINVAL; 1258 } 1259 1260 return 0; 1261 } 1262 1263 /** 1264 * omap_calculate_ecc_bch_sw - ECC generator for sector for SW based correction 1265 * @mtd: MTD device structure 1266 * @dat: The pointer to data on which ecc is computed 1267 * @ecc_code: The ecc_code buffer 1268 * 1269 * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used 1270 * when SW based correction is required as ECC is required for one sector 1271 * at a time. 1272 */ 1273 static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, 1274 const u_char *dat, u_char *ecc_calc) 1275 { 1276 return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0); 1277 } 1278 1279 /** 1280 * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors 1281 * @mtd: MTD device structure 1282 * @dat: The pointer to data on which ecc is computed 1283 * @ecc_code: The ecc_code buffer 1284 * 1285 * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go. 1286 */ 1287 static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd, 1288 const u_char *dat, u_char *ecc_calc) 1289 { 1290 struct omap_nand_info *info = mtd_to_omap(mtd); 1291 int eccbytes = info->nand.ecc.bytes; 1292 unsigned long nsectors; 1293 int i, ret; 1294 1295 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; 1296 for (i = 0; i < nsectors; i++) { 1297 ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i); 1298 if (ret) 1299 return ret; 1300 1301 ecc_calc += eccbytes; 1302 } 1303 1304 return 0; 1305 } 1306 1307 /** 1308 * erased_sector_bitflips - count bit flips 1309 * @data: data sector buffer 1310 * @oob: oob buffer 1311 * @info: omap_nand_info 1312 * 1313 * Check the bit flips in erased page falls below correctable level. 1314 * If falls below, report the page as erased with correctable bit 1315 * flip, else report as uncorrectable page. 1316 */ 1317 static int erased_sector_bitflips(u_char *data, u_char *oob, 1318 struct omap_nand_info *info) 1319 { 1320 int flip_bits = 0, i; 1321 1322 for (i = 0; i < info->nand.ecc.size; i++) { 1323 flip_bits += hweight8(~data[i]); 1324 if (flip_bits > info->nand.ecc.strength) 1325 return 0; 1326 } 1327 1328 for (i = 0; i < info->nand.ecc.bytes - 1; i++) { 1329 flip_bits += hweight8(~oob[i]); 1330 if (flip_bits > info->nand.ecc.strength) 1331 return 0; 1332 } 1333 1334 /* 1335 * Bit flips falls in correctable level. 1336 * Fill data area with 0xFF 1337 */ 1338 if (flip_bits) { 1339 memset(data, 0xFF, info->nand.ecc.size); 1340 memset(oob, 0xFF, info->nand.ecc.bytes); 1341 } 1342 1343 return flip_bits; 1344 } 1345 1346 /** 1347 * omap_elm_correct_data - corrects page data area in case error reported 1348 * @mtd: MTD device structure 1349 * @data: page data 1350 * @read_ecc: ecc read from nand flash 1351 * @calc_ecc: ecc read from HW ECC registers 1352 * 1353 * Calculated ecc vector reported as zero in case of non-error pages. 1354 * In case of non-zero ecc vector, first filter out erased-pages, and 1355 * then process data via ELM to detect bit-flips. 1356 */ 1357 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, 1358 u_char *read_ecc, u_char *calc_ecc) 1359 { 1360 struct omap_nand_info *info = mtd_to_omap(mtd); 1361 struct nand_ecc_ctrl *ecc = &info->nand.ecc; 1362 int eccsteps = info->nand.ecc.steps; 1363 int i , j, stat = 0; 1364 int eccflag, actual_eccbytes; 1365 struct elm_errorvec err_vec[ERROR_VECTOR_MAX]; 1366 u_char *ecc_vec = calc_ecc; 1367 u_char *spare_ecc = read_ecc; 1368 u_char *erased_ecc_vec; 1369 u_char *buf; 1370 int bitflip_count; 1371 bool is_error_reported = false; 1372 u32 bit_pos, byte_pos, error_max, pos; 1373 int err; 1374 1375 switch (info->ecc_opt) { 1376 case OMAP_ECC_BCH4_CODE_HW: 1377 /* omit 7th ECC byte reserved for ROM code compatibility */ 1378 actual_eccbytes = ecc->bytes - 1; 1379 erased_ecc_vec = bch4_vector; 1380 break; 1381 case OMAP_ECC_BCH8_CODE_HW: 1382 /* omit 14th ECC byte reserved for ROM code compatibility */ 1383 actual_eccbytes = ecc->bytes - 1; 1384 erased_ecc_vec = bch8_vector; 1385 break; 1386 case OMAP_ECC_BCH16_CODE_HW: 1387 actual_eccbytes = ecc->bytes; 1388 erased_ecc_vec = bch16_vector; 1389 break; 1390 default: 1391 dev_err(&info->pdev->dev, "invalid driver configuration\n"); 1392 return -EINVAL; 1393 } 1394 1395 /* Initialize elm error vector to zero */ 1396 memset(err_vec, 0, sizeof(err_vec)); 1397 1398 for (i = 0; i < eccsteps ; i++) { 1399 eccflag = 0; /* initialize eccflag */ 1400 1401 /* 1402 * Check any error reported, 1403 * In case of error, non zero ecc reported. 1404 */ 1405 for (j = 0; j < actual_eccbytes; j++) { 1406 if (calc_ecc[j] != 0) { 1407 eccflag = 1; /* non zero ecc, error present */ 1408 break; 1409 } 1410 } 1411 1412 if (eccflag == 1) { 1413 if (memcmp(calc_ecc, erased_ecc_vec, 1414 actual_eccbytes) == 0) { 1415 /* 1416 * calc_ecc[] matches pattern for ECC(all 0xff) 1417 * so this is definitely an erased-page 1418 */ 1419 } else { 1420 buf = &data[info->nand.ecc.size * i]; 1421 /* 1422 * count number of 0-bits in read_buf. 1423 * This check can be removed once a similar 1424 * check is introduced in generic NAND driver 1425 */ 1426 bitflip_count = erased_sector_bitflips( 1427 buf, read_ecc, info); 1428 if (bitflip_count) { 1429 /* 1430 * number of 0-bits within ECC limits 1431 * So this may be an erased-page 1432 */ 1433 stat += bitflip_count; 1434 } else { 1435 /* 1436 * Too many 0-bits. It may be a 1437 * - programmed-page, OR 1438 * - erased-page with many bit-flips 1439 * So this page requires check by ELM 1440 */ 1441 err_vec[i].error_reported = true; 1442 is_error_reported = true; 1443 } 1444 } 1445 } 1446 1447 /* Update the ecc vector */ 1448 calc_ecc += ecc->bytes; 1449 read_ecc += ecc->bytes; 1450 } 1451 1452 /* Check if any error reported */ 1453 if (!is_error_reported) 1454 return stat; 1455 1456 /* Decode BCH error using ELM module */ 1457 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); 1458 1459 err = 0; 1460 for (i = 0; i < eccsteps; i++) { 1461 if (err_vec[i].error_uncorrectable) { 1462 dev_err(&info->pdev->dev, 1463 "uncorrectable bit-flips found\n"); 1464 err = -EBADMSG; 1465 } else if (err_vec[i].error_reported) { 1466 for (j = 0; j < err_vec[i].error_count; j++) { 1467 switch (info->ecc_opt) { 1468 case OMAP_ECC_BCH4_CODE_HW: 1469 /* Add 4 bits to take care of padding */ 1470 pos = err_vec[i].error_loc[j] + 1471 BCH4_BIT_PAD; 1472 break; 1473 case OMAP_ECC_BCH8_CODE_HW: 1474 case OMAP_ECC_BCH16_CODE_HW: 1475 pos = err_vec[i].error_loc[j]; 1476 break; 1477 default: 1478 return -EINVAL; 1479 } 1480 error_max = (ecc->size + actual_eccbytes) * 8; 1481 /* Calculate bit position of error */ 1482 bit_pos = pos % 8; 1483 1484 /* Calculate byte position of error */ 1485 byte_pos = (error_max - pos - 1) / 8; 1486 1487 if (pos < error_max) { 1488 if (byte_pos < 512) { 1489 pr_debug("bitflip@dat[%d]=%x\n", 1490 byte_pos, data[byte_pos]); 1491 data[byte_pos] ^= 1 << bit_pos; 1492 } else { 1493 pr_debug("bitflip@oob[%d]=%x\n", 1494 (byte_pos - 512), 1495 spare_ecc[byte_pos - 512]); 1496 spare_ecc[byte_pos - 512] ^= 1497 1 << bit_pos; 1498 } 1499 } else { 1500 dev_err(&info->pdev->dev, 1501 "invalid bit-flip @ %d:%d\n", 1502 byte_pos, bit_pos); 1503 err = -EBADMSG; 1504 } 1505 } 1506 } 1507 1508 /* Update number of correctable errors */ 1509 stat += err_vec[i].error_count; 1510 1511 /* Update page data with sector size */ 1512 data += ecc->size; 1513 spare_ecc += ecc->bytes; 1514 } 1515 1516 return (err) ? err : stat; 1517 } 1518 1519 /** 1520 * omap_write_page_bch - BCH ecc based write page function for entire page 1521 * @mtd: mtd info structure 1522 * @chip: nand chip info structure 1523 * @buf: data buffer 1524 * @oob_required: must write chip->oob_poi to OOB 1525 * @page: page 1526 * 1527 * Custom write page method evolved to support multi sector writing in one shot 1528 */ 1529 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip, 1530 const uint8_t *buf, int oob_required, int page) 1531 { 1532 int ret; 1533 uint8_t *ecc_calc = chip->ecc.calc_buf; 1534 1535 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 1536 1537 /* Enable GPMC ecc engine */ 1538 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 1539 1540 /* Write data */ 1541 chip->write_buf(mtd, buf, mtd->writesize); 1542 1543 /* Update ecc vector from GPMC result registers */ 1544 omap_calculate_ecc_bch_multi(mtd, buf, &ecc_calc[0]); 1545 1546 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 1547 chip->ecc.total); 1548 if (ret) 1549 return ret; 1550 1551 /* Write ecc vector to OOB area */ 1552 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1553 1554 return nand_prog_page_end_op(chip); 1555 } 1556 1557 /** 1558 * omap_write_subpage_bch - BCH hardware ECC based subpage write 1559 * @mtd: mtd info structure 1560 * @chip: nand chip info structure 1561 * @offset: column address of subpage within the page 1562 * @data_len: data length 1563 * @buf: data buffer 1564 * @oob_required: must write chip->oob_poi to OOB 1565 * @page: page number to write 1566 * 1567 * OMAP optimized subpage write method. 1568 */ 1569 static int omap_write_subpage_bch(struct mtd_info *mtd, 1570 struct nand_chip *chip, u32 offset, 1571 u32 data_len, const u8 *buf, 1572 int oob_required, int page) 1573 { 1574 u8 *ecc_calc = chip->ecc.calc_buf; 1575 int ecc_size = chip->ecc.size; 1576 int ecc_bytes = chip->ecc.bytes; 1577 int ecc_steps = chip->ecc.steps; 1578 u32 start_step = offset / ecc_size; 1579 u32 end_step = (offset + data_len - 1) / ecc_size; 1580 int step, ret = 0; 1581 1582 /* 1583 * Write entire page at one go as it would be optimal 1584 * as ECC is calculated by hardware. 1585 * ECC is calculated for all subpages but we choose 1586 * only what we want. 1587 */ 1588 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 1589 1590 /* Enable GPMC ECC engine */ 1591 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 1592 1593 /* Write data */ 1594 chip->write_buf(mtd, buf, mtd->writesize); 1595 1596 for (step = 0; step < ecc_steps; step++) { 1597 /* mask ECC of un-touched subpages by padding 0xFF */ 1598 if (step < start_step || step > end_step) 1599 memset(ecc_calc, 0xff, ecc_bytes); 1600 else 1601 ret = _omap_calculate_ecc_bch(mtd, buf, ecc_calc, step); 1602 1603 if (ret) 1604 return ret; 1605 1606 buf += ecc_size; 1607 ecc_calc += ecc_bytes; 1608 } 1609 1610 /* copy calculated ECC for whole page to chip->buffer->oob */ 1611 /* this include masked-value(0xFF) for unwritten subpages */ 1612 ecc_calc = chip->ecc.calc_buf; 1613 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 1614 chip->ecc.total); 1615 if (ret) 1616 return ret; 1617 1618 /* write OOB buffer to NAND device */ 1619 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1620 1621 return nand_prog_page_end_op(chip); 1622 } 1623 1624 /** 1625 * omap_read_page_bch - BCH ecc based page read function for entire page 1626 * @mtd: mtd info structure 1627 * @chip: nand chip info structure 1628 * @buf: buffer to store read data 1629 * @oob_required: caller requires OOB data read to chip->oob_poi 1630 * @page: page number to read 1631 * 1632 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module 1633 * used for error correction. 1634 * Custom method evolved to support ELM error correction & multi sector 1635 * reading. On reading page data area is read along with OOB data with 1636 * ecc engine enabled. ecc vector updated after read of OOB data. 1637 * For non error pages ecc vector reported as zero. 1638 */ 1639 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, 1640 uint8_t *buf, int oob_required, int page) 1641 { 1642 uint8_t *ecc_calc = chip->ecc.calc_buf; 1643 uint8_t *ecc_code = chip->ecc.code_buf; 1644 int stat, ret; 1645 unsigned int max_bitflips = 0; 1646 1647 nand_read_page_op(chip, page, 0, NULL, 0); 1648 1649 /* Enable GPMC ecc engine */ 1650 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1651 1652 /* Read data */ 1653 chip->read_buf(mtd, buf, mtd->writesize); 1654 1655 /* Read oob bytes */ 1656 nand_change_read_column_op(chip, 1657 mtd->writesize + BADBLOCK_MARKER_LENGTH, 1658 chip->oob_poi + BADBLOCK_MARKER_LENGTH, 1659 chip->ecc.total, false); 1660 1661 /* Calculate ecc bytes */ 1662 omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc); 1663 1664 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 1665 chip->ecc.total); 1666 if (ret) 1667 return ret; 1668 1669 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc); 1670 1671 if (stat < 0) { 1672 mtd->ecc_stats.failed++; 1673 } else { 1674 mtd->ecc_stats.corrected += stat; 1675 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1676 } 1677 1678 return max_bitflips; 1679 } 1680 1681 /** 1682 * is_elm_present - checks for presence of ELM module by scanning DT nodes 1683 * @omap_nand_info: NAND device structure containing platform data 1684 */ 1685 static bool is_elm_present(struct omap_nand_info *info, 1686 struct device_node *elm_node) 1687 { 1688 struct platform_device *pdev; 1689 1690 /* check whether elm-id is passed via DT */ 1691 if (!elm_node) { 1692 dev_err(&info->pdev->dev, "ELM devicetree node not found\n"); 1693 return false; 1694 } 1695 pdev = of_find_device_by_node(elm_node); 1696 /* check whether ELM device is registered */ 1697 if (!pdev) { 1698 dev_err(&info->pdev->dev, "ELM device not found\n"); 1699 return false; 1700 } 1701 /* ELM module available, now configure it */ 1702 info->elm_dev = &pdev->dev; 1703 return true; 1704 } 1705 1706 static bool omap2_nand_ecc_check(struct omap_nand_info *info) 1707 { 1708 bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm; 1709 1710 switch (info->ecc_opt) { 1711 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: 1712 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: 1713 ecc_needs_omap_bch = false; 1714 ecc_needs_bch = true; 1715 ecc_needs_elm = false; 1716 break; 1717 case OMAP_ECC_BCH4_CODE_HW: 1718 case OMAP_ECC_BCH8_CODE_HW: 1719 case OMAP_ECC_BCH16_CODE_HW: 1720 ecc_needs_omap_bch = true; 1721 ecc_needs_bch = false; 1722 ecc_needs_elm = true; 1723 break; 1724 default: 1725 ecc_needs_omap_bch = false; 1726 ecc_needs_bch = false; 1727 ecc_needs_elm = false; 1728 break; 1729 } 1730 1731 if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) { 1732 dev_err(&info->pdev->dev, 1733 "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); 1734 return false; 1735 } 1736 if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) { 1737 dev_err(&info->pdev->dev, 1738 "CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); 1739 return false; 1740 } 1741 if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) { 1742 dev_err(&info->pdev->dev, "ELM not available\n"); 1743 return false; 1744 } 1745 1746 return true; 1747 } 1748 1749 static const char * const nand_xfer_types[] = { 1750 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", 1751 [NAND_OMAP_POLLED] = "polled", 1752 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", 1753 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", 1754 }; 1755 1756 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info) 1757 { 1758 struct device_node *child = dev->of_node; 1759 int i; 1760 const char *s; 1761 u32 cs; 1762 1763 if (of_property_read_u32(child, "reg", &cs) < 0) { 1764 dev_err(dev, "reg not found in DT\n"); 1765 return -EINVAL; 1766 } 1767 1768 info->gpmc_cs = cs; 1769 1770 /* detect availability of ELM module. Won't be present pre-OMAP4 */ 1771 info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); 1772 if (!info->elm_of_node) { 1773 info->elm_of_node = of_parse_phandle(child, "elm_id", 0); 1774 if (!info->elm_of_node) 1775 dev_dbg(dev, "ti,elm-id not in DT\n"); 1776 } 1777 1778 /* select ecc-scheme for NAND */ 1779 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { 1780 dev_err(dev, "ti,nand-ecc-opt not found\n"); 1781 return -EINVAL; 1782 } 1783 1784 if (!strcmp(s, "sw")) { 1785 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW; 1786 } else if (!strcmp(s, "ham1") || 1787 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) { 1788 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW; 1789 } else if (!strcmp(s, "bch4")) { 1790 if (info->elm_of_node) 1791 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW; 1792 else 1793 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; 1794 } else if (!strcmp(s, "bch8")) { 1795 if (info->elm_of_node) 1796 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW; 1797 else 1798 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; 1799 } else if (!strcmp(s, "bch16")) { 1800 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW; 1801 } else { 1802 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n"); 1803 return -EINVAL; 1804 } 1805 1806 /* select data transfer mode */ 1807 if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) { 1808 for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) { 1809 if (!strcasecmp(s, nand_xfer_types[i])) { 1810 info->xfer_type = i; 1811 return 0; 1812 } 1813 } 1814 1815 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n"); 1816 return -EINVAL; 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int omap_ooblayout_ecc(struct mtd_info *mtd, int section, 1823 struct mtd_oob_region *oobregion) 1824 { 1825 struct omap_nand_info *info = mtd_to_omap(mtd); 1826 struct nand_chip *chip = &info->nand; 1827 int off = BADBLOCK_MARKER_LENGTH; 1828 1829 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && 1830 !(chip->options & NAND_BUSWIDTH_16)) 1831 off = 1; 1832 1833 if (section) 1834 return -ERANGE; 1835 1836 oobregion->offset = off; 1837 oobregion->length = chip->ecc.total; 1838 1839 return 0; 1840 } 1841 1842 static int omap_ooblayout_free(struct mtd_info *mtd, int section, 1843 struct mtd_oob_region *oobregion) 1844 { 1845 struct omap_nand_info *info = mtd_to_omap(mtd); 1846 struct nand_chip *chip = &info->nand; 1847 int off = BADBLOCK_MARKER_LENGTH; 1848 1849 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && 1850 !(chip->options & NAND_BUSWIDTH_16)) 1851 off = 1; 1852 1853 if (section) 1854 return -ERANGE; 1855 1856 off += chip->ecc.total; 1857 if (off >= mtd->oobsize) 1858 return -ERANGE; 1859 1860 oobregion->offset = off; 1861 oobregion->length = mtd->oobsize - off; 1862 1863 return 0; 1864 } 1865 1866 static const struct mtd_ooblayout_ops omap_ooblayout_ops = { 1867 .ecc = omap_ooblayout_ecc, 1868 .free = omap_ooblayout_free, 1869 }; 1870 1871 static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section, 1872 struct mtd_oob_region *oobregion) 1873 { 1874 struct nand_chip *chip = mtd_to_nand(mtd); 1875 int off = BADBLOCK_MARKER_LENGTH; 1876 1877 if (section >= chip->ecc.steps) 1878 return -ERANGE; 1879 1880 /* 1881 * When SW correction is employed, one OMAP specific marker byte is 1882 * reserved after each ECC step. 1883 */ 1884 oobregion->offset = off + (section * (chip->ecc.bytes + 1)); 1885 oobregion->length = chip->ecc.bytes; 1886 1887 return 0; 1888 } 1889 1890 static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section, 1891 struct mtd_oob_region *oobregion) 1892 { 1893 struct nand_chip *chip = mtd_to_nand(mtd); 1894 int off = BADBLOCK_MARKER_LENGTH; 1895 1896 if (section) 1897 return -ERANGE; 1898 1899 /* 1900 * When SW correction is employed, one OMAP specific marker byte is 1901 * reserved after each ECC step. 1902 */ 1903 off += ((chip->ecc.bytes + 1) * chip->ecc.steps); 1904 if (off >= mtd->oobsize) 1905 return -ERANGE; 1906 1907 oobregion->offset = off; 1908 oobregion->length = mtd->oobsize - off; 1909 1910 return 0; 1911 } 1912 1913 static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = { 1914 .ecc = omap_sw_ooblayout_ecc, 1915 .free = omap_sw_ooblayout_free, 1916 }; 1917 1918 static int omap_nand_probe(struct platform_device *pdev) 1919 { 1920 struct omap_nand_info *info; 1921 struct mtd_info *mtd; 1922 struct nand_chip *nand_chip; 1923 int err; 1924 dma_cap_mask_t mask; 1925 struct resource *res; 1926 struct device *dev = &pdev->dev; 1927 int min_oobbytes = BADBLOCK_MARKER_LENGTH; 1928 int oobbytes_per_step; 1929 1930 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), 1931 GFP_KERNEL); 1932 if (!info) 1933 return -ENOMEM; 1934 1935 info->pdev = pdev; 1936 1937 err = omap_get_dt_info(dev, info); 1938 if (err) 1939 return err; 1940 1941 info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs); 1942 if (!info->ops) { 1943 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n"); 1944 return -ENODEV; 1945 } 1946 1947 nand_chip = &info->nand; 1948 mtd = nand_to_mtd(nand_chip); 1949 mtd->dev.parent = &pdev->dev; 1950 nand_chip->ecc.priv = NULL; 1951 nand_set_flash_node(nand_chip, dev->of_node); 1952 1953 if (!mtd->name) { 1954 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, 1955 "omap2-nand.%d", info->gpmc_cs); 1956 if (!mtd->name) { 1957 dev_err(&pdev->dev, "Failed to set MTD name\n"); 1958 return -ENOMEM; 1959 } 1960 } 1961 1962 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1963 nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); 1964 if (IS_ERR(nand_chip->IO_ADDR_R)) 1965 return PTR_ERR(nand_chip->IO_ADDR_R); 1966 1967 info->phys_base = res->start; 1968 1969 nand_chip->controller = &omap_gpmc_controller; 1970 1971 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R; 1972 nand_chip->cmd_ctrl = omap_hwcontrol; 1973 1974 info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb", 1975 GPIOD_IN); 1976 if (IS_ERR(info->ready_gpiod)) { 1977 dev_err(dev, "failed to get ready gpio\n"); 1978 return PTR_ERR(info->ready_gpiod); 1979 } 1980 1981 /* 1982 * If RDY/BSY line is connected to OMAP then use the omap ready 1983 * function and the generic nand_wait function which reads the status 1984 * register after monitoring the RDY/BSY line. Otherwise use a standard 1985 * chip delay which is slightly more than tR (AC Timing) of the NAND 1986 * device and read status register until you get a failure or success 1987 */ 1988 if (info->ready_gpiod) { 1989 nand_chip->dev_ready = omap_dev_ready; 1990 nand_chip->chip_delay = 0; 1991 } else { 1992 nand_chip->waitfunc = omap_wait; 1993 nand_chip->chip_delay = 50; 1994 } 1995 1996 if (info->flash_bbt) 1997 nand_chip->bbt_options |= NAND_BBT_USE_FLASH; 1998 1999 /* scan NAND device connected to chip controller */ 2000 nand_chip->options |= info->devsize & NAND_BUSWIDTH_16; 2001 err = nand_scan_ident(mtd, 1, NULL); 2002 if (err) { 2003 dev_err(&info->pdev->dev, 2004 "scan failed, may be bus-width mismatch\n"); 2005 goto return_error; 2006 } 2007 2008 if (nand_chip->bbt_options & NAND_BBT_USE_FLASH) 2009 nand_chip->bbt_options |= NAND_BBT_NO_OOB; 2010 else 2011 nand_chip->options |= NAND_SKIP_BBTSCAN; 2012 2013 /* re-populate low-level callbacks based on xfer modes */ 2014 switch (info->xfer_type) { 2015 case NAND_OMAP_PREFETCH_POLLED: 2016 nand_chip->read_buf = omap_read_buf_pref; 2017 nand_chip->write_buf = omap_write_buf_pref; 2018 break; 2019 2020 case NAND_OMAP_POLLED: 2021 /* Use nand_base defaults for {read,write}_buf */ 2022 break; 2023 2024 case NAND_OMAP_PREFETCH_DMA: 2025 dma_cap_zero(mask); 2026 dma_cap_set(DMA_SLAVE, mask); 2027 info->dma = dma_request_chan(pdev->dev.parent, "rxtx"); 2028 2029 if (IS_ERR(info->dma)) { 2030 dev_err(&pdev->dev, "DMA engine request failed\n"); 2031 err = PTR_ERR(info->dma); 2032 goto return_error; 2033 } else { 2034 struct dma_slave_config cfg; 2035 2036 memset(&cfg, 0, sizeof(cfg)); 2037 cfg.src_addr = info->phys_base; 2038 cfg.dst_addr = info->phys_base; 2039 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2040 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2041 cfg.src_maxburst = 16; 2042 cfg.dst_maxburst = 16; 2043 err = dmaengine_slave_config(info->dma, &cfg); 2044 if (err) { 2045 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", 2046 err); 2047 goto return_error; 2048 } 2049 nand_chip->read_buf = omap_read_buf_dma_pref; 2050 nand_chip->write_buf = omap_write_buf_dma_pref; 2051 } 2052 break; 2053 2054 case NAND_OMAP_PREFETCH_IRQ: 2055 info->gpmc_irq_fifo = platform_get_irq(pdev, 0); 2056 if (info->gpmc_irq_fifo <= 0) { 2057 dev_err(&pdev->dev, "error getting fifo irq\n"); 2058 err = -ENODEV; 2059 goto return_error; 2060 } 2061 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo, 2062 omap_nand_irq, IRQF_SHARED, 2063 "gpmc-nand-fifo", info); 2064 if (err) { 2065 dev_err(&pdev->dev, "requesting irq(%d) error:%d", 2066 info->gpmc_irq_fifo, err); 2067 info->gpmc_irq_fifo = 0; 2068 goto return_error; 2069 } 2070 2071 info->gpmc_irq_count = platform_get_irq(pdev, 1); 2072 if (info->gpmc_irq_count <= 0) { 2073 dev_err(&pdev->dev, "error getting count irq\n"); 2074 err = -ENODEV; 2075 goto return_error; 2076 } 2077 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count, 2078 omap_nand_irq, IRQF_SHARED, 2079 "gpmc-nand-count", info); 2080 if (err) { 2081 dev_err(&pdev->dev, "requesting irq(%d) error:%d", 2082 info->gpmc_irq_count, err); 2083 info->gpmc_irq_count = 0; 2084 goto return_error; 2085 } 2086 2087 nand_chip->read_buf = omap_read_buf_irq_pref; 2088 nand_chip->write_buf = omap_write_buf_irq_pref; 2089 2090 break; 2091 2092 default: 2093 dev_err(&pdev->dev, 2094 "xfer_type(%d) not supported!\n", info->xfer_type); 2095 err = -EINVAL; 2096 goto return_error; 2097 } 2098 2099 if (!omap2_nand_ecc_check(info)) { 2100 err = -EINVAL; 2101 goto return_error; 2102 } 2103 2104 /* 2105 * Bail out earlier to let NAND_ECC_SOFT code create its own 2106 * ooblayout instead of using ours. 2107 */ 2108 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) { 2109 nand_chip->ecc.mode = NAND_ECC_SOFT; 2110 nand_chip->ecc.algo = NAND_ECC_HAMMING; 2111 goto scan_tail; 2112 } 2113 2114 /* populate MTD interface based on ECC scheme */ 2115 switch (info->ecc_opt) { 2116 case OMAP_ECC_HAM1_CODE_HW: 2117 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); 2118 nand_chip->ecc.mode = NAND_ECC_HW; 2119 nand_chip->ecc.bytes = 3; 2120 nand_chip->ecc.size = 512; 2121 nand_chip->ecc.strength = 1; 2122 nand_chip->ecc.calculate = omap_calculate_ecc; 2123 nand_chip->ecc.hwctl = omap_enable_hwecc; 2124 nand_chip->ecc.correct = omap_correct_data; 2125 mtd_set_ooblayout(mtd, &omap_ooblayout_ops); 2126 oobbytes_per_step = nand_chip->ecc.bytes; 2127 2128 if (!(nand_chip->options & NAND_BUSWIDTH_16)) 2129 min_oobbytes = 1; 2130 2131 break; 2132 2133 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: 2134 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); 2135 nand_chip->ecc.mode = NAND_ECC_HW; 2136 nand_chip->ecc.size = 512; 2137 nand_chip->ecc.bytes = 7; 2138 nand_chip->ecc.strength = 4; 2139 nand_chip->ecc.hwctl = omap_enable_hwecc_bch; 2140 nand_chip->ecc.correct = nand_bch_correct_data; 2141 nand_chip->ecc.calculate = omap_calculate_ecc_bch_sw; 2142 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops); 2143 /* Reserve one byte for the OMAP marker */ 2144 oobbytes_per_step = nand_chip->ecc.bytes + 1; 2145 /* software bch library is used for locating errors */ 2146 nand_chip->ecc.priv = nand_bch_init(mtd); 2147 if (!nand_chip->ecc.priv) { 2148 dev_err(&info->pdev->dev, "unable to use BCH library\n"); 2149 err = -EINVAL; 2150 goto return_error; 2151 } 2152 break; 2153 2154 case OMAP_ECC_BCH4_CODE_HW: 2155 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); 2156 nand_chip->ecc.mode = NAND_ECC_HW; 2157 nand_chip->ecc.size = 512; 2158 /* 14th bit is kept reserved for ROM-code compatibility */ 2159 nand_chip->ecc.bytes = 7 + 1; 2160 nand_chip->ecc.strength = 4; 2161 nand_chip->ecc.hwctl = omap_enable_hwecc_bch; 2162 nand_chip->ecc.correct = omap_elm_correct_data; 2163 nand_chip->ecc.read_page = omap_read_page_bch; 2164 nand_chip->ecc.write_page = omap_write_page_bch; 2165 nand_chip->ecc.write_subpage = omap_write_subpage_bch; 2166 mtd_set_ooblayout(mtd, &omap_ooblayout_ops); 2167 oobbytes_per_step = nand_chip->ecc.bytes; 2168 2169 err = elm_config(info->elm_dev, BCH4_ECC, 2170 mtd->writesize / nand_chip->ecc.size, 2171 nand_chip->ecc.size, nand_chip->ecc.bytes); 2172 if (err < 0) 2173 goto return_error; 2174 break; 2175 2176 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: 2177 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); 2178 nand_chip->ecc.mode = NAND_ECC_HW; 2179 nand_chip->ecc.size = 512; 2180 nand_chip->ecc.bytes = 13; 2181 nand_chip->ecc.strength = 8; 2182 nand_chip->ecc.hwctl = omap_enable_hwecc_bch; 2183 nand_chip->ecc.correct = nand_bch_correct_data; 2184 nand_chip->ecc.calculate = omap_calculate_ecc_bch_sw; 2185 mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops); 2186 /* Reserve one byte for the OMAP marker */ 2187 oobbytes_per_step = nand_chip->ecc.bytes + 1; 2188 /* software bch library is used for locating errors */ 2189 nand_chip->ecc.priv = nand_bch_init(mtd); 2190 if (!nand_chip->ecc.priv) { 2191 dev_err(&info->pdev->dev, "unable to use BCH library\n"); 2192 err = -EINVAL; 2193 goto return_error; 2194 } 2195 break; 2196 2197 case OMAP_ECC_BCH8_CODE_HW: 2198 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); 2199 nand_chip->ecc.mode = NAND_ECC_HW; 2200 nand_chip->ecc.size = 512; 2201 /* 14th bit is kept reserved for ROM-code compatibility */ 2202 nand_chip->ecc.bytes = 13 + 1; 2203 nand_chip->ecc.strength = 8; 2204 nand_chip->ecc.hwctl = omap_enable_hwecc_bch; 2205 nand_chip->ecc.correct = omap_elm_correct_data; 2206 nand_chip->ecc.read_page = omap_read_page_bch; 2207 nand_chip->ecc.write_page = omap_write_page_bch; 2208 nand_chip->ecc.write_subpage = omap_write_subpage_bch; 2209 mtd_set_ooblayout(mtd, &omap_ooblayout_ops); 2210 oobbytes_per_step = nand_chip->ecc.bytes; 2211 2212 err = elm_config(info->elm_dev, BCH8_ECC, 2213 mtd->writesize / nand_chip->ecc.size, 2214 nand_chip->ecc.size, nand_chip->ecc.bytes); 2215 if (err < 0) 2216 goto return_error; 2217 2218 break; 2219 2220 case OMAP_ECC_BCH16_CODE_HW: 2221 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); 2222 nand_chip->ecc.mode = NAND_ECC_HW; 2223 nand_chip->ecc.size = 512; 2224 nand_chip->ecc.bytes = 26; 2225 nand_chip->ecc.strength = 16; 2226 nand_chip->ecc.hwctl = omap_enable_hwecc_bch; 2227 nand_chip->ecc.correct = omap_elm_correct_data; 2228 nand_chip->ecc.read_page = omap_read_page_bch; 2229 nand_chip->ecc.write_page = omap_write_page_bch; 2230 nand_chip->ecc.write_subpage = omap_write_subpage_bch; 2231 mtd_set_ooblayout(mtd, &omap_ooblayout_ops); 2232 oobbytes_per_step = nand_chip->ecc.bytes; 2233 2234 err = elm_config(info->elm_dev, BCH16_ECC, 2235 mtd->writesize / nand_chip->ecc.size, 2236 nand_chip->ecc.size, nand_chip->ecc.bytes); 2237 if (err < 0) 2238 goto return_error; 2239 2240 break; 2241 default: 2242 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n"); 2243 err = -EINVAL; 2244 goto return_error; 2245 } 2246 2247 /* check if NAND device's OOB is enough to store ECC signatures */ 2248 min_oobbytes += (oobbytes_per_step * 2249 (mtd->writesize / nand_chip->ecc.size)); 2250 if (mtd->oobsize < min_oobbytes) { 2251 dev_err(&info->pdev->dev, 2252 "not enough OOB bytes required = %d, available=%d\n", 2253 min_oobbytes, mtd->oobsize); 2254 err = -EINVAL; 2255 goto return_error; 2256 } 2257 2258 scan_tail: 2259 /* second phase scan */ 2260 err = nand_scan_tail(mtd); 2261 if (err) 2262 goto return_error; 2263 2264 err = mtd_device_register(mtd, NULL, 0); 2265 if (err) 2266 goto cleanup_nand; 2267 2268 platform_set_drvdata(pdev, mtd); 2269 2270 return 0; 2271 2272 cleanup_nand: 2273 nand_cleanup(nand_chip); 2274 2275 return_error: 2276 if (!IS_ERR_OR_NULL(info->dma)) 2277 dma_release_channel(info->dma); 2278 if (nand_chip->ecc.priv) { 2279 nand_bch_free(nand_chip->ecc.priv); 2280 nand_chip->ecc.priv = NULL; 2281 } 2282 return err; 2283 } 2284 2285 static int omap_nand_remove(struct platform_device *pdev) 2286 { 2287 struct mtd_info *mtd = platform_get_drvdata(pdev); 2288 struct nand_chip *nand_chip = mtd_to_nand(mtd); 2289 struct omap_nand_info *info = mtd_to_omap(mtd); 2290 if (nand_chip->ecc.priv) { 2291 nand_bch_free(nand_chip->ecc.priv); 2292 nand_chip->ecc.priv = NULL; 2293 } 2294 if (info->dma) 2295 dma_release_channel(info->dma); 2296 nand_release(mtd); 2297 return 0; 2298 } 2299 2300 static const struct of_device_id omap_nand_ids[] = { 2301 { .compatible = "ti,omap2-nand", }, 2302 {}, 2303 }; 2304 MODULE_DEVICE_TABLE(of, omap_nand_ids); 2305 2306 static struct platform_driver omap_nand_driver = { 2307 .probe = omap_nand_probe, 2308 .remove = omap_nand_remove, 2309 .driver = { 2310 .name = DRIVER_NAME, 2311 .of_match_table = of_match_ptr(omap_nand_ids), 2312 }, 2313 }; 2314 2315 module_platform_driver(omap_nand_driver); 2316 2317 MODULE_ALIAS("platform:" DRIVER_NAME); 2318 MODULE_LICENSE("GPL"); 2319 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); 2320