1 /* 2 * Overview: 3 * Platform independent driver for NDFC (NanD Flash Controller) 4 * integrated into EP440 cores 5 * 6 * Ported to an OF platform driver by Sean MacLennan 7 * 8 * The NDFC supports multiple chips, but this driver only supports a 9 * single chip since I do not have access to any boards with 10 * multiple chips. 11 * 12 * Author: Thomas Gleixner 13 * 14 * Copyright 2006 IBM 15 * Copyright 2008 PIKA Technologies 16 * Sean MacLennan <smaclennan@pikatech.com> 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 */ 24 #include <linux/module.h> 25 #include <linux/mtd/rawnand.h> 26 #include <linux/mtd/nand_ecc.h> 27 #include <linux/mtd/partitions.h> 28 #include <linux/mtd/ndfc.h> 29 #include <linux/slab.h> 30 #include <linux/mtd/mtd.h> 31 #include <linux/of_address.h> 32 #include <linux/of_platform.h> 33 #include <asm/io.h> 34 35 #define NDFC_MAX_CS 4 36 37 struct ndfc_controller { 38 struct platform_device *ofdev; 39 void __iomem *ndfcbase; 40 struct nand_chip chip; 41 int chip_select; 42 struct nand_controller ndfc_control; 43 }; 44 45 static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS]; 46 47 static void ndfc_select_chip(struct nand_chip *nchip, int chip) 48 { 49 uint32_t ccr; 50 struct ndfc_controller *ndfc = nand_get_controller_data(nchip); 51 52 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); 53 if (chip >= 0) { 54 ccr &= ~NDFC_CCR_BS_MASK; 55 ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); 56 } else 57 ccr |= NDFC_CCR_RESET_CE; 58 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); 59 } 60 61 static void ndfc_hwcontrol(struct nand_chip *chip, int cmd, unsigned int ctrl) 62 { 63 struct ndfc_controller *ndfc = nand_get_controller_data(chip); 64 65 if (cmd == NAND_CMD_NONE) 66 return; 67 68 if (ctrl & NAND_CLE) 69 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); 70 else 71 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); 72 } 73 74 static int ndfc_ready(struct nand_chip *chip) 75 { 76 struct ndfc_controller *ndfc = nand_get_controller_data(chip); 77 78 return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; 79 } 80 81 static void ndfc_enable_hwecc(struct nand_chip *chip, int mode) 82 { 83 uint32_t ccr; 84 struct ndfc_controller *ndfc = nand_get_controller_data(chip); 85 86 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); 87 ccr |= NDFC_CCR_RESET_ECC; 88 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); 89 wmb(); 90 } 91 92 static int ndfc_calculate_ecc(struct nand_chip *chip, 93 const u_char *dat, u_char *ecc_code) 94 { 95 struct ndfc_controller *ndfc = nand_get_controller_data(chip); 96 uint32_t ecc; 97 uint8_t *p = (uint8_t *)&ecc; 98 99 wmb(); 100 ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); 101 /* The NDFC uses Smart Media (SMC) bytes order */ 102 ecc_code[0] = p[1]; 103 ecc_code[1] = p[2]; 104 ecc_code[2] = p[3]; 105 106 return 0; 107 } 108 109 /* 110 * Speedups for buffer read/write/verify 111 * 112 * NDFC allows 32bit read/write of data. So we can speed up the buffer 113 * functions. No further checking, as nand_base will always read/write 114 * page aligned. 115 */ 116 static void ndfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 117 { 118 struct ndfc_controller *ndfc = nand_get_controller_data(chip); 119 uint32_t *p = (uint32_t *) buf; 120 121 for(;len > 0; len -= 4) 122 *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); 123 } 124 125 static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) 126 { 127 struct ndfc_controller *ndfc = nand_get_controller_data(chip); 128 uint32_t *p = (uint32_t *) buf; 129 130 for(;len > 0; len -= 4) 131 out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); 132 } 133 134 /* 135 * Initialize chip structure 136 */ 137 static int ndfc_chip_init(struct ndfc_controller *ndfc, 138 struct device_node *node) 139 { 140 struct device_node *flash_np; 141 struct nand_chip *chip = &ndfc->chip; 142 struct mtd_info *mtd = nand_to_mtd(chip); 143 int ret; 144 145 chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; 146 chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; 147 chip->legacy.cmd_ctrl = ndfc_hwcontrol; 148 chip->legacy.dev_ready = ndfc_ready; 149 chip->legacy.select_chip = ndfc_select_chip; 150 chip->legacy.chip_delay = 50; 151 chip->controller = &ndfc->ndfc_control; 152 chip->legacy.read_buf = ndfc_read_buf; 153 chip->legacy.write_buf = ndfc_write_buf; 154 chip->ecc.correct = nand_correct_data; 155 chip->ecc.hwctl = ndfc_enable_hwecc; 156 chip->ecc.calculate = ndfc_calculate_ecc; 157 chip->ecc.mode = NAND_ECC_HW; 158 chip->ecc.size = 256; 159 chip->ecc.bytes = 3; 160 chip->ecc.strength = 1; 161 nand_set_controller_data(chip, ndfc); 162 163 mtd->dev.parent = &ndfc->ofdev->dev; 164 165 flash_np = of_get_next_child(node, NULL); 166 if (!flash_np) 167 return -ENODEV; 168 nand_set_flash_node(chip, flash_np); 169 170 mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev), 171 flash_np); 172 if (!mtd->name) { 173 ret = -ENOMEM; 174 goto err; 175 } 176 177 ret = nand_scan(chip, 1); 178 if (ret) 179 goto err; 180 181 ret = mtd_device_register(mtd, NULL, 0); 182 183 err: 184 of_node_put(flash_np); 185 if (ret) 186 kfree(mtd->name); 187 return ret; 188 } 189 190 static int ndfc_probe(struct platform_device *ofdev) 191 { 192 struct ndfc_controller *ndfc; 193 const __be32 *reg; 194 u32 ccr; 195 u32 cs; 196 int err, len; 197 198 /* Read the reg property to get the chip select */ 199 reg = of_get_property(ofdev->dev.of_node, "reg", &len); 200 if (reg == NULL || len != 12) { 201 dev_err(&ofdev->dev, "unable read reg property (%d)\n", len); 202 return -ENOENT; 203 } 204 205 cs = be32_to_cpu(reg[0]); 206 if (cs >= NDFC_MAX_CS) { 207 dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); 208 return -EINVAL; 209 } 210 211 ndfc = &ndfc_ctrl[cs]; 212 ndfc->chip_select = cs; 213 214 nand_controller_init(&ndfc->ndfc_control); 215 ndfc->ofdev = ofdev; 216 dev_set_drvdata(&ofdev->dev, ndfc); 217 218 ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); 219 if (!ndfc->ndfcbase) { 220 dev_err(&ofdev->dev, "failed to get memory\n"); 221 return -EIO; 222 } 223 224 ccr = NDFC_CCR_BS(ndfc->chip_select); 225 226 /* It is ok if ccr does not exist - just default to 0 */ 227 reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); 228 if (reg) 229 ccr |= be32_to_cpup(reg); 230 231 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); 232 233 /* Set the bank settings if given */ 234 reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); 235 if (reg) { 236 int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); 237 out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); 238 } 239 240 err = ndfc_chip_init(ndfc, ofdev->dev.of_node); 241 if (err) { 242 iounmap(ndfc->ndfcbase); 243 return err; 244 } 245 246 return 0; 247 } 248 249 static int ndfc_remove(struct platform_device *ofdev) 250 { 251 struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); 252 struct mtd_info *mtd = nand_to_mtd(&ndfc->chip); 253 254 nand_release(&ndfc->chip); 255 kfree(mtd->name); 256 257 return 0; 258 } 259 260 static const struct of_device_id ndfc_match[] = { 261 { .compatible = "ibm,ndfc", }, 262 {} 263 }; 264 MODULE_DEVICE_TABLE(of, ndfc_match); 265 266 static struct platform_driver ndfc_driver = { 267 .driver = { 268 .name = "ndfc", 269 .of_match_table = ndfc_match, 270 }, 271 .probe = ndfc_probe, 272 .remove = ndfc_remove, 273 }; 274 275 module_platform_driver(ndfc_driver); 276 277 MODULE_LICENSE("GPL"); 278 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); 279 MODULE_DESCRIPTION("OF Platform driver for NDFC"); 280