1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2017 Free Electrons
4  * Copyright (C) 2017 NextThing Co
5  *
6  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
7  */
8 
9 #include "internals.h"
10 
11 /* Bit for detecting BENAND */
12 #define TOSHIBA_NAND_ID4_IS_BENAND		BIT(7)
13 
14 /* Recommended to rewrite for BENAND */
15 #define TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED	BIT(3)
16 
17 /* ECC Status Read Command for BENAND */
18 #define TOSHIBA_NAND_CMD_ECC_STATUS_READ	0x7A
19 
20 /* ECC Status Mask for BENAND */
21 #define TOSHIBA_NAND_ECC_STATUS_MASK		0x0F
22 
23 /* Uncorrectable Error for BENAND */
24 #define TOSHIBA_NAND_ECC_STATUS_UNCORR		0x0F
25 
26 /* Max ECC Steps for BENAND */
27 #define TOSHIBA_NAND_MAX_ECC_STEPS		8
28 
29 static int toshiba_nand_benand_read_eccstatus_op(struct nand_chip *chip,
30 						 u8 *buf)
31 {
32 	u8 *ecc_status = buf;
33 
34 	if (nand_has_exec_op(chip)) {
35 		const struct nand_sdr_timings *sdr =
36 			nand_get_sdr_timings(nand_get_interface_config(chip));
37 		struct nand_op_instr instrs[] = {
38 			NAND_OP_CMD(TOSHIBA_NAND_CMD_ECC_STATUS_READ,
39 				    PSEC_TO_NSEC(sdr->tADL_min)),
40 			NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0),
41 		};
42 		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
43 
44 		return nand_exec_op(chip, &op);
45 	}
46 
47 	return -ENOTSUPP;
48 }
49 
50 static int toshiba_nand_benand_eccstatus(struct nand_chip *chip)
51 {
52 	struct mtd_info *mtd = nand_to_mtd(chip);
53 	int ret;
54 	unsigned int max_bitflips = 0;
55 	u8 status, ecc_status[TOSHIBA_NAND_MAX_ECC_STEPS];
56 
57 	/* Check Status */
58 	ret = toshiba_nand_benand_read_eccstatus_op(chip, ecc_status);
59 	if (!ret) {
60 		unsigned int i, bitflips = 0;
61 
62 		for (i = 0; i < chip->ecc.steps; i++) {
63 			bitflips = ecc_status[i] & TOSHIBA_NAND_ECC_STATUS_MASK;
64 			if (bitflips == TOSHIBA_NAND_ECC_STATUS_UNCORR) {
65 				mtd->ecc_stats.failed++;
66 			} else {
67 				mtd->ecc_stats.corrected += bitflips;
68 				max_bitflips = max(max_bitflips, bitflips);
69 			}
70 		}
71 
72 		return max_bitflips;
73 	}
74 
75 	/*
76 	 * Fallback to regular status check if
77 	 * toshiba_nand_benand_read_eccstatus_op() failed.
78 	 */
79 	ret = nand_status_op(chip, &status);
80 	if (ret)
81 		return ret;
82 
83 	if (status & NAND_STATUS_FAIL) {
84 		/* uncorrected */
85 		mtd->ecc_stats.failed++;
86 	} else if (status & TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED) {
87 		/* corrected */
88 		max_bitflips = mtd->bitflip_threshold;
89 		mtd->ecc_stats.corrected += max_bitflips;
90 	}
91 
92 	return max_bitflips;
93 }
94 
95 static int
96 toshiba_nand_read_page_benand(struct nand_chip *chip, uint8_t *buf,
97 			      int oob_required, int page)
98 {
99 	int ret;
100 
101 	ret = nand_read_page_raw(chip, buf, oob_required, page);
102 	if (ret)
103 		return ret;
104 
105 	return toshiba_nand_benand_eccstatus(chip);
106 }
107 
108 static int
109 toshiba_nand_read_subpage_benand(struct nand_chip *chip, uint32_t data_offs,
110 				 uint32_t readlen, uint8_t *bufpoi, int page)
111 {
112 	int ret;
113 
114 	ret = nand_read_page_op(chip, page, data_offs,
115 				bufpoi + data_offs, readlen);
116 	if (ret)
117 		return ret;
118 
119 	return toshiba_nand_benand_eccstatus(chip);
120 }
121 
122 static void toshiba_nand_benand_init(struct nand_chip *chip)
123 {
124 	struct mtd_info *mtd = nand_to_mtd(chip);
125 
126 	/*
127 	 * On BENAND, the entire OOB region can be used by the MTD user.
128 	 * The calculated ECC bytes are stored into other isolated
129 	 * area which is not accessible to users.
130 	 * This is why chip->ecc.bytes = 0.
131 	 */
132 	chip->ecc.bytes = 0;
133 	chip->ecc.size = 512;
134 	chip->ecc.strength = 8;
135 	chip->ecc.read_page = toshiba_nand_read_page_benand;
136 	chip->ecc.read_subpage = toshiba_nand_read_subpage_benand;
137 	chip->ecc.write_page = nand_write_page_raw;
138 	chip->ecc.read_page_raw = nand_read_page_raw_notsupp;
139 	chip->ecc.write_page_raw = nand_write_page_raw_notsupp;
140 
141 	chip->options |= NAND_SUBPAGE_READ;
142 
143 	mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
144 }
145 
146 static void toshiba_nand_decode_id(struct nand_chip *chip)
147 {
148 	struct mtd_info *mtd = nand_to_mtd(chip);
149 	struct nand_memory_organization *memorg;
150 
151 	memorg = nanddev_get_memorg(&chip->base);
152 
153 	nand_decode_ext_id(chip);
154 
155 	/*
156 	 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
157 	 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
158 	 * follows:
159 	 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
160 	 *                         110b -> 24nm
161 	 * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
162 	 */
163 	if (chip->id.len >= 6 && nand_is_slc(chip) &&
164 	    (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
165 	    !(chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND) /* !BENAND */) {
166 		memorg->oobsize = 32 * memorg->pagesize >> 9;
167 		mtd->oobsize = memorg->oobsize;
168 	}
169 
170 	/*
171 	 * Extract ECC requirements from 6th id byte.
172 	 * For Toshiba SLC, ecc requrements are as follows:
173 	 *  - 43nm: 1 bit ECC for each 512Byte is required.
174 	 *  - 32nm: 4 bit ECC for each 512Byte is required.
175 	 *  - 24nm: 8 bit ECC for each 512Byte is required.
176 	 */
177 	if (chip->id.len >= 6 && nand_is_slc(chip)) {
178 		chip->base.eccreq.step_size = 512;
179 		switch (chip->id.data[5] & 0x7) {
180 		case 0x4:
181 			chip->base.eccreq.strength = 1;
182 			break;
183 		case 0x5:
184 			chip->base.eccreq.strength = 4;
185 			break;
186 		case 0x6:
187 			chip->base.eccreq.strength = 8;
188 			break;
189 		default:
190 			WARN(1, "Could not get ECC info");
191 			chip->base.eccreq.step_size = 0;
192 			break;
193 		}
194 	}
195 }
196 
197 static int
198 tc58teg5dclta00_choose_interface_config(struct nand_chip *chip,
199 					struct nand_interface_config *iface)
200 {
201 	onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 5);
202 
203 	return nand_choose_best_sdr_timings(chip, iface, NULL);
204 }
205 
206 static int
207 tc58nvg0s3e_choose_interface_config(struct nand_chip *chip,
208 				    struct nand_interface_config *iface)
209 {
210 	onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 2);
211 
212 	return nand_choose_best_sdr_timings(chip, iface, NULL);
213 }
214 
215 static int
216 th58nvg2s3hbai4_choose_interface_config(struct nand_chip *chip,
217 					struct nand_interface_config *iface)
218 {
219 	struct nand_sdr_timings *sdr = &iface->timings.sdr;
220 
221 	/* Start with timings from the closest timing mode, mode 4. */
222 	onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
223 
224 	/* Patch timings that differ from mode 4. */
225 	sdr->tALS_min = 12000;
226 	sdr->tCHZ_max = 20000;
227 	sdr->tCLS_min = 12000;
228 	sdr->tCOH_min = 0;
229 	sdr->tDS_min = 12000;
230 	sdr->tRHOH_min = 25000;
231 	sdr->tRHW_min = 30000;
232 	sdr->tRHZ_max = 60000;
233 	sdr->tWHR_min = 60000;
234 
235 	/* Patch timings not part of onfi timing mode. */
236 	sdr->tPROG_max = 700000000;
237 	sdr->tBERS_max = 5000000000;
238 
239 	return nand_choose_best_sdr_timings(chip, iface, sdr);
240 }
241 
242 static int tc58teg5dclta00_init(struct nand_chip *chip)
243 {
244 	struct mtd_info *mtd = nand_to_mtd(chip);
245 
246 	chip->ops.choose_interface_config =
247 		&tc58teg5dclta00_choose_interface_config;
248 	chip->options |= NAND_NEED_SCRAMBLING;
249 	mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme);
250 
251 	return 0;
252 }
253 
254 static int tc58nvg0s3e_init(struct nand_chip *chip)
255 {
256 	chip->ops.choose_interface_config =
257 		&tc58nvg0s3e_choose_interface_config;
258 
259 	return 0;
260 }
261 
262 static int th58nvg2s3hbai4_init(struct nand_chip *chip)
263 {
264 	chip->ops.choose_interface_config =
265 		&th58nvg2s3hbai4_choose_interface_config;
266 
267 	return 0;
268 }
269 
270 static int toshiba_nand_init(struct nand_chip *chip)
271 {
272 	if (nand_is_slc(chip))
273 		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
274 
275 	/* Check that chip is BENAND and ECC mode is on-die */
276 	if (nand_is_slc(chip) && chip->ecc.mode == NAND_ECC_ON_DIE &&
277 	    chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND)
278 		toshiba_nand_benand_init(chip);
279 
280 	if (!strcmp("TC58TEG5DCLTA00", chip->parameters.model))
281 		tc58teg5dclta00_init(chip);
282 	if (!strncmp("TC58NVG0S3E", chip->parameters.model,
283 		     sizeof("TC58NVG0S3E") - 1))
284 		tc58nvg0s3e_init(chip);
285 	if (!strncmp("TH58NVG2S3HBAI4", chip->parameters.model,
286 		     sizeof("TH58NVG2S3HBAI4") - 1))
287 		th58nvg2s3hbai4_init(chip);
288 
289 	return 0;
290 }
291 
292 const struct nand_manufacturer_ops toshiba_nand_manuf_ops = {
293 	.detect = toshiba_nand_decode_id,
294 	.init = toshiba_nand_init,
295 };
296