1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 4 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 5 * 6 * Credits: 7 * David Woodhouse for adding multichip support 8 * 9 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 10 * rework for 2K page size chips 11 * 12 * This file contains all legacy helpers/code that should be removed 13 * at some point. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/nmi.h> 19 20 #include "internals.h" 21 22 /** 23 * nand_read_byte - [DEFAULT] read one byte from the chip 24 * @chip: NAND chip object 25 * 26 * Default read function for 8bit buswidth 27 */ 28 static uint8_t nand_read_byte(struct nand_chip *chip) 29 { 30 return readb(chip->legacy.IO_ADDR_R); 31 } 32 33 /** 34 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip 35 * @chip: NAND chip object 36 * 37 * Default read function for 16bit buswidth with endianness conversion. 38 * 39 */ 40 static uint8_t nand_read_byte16(struct nand_chip *chip) 41 { 42 return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R)); 43 } 44 45 /** 46 * nand_select_chip - [DEFAULT] control CE line 47 * @chip: NAND chip object 48 * @chipnr: chipnumber to select, -1 for deselect 49 * 50 * Default select function for 1 chip devices. 51 */ 52 static void nand_select_chip(struct nand_chip *chip, int chipnr) 53 { 54 switch (chipnr) { 55 case -1: 56 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 57 0 | NAND_CTRL_CHANGE); 58 break; 59 case 0: 60 break; 61 62 default: 63 BUG(); 64 } 65 } 66 67 /** 68 * nand_write_byte - [DEFAULT] write single byte to chip 69 * @chip: NAND chip object 70 * @byte: value to write 71 * 72 * Default function to write a byte to I/O[7:0] 73 */ 74 static void nand_write_byte(struct nand_chip *chip, uint8_t byte) 75 { 76 chip->legacy.write_buf(chip, &byte, 1); 77 } 78 79 /** 80 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 81 * @chip: NAND chip object 82 * @byte: value to write 83 * 84 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. 85 */ 86 static void nand_write_byte16(struct nand_chip *chip, uint8_t byte) 87 { 88 uint16_t word = byte; 89 90 /* 91 * It's not entirely clear what should happen to I/O[15:8] when writing 92 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: 93 * 94 * When the host supports a 16-bit bus width, only data is 95 * transferred at the 16-bit width. All address and command line 96 * transfers shall use only the lower 8-bits of the data bus. During 97 * command transfers, the host may place any value on the upper 98 * 8-bits of the data bus. During address transfers, the host shall 99 * set the upper 8-bits of the data bus to 00h. 100 * 101 * One user of the write_byte callback is nand_set_features. The 102 * four parameters are specified to be written to I/O[7:0], but this is 103 * neither an address nor a command transfer. Let's assume a 0 on the 104 * upper I/O lines is OK. 105 */ 106 chip->legacy.write_buf(chip, (uint8_t *)&word, 2); 107 } 108 109 /** 110 * nand_write_buf - [DEFAULT] write buffer to chip 111 * @chip: NAND chip object 112 * @buf: data buffer 113 * @len: number of bytes to write 114 * 115 * Default write function for 8bit buswidth. 116 */ 117 static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) 118 { 119 iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len); 120 } 121 122 /** 123 * nand_read_buf - [DEFAULT] read chip data into buffer 124 * @chip: NAND chip object 125 * @buf: buffer to store date 126 * @len: number of bytes to read 127 * 128 * Default read function for 8bit buswidth. 129 */ 130 static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 131 { 132 ioread8_rep(chip->legacy.IO_ADDR_R, buf, len); 133 } 134 135 /** 136 * nand_write_buf16 - [DEFAULT] write buffer to chip 137 * @chip: NAND chip object 138 * @buf: data buffer 139 * @len: number of bytes to write 140 * 141 * Default write function for 16bit buswidth. 142 */ 143 static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf, 144 int len) 145 { 146 u16 *p = (u16 *) buf; 147 148 iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1); 149 } 150 151 /** 152 * nand_read_buf16 - [DEFAULT] read chip data into buffer 153 * @chip: NAND chip object 154 * @buf: buffer to store date 155 * @len: number of bytes to read 156 * 157 * Default read function for 16bit buswidth. 158 */ 159 static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len) 160 { 161 u16 *p = (u16 *) buf; 162 163 ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1); 164 } 165 166 /** 167 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. 168 * @mtd: MTD device structure 169 * @timeo: Timeout 170 * 171 * Helper function for nand_wait_ready used when needing to wait in interrupt 172 * context. 173 */ 174 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) 175 { 176 struct nand_chip *chip = mtd_to_nand(mtd); 177 int i; 178 179 /* Wait for the device to get ready */ 180 for (i = 0; i < timeo; i++) { 181 if (chip->legacy.dev_ready(chip)) 182 break; 183 touch_softlockup_watchdog(); 184 mdelay(1); 185 } 186 } 187 188 /** 189 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. 190 * @chip: NAND chip object 191 * 192 * Wait for the ready pin after a command, and warn if a timeout occurs. 193 */ 194 void nand_wait_ready(struct nand_chip *chip) 195 { 196 struct mtd_info *mtd = nand_to_mtd(chip); 197 unsigned long timeo = 400; 198 199 if (in_interrupt() || oops_in_progress) 200 return panic_nand_wait_ready(mtd, timeo); 201 202 /* Wait until command is processed or timeout occurs */ 203 timeo = jiffies + msecs_to_jiffies(timeo); 204 do { 205 if (chip->legacy.dev_ready(chip)) 206 return; 207 cond_resched(); 208 } while (time_before(jiffies, timeo)); 209 210 if (!chip->legacy.dev_ready(chip)) 211 pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); 212 } 213 EXPORT_SYMBOL_GPL(nand_wait_ready); 214 215 /** 216 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. 217 * @mtd: MTD device structure 218 * @timeo: Timeout in ms 219 * 220 * Wait for status ready (i.e. command done) or timeout. 221 */ 222 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) 223 { 224 register struct nand_chip *chip = mtd_to_nand(mtd); 225 int ret; 226 227 timeo = jiffies + msecs_to_jiffies(timeo); 228 do { 229 u8 status; 230 231 ret = nand_read_data_op(chip, &status, sizeof(status), true); 232 if (ret) 233 return; 234 235 if (status & NAND_STATUS_READY) 236 break; 237 touch_softlockup_watchdog(); 238 } while (time_before(jiffies, timeo)); 239 }; 240 241 /** 242 * nand_command - [DEFAULT] Send command to NAND device 243 * @chip: NAND chip object 244 * @command: the command to be sent 245 * @column: the column address for this command, -1 if none 246 * @page_addr: the page address for this command, -1 if none 247 * 248 * Send command to NAND device. This function is used for small page devices 249 * (512 Bytes per page). 250 */ 251 static void nand_command(struct nand_chip *chip, unsigned int command, 252 int column, int page_addr) 253 { 254 struct mtd_info *mtd = nand_to_mtd(chip); 255 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; 256 257 /* Write out the command to the device */ 258 if (command == NAND_CMD_SEQIN) { 259 int readcmd; 260 261 if (column >= mtd->writesize) { 262 /* OOB area */ 263 column -= mtd->writesize; 264 readcmd = NAND_CMD_READOOB; 265 } else if (column < 256) { 266 /* First 256 bytes --> READ0 */ 267 readcmd = NAND_CMD_READ0; 268 } else { 269 column -= 256; 270 readcmd = NAND_CMD_READ1; 271 } 272 chip->legacy.cmd_ctrl(chip, readcmd, ctrl); 273 ctrl &= ~NAND_CTRL_CHANGE; 274 } 275 if (command != NAND_CMD_NONE) 276 chip->legacy.cmd_ctrl(chip, command, ctrl); 277 278 /* Address cycle, when necessary */ 279 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; 280 /* Serially input address */ 281 if (column != -1) { 282 /* Adjust columns for 16 bit buswidth */ 283 if (chip->options & NAND_BUSWIDTH_16 && 284 !nand_opcode_8bits(command)) 285 column >>= 1; 286 chip->legacy.cmd_ctrl(chip, column, ctrl); 287 ctrl &= ~NAND_CTRL_CHANGE; 288 } 289 if (page_addr != -1) { 290 chip->legacy.cmd_ctrl(chip, page_addr, ctrl); 291 ctrl &= ~NAND_CTRL_CHANGE; 292 chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl); 293 if (chip->options & NAND_ROW_ADDR_3) 294 chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl); 295 } 296 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 297 NAND_NCE | NAND_CTRL_CHANGE); 298 299 /* 300 * Program and erase have their own busy handlers status and sequential 301 * in needs no delay 302 */ 303 switch (command) { 304 305 case NAND_CMD_NONE: 306 case NAND_CMD_PAGEPROG: 307 case NAND_CMD_ERASE1: 308 case NAND_CMD_ERASE2: 309 case NAND_CMD_SEQIN: 310 case NAND_CMD_STATUS: 311 case NAND_CMD_READID: 312 case NAND_CMD_SET_FEATURES: 313 return; 314 315 case NAND_CMD_RESET: 316 if (chip->legacy.dev_ready) 317 break; 318 udelay(chip->legacy.chip_delay); 319 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS, 320 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 321 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 322 NAND_NCE | NAND_CTRL_CHANGE); 323 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ 324 nand_wait_status_ready(mtd, 250); 325 return; 326 327 /* This applies to read commands */ 328 case NAND_CMD_READ0: 329 /* 330 * READ0 is sometimes used to exit GET STATUS mode. When this 331 * is the case no address cycles are requested, and we can use 332 * this information to detect that we should not wait for the 333 * device to be ready. 334 */ 335 if (column == -1 && page_addr == -1) 336 return; 337 338 default: 339 /* 340 * If we don't have access to the busy pin, we apply the given 341 * command delay 342 */ 343 if (!chip->legacy.dev_ready) { 344 udelay(chip->legacy.chip_delay); 345 return; 346 } 347 } 348 /* 349 * Apply this short delay always to ensure that we do wait tWB in 350 * any case on any machine. 351 */ 352 ndelay(100); 353 354 nand_wait_ready(chip); 355 } 356 357 static void nand_ccs_delay(struct nand_chip *chip) 358 { 359 /* 360 * The controller already takes care of waiting for tCCS when the RNDIN 361 * or RNDOUT command is sent, return directly. 362 */ 363 if (!(chip->options & NAND_WAIT_TCCS)) 364 return; 365 366 /* 367 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns 368 * (which should be safe for all NANDs). 369 */ 370 if (chip->setup_data_interface) 371 ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000); 372 else 373 ndelay(500); 374 } 375 376 /** 377 * nand_command_lp - [DEFAULT] Send command to NAND large page device 378 * @chip: NAND chip object 379 * @command: the command to be sent 380 * @column: the column address for this command, -1 if none 381 * @page_addr: the page address for this command, -1 if none 382 * 383 * Send command to NAND device. This is the version for the new large page 384 * devices. We don't have the separate regions as we have in the small page 385 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. 386 */ 387 static void nand_command_lp(struct nand_chip *chip, unsigned int command, 388 int column, int page_addr) 389 { 390 struct mtd_info *mtd = nand_to_mtd(chip); 391 392 /* Emulate NAND_CMD_READOOB */ 393 if (command == NAND_CMD_READOOB) { 394 column += mtd->writesize; 395 command = NAND_CMD_READ0; 396 } 397 398 /* Command latch cycle */ 399 if (command != NAND_CMD_NONE) 400 chip->legacy.cmd_ctrl(chip, command, 401 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 402 403 if (column != -1 || page_addr != -1) { 404 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; 405 406 /* Serially input address */ 407 if (column != -1) { 408 /* Adjust columns for 16 bit buswidth */ 409 if (chip->options & NAND_BUSWIDTH_16 && 410 !nand_opcode_8bits(command)) 411 column >>= 1; 412 chip->legacy.cmd_ctrl(chip, column, ctrl); 413 ctrl &= ~NAND_CTRL_CHANGE; 414 415 /* Only output a single addr cycle for 8bits opcodes. */ 416 if (!nand_opcode_8bits(command)) 417 chip->legacy.cmd_ctrl(chip, column >> 8, ctrl); 418 } 419 if (page_addr != -1) { 420 chip->legacy.cmd_ctrl(chip, page_addr, ctrl); 421 chip->legacy.cmd_ctrl(chip, page_addr >> 8, 422 NAND_NCE | NAND_ALE); 423 if (chip->options & NAND_ROW_ADDR_3) 424 chip->legacy.cmd_ctrl(chip, page_addr >> 16, 425 NAND_NCE | NAND_ALE); 426 } 427 } 428 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 429 NAND_NCE | NAND_CTRL_CHANGE); 430 431 /* 432 * Program and erase have their own busy handlers status, sequential 433 * in and status need no delay. 434 */ 435 switch (command) { 436 437 case NAND_CMD_NONE: 438 case NAND_CMD_CACHEDPROG: 439 case NAND_CMD_PAGEPROG: 440 case NAND_CMD_ERASE1: 441 case NAND_CMD_ERASE2: 442 case NAND_CMD_SEQIN: 443 case NAND_CMD_STATUS: 444 case NAND_CMD_READID: 445 case NAND_CMD_SET_FEATURES: 446 return; 447 448 case NAND_CMD_RNDIN: 449 nand_ccs_delay(chip); 450 return; 451 452 case NAND_CMD_RESET: 453 if (chip->legacy.dev_ready) 454 break; 455 udelay(chip->legacy.chip_delay); 456 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS, 457 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 458 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 459 NAND_NCE | NAND_CTRL_CHANGE); 460 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ 461 nand_wait_status_ready(mtd, 250); 462 return; 463 464 case NAND_CMD_RNDOUT: 465 /* No ready / busy check necessary */ 466 chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART, 467 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 468 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 469 NAND_NCE | NAND_CTRL_CHANGE); 470 471 nand_ccs_delay(chip); 472 return; 473 474 case NAND_CMD_READ0: 475 /* 476 * READ0 is sometimes used to exit GET STATUS mode. When this 477 * is the case no address cycles are requested, and we can use 478 * this information to detect that READSTART should not be 479 * issued. 480 */ 481 if (column == -1 && page_addr == -1) 482 return; 483 484 chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART, 485 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 486 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 487 NAND_NCE | NAND_CTRL_CHANGE); 488 489 /* This applies to read commands */ 490 default: 491 /* 492 * If we don't have access to the busy pin, we apply the given 493 * command delay. 494 */ 495 if (!chip->legacy.dev_ready) { 496 udelay(chip->legacy.chip_delay); 497 return; 498 } 499 } 500 501 /* 502 * Apply this short delay always to ensure that we do wait tWB in 503 * any case on any machine. 504 */ 505 ndelay(100); 506 507 nand_wait_ready(chip); 508 } 509 510 /** 511 * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP 512 * @chip: nand chip info structure 513 * @addr: feature address. 514 * @subfeature_param: the subfeature parameters, a four bytes array. 515 * 516 * Should be used by NAND controller drivers that do not support the SET/GET 517 * FEATURES operations. 518 */ 519 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr, 520 u8 *subfeature_param) 521 { 522 return -ENOTSUPP; 523 } 524 EXPORT_SYMBOL(nand_get_set_features_notsupp); 525 526 /** 527 * nand_wait - [DEFAULT] wait until the command is done 528 * @mtd: MTD device structure 529 * @chip: NAND chip structure 530 * 531 * Wait for command done. This applies to erase and program only. 532 */ 533 static int nand_wait(struct nand_chip *chip) 534 { 535 536 unsigned long timeo = 400; 537 u8 status; 538 int ret; 539 540 /* 541 * Apply this short delay always to ensure that we do wait tWB in any 542 * case on any machine. 543 */ 544 ndelay(100); 545 546 ret = nand_status_op(chip, NULL); 547 if (ret) 548 return ret; 549 550 if (in_interrupt() || oops_in_progress) 551 panic_nand_wait(chip, timeo); 552 else { 553 timeo = jiffies + msecs_to_jiffies(timeo); 554 do { 555 if (chip->legacy.dev_ready) { 556 if (chip->legacy.dev_ready(chip)) 557 break; 558 } else { 559 ret = nand_read_data_op(chip, &status, 560 sizeof(status), true); 561 if (ret) 562 return ret; 563 564 if (status & NAND_STATUS_READY) 565 break; 566 } 567 cond_resched(); 568 } while (time_before(jiffies, timeo)); 569 } 570 571 ret = nand_read_data_op(chip, &status, sizeof(status), true); 572 if (ret) 573 return ret; 574 575 /* This can happen if in case of timeout or buggy dev_ready */ 576 WARN_ON(!(status & NAND_STATUS_READY)); 577 return status; 578 } 579 580 void nand_legacy_set_defaults(struct nand_chip *chip) 581 { 582 unsigned int busw = chip->options & NAND_BUSWIDTH_16; 583 584 if (chip->exec_op) 585 return; 586 587 /* check for proper chip_delay setup, set 20us if not */ 588 if (!chip->legacy.chip_delay) 589 chip->legacy.chip_delay = 20; 590 591 /* check, if a user supplied command function given */ 592 if (!chip->legacy.cmdfunc && !chip->exec_op) 593 chip->legacy.cmdfunc = nand_command; 594 595 /* check, if a user supplied wait function given */ 596 if (chip->legacy.waitfunc == NULL) 597 chip->legacy.waitfunc = nand_wait; 598 599 if (!chip->select_chip) 600 chip->select_chip = nand_select_chip; 601 602 /* If called twice, pointers that depend on busw may need to be reset */ 603 if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte) 604 chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte; 605 if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf) 606 chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf; 607 if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte) 608 chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte; 609 if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf) 610 chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf; 611 } 612 613 void nand_legacy_adjust_cmdfunc(struct nand_chip *chip) 614 { 615 struct mtd_info *mtd = nand_to_mtd(chip); 616 617 /* Do not replace user supplied command function! */ 618 if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command) 619 chip->legacy.cmdfunc = nand_command_lp; 620 } 621 622 int nand_legacy_check_hooks(struct nand_chip *chip) 623 { 624 /* 625 * ->legacy.cmdfunc() is legacy and will only be used if ->exec_op() is 626 * not populated. 627 */ 628 if (chip->exec_op) 629 return 0; 630 631 /* 632 * Default functions assigned for ->legacy.cmdfunc() and 633 * ->select_chip() both expect ->legacy.cmd_ctrl() to be populated. 634 */ 635 if ((!chip->legacy.cmdfunc || !chip->select_chip) && 636 !chip->legacy.cmd_ctrl) { 637 pr_err("->legacy.cmd_ctrl() should be provided\n"); 638 return -EINVAL; 639 } 640 641 return 0; 642 } 643