1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/slab.h> 9 #include <linux/init.h> 10 #include <linux/module.h> 11 #include <linux/mtd/mtd.h> 12 #include <linux/mtd/rawnand.h> 13 #include <linux/mtd/partitions.h> 14 #include <linux/interrupt.h> 15 #include <linux/device.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/completion.h> 22 #include <linux/of.h> 23 24 #define DRIVER_NAME "mxc_nand" 25 26 /* Addresses for NFC registers */ 27 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) 28 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) 29 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) 30 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) 31 #define NFC_V1_V2_CONFIG (host->regs + 0x0a) 32 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) 33 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) 34 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10) 35 #define NFC_V1_V2_WRPROT (host->regs + 0x12) 36 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) 37 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) 38 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) 39 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) 40 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) 41 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) 42 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) 43 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) 44 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) 45 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) 46 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) 47 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) 48 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) 49 50 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) 51 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) 52 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) 53 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) 54 #define NFC_V1_V2_CONFIG1_BIG (1 << 5) 55 #define NFC_V1_V2_CONFIG1_RST (1 << 6) 56 #define NFC_V1_V2_CONFIG1_CE (1 << 7) 57 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) 58 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) 59 #define NFC_V2_CONFIG1_FP_INT (1 << 11) 60 61 #define NFC_V1_V2_CONFIG2_INT (1 << 15) 62 63 /* 64 * Operation modes for the NFC. Valid for v1, v2 and v3 65 * type controllers. 66 */ 67 #define NFC_CMD (1 << 0) 68 #define NFC_ADDR (1 << 1) 69 #define NFC_INPUT (1 << 2) 70 #define NFC_OUTPUT (1 << 3) 71 #define NFC_ID (1 << 4) 72 #define NFC_STATUS (1 << 5) 73 74 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) 75 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) 76 77 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) 78 #define NFC_V3_CONFIG1_SP_EN (1 << 0) 79 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) 80 81 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) 82 83 #define NFC_V3_LAUNCH (host->regs_axi + 0x40) 84 85 #define NFC_V3_WRPROT (host->regs_ip + 0x0) 86 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) 87 #define NFC_V3_WRPROT_LOCK (1 << 1) 88 #define NFC_V3_WRPROT_UNLOCK (1 << 2) 89 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) 90 91 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) 92 93 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) 94 #define NFC_V3_CONFIG2_PS_512 (0 << 0) 95 #define NFC_V3_CONFIG2_PS_2048 (1 << 0) 96 #define NFC_V3_CONFIG2_PS_4096 (2 << 0) 97 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) 98 #define NFC_V3_CONFIG2_ECC_EN (1 << 3) 99 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) 100 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) 101 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) 102 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) 103 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) 104 #define NFC_V3_CONFIG2_INT_MSK (1 << 15) 105 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) 106 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) 107 108 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) 109 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) 110 #define NFC_V3_CONFIG3_FW8 (1 << 3) 111 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) 112 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) 113 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) 114 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) 115 116 #define NFC_V3_IPC (host->regs_ip + 0x2C) 117 #define NFC_V3_IPC_CREQ (1 << 0) 118 #define NFC_V3_IPC_INT (1 << 31) 119 120 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) 121 122 struct mxc_nand_host; 123 124 struct mxc_nand_devtype_data { 125 void (*preset)(struct mtd_info *); 126 int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc, 127 int page); 128 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); 129 void (*send_addr)(struct mxc_nand_host *, uint16_t, int); 130 void (*send_page)(struct mtd_info *, unsigned int); 131 void (*send_read_id)(struct mxc_nand_host *); 132 uint16_t (*get_dev_status)(struct mxc_nand_host *); 133 int (*check_int)(struct mxc_nand_host *); 134 void (*irq_control)(struct mxc_nand_host *, int); 135 u32 (*get_ecc_status)(struct mxc_nand_host *); 136 const struct mtd_ooblayout_ops *ooblayout; 137 void (*select_chip)(struct nand_chip *chip, int cs); 138 int (*setup_interface)(struct nand_chip *chip, int csline, 139 const struct nand_interface_config *conf); 140 void (*enable_hwecc)(struct nand_chip *chip, bool enable); 141 142 /* 143 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked 144 * (CONFIG1:INT_MSK is set). To handle this the driver uses 145 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK 146 */ 147 int irqpending_quirk; 148 int needs_ip; 149 150 size_t regs_offset; 151 size_t spare0_offset; 152 size_t axi_offset; 153 154 int spare_len; 155 int eccbytes; 156 int eccsize; 157 int ppb_shift; 158 }; 159 160 struct mxc_nand_host { 161 struct nand_chip nand; 162 struct device *dev; 163 164 void __iomem *spare0; 165 void __iomem *main_area0; 166 167 void __iomem *base; 168 void __iomem *regs; 169 void __iomem *regs_axi; 170 void __iomem *regs_ip; 171 int status_request; 172 struct clk *clk; 173 int clk_act; 174 int irq; 175 int eccsize; 176 int used_oobsize; 177 int active_cs; 178 179 struct completion op_completion; 180 181 uint8_t *data_buf; 182 unsigned int buf_start; 183 184 const struct mxc_nand_devtype_data *devtype_data; 185 }; 186 187 static const char * const part_probes[] = { 188 "cmdlinepart", "RedBoot", "ofpart", NULL }; 189 190 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) 191 { 192 int i; 193 u32 *t = trg; 194 const __iomem u32 *s = src; 195 196 for (i = 0; i < (size >> 2); i++) 197 *t++ = __raw_readl(s++); 198 } 199 200 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size) 201 { 202 int i; 203 u16 *t = trg; 204 const __iomem u16 *s = src; 205 206 /* We assume that src (IO) is always 32bit aligned */ 207 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) { 208 memcpy32_fromio(trg, src, size); 209 return; 210 } 211 212 for (i = 0; i < (size >> 1); i++) 213 *t++ = __raw_readw(s++); 214 } 215 216 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size) 217 { 218 /* __iowrite32_copy use 32bit size values so divide by 4 */ 219 __iowrite32_copy(trg, src, size / 4); 220 } 221 222 static void memcpy16_toio(void __iomem *trg, const void *src, int size) 223 { 224 int i; 225 __iomem u16 *t = trg; 226 const u16 *s = src; 227 228 /* We assume that trg (IO) is always 32bit aligned */ 229 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) { 230 memcpy32_toio(trg, src, size); 231 return; 232 } 233 234 for (i = 0; i < (size >> 1); i++) 235 __raw_writew(*s++, t++); 236 } 237 238 /* 239 * The controller splits a page into data chunks of 512 bytes + partial oob. 240 * There are writesize / 512 such chunks, the size of the partial oob parts is 241 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then 242 * contains additionally the byte lost by rounding (if any). 243 * This function handles the needed shuffling between host->data_buf (which 244 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes 245 * spare) and the NFC buffer. 246 */ 247 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf) 248 { 249 struct nand_chip *this = mtd_to_nand(mtd); 250 struct mxc_nand_host *host = nand_get_controller_data(this); 251 u16 i, oob_chunk_size; 252 u16 num_chunks = mtd->writesize / 512; 253 254 u8 *d = buf; 255 u8 __iomem *s = host->spare0; 256 u16 sparebuf_size = host->devtype_data->spare_len; 257 258 /* size of oob chunk for all but possibly the last one */ 259 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1; 260 261 if (bfrom) { 262 for (i = 0; i < num_chunks - 1; i++) 263 memcpy16_fromio(d + i * oob_chunk_size, 264 s + i * sparebuf_size, 265 oob_chunk_size); 266 267 /* the last chunk */ 268 memcpy16_fromio(d + i * oob_chunk_size, 269 s + i * sparebuf_size, 270 host->used_oobsize - i * oob_chunk_size); 271 } else { 272 for (i = 0; i < num_chunks - 1; i++) 273 memcpy16_toio(&s[i * sparebuf_size], 274 &d[i * oob_chunk_size], 275 oob_chunk_size); 276 277 /* the last chunk */ 278 memcpy16_toio(&s[i * sparebuf_size], 279 &d[i * oob_chunk_size], 280 host->used_oobsize - i * oob_chunk_size); 281 } 282 } 283 284 /* 285 * MXC NANDFC can only perform full page+spare or spare-only read/write. When 286 * the upper layers perform a read/write buf operation, the saved column address 287 * is used to index into the full page. So usually this function is called with 288 * column == 0 (unless no column cycle is needed indicated by column == -1) 289 */ 290 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) 291 { 292 struct nand_chip *nand_chip = mtd_to_nand(mtd); 293 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 294 295 /* Write out column address, if necessary */ 296 if (column != -1) { 297 host->devtype_data->send_addr(host, column & 0xff, 298 page_addr == -1); 299 if (mtd->writesize > 512) 300 /* another col addr cycle for 2k page */ 301 host->devtype_data->send_addr(host, 302 (column >> 8) & 0xff, 303 false); 304 } 305 306 /* Write out page address, if necessary */ 307 if (page_addr != -1) { 308 /* paddr_0 - p_addr_7 */ 309 host->devtype_data->send_addr(host, (page_addr & 0xff), false); 310 311 if (mtd->writesize > 512) { 312 if (mtd->size >= 0x10000000) { 313 /* paddr_8 - paddr_15 */ 314 host->devtype_data->send_addr(host, 315 (page_addr >> 8) & 0xff, 316 false); 317 host->devtype_data->send_addr(host, 318 (page_addr >> 16) & 0xff, 319 true); 320 } else 321 /* paddr_8 - paddr_15 */ 322 host->devtype_data->send_addr(host, 323 (page_addr >> 8) & 0xff, true); 324 } else { 325 if (nand_chip->options & NAND_ROW_ADDR_3) { 326 /* paddr_8 - paddr_15 */ 327 host->devtype_data->send_addr(host, 328 (page_addr >> 8) & 0xff, 329 false); 330 host->devtype_data->send_addr(host, 331 (page_addr >> 16) & 0xff, 332 true); 333 } else 334 /* paddr_8 - paddr_15 */ 335 host->devtype_data->send_addr(host, 336 (page_addr >> 8) & 0xff, true); 337 } 338 } 339 } 340 341 static int check_int_v3(struct mxc_nand_host *host) 342 { 343 uint32_t tmp; 344 345 tmp = readl(NFC_V3_IPC); 346 if (!(tmp & NFC_V3_IPC_INT)) 347 return 0; 348 349 tmp &= ~NFC_V3_IPC_INT; 350 writel(tmp, NFC_V3_IPC); 351 352 return 1; 353 } 354 355 static int check_int_v1_v2(struct mxc_nand_host *host) 356 { 357 uint32_t tmp; 358 359 tmp = readw(NFC_V1_V2_CONFIG2); 360 if (!(tmp & NFC_V1_V2_CONFIG2_INT)) 361 return 0; 362 363 if (!host->devtype_data->irqpending_quirk) 364 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); 365 366 return 1; 367 } 368 369 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) 370 { 371 uint16_t tmp; 372 373 tmp = readw(NFC_V1_V2_CONFIG1); 374 375 if (activate) 376 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; 377 else 378 tmp |= NFC_V1_V2_CONFIG1_INT_MSK; 379 380 writew(tmp, NFC_V1_V2_CONFIG1); 381 } 382 383 static void irq_control_v3(struct mxc_nand_host *host, int activate) 384 { 385 uint32_t tmp; 386 387 tmp = readl(NFC_V3_CONFIG2); 388 389 if (activate) 390 tmp &= ~NFC_V3_CONFIG2_INT_MSK; 391 else 392 tmp |= NFC_V3_CONFIG2_INT_MSK; 393 394 writel(tmp, NFC_V3_CONFIG2); 395 } 396 397 static void irq_control(struct mxc_nand_host *host, int activate) 398 { 399 if (host->devtype_data->irqpending_quirk) { 400 if (activate) 401 enable_irq(host->irq); 402 else 403 disable_irq_nosync(host->irq); 404 } else { 405 host->devtype_data->irq_control(host, activate); 406 } 407 } 408 409 static u32 get_ecc_status_v1(struct mxc_nand_host *host) 410 { 411 return readw(NFC_V1_V2_ECC_STATUS_RESULT); 412 } 413 414 static u32 get_ecc_status_v2(struct mxc_nand_host *host) 415 { 416 return readl(NFC_V1_V2_ECC_STATUS_RESULT); 417 } 418 419 static u32 get_ecc_status_v3(struct mxc_nand_host *host) 420 { 421 return readl(NFC_V3_ECC_STATUS_RESULT); 422 } 423 424 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) 425 { 426 struct mxc_nand_host *host = dev_id; 427 428 if (!host->devtype_data->check_int(host)) 429 return IRQ_NONE; 430 431 irq_control(host, 0); 432 433 complete(&host->op_completion); 434 435 return IRQ_HANDLED; 436 } 437 438 /* This function polls the NANDFC to wait for the basic operation to 439 * complete by checking the INT bit of config2 register. 440 */ 441 static int wait_op_done(struct mxc_nand_host *host, int useirq) 442 { 443 int ret = 0; 444 445 /* 446 * If operation is already complete, don't bother to setup an irq or a 447 * loop. 448 */ 449 if (host->devtype_data->check_int(host)) 450 return 0; 451 452 if (useirq) { 453 unsigned long timeout; 454 455 reinit_completion(&host->op_completion); 456 457 irq_control(host, 1); 458 459 timeout = wait_for_completion_timeout(&host->op_completion, HZ); 460 if (!timeout && !host->devtype_data->check_int(host)) { 461 dev_dbg(host->dev, "timeout waiting for irq\n"); 462 ret = -ETIMEDOUT; 463 } 464 } else { 465 int max_retries = 8000; 466 int done; 467 468 do { 469 udelay(1); 470 471 done = host->devtype_data->check_int(host); 472 if (done) 473 break; 474 475 } while (--max_retries); 476 477 if (!done) { 478 dev_dbg(host->dev, "timeout polling for completion\n"); 479 ret = -ETIMEDOUT; 480 } 481 } 482 483 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq); 484 485 return ret; 486 } 487 488 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) 489 { 490 /* fill command */ 491 writel(cmd, NFC_V3_FLASH_CMD); 492 493 /* send out command */ 494 writel(NFC_CMD, NFC_V3_LAUNCH); 495 496 /* Wait for operation to complete */ 497 wait_op_done(host, useirq); 498 } 499 500 /* This function issues the specified command to the NAND device and 501 * waits for completion. */ 502 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) 503 { 504 dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq); 505 506 writew(cmd, NFC_V1_V2_FLASH_CMD); 507 writew(NFC_CMD, NFC_V1_V2_CONFIG2); 508 509 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { 510 int max_retries = 100; 511 /* Reset completion is indicated by NFC_CONFIG2 */ 512 /* being set to 0 */ 513 while (max_retries-- > 0) { 514 if (readw(NFC_V1_V2_CONFIG2) == 0) { 515 break; 516 } 517 udelay(1); 518 } 519 if (max_retries < 0) 520 dev_dbg(host->dev, "%s: RESET failed\n", __func__); 521 } else { 522 /* Wait for operation to complete */ 523 wait_op_done(host, useirq); 524 } 525 } 526 527 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) 528 { 529 /* fill address */ 530 writel(addr, NFC_V3_FLASH_ADDR0); 531 532 /* send out address */ 533 writel(NFC_ADDR, NFC_V3_LAUNCH); 534 535 wait_op_done(host, 0); 536 } 537 538 /* This function sends an address (or partial address) to the 539 * NAND device. The address is used to select the source/destination for 540 * a NAND command. */ 541 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) 542 { 543 dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast); 544 545 writew(addr, NFC_V1_V2_FLASH_ADDR); 546 writew(NFC_ADDR, NFC_V1_V2_CONFIG2); 547 548 /* Wait for operation to complete */ 549 wait_op_done(host, islast); 550 } 551 552 static void send_page_v3(struct mtd_info *mtd, unsigned int ops) 553 { 554 struct nand_chip *nand_chip = mtd_to_nand(mtd); 555 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 556 uint32_t tmp; 557 558 tmp = readl(NFC_V3_CONFIG1); 559 tmp &= ~(7 << 4); 560 writel(tmp, NFC_V3_CONFIG1); 561 562 /* transfer data from NFC ram to nand */ 563 writel(ops, NFC_V3_LAUNCH); 564 565 wait_op_done(host, false); 566 } 567 568 static void send_page_v2(struct mtd_info *mtd, unsigned int ops) 569 { 570 struct nand_chip *nand_chip = mtd_to_nand(mtd); 571 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 572 573 /* NANDFC buffer 0 is used for page read/write */ 574 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 575 576 writew(ops, NFC_V1_V2_CONFIG2); 577 578 /* Wait for operation to complete */ 579 wait_op_done(host, true); 580 } 581 582 static void send_page_v1(struct mtd_info *mtd, unsigned int ops) 583 { 584 struct nand_chip *nand_chip = mtd_to_nand(mtd); 585 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 586 int bufs, i; 587 588 if (mtd->writesize > 512) 589 bufs = 4; 590 else 591 bufs = 1; 592 593 for (i = 0; i < bufs; i++) { 594 595 /* NANDFC buffer 0 is used for page read/write */ 596 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); 597 598 writew(ops, NFC_V1_V2_CONFIG2); 599 600 /* Wait for operation to complete */ 601 wait_op_done(host, true); 602 } 603 } 604 605 static void send_read_id_v3(struct mxc_nand_host *host) 606 { 607 /* Read ID into main buffer */ 608 writel(NFC_ID, NFC_V3_LAUNCH); 609 610 wait_op_done(host, true); 611 612 memcpy32_fromio(host->data_buf, host->main_area0, 16); 613 } 614 615 /* Request the NANDFC to perform a read of the NAND device ID. */ 616 static void send_read_id_v1_v2(struct mxc_nand_host *host) 617 { 618 /* NANDFC buffer 0 is used for device ID output */ 619 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 620 621 writew(NFC_ID, NFC_V1_V2_CONFIG2); 622 623 /* Wait for operation to complete */ 624 wait_op_done(host, true); 625 626 memcpy32_fromio(host->data_buf, host->main_area0, 16); 627 } 628 629 static uint16_t get_dev_status_v3(struct mxc_nand_host *host) 630 { 631 writew(NFC_STATUS, NFC_V3_LAUNCH); 632 wait_op_done(host, true); 633 634 return readl(NFC_V3_CONFIG1) >> 16; 635 } 636 637 /* This function requests the NANDFC to perform a read of the 638 * NAND device status and returns the current status. */ 639 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) 640 { 641 void __iomem *main_buf = host->main_area0; 642 uint32_t store; 643 uint16_t ret; 644 645 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 646 647 /* 648 * The device status is stored in main_area0. To 649 * prevent corruption of the buffer save the value 650 * and restore it afterwards. 651 */ 652 store = readl(main_buf); 653 654 writew(NFC_STATUS, NFC_V1_V2_CONFIG2); 655 wait_op_done(host, true); 656 657 ret = readw(main_buf); 658 659 writel(store, main_buf); 660 661 return ret; 662 } 663 664 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable) 665 { 666 struct mxc_nand_host *host = nand_get_controller_data(chip); 667 uint16_t config1; 668 669 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 670 return; 671 672 config1 = readw(NFC_V1_V2_CONFIG1); 673 674 if (enable) 675 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 676 else 677 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN; 678 679 writew(config1, NFC_V1_V2_CONFIG1); 680 } 681 682 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable) 683 { 684 struct mxc_nand_host *host = nand_get_controller_data(chip); 685 uint32_t config2; 686 687 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 688 return; 689 690 config2 = readl(NFC_V3_CONFIG2); 691 692 if (enable) 693 config2 |= NFC_V3_CONFIG2_ECC_EN; 694 else 695 config2 &= ~NFC_V3_CONFIG2_ECC_EN; 696 697 writel(config2, NFC_V3_CONFIG2); 698 } 699 700 /* This functions is used by upper layer to checks if device is ready */ 701 static int mxc_nand_dev_ready(struct nand_chip *chip) 702 { 703 /* 704 * NFC handles R/B internally. Therefore, this function 705 * always returns status as ready. 706 */ 707 return 1; 708 } 709 710 static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob, 711 bool ecc, int page) 712 { 713 struct mtd_info *mtd = nand_to_mtd(chip); 714 struct mxc_nand_host *host = nand_get_controller_data(chip); 715 unsigned int bitflips_corrected = 0; 716 int no_subpages; 717 int i; 718 719 host->devtype_data->enable_hwecc(chip, ecc); 720 721 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); 722 mxc_do_addr_cycle(mtd, 0, page); 723 724 if (mtd->writesize > 512) 725 host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true); 726 727 no_subpages = mtd->writesize >> 9; 728 729 for (i = 0; i < no_subpages; i++) { 730 uint16_t ecc_stats; 731 732 /* NANDFC buffer 0 is used for page read/write */ 733 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); 734 735 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2); 736 737 /* Wait for operation to complete */ 738 wait_op_done(host, true); 739 740 ecc_stats = get_ecc_status_v1(host); 741 742 ecc_stats >>= 2; 743 744 if (buf && ecc) { 745 switch (ecc_stats & 0x3) { 746 case 0: 747 default: 748 break; 749 case 1: 750 mtd->ecc_stats.corrected++; 751 bitflips_corrected = 1; 752 break; 753 case 2: 754 mtd->ecc_stats.failed++; 755 break; 756 } 757 } 758 } 759 760 if (buf) 761 memcpy32_fromio(buf, host->main_area0, mtd->writesize); 762 if (oob) 763 copy_spare(mtd, true, oob); 764 765 return bitflips_corrected; 766 } 767 768 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf, 769 void *oob, bool ecc, int page) 770 { 771 struct mtd_info *mtd = nand_to_mtd(chip); 772 struct mxc_nand_host *host = nand_get_controller_data(chip); 773 unsigned int max_bitflips = 0; 774 u32 ecc_stat, err; 775 int no_subpages; 776 u8 ecc_bit_mask, err_limit; 777 778 host->devtype_data->enable_hwecc(chip, ecc); 779 780 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); 781 mxc_do_addr_cycle(mtd, 0, page); 782 783 if (mtd->writesize > 512) 784 host->devtype_data->send_cmd(host, 785 NAND_CMD_READSTART, true); 786 787 host->devtype_data->send_page(mtd, NFC_OUTPUT); 788 789 if (buf) 790 memcpy32_fromio(buf, host->main_area0, mtd->writesize); 791 if (oob) 792 copy_spare(mtd, true, oob); 793 794 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; 795 err_limit = (host->eccsize == 4) ? 0x4 : 0x8; 796 797 no_subpages = mtd->writesize >> 9; 798 799 ecc_stat = host->devtype_data->get_ecc_status(host); 800 801 do { 802 err = ecc_stat & ecc_bit_mask; 803 if (err > err_limit) { 804 mtd->ecc_stats.failed++; 805 } else { 806 mtd->ecc_stats.corrected += err; 807 max_bitflips = max_t(unsigned int, max_bitflips, err); 808 } 809 810 ecc_stat >>= 4; 811 } while (--no_subpages); 812 813 return max_bitflips; 814 } 815 816 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf, 817 int oob_required, int page) 818 { 819 struct mxc_nand_host *host = nand_get_controller_data(chip); 820 void *oob_buf; 821 822 if (oob_required) 823 oob_buf = chip->oob_poi; 824 else 825 oob_buf = NULL; 826 827 return host->devtype_data->read_page(chip, buf, oob_buf, 1, page); 828 } 829 830 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, 831 int oob_required, int page) 832 { 833 struct mxc_nand_host *host = nand_get_controller_data(chip); 834 void *oob_buf; 835 836 if (oob_required) 837 oob_buf = chip->oob_poi; 838 else 839 oob_buf = NULL; 840 841 return host->devtype_data->read_page(chip, buf, oob_buf, 0, page); 842 } 843 844 static int mxc_nand_read_oob(struct nand_chip *chip, int page) 845 { 846 struct mxc_nand_host *host = nand_get_controller_data(chip); 847 848 return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0, 849 page); 850 } 851 852 static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf, 853 bool ecc, int page) 854 { 855 struct mtd_info *mtd = nand_to_mtd(chip); 856 struct mxc_nand_host *host = nand_get_controller_data(chip); 857 858 host->devtype_data->enable_hwecc(chip, ecc); 859 860 host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false); 861 mxc_do_addr_cycle(mtd, 0, page); 862 863 memcpy32_toio(host->main_area0, buf, mtd->writesize); 864 copy_spare(mtd, false, chip->oob_poi); 865 866 host->devtype_data->send_page(mtd, NFC_INPUT); 867 host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true); 868 mxc_do_addr_cycle(mtd, 0, page); 869 870 return 0; 871 } 872 873 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf, 874 int oob_required, int page) 875 { 876 return mxc_nand_write_page(chip, buf, true, page); 877 } 878 879 static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 880 int oob_required, int page) 881 { 882 return mxc_nand_write_page(chip, buf, false, page); 883 } 884 885 static int mxc_nand_write_oob(struct nand_chip *chip, int page) 886 { 887 struct mtd_info *mtd = nand_to_mtd(chip); 888 struct mxc_nand_host *host = nand_get_controller_data(chip); 889 890 memset(host->data_buf, 0xff, mtd->writesize); 891 892 return mxc_nand_write_page(chip, host->data_buf, false, page); 893 } 894 895 static u_char mxc_nand_read_byte(struct nand_chip *nand_chip) 896 { 897 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 898 uint8_t ret; 899 900 /* Check for status request */ 901 if (host->status_request) 902 return host->devtype_data->get_dev_status(host) & 0xFF; 903 904 if (nand_chip->options & NAND_BUSWIDTH_16) { 905 /* only take the lower byte of each word */ 906 ret = *(uint16_t *)(host->data_buf + host->buf_start); 907 908 host->buf_start += 2; 909 } else { 910 ret = *(uint8_t *)(host->data_buf + host->buf_start); 911 host->buf_start++; 912 } 913 914 dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start); 915 return ret; 916 } 917 918 /* Write data of length len to buffer buf. The data to be 919 * written on NAND Flash is first copied to RAMbuffer. After the Data Input 920 * Operation by the NFC, the data is written to NAND Flash */ 921 static void mxc_nand_write_buf(struct nand_chip *nand_chip, const u_char *buf, 922 int len) 923 { 924 struct mtd_info *mtd = nand_to_mtd(nand_chip); 925 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 926 u16 col = host->buf_start; 927 int n = mtd->oobsize + mtd->writesize - col; 928 929 n = min(n, len); 930 931 memcpy(host->data_buf + col, buf, n); 932 933 host->buf_start += n; 934 } 935 936 /* Read the data buffer from the NAND Flash. To read the data from NAND 937 * Flash first the data output cycle is initiated by the NFC, which copies 938 * the data to RAMbuffer. This data of length len is then copied to buffer buf. 939 */ 940 static void mxc_nand_read_buf(struct nand_chip *nand_chip, u_char *buf, 941 int len) 942 { 943 struct mtd_info *mtd = nand_to_mtd(nand_chip); 944 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 945 u16 col = host->buf_start; 946 int n = mtd->oobsize + mtd->writesize - col; 947 948 n = min(n, len); 949 950 memcpy(buf, host->data_buf + col, n); 951 952 host->buf_start += n; 953 } 954 955 /* This function is used by upper layer for select and 956 * deselect of the NAND chip */ 957 static void mxc_nand_select_chip_v1_v3(struct nand_chip *nand_chip, int chip) 958 { 959 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 960 961 if (chip == -1) { 962 /* Disable the NFC clock */ 963 if (host->clk_act) { 964 clk_disable_unprepare(host->clk); 965 host->clk_act = 0; 966 } 967 return; 968 } 969 970 if (!host->clk_act) { 971 /* Enable the NFC clock */ 972 clk_prepare_enable(host->clk); 973 host->clk_act = 1; 974 } 975 } 976 977 static void mxc_nand_select_chip_v2(struct nand_chip *nand_chip, int chip) 978 { 979 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 980 981 if (chip == -1) { 982 /* Disable the NFC clock */ 983 if (host->clk_act) { 984 clk_disable_unprepare(host->clk); 985 host->clk_act = 0; 986 } 987 return; 988 } 989 990 if (!host->clk_act) { 991 /* Enable the NFC clock */ 992 clk_prepare_enable(host->clk); 993 host->clk_act = 1; 994 } 995 996 host->active_cs = chip; 997 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 998 } 999 1000 #define MXC_V1_ECCBYTES 5 1001 1002 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section, 1003 struct mtd_oob_region *oobregion) 1004 { 1005 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1006 1007 if (section >= nand_chip->ecc.steps) 1008 return -ERANGE; 1009 1010 oobregion->offset = (section * 16) + 6; 1011 oobregion->length = MXC_V1_ECCBYTES; 1012 1013 return 0; 1014 } 1015 1016 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section, 1017 struct mtd_oob_region *oobregion) 1018 { 1019 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1020 1021 if (section > nand_chip->ecc.steps) 1022 return -ERANGE; 1023 1024 if (!section) { 1025 if (mtd->writesize <= 512) { 1026 oobregion->offset = 0; 1027 oobregion->length = 5; 1028 } else { 1029 oobregion->offset = 2; 1030 oobregion->length = 4; 1031 } 1032 } else { 1033 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6; 1034 if (section < nand_chip->ecc.steps) 1035 oobregion->length = (section * 16) + 6 - 1036 oobregion->offset; 1037 else 1038 oobregion->length = mtd->oobsize - oobregion->offset; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = { 1045 .ecc = mxc_v1_ooblayout_ecc, 1046 .free = mxc_v1_ooblayout_free, 1047 }; 1048 1049 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section, 1050 struct mtd_oob_region *oobregion) 1051 { 1052 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1053 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; 1054 1055 if (section >= nand_chip->ecc.steps) 1056 return -ERANGE; 1057 1058 oobregion->offset = (section * stepsize) + 7; 1059 oobregion->length = nand_chip->ecc.bytes; 1060 1061 return 0; 1062 } 1063 1064 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section, 1065 struct mtd_oob_region *oobregion) 1066 { 1067 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1068 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; 1069 1070 if (section >= nand_chip->ecc.steps) 1071 return -ERANGE; 1072 1073 if (!section) { 1074 if (mtd->writesize <= 512) { 1075 oobregion->offset = 0; 1076 oobregion->length = 5; 1077 } else { 1078 oobregion->offset = 2; 1079 oobregion->length = 4; 1080 } 1081 } else { 1082 oobregion->offset = section * stepsize; 1083 oobregion->length = 7; 1084 } 1085 1086 return 0; 1087 } 1088 1089 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = { 1090 .ecc = mxc_v2_ooblayout_ecc, 1091 .free = mxc_v2_ooblayout_free, 1092 }; 1093 1094 /* 1095 * v2 and v3 type controllers can do 4bit or 8bit ecc depending 1096 * on how much oob the nand chip has. For 8bit ecc we need at least 1097 * 26 bytes of oob data per 512 byte block. 1098 */ 1099 static int get_eccsize(struct mtd_info *mtd) 1100 { 1101 int oobbytes_per_512 = 0; 1102 1103 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; 1104 1105 if (oobbytes_per_512 < 26) 1106 return 4; 1107 else 1108 return 8; 1109 } 1110 1111 static void preset_v1(struct mtd_info *mtd) 1112 { 1113 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1114 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1115 uint16_t config1 = 0; 1116 1117 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST && 1118 mtd->writesize) 1119 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1120 1121 if (!host->devtype_data->irqpending_quirk) 1122 config1 |= NFC_V1_V2_CONFIG1_INT_MSK; 1123 1124 host->eccsize = 1; 1125 1126 writew(config1, NFC_V1_V2_CONFIG1); 1127 /* preset operation */ 1128 1129 /* Unlock the internal RAM Buffer */ 1130 writew(0x2, NFC_V1_V2_CONFIG); 1131 1132 /* Blocks to be unlocked */ 1133 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); 1134 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); 1135 1136 /* Unlock Block Command for given address range */ 1137 writew(0x4, NFC_V1_V2_WRPROT); 1138 } 1139 1140 static int mxc_nand_v2_setup_interface(struct nand_chip *chip, int csline, 1141 const struct nand_interface_config *conf) 1142 { 1143 struct mxc_nand_host *host = nand_get_controller_data(chip); 1144 int tRC_min_ns, tRC_ps, ret; 1145 unsigned long rate, rate_round; 1146 const struct nand_sdr_timings *timings; 1147 u16 config1; 1148 1149 timings = nand_get_sdr_timings(conf); 1150 if (IS_ERR(timings)) 1151 return -ENOTSUPP; 1152 1153 config1 = readw(NFC_V1_V2_CONFIG1); 1154 1155 tRC_min_ns = timings->tRC_min / 1000; 1156 rate = 1000000000 / tRC_min_ns; 1157 1158 /* 1159 * For tRC < 30ns we have to use EDO mode. In this case the controller 1160 * does one access per clock cycle. Otherwise the controller does one 1161 * access in two clock cycles, thus we have to double the rate to the 1162 * controller. 1163 */ 1164 if (tRC_min_ns < 30) { 1165 rate_round = clk_round_rate(host->clk, rate); 1166 config1 |= NFC_V2_CONFIG1_ONE_CYCLE; 1167 tRC_ps = 1000000000 / (rate_round / 1000); 1168 } else { 1169 rate *= 2; 1170 rate_round = clk_round_rate(host->clk, rate); 1171 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE; 1172 tRC_ps = 1000000000 / (rate_round / 1000 / 2); 1173 } 1174 1175 /* 1176 * The timing values compared against are from the i.MX25 Automotive 1177 * datasheet, Table 50. NFC Timing Parameters 1178 */ 1179 if (timings->tCLS_min > tRC_ps - 1000 || 1180 timings->tCLH_min > tRC_ps - 2000 || 1181 timings->tCS_min > tRC_ps - 1000 || 1182 timings->tCH_min > tRC_ps - 2000 || 1183 timings->tWP_min > tRC_ps - 1500 || 1184 timings->tALS_min > tRC_ps || 1185 timings->tALH_min > tRC_ps - 3000 || 1186 timings->tDS_min > tRC_ps || 1187 timings->tDH_min > tRC_ps - 5000 || 1188 timings->tWC_min > 2 * tRC_ps || 1189 timings->tWH_min > tRC_ps - 2500 || 1190 timings->tRR_min > 6 * tRC_ps || 1191 timings->tRP_min > 3 * tRC_ps / 2 || 1192 timings->tRC_min > 2 * tRC_ps || 1193 timings->tREH_min > (tRC_ps / 2) - 2500) { 1194 dev_dbg(host->dev, "Timing out of bounds\n"); 1195 return -EINVAL; 1196 } 1197 1198 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1199 return 0; 1200 1201 ret = clk_set_rate(host->clk, rate); 1202 if (ret) 1203 return ret; 1204 1205 writew(config1, NFC_V1_V2_CONFIG1); 1206 1207 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round, 1208 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" : 1209 "normal"); 1210 1211 return 0; 1212 } 1213 1214 static void preset_v2(struct mtd_info *mtd) 1215 { 1216 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1217 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1218 uint16_t config1 = 0; 1219 1220 config1 |= NFC_V2_CONFIG1_FP_INT; 1221 1222 if (!host->devtype_data->irqpending_quirk) 1223 config1 |= NFC_V1_V2_CONFIG1_INT_MSK; 1224 1225 if (mtd->writesize) { 1226 uint16_t pages_per_block = mtd->erasesize / mtd->writesize; 1227 1228 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1229 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1230 1231 host->eccsize = get_eccsize(mtd); 1232 if (host->eccsize == 4) 1233 config1 |= NFC_V2_CONFIG1_ECC_MODE_4; 1234 1235 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); 1236 } else { 1237 host->eccsize = 1; 1238 } 1239 1240 writew(config1, NFC_V1_V2_CONFIG1); 1241 /* preset operation */ 1242 1243 /* spare area size in 16-bit half-words */ 1244 writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA); 1245 1246 /* Unlock the internal RAM Buffer */ 1247 writew(0x2, NFC_V1_V2_CONFIG); 1248 1249 /* Blocks to be unlocked */ 1250 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); 1251 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); 1252 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); 1253 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); 1254 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); 1255 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); 1256 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); 1257 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); 1258 1259 /* Unlock Block Command for given address range */ 1260 writew(0x4, NFC_V1_V2_WRPROT); 1261 } 1262 1263 static void preset_v3(struct mtd_info *mtd) 1264 { 1265 struct nand_chip *chip = mtd_to_nand(mtd); 1266 struct mxc_nand_host *host = nand_get_controller_data(chip); 1267 uint32_t config2, config3; 1268 int i, addr_phases; 1269 1270 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); 1271 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); 1272 1273 /* Unlock the internal RAM Buffer */ 1274 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, 1275 NFC_V3_WRPROT); 1276 1277 /* Blocks to be unlocked */ 1278 for (i = 0; i < NAND_MAX_CHIPS; i++) 1279 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); 1280 1281 writel(0, NFC_V3_IPC); 1282 1283 config2 = NFC_V3_CONFIG2_ONE_CYCLE | 1284 NFC_V3_CONFIG2_2CMD_PHASES | 1285 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | 1286 NFC_V3_CONFIG2_ST_CMD(0x70) | 1287 NFC_V3_CONFIG2_INT_MSK | 1288 NFC_V3_CONFIG2_NUM_ADDR_PHASE0; 1289 1290 addr_phases = fls(chip->pagemask) >> 3; 1291 1292 if (mtd->writesize == 2048) { 1293 config2 |= NFC_V3_CONFIG2_PS_2048; 1294 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); 1295 } else if (mtd->writesize == 4096) { 1296 config2 |= NFC_V3_CONFIG2_PS_4096; 1297 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); 1298 } else { 1299 config2 |= NFC_V3_CONFIG2_PS_512; 1300 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); 1301 } 1302 1303 if (mtd->writesize) { 1304 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1305 config2 |= NFC_V3_CONFIG2_ECC_EN; 1306 1307 config2 |= NFC_V3_CONFIG2_PPB( 1308 ffs(mtd->erasesize / mtd->writesize) - 6, 1309 host->devtype_data->ppb_shift); 1310 host->eccsize = get_eccsize(mtd); 1311 if (host->eccsize == 8) 1312 config2 |= NFC_V3_CONFIG2_ECC_MODE_8; 1313 } 1314 1315 writel(config2, NFC_V3_CONFIG2); 1316 1317 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | 1318 NFC_V3_CONFIG3_NO_SDMA | 1319 NFC_V3_CONFIG3_RBB_MODE | 1320 NFC_V3_CONFIG3_SBB(6) | /* Reset default */ 1321 NFC_V3_CONFIG3_ADD_OP(0); 1322 1323 if (!(chip->options & NAND_BUSWIDTH_16)) 1324 config3 |= NFC_V3_CONFIG3_FW8; 1325 1326 writel(config3, NFC_V3_CONFIG3); 1327 1328 writel(0, NFC_V3_DELAY_LINE); 1329 } 1330 1331 /* Used by the upper layer to write command to NAND Flash for 1332 * different operations to be carried out on NAND Flash */ 1333 static void mxc_nand_command(struct nand_chip *nand_chip, unsigned command, 1334 int column, int page_addr) 1335 { 1336 struct mtd_info *mtd = nand_to_mtd(nand_chip); 1337 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1338 1339 dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", 1340 command, column, page_addr); 1341 1342 /* Reset command state information */ 1343 host->status_request = false; 1344 1345 /* Command pre-processing step */ 1346 switch (command) { 1347 case NAND_CMD_RESET: 1348 host->devtype_data->preset(mtd); 1349 host->devtype_data->send_cmd(host, command, false); 1350 break; 1351 1352 case NAND_CMD_STATUS: 1353 host->buf_start = 0; 1354 host->status_request = true; 1355 1356 host->devtype_data->send_cmd(host, command, true); 1357 WARN_ONCE(column != -1 || page_addr != -1, 1358 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", 1359 command, column, page_addr); 1360 mxc_do_addr_cycle(mtd, column, page_addr); 1361 break; 1362 1363 case NAND_CMD_READID: 1364 host->devtype_data->send_cmd(host, command, true); 1365 mxc_do_addr_cycle(mtd, column, page_addr); 1366 host->devtype_data->send_read_id(host); 1367 host->buf_start = 0; 1368 break; 1369 1370 case NAND_CMD_ERASE1: 1371 case NAND_CMD_ERASE2: 1372 host->devtype_data->send_cmd(host, command, false); 1373 WARN_ONCE(column != -1, 1374 "Unexpected column value (cmd=%u, col=%d)\n", 1375 command, column); 1376 mxc_do_addr_cycle(mtd, column, page_addr); 1377 1378 break; 1379 case NAND_CMD_PARAM: 1380 host->devtype_data->send_cmd(host, command, false); 1381 mxc_do_addr_cycle(mtd, column, page_addr); 1382 host->devtype_data->send_page(mtd, NFC_OUTPUT); 1383 memcpy32_fromio(host->data_buf, host->main_area0, 512); 1384 host->buf_start = 0; 1385 break; 1386 default: 1387 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n", 1388 command); 1389 break; 1390 } 1391 } 1392 1393 static int mxc_nand_set_features(struct nand_chip *chip, int addr, 1394 u8 *subfeature_param) 1395 { 1396 struct mtd_info *mtd = nand_to_mtd(chip); 1397 struct mxc_nand_host *host = nand_get_controller_data(chip); 1398 int i; 1399 1400 host->buf_start = 0; 1401 1402 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1403 chip->legacy.write_byte(chip, subfeature_param[i]); 1404 1405 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); 1406 host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false); 1407 mxc_do_addr_cycle(mtd, addr, -1); 1408 host->devtype_data->send_page(mtd, NFC_INPUT); 1409 1410 return 0; 1411 } 1412 1413 static int mxc_nand_get_features(struct nand_chip *chip, int addr, 1414 u8 *subfeature_param) 1415 { 1416 struct mtd_info *mtd = nand_to_mtd(chip); 1417 struct mxc_nand_host *host = nand_get_controller_data(chip); 1418 int i; 1419 1420 host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false); 1421 mxc_do_addr_cycle(mtd, addr, -1); 1422 host->devtype_data->send_page(mtd, NFC_OUTPUT); 1423 memcpy32_fromio(host->data_buf, host->main_area0, 512); 1424 host->buf_start = 0; 1425 1426 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1427 *subfeature_param++ = chip->legacy.read_byte(chip); 1428 1429 return 0; 1430 } 1431 1432 /* 1433 * The generic flash bbt descriptors overlap with our ecc 1434 * hardware, so define some i.MX specific ones. 1435 */ 1436 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; 1437 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; 1438 1439 static struct nand_bbt_descr bbt_main_descr = { 1440 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 1441 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1442 .offs = 0, 1443 .len = 4, 1444 .veroffs = 4, 1445 .maxblocks = 4, 1446 .pattern = bbt_pattern, 1447 }; 1448 1449 static struct nand_bbt_descr bbt_mirror_descr = { 1450 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 1451 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1452 .offs = 0, 1453 .len = 4, 1454 .veroffs = 4, 1455 .maxblocks = 4, 1456 .pattern = mirror_pattern, 1457 }; 1458 1459 /* v1 + irqpending_quirk: i.MX21 */ 1460 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { 1461 .preset = preset_v1, 1462 .read_page = mxc_nand_read_page_v1, 1463 .send_cmd = send_cmd_v1_v2, 1464 .send_addr = send_addr_v1_v2, 1465 .send_page = send_page_v1, 1466 .send_read_id = send_read_id_v1_v2, 1467 .get_dev_status = get_dev_status_v1_v2, 1468 .check_int = check_int_v1_v2, 1469 .irq_control = irq_control_v1_v2, 1470 .get_ecc_status = get_ecc_status_v1, 1471 .ooblayout = &mxc_v1_ooblayout_ops, 1472 .select_chip = mxc_nand_select_chip_v1_v3, 1473 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1474 .irqpending_quirk = 1, 1475 .needs_ip = 0, 1476 .regs_offset = 0xe00, 1477 .spare0_offset = 0x800, 1478 .spare_len = 16, 1479 .eccbytes = 3, 1480 .eccsize = 1, 1481 }; 1482 1483 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ 1484 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { 1485 .preset = preset_v1, 1486 .read_page = mxc_nand_read_page_v1, 1487 .send_cmd = send_cmd_v1_v2, 1488 .send_addr = send_addr_v1_v2, 1489 .send_page = send_page_v1, 1490 .send_read_id = send_read_id_v1_v2, 1491 .get_dev_status = get_dev_status_v1_v2, 1492 .check_int = check_int_v1_v2, 1493 .irq_control = irq_control_v1_v2, 1494 .get_ecc_status = get_ecc_status_v1, 1495 .ooblayout = &mxc_v1_ooblayout_ops, 1496 .select_chip = mxc_nand_select_chip_v1_v3, 1497 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1498 .irqpending_quirk = 0, 1499 .needs_ip = 0, 1500 .regs_offset = 0xe00, 1501 .spare0_offset = 0x800, 1502 .axi_offset = 0, 1503 .spare_len = 16, 1504 .eccbytes = 3, 1505 .eccsize = 1, 1506 }; 1507 1508 /* v21: i.MX25, i.MX35 */ 1509 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { 1510 .preset = preset_v2, 1511 .read_page = mxc_nand_read_page_v2_v3, 1512 .send_cmd = send_cmd_v1_v2, 1513 .send_addr = send_addr_v1_v2, 1514 .send_page = send_page_v2, 1515 .send_read_id = send_read_id_v1_v2, 1516 .get_dev_status = get_dev_status_v1_v2, 1517 .check_int = check_int_v1_v2, 1518 .irq_control = irq_control_v1_v2, 1519 .get_ecc_status = get_ecc_status_v2, 1520 .ooblayout = &mxc_v2_ooblayout_ops, 1521 .select_chip = mxc_nand_select_chip_v2, 1522 .setup_interface = mxc_nand_v2_setup_interface, 1523 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1524 .irqpending_quirk = 0, 1525 .needs_ip = 0, 1526 .regs_offset = 0x1e00, 1527 .spare0_offset = 0x1000, 1528 .axi_offset = 0, 1529 .spare_len = 64, 1530 .eccbytes = 9, 1531 .eccsize = 0, 1532 }; 1533 1534 /* v3.2a: i.MX51 */ 1535 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { 1536 .preset = preset_v3, 1537 .read_page = mxc_nand_read_page_v2_v3, 1538 .send_cmd = send_cmd_v3, 1539 .send_addr = send_addr_v3, 1540 .send_page = send_page_v3, 1541 .send_read_id = send_read_id_v3, 1542 .get_dev_status = get_dev_status_v3, 1543 .check_int = check_int_v3, 1544 .irq_control = irq_control_v3, 1545 .get_ecc_status = get_ecc_status_v3, 1546 .ooblayout = &mxc_v2_ooblayout_ops, 1547 .select_chip = mxc_nand_select_chip_v1_v3, 1548 .enable_hwecc = mxc_nand_enable_hwecc_v3, 1549 .irqpending_quirk = 0, 1550 .needs_ip = 1, 1551 .regs_offset = 0, 1552 .spare0_offset = 0x1000, 1553 .axi_offset = 0x1e00, 1554 .spare_len = 64, 1555 .eccbytes = 0, 1556 .eccsize = 0, 1557 .ppb_shift = 7, 1558 }; 1559 1560 /* v3.2b: i.MX53 */ 1561 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { 1562 .preset = preset_v3, 1563 .read_page = mxc_nand_read_page_v2_v3, 1564 .send_cmd = send_cmd_v3, 1565 .send_addr = send_addr_v3, 1566 .send_page = send_page_v3, 1567 .send_read_id = send_read_id_v3, 1568 .get_dev_status = get_dev_status_v3, 1569 .check_int = check_int_v3, 1570 .irq_control = irq_control_v3, 1571 .get_ecc_status = get_ecc_status_v3, 1572 .ooblayout = &mxc_v2_ooblayout_ops, 1573 .select_chip = mxc_nand_select_chip_v1_v3, 1574 .enable_hwecc = mxc_nand_enable_hwecc_v3, 1575 .irqpending_quirk = 0, 1576 .needs_ip = 1, 1577 .regs_offset = 0, 1578 .spare0_offset = 0x1000, 1579 .axi_offset = 0x1e00, 1580 .spare_len = 64, 1581 .eccbytes = 0, 1582 .eccsize = 0, 1583 .ppb_shift = 8, 1584 }; 1585 1586 static inline int is_imx21_nfc(struct mxc_nand_host *host) 1587 { 1588 return host->devtype_data == &imx21_nand_devtype_data; 1589 } 1590 1591 static inline int is_imx27_nfc(struct mxc_nand_host *host) 1592 { 1593 return host->devtype_data == &imx27_nand_devtype_data; 1594 } 1595 1596 static inline int is_imx25_nfc(struct mxc_nand_host *host) 1597 { 1598 return host->devtype_data == &imx25_nand_devtype_data; 1599 } 1600 1601 static const struct of_device_id mxcnd_dt_ids[] = { 1602 { .compatible = "fsl,imx21-nand", .data = &imx21_nand_devtype_data, }, 1603 { .compatible = "fsl,imx27-nand", .data = &imx27_nand_devtype_data, }, 1604 { .compatible = "fsl,imx25-nand", .data = &imx25_nand_devtype_data, }, 1605 { .compatible = "fsl,imx51-nand", .data = &imx51_nand_devtype_data, }, 1606 { .compatible = "fsl,imx53-nand", .data = &imx53_nand_devtype_data, }, 1607 { /* sentinel */ } 1608 }; 1609 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids); 1610 1611 static int mxcnd_attach_chip(struct nand_chip *chip) 1612 { 1613 struct mtd_info *mtd = nand_to_mtd(chip); 1614 struct mxc_nand_host *host = nand_get_controller_data(chip); 1615 struct device *dev = mtd->dev.parent; 1616 1617 chip->ecc.bytes = host->devtype_data->eccbytes; 1618 host->eccsize = host->devtype_data->eccsize; 1619 chip->ecc.size = 512; 1620 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout); 1621 1622 switch (chip->ecc.engine_type) { 1623 case NAND_ECC_ENGINE_TYPE_ON_HOST: 1624 chip->ecc.read_page = mxc_nand_read_page; 1625 chip->ecc.read_page_raw = mxc_nand_read_page_raw; 1626 chip->ecc.read_oob = mxc_nand_read_oob; 1627 chip->ecc.write_page = mxc_nand_write_page_ecc; 1628 chip->ecc.write_page_raw = mxc_nand_write_page_raw; 1629 chip->ecc.write_oob = mxc_nand_write_oob; 1630 break; 1631 1632 case NAND_ECC_ENGINE_TYPE_SOFT: 1633 break; 1634 1635 default: 1636 return -EINVAL; 1637 } 1638 1639 if (chip->bbt_options & NAND_BBT_USE_FLASH) { 1640 chip->bbt_td = &bbt_main_descr; 1641 chip->bbt_md = &bbt_mirror_descr; 1642 } 1643 1644 /* Allocate the right size buffer now */ 1645 devm_kfree(dev, (void *)host->data_buf); 1646 host->data_buf = devm_kzalloc(dev, mtd->writesize + mtd->oobsize, 1647 GFP_KERNEL); 1648 if (!host->data_buf) 1649 return -ENOMEM; 1650 1651 /* Call preset again, with correct writesize chip time */ 1652 host->devtype_data->preset(mtd); 1653 1654 if (!chip->ecc.bytes) { 1655 if (host->eccsize == 8) 1656 chip->ecc.bytes = 18; 1657 else if (host->eccsize == 4) 1658 chip->ecc.bytes = 9; 1659 } 1660 1661 /* 1662 * Experimentation shows that i.MX NFC can only handle up to 218 oob 1663 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare() 1664 * into copying invalid data to/from the spare IO buffer, as this 1665 * might cause ECC data corruption when doing sub-page write to a 1666 * partially written page. 1667 */ 1668 host->used_oobsize = min(mtd->oobsize, 218U); 1669 1670 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 1671 if (is_imx21_nfc(host) || is_imx27_nfc(host)) 1672 chip->ecc.strength = 1; 1673 else 1674 chip->ecc.strength = (host->eccsize == 4) ? 4 : 8; 1675 } 1676 1677 return 0; 1678 } 1679 1680 static int mxcnd_setup_interface(struct nand_chip *chip, int chipnr, 1681 const struct nand_interface_config *conf) 1682 { 1683 struct mxc_nand_host *host = nand_get_controller_data(chip); 1684 1685 return host->devtype_data->setup_interface(chip, chipnr, conf); 1686 } 1687 1688 static const struct nand_controller_ops mxcnd_controller_ops = { 1689 .attach_chip = mxcnd_attach_chip, 1690 .setup_interface = mxcnd_setup_interface, 1691 }; 1692 1693 static int mxcnd_probe(struct platform_device *pdev) 1694 { 1695 struct nand_chip *this; 1696 struct mtd_info *mtd; 1697 struct mxc_nand_host *host; 1698 int err = 0; 1699 1700 /* Allocate memory for MTD device structure and private data */ 1701 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host), 1702 GFP_KERNEL); 1703 if (!host) 1704 return -ENOMEM; 1705 1706 /* allocate a temporary buffer for the nand_scan_ident() */ 1707 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL); 1708 if (!host->data_buf) 1709 return -ENOMEM; 1710 1711 host->dev = &pdev->dev; 1712 /* structures must be linked */ 1713 this = &host->nand; 1714 mtd = nand_to_mtd(this); 1715 mtd->dev.parent = &pdev->dev; 1716 mtd->name = DRIVER_NAME; 1717 1718 /* 50 us command delay time */ 1719 this->legacy.chip_delay = 5; 1720 1721 nand_set_controller_data(this, host); 1722 nand_set_flash_node(this, pdev->dev.of_node); 1723 this->legacy.dev_ready = mxc_nand_dev_ready; 1724 this->legacy.cmdfunc = mxc_nand_command; 1725 this->legacy.read_byte = mxc_nand_read_byte; 1726 this->legacy.write_buf = mxc_nand_write_buf; 1727 this->legacy.read_buf = mxc_nand_read_buf; 1728 this->legacy.set_features = mxc_nand_set_features; 1729 this->legacy.get_features = mxc_nand_get_features; 1730 1731 host->clk = devm_clk_get(&pdev->dev, NULL); 1732 if (IS_ERR(host->clk)) 1733 return PTR_ERR(host->clk); 1734 1735 host->devtype_data = device_get_match_data(&pdev->dev); 1736 1737 if (!host->devtype_data->setup_interface) 1738 this->options |= NAND_KEEP_TIMINGS; 1739 1740 if (host->devtype_data->needs_ip) { 1741 host->regs_ip = devm_platform_ioremap_resource(pdev, 0); 1742 if (IS_ERR(host->regs_ip)) 1743 return PTR_ERR(host->regs_ip); 1744 1745 host->base = devm_platform_ioremap_resource(pdev, 1); 1746 } else { 1747 host->base = devm_platform_ioremap_resource(pdev, 0); 1748 } 1749 1750 if (IS_ERR(host->base)) 1751 return PTR_ERR(host->base); 1752 1753 host->main_area0 = host->base; 1754 1755 if (host->devtype_data->regs_offset) 1756 host->regs = host->base + host->devtype_data->regs_offset; 1757 host->spare0 = host->base + host->devtype_data->spare0_offset; 1758 if (host->devtype_data->axi_offset) 1759 host->regs_axi = host->base + host->devtype_data->axi_offset; 1760 1761 this->legacy.select_chip = host->devtype_data->select_chip; 1762 1763 init_completion(&host->op_completion); 1764 1765 host->irq = platform_get_irq(pdev, 0); 1766 if (host->irq < 0) 1767 return host->irq; 1768 1769 /* 1770 * Use host->devtype_data->irq_control() here instead of irq_control() 1771 * because we must not disable_irq_nosync without having requested the 1772 * irq. 1773 */ 1774 host->devtype_data->irq_control(host, 0); 1775 1776 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, 1777 0, DRIVER_NAME, host); 1778 if (err) 1779 return err; 1780 1781 err = clk_prepare_enable(host->clk); 1782 if (err) 1783 return err; 1784 host->clk_act = 1; 1785 1786 /* 1787 * Now that we "own" the interrupt make sure the interrupt mask bit is 1788 * cleared on i.MX21. Otherwise we can't read the interrupt status bit 1789 * on this machine. 1790 */ 1791 if (host->devtype_data->irqpending_quirk) { 1792 disable_irq_nosync(host->irq); 1793 host->devtype_data->irq_control(host, 1); 1794 } 1795 1796 /* Scan the NAND device */ 1797 this->legacy.dummy_controller.ops = &mxcnd_controller_ops; 1798 err = nand_scan(this, is_imx25_nfc(host) ? 4 : 1); 1799 if (err) 1800 goto escan; 1801 1802 /* Register the partitions */ 1803 err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0); 1804 if (err) 1805 goto cleanup_nand; 1806 1807 platform_set_drvdata(pdev, host); 1808 1809 return 0; 1810 1811 cleanup_nand: 1812 nand_cleanup(this); 1813 escan: 1814 if (host->clk_act) 1815 clk_disable_unprepare(host->clk); 1816 1817 return err; 1818 } 1819 1820 static void mxcnd_remove(struct platform_device *pdev) 1821 { 1822 struct mxc_nand_host *host = platform_get_drvdata(pdev); 1823 struct nand_chip *chip = &host->nand; 1824 int ret; 1825 1826 ret = mtd_device_unregister(nand_to_mtd(chip)); 1827 WARN_ON(ret); 1828 nand_cleanup(chip); 1829 if (host->clk_act) 1830 clk_disable_unprepare(host->clk); 1831 } 1832 1833 static struct platform_driver mxcnd_driver = { 1834 .driver = { 1835 .name = DRIVER_NAME, 1836 .of_match_table = mxcnd_dt_ids, 1837 }, 1838 .probe = mxcnd_probe, 1839 .remove_new = mxcnd_remove, 1840 }; 1841 module_platform_driver(mxcnd_driver); 1842 1843 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1844 MODULE_DESCRIPTION("MXC NAND MTD driver"); 1845 MODULE_LICENSE("GPL"); 1846