1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/slab.h> 9 #include <linux/init.h> 10 #include <linux/module.h> 11 #include <linux/mtd/mtd.h> 12 #include <linux/mtd/rawnand.h> 13 #include <linux/mtd/partitions.h> 14 #include <linux/interrupt.h> 15 #include <linux/device.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/err.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/completion.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_data/mtd-mxc_nand.h> 25 26 #define DRIVER_NAME "mxc_nand" 27 28 /* Addresses for NFC registers */ 29 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) 30 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) 31 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) 32 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) 33 #define NFC_V1_V2_CONFIG (host->regs + 0x0a) 34 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) 35 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) 36 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10) 37 #define NFC_V1_V2_WRPROT (host->regs + 0x12) 38 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) 39 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) 40 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) 41 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) 42 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) 43 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) 44 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) 45 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) 46 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) 47 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) 48 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) 49 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) 50 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) 51 52 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) 53 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) 54 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) 55 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) 56 #define NFC_V1_V2_CONFIG1_BIG (1 << 5) 57 #define NFC_V1_V2_CONFIG1_RST (1 << 6) 58 #define NFC_V1_V2_CONFIG1_CE (1 << 7) 59 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) 60 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) 61 #define NFC_V2_CONFIG1_FP_INT (1 << 11) 62 63 #define NFC_V1_V2_CONFIG2_INT (1 << 15) 64 65 /* 66 * Operation modes for the NFC. Valid for v1, v2 and v3 67 * type controllers. 68 */ 69 #define NFC_CMD (1 << 0) 70 #define NFC_ADDR (1 << 1) 71 #define NFC_INPUT (1 << 2) 72 #define NFC_OUTPUT (1 << 3) 73 #define NFC_ID (1 << 4) 74 #define NFC_STATUS (1 << 5) 75 76 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) 77 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) 78 79 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) 80 #define NFC_V3_CONFIG1_SP_EN (1 << 0) 81 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) 82 83 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) 84 85 #define NFC_V3_LAUNCH (host->regs_axi + 0x40) 86 87 #define NFC_V3_WRPROT (host->regs_ip + 0x0) 88 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) 89 #define NFC_V3_WRPROT_LOCK (1 << 1) 90 #define NFC_V3_WRPROT_UNLOCK (1 << 2) 91 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) 92 93 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) 94 95 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) 96 #define NFC_V3_CONFIG2_PS_512 (0 << 0) 97 #define NFC_V3_CONFIG2_PS_2048 (1 << 0) 98 #define NFC_V3_CONFIG2_PS_4096 (2 << 0) 99 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) 100 #define NFC_V3_CONFIG2_ECC_EN (1 << 3) 101 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) 102 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) 103 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) 104 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) 105 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) 106 #define NFC_V3_CONFIG2_INT_MSK (1 << 15) 107 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) 108 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) 109 110 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) 111 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) 112 #define NFC_V3_CONFIG3_FW8 (1 << 3) 113 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) 114 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) 115 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) 116 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) 117 118 #define NFC_V3_IPC (host->regs_ip + 0x2C) 119 #define NFC_V3_IPC_CREQ (1 << 0) 120 #define NFC_V3_IPC_INT (1 << 31) 121 122 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) 123 124 struct mxc_nand_host; 125 126 struct mxc_nand_devtype_data { 127 void (*preset)(struct mtd_info *); 128 int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc, 129 int page); 130 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); 131 void (*send_addr)(struct mxc_nand_host *, uint16_t, int); 132 void (*send_page)(struct mtd_info *, unsigned int); 133 void (*send_read_id)(struct mxc_nand_host *); 134 uint16_t (*get_dev_status)(struct mxc_nand_host *); 135 int (*check_int)(struct mxc_nand_host *); 136 void (*irq_control)(struct mxc_nand_host *, int); 137 u32 (*get_ecc_status)(struct mxc_nand_host *); 138 const struct mtd_ooblayout_ops *ooblayout; 139 void (*select_chip)(struct nand_chip *chip, int cs); 140 int (*setup_data_interface)(struct nand_chip *chip, int csline, 141 const struct nand_data_interface *conf); 142 void (*enable_hwecc)(struct nand_chip *chip, bool enable); 143 144 /* 145 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked 146 * (CONFIG1:INT_MSK is set). To handle this the driver uses 147 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK 148 */ 149 int irqpending_quirk; 150 int needs_ip; 151 152 size_t regs_offset; 153 size_t spare0_offset; 154 size_t axi_offset; 155 156 int spare_len; 157 int eccbytes; 158 int eccsize; 159 int ppb_shift; 160 }; 161 162 struct mxc_nand_host { 163 struct nand_chip nand; 164 struct device *dev; 165 166 void __iomem *spare0; 167 void __iomem *main_area0; 168 169 void __iomem *base; 170 void __iomem *regs; 171 void __iomem *regs_axi; 172 void __iomem *regs_ip; 173 int status_request; 174 struct clk *clk; 175 int clk_act; 176 int irq; 177 int eccsize; 178 int used_oobsize; 179 int active_cs; 180 181 struct completion op_completion; 182 183 uint8_t *data_buf; 184 unsigned int buf_start; 185 186 const struct mxc_nand_devtype_data *devtype_data; 187 struct mxc_nand_platform_data pdata; 188 }; 189 190 static const char * const part_probes[] = { 191 "cmdlinepart", "RedBoot", "ofpart", NULL }; 192 193 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) 194 { 195 int i; 196 u32 *t = trg; 197 const __iomem u32 *s = src; 198 199 for (i = 0; i < (size >> 2); i++) 200 *t++ = __raw_readl(s++); 201 } 202 203 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size) 204 { 205 int i; 206 u16 *t = trg; 207 const __iomem u16 *s = src; 208 209 /* We assume that src (IO) is always 32bit aligned */ 210 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) { 211 memcpy32_fromio(trg, src, size); 212 return; 213 } 214 215 for (i = 0; i < (size >> 1); i++) 216 *t++ = __raw_readw(s++); 217 } 218 219 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size) 220 { 221 /* __iowrite32_copy use 32bit size values so divide by 4 */ 222 __iowrite32_copy(trg, src, size / 4); 223 } 224 225 static void memcpy16_toio(void __iomem *trg, const void *src, int size) 226 { 227 int i; 228 __iomem u16 *t = trg; 229 const u16 *s = src; 230 231 /* We assume that trg (IO) is always 32bit aligned */ 232 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) { 233 memcpy32_toio(trg, src, size); 234 return; 235 } 236 237 for (i = 0; i < (size >> 1); i++) 238 __raw_writew(*s++, t++); 239 } 240 241 /* 242 * The controller splits a page into data chunks of 512 bytes + partial oob. 243 * There are writesize / 512 such chunks, the size of the partial oob parts is 244 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then 245 * contains additionally the byte lost by rounding (if any). 246 * This function handles the needed shuffling between host->data_buf (which 247 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes 248 * spare) and the NFC buffer. 249 */ 250 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf) 251 { 252 struct nand_chip *this = mtd_to_nand(mtd); 253 struct mxc_nand_host *host = nand_get_controller_data(this); 254 u16 i, oob_chunk_size; 255 u16 num_chunks = mtd->writesize / 512; 256 257 u8 *d = buf; 258 u8 __iomem *s = host->spare0; 259 u16 sparebuf_size = host->devtype_data->spare_len; 260 261 /* size of oob chunk for all but possibly the last one */ 262 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1; 263 264 if (bfrom) { 265 for (i = 0; i < num_chunks - 1; i++) 266 memcpy16_fromio(d + i * oob_chunk_size, 267 s + i * sparebuf_size, 268 oob_chunk_size); 269 270 /* the last chunk */ 271 memcpy16_fromio(d + i * oob_chunk_size, 272 s + i * sparebuf_size, 273 host->used_oobsize - i * oob_chunk_size); 274 } else { 275 for (i = 0; i < num_chunks - 1; i++) 276 memcpy16_toio(&s[i * sparebuf_size], 277 &d[i * oob_chunk_size], 278 oob_chunk_size); 279 280 /* the last chunk */ 281 memcpy16_toio(&s[i * sparebuf_size], 282 &d[i * oob_chunk_size], 283 host->used_oobsize - i * oob_chunk_size); 284 } 285 } 286 287 /* 288 * MXC NANDFC can only perform full page+spare or spare-only read/write. When 289 * the upper layers perform a read/write buf operation, the saved column address 290 * is used to index into the full page. So usually this function is called with 291 * column == 0 (unless no column cycle is needed indicated by column == -1) 292 */ 293 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) 294 { 295 struct nand_chip *nand_chip = mtd_to_nand(mtd); 296 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 297 298 /* Write out column address, if necessary */ 299 if (column != -1) { 300 host->devtype_data->send_addr(host, column & 0xff, 301 page_addr == -1); 302 if (mtd->writesize > 512) 303 /* another col addr cycle for 2k page */ 304 host->devtype_data->send_addr(host, 305 (column >> 8) & 0xff, 306 false); 307 } 308 309 /* Write out page address, if necessary */ 310 if (page_addr != -1) { 311 /* paddr_0 - p_addr_7 */ 312 host->devtype_data->send_addr(host, (page_addr & 0xff), false); 313 314 if (mtd->writesize > 512) { 315 if (mtd->size >= 0x10000000) { 316 /* paddr_8 - paddr_15 */ 317 host->devtype_data->send_addr(host, 318 (page_addr >> 8) & 0xff, 319 false); 320 host->devtype_data->send_addr(host, 321 (page_addr >> 16) & 0xff, 322 true); 323 } else 324 /* paddr_8 - paddr_15 */ 325 host->devtype_data->send_addr(host, 326 (page_addr >> 8) & 0xff, true); 327 } else { 328 if (nand_chip->options & NAND_ROW_ADDR_3) { 329 /* paddr_8 - paddr_15 */ 330 host->devtype_data->send_addr(host, 331 (page_addr >> 8) & 0xff, 332 false); 333 host->devtype_data->send_addr(host, 334 (page_addr >> 16) & 0xff, 335 true); 336 } else 337 /* paddr_8 - paddr_15 */ 338 host->devtype_data->send_addr(host, 339 (page_addr >> 8) & 0xff, true); 340 } 341 } 342 } 343 344 static int check_int_v3(struct mxc_nand_host *host) 345 { 346 uint32_t tmp; 347 348 tmp = readl(NFC_V3_IPC); 349 if (!(tmp & NFC_V3_IPC_INT)) 350 return 0; 351 352 tmp &= ~NFC_V3_IPC_INT; 353 writel(tmp, NFC_V3_IPC); 354 355 return 1; 356 } 357 358 static int check_int_v1_v2(struct mxc_nand_host *host) 359 { 360 uint32_t tmp; 361 362 tmp = readw(NFC_V1_V2_CONFIG2); 363 if (!(tmp & NFC_V1_V2_CONFIG2_INT)) 364 return 0; 365 366 if (!host->devtype_data->irqpending_quirk) 367 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); 368 369 return 1; 370 } 371 372 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) 373 { 374 uint16_t tmp; 375 376 tmp = readw(NFC_V1_V2_CONFIG1); 377 378 if (activate) 379 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; 380 else 381 tmp |= NFC_V1_V2_CONFIG1_INT_MSK; 382 383 writew(tmp, NFC_V1_V2_CONFIG1); 384 } 385 386 static void irq_control_v3(struct mxc_nand_host *host, int activate) 387 { 388 uint32_t tmp; 389 390 tmp = readl(NFC_V3_CONFIG2); 391 392 if (activate) 393 tmp &= ~NFC_V3_CONFIG2_INT_MSK; 394 else 395 tmp |= NFC_V3_CONFIG2_INT_MSK; 396 397 writel(tmp, NFC_V3_CONFIG2); 398 } 399 400 static void irq_control(struct mxc_nand_host *host, int activate) 401 { 402 if (host->devtype_data->irqpending_quirk) { 403 if (activate) 404 enable_irq(host->irq); 405 else 406 disable_irq_nosync(host->irq); 407 } else { 408 host->devtype_data->irq_control(host, activate); 409 } 410 } 411 412 static u32 get_ecc_status_v1(struct mxc_nand_host *host) 413 { 414 return readw(NFC_V1_V2_ECC_STATUS_RESULT); 415 } 416 417 static u32 get_ecc_status_v2(struct mxc_nand_host *host) 418 { 419 return readl(NFC_V1_V2_ECC_STATUS_RESULT); 420 } 421 422 static u32 get_ecc_status_v3(struct mxc_nand_host *host) 423 { 424 return readl(NFC_V3_ECC_STATUS_RESULT); 425 } 426 427 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) 428 { 429 struct mxc_nand_host *host = dev_id; 430 431 if (!host->devtype_data->check_int(host)) 432 return IRQ_NONE; 433 434 irq_control(host, 0); 435 436 complete(&host->op_completion); 437 438 return IRQ_HANDLED; 439 } 440 441 /* This function polls the NANDFC to wait for the basic operation to 442 * complete by checking the INT bit of config2 register. 443 */ 444 static int wait_op_done(struct mxc_nand_host *host, int useirq) 445 { 446 int ret = 0; 447 448 /* 449 * If operation is already complete, don't bother to setup an irq or a 450 * loop. 451 */ 452 if (host->devtype_data->check_int(host)) 453 return 0; 454 455 if (useirq) { 456 unsigned long timeout; 457 458 reinit_completion(&host->op_completion); 459 460 irq_control(host, 1); 461 462 timeout = wait_for_completion_timeout(&host->op_completion, HZ); 463 if (!timeout && !host->devtype_data->check_int(host)) { 464 dev_dbg(host->dev, "timeout waiting for irq\n"); 465 ret = -ETIMEDOUT; 466 } 467 } else { 468 int max_retries = 8000; 469 int done; 470 471 do { 472 udelay(1); 473 474 done = host->devtype_data->check_int(host); 475 if (done) 476 break; 477 478 } while (--max_retries); 479 480 if (!done) { 481 dev_dbg(host->dev, "timeout polling for completion\n"); 482 ret = -ETIMEDOUT; 483 } 484 } 485 486 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq); 487 488 return ret; 489 } 490 491 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) 492 { 493 /* fill command */ 494 writel(cmd, NFC_V3_FLASH_CMD); 495 496 /* send out command */ 497 writel(NFC_CMD, NFC_V3_LAUNCH); 498 499 /* Wait for operation to complete */ 500 wait_op_done(host, useirq); 501 } 502 503 /* This function issues the specified command to the NAND device and 504 * waits for completion. */ 505 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) 506 { 507 dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq); 508 509 writew(cmd, NFC_V1_V2_FLASH_CMD); 510 writew(NFC_CMD, NFC_V1_V2_CONFIG2); 511 512 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { 513 int max_retries = 100; 514 /* Reset completion is indicated by NFC_CONFIG2 */ 515 /* being set to 0 */ 516 while (max_retries-- > 0) { 517 if (readw(NFC_V1_V2_CONFIG2) == 0) { 518 break; 519 } 520 udelay(1); 521 } 522 if (max_retries < 0) 523 dev_dbg(host->dev, "%s: RESET failed\n", __func__); 524 } else { 525 /* Wait for operation to complete */ 526 wait_op_done(host, useirq); 527 } 528 } 529 530 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) 531 { 532 /* fill address */ 533 writel(addr, NFC_V3_FLASH_ADDR0); 534 535 /* send out address */ 536 writel(NFC_ADDR, NFC_V3_LAUNCH); 537 538 wait_op_done(host, 0); 539 } 540 541 /* This function sends an address (or partial address) to the 542 * NAND device. The address is used to select the source/destination for 543 * a NAND command. */ 544 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) 545 { 546 dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast); 547 548 writew(addr, NFC_V1_V2_FLASH_ADDR); 549 writew(NFC_ADDR, NFC_V1_V2_CONFIG2); 550 551 /* Wait for operation to complete */ 552 wait_op_done(host, islast); 553 } 554 555 static void send_page_v3(struct mtd_info *mtd, unsigned int ops) 556 { 557 struct nand_chip *nand_chip = mtd_to_nand(mtd); 558 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 559 uint32_t tmp; 560 561 tmp = readl(NFC_V3_CONFIG1); 562 tmp &= ~(7 << 4); 563 writel(tmp, NFC_V3_CONFIG1); 564 565 /* transfer data from NFC ram to nand */ 566 writel(ops, NFC_V3_LAUNCH); 567 568 wait_op_done(host, false); 569 } 570 571 static void send_page_v2(struct mtd_info *mtd, unsigned int ops) 572 { 573 struct nand_chip *nand_chip = mtd_to_nand(mtd); 574 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 575 576 /* NANDFC buffer 0 is used for page read/write */ 577 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 578 579 writew(ops, NFC_V1_V2_CONFIG2); 580 581 /* Wait for operation to complete */ 582 wait_op_done(host, true); 583 } 584 585 static void send_page_v1(struct mtd_info *mtd, unsigned int ops) 586 { 587 struct nand_chip *nand_chip = mtd_to_nand(mtd); 588 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 589 int bufs, i; 590 591 if (mtd->writesize > 512) 592 bufs = 4; 593 else 594 bufs = 1; 595 596 for (i = 0; i < bufs; i++) { 597 598 /* NANDFC buffer 0 is used for page read/write */ 599 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); 600 601 writew(ops, NFC_V1_V2_CONFIG2); 602 603 /* Wait for operation to complete */ 604 wait_op_done(host, true); 605 } 606 } 607 608 static void send_read_id_v3(struct mxc_nand_host *host) 609 { 610 /* Read ID into main buffer */ 611 writel(NFC_ID, NFC_V3_LAUNCH); 612 613 wait_op_done(host, true); 614 615 memcpy32_fromio(host->data_buf, host->main_area0, 16); 616 } 617 618 /* Request the NANDFC to perform a read of the NAND device ID. */ 619 static void send_read_id_v1_v2(struct mxc_nand_host *host) 620 { 621 /* NANDFC buffer 0 is used for device ID output */ 622 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 623 624 writew(NFC_ID, NFC_V1_V2_CONFIG2); 625 626 /* Wait for operation to complete */ 627 wait_op_done(host, true); 628 629 memcpy32_fromio(host->data_buf, host->main_area0, 16); 630 } 631 632 static uint16_t get_dev_status_v3(struct mxc_nand_host *host) 633 { 634 writew(NFC_STATUS, NFC_V3_LAUNCH); 635 wait_op_done(host, true); 636 637 return readl(NFC_V3_CONFIG1) >> 16; 638 } 639 640 /* This function requests the NANDFC to perform a read of the 641 * NAND device status and returns the current status. */ 642 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) 643 { 644 void __iomem *main_buf = host->main_area0; 645 uint32_t store; 646 uint16_t ret; 647 648 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 649 650 /* 651 * The device status is stored in main_area0. To 652 * prevent corruption of the buffer save the value 653 * and restore it afterwards. 654 */ 655 store = readl(main_buf); 656 657 writew(NFC_STATUS, NFC_V1_V2_CONFIG2); 658 wait_op_done(host, true); 659 660 ret = readw(main_buf); 661 662 writel(store, main_buf); 663 664 return ret; 665 } 666 667 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable) 668 { 669 struct mxc_nand_host *host = nand_get_controller_data(chip); 670 uint16_t config1; 671 672 if (chip->ecc.mode != NAND_ECC_HW) 673 return; 674 675 config1 = readw(NFC_V1_V2_CONFIG1); 676 677 if (enable) 678 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 679 else 680 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN; 681 682 writew(config1, NFC_V1_V2_CONFIG1); 683 } 684 685 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable) 686 { 687 struct mxc_nand_host *host = nand_get_controller_data(chip); 688 uint32_t config2; 689 690 if (chip->ecc.mode != NAND_ECC_HW) 691 return; 692 693 config2 = readl(NFC_V3_CONFIG2); 694 695 if (enable) 696 config2 |= NFC_V3_CONFIG2_ECC_EN; 697 else 698 config2 &= ~NFC_V3_CONFIG2_ECC_EN; 699 700 writel(config2, NFC_V3_CONFIG2); 701 } 702 703 /* This functions is used by upper layer to checks if device is ready */ 704 static int mxc_nand_dev_ready(struct nand_chip *chip) 705 { 706 /* 707 * NFC handles R/B internally. Therefore, this function 708 * always returns status as ready. 709 */ 710 return 1; 711 } 712 713 static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob, 714 bool ecc, int page) 715 { 716 struct mtd_info *mtd = nand_to_mtd(chip); 717 struct mxc_nand_host *host = nand_get_controller_data(chip); 718 unsigned int bitflips_corrected = 0; 719 int no_subpages; 720 int i; 721 722 host->devtype_data->enable_hwecc(chip, ecc); 723 724 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); 725 mxc_do_addr_cycle(mtd, 0, page); 726 727 if (mtd->writesize > 512) 728 host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true); 729 730 no_subpages = mtd->writesize >> 9; 731 732 for (i = 0; i < no_subpages; i++) { 733 uint16_t ecc_stats; 734 735 /* NANDFC buffer 0 is used for page read/write */ 736 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); 737 738 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2); 739 740 /* Wait for operation to complete */ 741 wait_op_done(host, true); 742 743 ecc_stats = get_ecc_status_v1(host); 744 745 ecc_stats >>= 2; 746 747 if (buf && ecc) { 748 switch (ecc_stats & 0x3) { 749 case 0: 750 default: 751 break; 752 case 1: 753 mtd->ecc_stats.corrected++; 754 bitflips_corrected = 1; 755 break; 756 case 2: 757 mtd->ecc_stats.failed++; 758 break; 759 } 760 } 761 } 762 763 if (buf) 764 memcpy32_fromio(buf, host->main_area0, mtd->writesize); 765 if (oob) 766 copy_spare(mtd, true, oob); 767 768 return bitflips_corrected; 769 } 770 771 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf, 772 void *oob, bool ecc, int page) 773 { 774 struct mtd_info *mtd = nand_to_mtd(chip); 775 struct mxc_nand_host *host = nand_get_controller_data(chip); 776 unsigned int max_bitflips = 0; 777 u32 ecc_stat, err; 778 int no_subpages; 779 u8 ecc_bit_mask, err_limit; 780 781 host->devtype_data->enable_hwecc(chip, ecc); 782 783 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); 784 mxc_do_addr_cycle(mtd, 0, page); 785 786 if (mtd->writesize > 512) 787 host->devtype_data->send_cmd(host, 788 NAND_CMD_READSTART, true); 789 790 host->devtype_data->send_page(mtd, NFC_OUTPUT); 791 792 if (buf) 793 memcpy32_fromio(buf, host->main_area0, mtd->writesize); 794 if (oob) 795 copy_spare(mtd, true, oob); 796 797 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; 798 err_limit = (host->eccsize == 4) ? 0x4 : 0x8; 799 800 no_subpages = mtd->writesize >> 9; 801 802 ecc_stat = host->devtype_data->get_ecc_status(host); 803 804 do { 805 err = ecc_stat & ecc_bit_mask; 806 if (err > err_limit) { 807 mtd->ecc_stats.failed++; 808 } else { 809 mtd->ecc_stats.corrected += err; 810 max_bitflips = max_t(unsigned int, max_bitflips, err); 811 } 812 813 ecc_stat >>= 4; 814 } while (--no_subpages); 815 816 return max_bitflips; 817 } 818 819 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf, 820 int oob_required, int page) 821 { 822 struct mxc_nand_host *host = nand_get_controller_data(chip); 823 void *oob_buf; 824 825 if (oob_required) 826 oob_buf = chip->oob_poi; 827 else 828 oob_buf = NULL; 829 830 return host->devtype_data->read_page(chip, buf, oob_buf, 1, page); 831 } 832 833 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, 834 int oob_required, int page) 835 { 836 struct mxc_nand_host *host = nand_get_controller_data(chip); 837 void *oob_buf; 838 839 if (oob_required) 840 oob_buf = chip->oob_poi; 841 else 842 oob_buf = NULL; 843 844 return host->devtype_data->read_page(chip, buf, oob_buf, 0, page); 845 } 846 847 static int mxc_nand_read_oob(struct nand_chip *chip, int page) 848 { 849 struct mxc_nand_host *host = nand_get_controller_data(chip); 850 851 return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0, 852 page); 853 } 854 855 static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf, 856 bool ecc, int page) 857 { 858 struct mtd_info *mtd = nand_to_mtd(chip); 859 struct mxc_nand_host *host = nand_get_controller_data(chip); 860 861 host->devtype_data->enable_hwecc(chip, ecc); 862 863 host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false); 864 mxc_do_addr_cycle(mtd, 0, page); 865 866 memcpy32_toio(host->main_area0, buf, mtd->writesize); 867 copy_spare(mtd, false, chip->oob_poi); 868 869 host->devtype_data->send_page(mtd, NFC_INPUT); 870 host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true); 871 mxc_do_addr_cycle(mtd, 0, page); 872 873 return 0; 874 } 875 876 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf, 877 int oob_required, int page) 878 { 879 return mxc_nand_write_page(chip, buf, true, page); 880 } 881 882 static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 883 int oob_required, int page) 884 { 885 return mxc_nand_write_page(chip, buf, false, page); 886 } 887 888 static int mxc_nand_write_oob(struct nand_chip *chip, int page) 889 { 890 struct mtd_info *mtd = nand_to_mtd(chip); 891 struct mxc_nand_host *host = nand_get_controller_data(chip); 892 893 memset(host->data_buf, 0xff, mtd->writesize); 894 895 return mxc_nand_write_page(chip, host->data_buf, false, page); 896 } 897 898 static u_char mxc_nand_read_byte(struct nand_chip *nand_chip) 899 { 900 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 901 uint8_t ret; 902 903 /* Check for status request */ 904 if (host->status_request) 905 return host->devtype_data->get_dev_status(host) & 0xFF; 906 907 if (nand_chip->options & NAND_BUSWIDTH_16) { 908 /* only take the lower byte of each word */ 909 ret = *(uint16_t *)(host->data_buf + host->buf_start); 910 911 host->buf_start += 2; 912 } else { 913 ret = *(uint8_t *)(host->data_buf + host->buf_start); 914 host->buf_start++; 915 } 916 917 dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start); 918 return ret; 919 } 920 921 /* Write data of length len to buffer buf. The data to be 922 * written on NAND Flash is first copied to RAMbuffer. After the Data Input 923 * Operation by the NFC, the data is written to NAND Flash */ 924 static void mxc_nand_write_buf(struct nand_chip *nand_chip, const u_char *buf, 925 int len) 926 { 927 struct mtd_info *mtd = nand_to_mtd(nand_chip); 928 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 929 u16 col = host->buf_start; 930 int n = mtd->oobsize + mtd->writesize - col; 931 932 n = min(n, len); 933 934 memcpy(host->data_buf + col, buf, n); 935 936 host->buf_start += n; 937 } 938 939 /* Read the data buffer from the NAND Flash. To read the data from NAND 940 * Flash first the data output cycle is initiated by the NFC, which copies 941 * the data to RAMbuffer. This data of length len is then copied to buffer buf. 942 */ 943 static void mxc_nand_read_buf(struct nand_chip *nand_chip, u_char *buf, 944 int len) 945 { 946 struct mtd_info *mtd = nand_to_mtd(nand_chip); 947 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 948 u16 col = host->buf_start; 949 int n = mtd->oobsize + mtd->writesize - col; 950 951 n = min(n, len); 952 953 memcpy(buf, host->data_buf + col, n); 954 955 host->buf_start += n; 956 } 957 958 /* This function is used by upper layer for select and 959 * deselect of the NAND chip */ 960 static void mxc_nand_select_chip_v1_v3(struct nand_chip *nand_chip, int chip) 961 { 962 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 963 964 if (chip == -1) { 965 /* Disable the NFC clock */ 966 if (host->clk_act) { 967 clk_disable_unprepare(host->clk); 968 host->clk_act = 0; 969 } 970 return; 971 } 972 973 if (!host->clk_act) { 974 /* Enable the NFC clock */ 975 clk_prepare_enable(host->clk); 976 host->clk_act = 1; 977 } 978 } 979 980 static void mxc_nand_select_chip_v2(struct nand_chip *nand_chip, int chip) 981 { 982 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 983 984 if (chip == -1) { 985 /* Disable the NFC clock */ 986 if (host->clk_act) { 987 clk_disable_unprepare(host->clk); 988 host->clk_act = 0; 989 } 990 return; 991 } 992 993 if (!host->clk_act) { 994 /* Enable the NFC clock */ 995 clk_prepare_enable(host->clk); 996 host->clk_act = 1; 997 } 998 999 host->active_cs = chip; 1000 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); 1001 } 1002 1003 #define MXC_V1_ECCBYTES 5 1004 1005 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section, 1006 struct mtd_oob_region *oobregion) 1007 { 1008 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1009 1010 if (section >= nand_chip->ecc.steps) 1011 return -ERANGE; 1012 1013 oobregion->offset = (section * 16) + 6; 1014 oobregion->length = MXC_V1_ECCBYTES; 1015 1016 return 0; 1017 } 1018 1019 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section, 1020 struct mtd_oob_region *oobregion) 1021 { 1022 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1023 1024 if (section > nand_chip->ecc.steps) 1025 return -ERANGE; 1026 1027 if (!section) { 1028 if (mtd->writesize <= 512) { 1029 oobregion->offset = 0; 1030 oobregion->length = 5; 1031 } else { 1032 oobregion->offset = 2; 1033 oobregion->length = 4; 1034 } 1035 } else { 1036 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6; 1037 if (section < nand_chip->ecc.steps) 1038 oobregion->length = (section * 16) + 6 - 1039 oobregion->offset; 1040 else 1041 oobregion->length = mtd->oobsize - oobregion->offset; 1042 } 1043 1044 return 0; 1045 } 1046 1047 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = { 1048 .ecc = mxc_v1_ooblayout_ecc, 1049 .free = mxc_v1_ooblayout_free, 1050 }; 1051 1052 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section, 1053 struct mtd_oob_region *oobregion) 1054 { 1055 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1056 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; 1057 1058 if (section >= nand_chip->ecc.steps) 1059 return -ERANGE; 1060 1061 oobregion->offset = (section * stepsize) + 7; 1062 oobregion->length = nand_chip->ecc.bytes; 1063 1064 return 0; 1065 } 1066 1067 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section, 1068 struct mtd_oob_region *oobregion) 1069 { 1070 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1071 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26; 1072 1073 if (section >= nand_chip->ecc.steps) 1074 return -ERANGE; 1075 1076 if (!section) { 1077 if (mtd->writesize <= 512) { 1078 oobregion->offset = 0; 1079 oobregion->length = 5; 1080 } else { 1081 oobregion->offset = 2; 1082 oobregion->length = 4; 1083 } 1084 } else { 1085 oobregion->offset = section * stepsize; 1086 oobregion->length = 7; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = { 1093 .ecc = mxc_v2_ooblayout_ecc, 1094 .free = mxc_v2_ooblayout_free, 1095 }; 1096 1097 /* 1098 * v2 and v3 type controllers can do 4bit or 8bit ecc depending 1099 * on how much oob the nand chip has. For 8bit ecc we need at least 1100 * 26 bytes of oob data per 512 byte block. 1101 */ 1102 static int get_eccsize(struct mtd_info *mtd) 1103 { 1104 int oobbytes_per_512 = 0; 1105 1106 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; 1107 1108 if (oobbytes_per_512 < 26) 1109 return 4; 1110 else 1111 return 8; 1112 } 1113 1114 static void preset_v1(struct mtd_info *mtd) 1115 { 1116 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1117 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1118 uint16_t config1 = 0; 1119 1120 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize) 1121 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1122 1123 if (!host->devtype_data->irqpending_quirk) 1124 config1 |= NFC_V1_V2_CONFIG1_INT_MSK; 1125 1126 host->eccsize = 1; 1127 1128 writew(config1, NFC_V1_V2_CONFIG1); 1129 /* preset operation */ 1130 1131 /* Unlock the internal RAM Buffer */ 1132 writew(0x2, NFC_V1_V2_CONFIG); 1133 1134 /* Blocks to be unlocked */ 1135 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); 1136 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); 1137 1138 /* Unlock Block Command for given address range */ 1139 writew(0x4, NFC_V1_V2_WRPROT); 1140 } 1141 1142 static int mxc_nand_v2_setup_data_interface(struct nand_chip *chip, int csline, 1143 const struct nand_data_interface *conf) 1144 { 1145 struct mxc_nand_host *host = nand_get_controller_data(chip); 1146 int tRC_min_ns, tRC_ps, ret; 1147 unsigned long rate, rate_round; 1148 const struct nand_sdr_timings *timings; 1149 u16 config1; 1150 1151 timings = nand_get_sdr_timings(conf); 1152 if (IS_ERR(timings)) 1153 return -ENOTSUPP; 1154 1155 config1 = readw(NFC_V1_V2_CONFIG1); 1156 1157 tRC_min_ns = timings->tRC_min / 1000; 1158 rate = 1000000000 / tRC_min_ns; 1159 1160 /* 1161 * For tRC < 30ns we have to use EDO mode. In this case the controller 1162 * does one access per clock cycle. Otherwise the controller does one 1163 * access in two clock cycles, thus we have to double the rate to the 1164 * controller. 1165 */ 1166 if (tRC_min_ns < 30) { 1167 rate_round = clk_round_rate(host->clk, rate); 1168 config1 |= NFC_V2_CONFIG1_ONE_CYCLE; 1169 tRC_ps = 1000000000 / (rate_round / 1000); 1170 } else { 1171 rate *= 2; 1172 rate_round = clk_round_rate(host->clk, rate); 1173 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE; 1174 tRC_ps = 1000000000 / (rate_round / 1000 / 2); 1175 } 1176 1177 /* 1178 * The timing values compared against are from the i.MX25 Automotive 1179 * datasheet, Table 50. NFC Timing Parameters 1180 */ 1181 if (timings->tCLS_min > tRC_ps - 1000 || 1182 timings->tCLH_min > tRC_ps - 2000 || 1183 timings->tCS_min > tRC_ps - 1000 || 1184 timings->tCH_min > tRC_ps - 2000 || 1185 timings->tWP_min > tRC_ps - 1500 || 1186 timings->tALS_min > tRC_ps || 1187 timings->tALH_min > tRC_ps - 3000 || 1188 timings->tDS_min > tRC_ps || 1189 timings->tDH_min > tRC_ps - 5000 || 1190 timings->tWC_min > 2 * tRC_ps || 1191 timings->tWH_min > tRC_ps - 2500 || 1192 timings->tRR_min > 6 * tRC_ps || 1193 timings->tRP_min > 3 * tRC_ps / 2 || 1194 timings->tRC_min > 2 * tRC_ps || 1195 timings->tREH_min > (tRC_ps / 2) - 2500) { 1196 dev_dbg(host->dev, "Timing out of bounds\n"); 1197 return -EINVAL; 1198 } 1199 1200 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1201 return 0; 1202 1203 ret = clk_set_rate(host->clk, rate); 1204 if (ret) 1205 return ret; 1206 1207 writew(config1, NFC_V1_V2_CONFIG1); 1208 1209 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round, 1210 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" : 1211 "normal"); 1212 1213 return 0; 1214 } 1215 1216 static void preset_v2(struct mtd_info *mtd) 1217 { 1218 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1219 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1220 uint16_t config1 = 0; 1221 1222 config1 |= NFC_V2_CONFIG1_FP_INT; 1223 1224 if (!host->devtype_data->irqpending_quirk) 1225 config1 |= NFC_V1_V2_CONFIG1_INT_MSK; 1226 1227 if (mtd->writesize) { 1228 uint16_t pages_per_block = mtd->erasesize / mtd->writesize; 1229 1230 if (nand_chip->ecc.mode == NAND_ECC_HW) 1231 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1232 1233 host->eccsize = get_eccsize(mtd); 1234 if (host->eccsize == 4) 1235 config1 |= NFC_V2_CONFIG1_ECC_MODE_4; 1236 1237 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); 1238 } else { 1239 host->eccsize = 1; 1240 } 1241 1242 writew(config1, NFC_V1_V2_CONFIG1); 1243 /* preset operation */ 1244 1245 /* spare area size in 16-bit half-words */ 1246 writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA); 1247 1248 /* Unlock the internal RAM Buffer */ 1249 writew(0x2, NFC_V1_V2_CONFIG); 1250 1251 /* Blocks to be unlocked */ 1252 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); 1253 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); 1254 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); 1255 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); 1256 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); 1257 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); 1258 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); 1259 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); 1260 1261 /* Unlock Block Command for given address range */ 1262 writew(0x4, NFC_V1_V2_WRPROT); 1263 } 1264 1265 static void preset_v3(struct mtd_info *mtd) 1266 { 1267 struct nand_chip *chip = mtd_to_nand(mtd); 1268 struct mxc_nand_host *host = nand_get_controller_data(chip); 1269 uint32_t config2, config3; 1270 int i, addr_phases; 1271 1272 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); 1273 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); 1274 1275 /* Unlock the internal RAM Buffer */ 1276 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, 1277 NFC_V3_WRPROT); 1278 1279 /* Blocks to be unlocked */ 1280 for (i = 0; i < NAND_MAX_CHIPS; i++) 1281 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); 1282 1283 writel(0, NFC_V3_IPC); 1284 1285 config2 = NFC_V3_CONFIG2_ONE_CYCLE | 1286 NFC_V3_CONFIG2_2CMD_PHASES | 1287 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | 1288 NFC_V3_CONFIG2_ST_CMD(0x70) | 1289 NFC_V3_CONFIG2_INT_MSK | 1290 NFC_V3_CONFIG2_NUM_ADDR_PHASE0; 1291 1292 addr_phases = fls(chip->pagemask) >> 3; 1293 1294 if (mtd->writesize == 2048) { 1295 config2 |= NFC_V3_CONFIG2_PS_2048; 1296 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); 1297 } else if (mtd->writesize == 4096) { 1298 config2 |= NFC_V3_CONFIG2_PS_4096; 1299 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); 1300 } else { 1301 config2 |= NFC_V3_CONFIG2_PS_512; 1302 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); 1303 } 1304 1305 if (mtd->writesize) { 1306 if (chip->ecc.mode == NAND_ECC_HW) 1307 config2 |= NFC_V3_CONFIG2_ECC_EN; 1308 1309 config2 |= NFC_V3_CONFIG2_PPB( 1310 ffs(mtd->erasesize / mtd->writesize) - 6, 1311 host->devtype_data->ppb_shift); 1312 host->eccsize = get_eccsize(mtd); 1313 if (host->eccsize == 8) 1314 config2 |= NFC_V3_CONFIG2_ECC_MODE_8; 1315 } 1316 1317 writel(config2, NFC_V3_CONFIG2); 1318 1319 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | 1320 NFC_V3_CONFIG3_NO_SDMA | 1321 NFC_V3_CONFIG3_RBB_MODE | 1322 NFC_V3_CONFIG3_SBB(6) | /* Reset default */ 1323 NFC_V3_CONFIG3_ADD_OP(0); 1324 1325 if (!(chip->options & NAND_BUSWIDTH_16)) 1326 config3 |= NFC_V3_CONFIG3_FW8; 1327 1328 writel(config3, NFC_V3_CONFIG3); 1329 1330 writel(0, NFC_V3_DELAY_LINE); 1331 } 1332 1333 /* Used by the upper layer to write command to NAND Flash for 1334 * different operations to be carried out on NAND Flash */ 1335 static void mxc_nand_command(struct nand_chip *nand_chip, unsigned command, 1336 int column, int page_addr) 1337 { 1338 struct mtd_info *mtd = nand_to_mtd(nand_chip); 1339 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1340 1341 dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", 1342 command, column, page_addr); 1343 1344 /* Reset command state information */ 1345 host->status_request = false; 1346 1347 /* Command pre-processing step */ 1348 switch (command) { 1349 case NAND_CMD_RESET: 1350 host->devtype_data->preset(mtd); 1351 host->devtype_data->send_cmd(host, command, false); 1352 break; 1353 1354 case NAND_CMD_STATUS: 1355 host->buf_start = 0; 1356 host->status_request = true; 1357 1358 host->devtype_data->send_cmd(host, command, true); 1359 WARN_ONCE(column != -1 || page_addr != -1, 1360 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n", 1361 command, column, page_addr); 1362 mxc_do_addr_cycle(mtd, column, page_addr); 1363 break; 1364 1365 case NAND_CMD_READID: 1366 host->devtype_data->send_cmd(host, command, true); 1367 mxc_do_addr_cycle(mtd, column, page_addr); 1368 host->devtype_data->send_read_id(host); 1369 host->buf_start = 0; 1370 break; 1371 1372 case NAND_CMD_ERASE1: 1373 case NAND_CMD_ERASE2: 1374 host->devtype_data->send_cmd(host, command, false); 1375 WARN_ONCE(column != -1, 1376 "Unexpected column value (cmd=%u, col=%d)\n", 1377 command, column); 1378 mxc_do_addr_cycle(mtd, column, page_addr); 1379 1380 break; 1381 case NAND_CMD_PARAM: 1382 host->devtype_data->send_cmd(host, command, false); 1383 mxc_do_addr_cycle(mtd, column, page_addr); 1384 host->devtype_data->send_page(mtd, NFC_OUTPUT); 1385 memcpy32_fromio(host->data_buf, host->main_area0, 512); 1386 host->buf_start = 0; 1387 break; 1388 default: 1389 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n", 1390 command); 1391 break; 1392 } 1393 } 1394 1395 static int mxc_nand_set_features(struct nand_chip *chip, int addr, 1396 u8 *subfeature_param) 1397 { 1398 struct mtd_info *mtd = nand_to_mtd(chip); 1399 struct mxc_nand_host *host = nand_get_controller_data(chip); 1400 int i; 1401 1402 host->buf_start = 0; 1403 1404 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1405 chip->legacy.write_byte(chip, subfeature_param[i]); 1406 1407 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); 1408 host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false); 1409 mxc_do_addr_cycle(mtd, addr, -1); 1410 host->devtype_data->send_page(mtd, NFC_INPUT); 1411 1412 return 0; 1413 } 1414 1415 static int mxc_nand_get_features(struct nand_chip *chip, int addr, 1416 u8 *subfeature_param) 1417 { 1418 struct mtd_info *mtd = nand_to_mtd(chip); 1419 struct mxc_nand_host *host = nand_get_controller_data(chip); 1420 int i; 1421 1422 host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false); 1423 mxc_do_addr_cycle(mtd, addr, -1); 1424 host->devtype_data->send_page(mtd, NFC_OUTPUT); 1425 memcpy32_fromio(host->data_buf, host->main_area0, 512); 1426 host->buf_start = 0; 1427 1428 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1429 *subfeature_param++ = chip->legacy.read_byte(chip); 1430 1431 return 0; 1432 } 1433 1434 /* 1435 * The generic flash bbt decriptors overlap with our ecc 1436 * hardware, so define some i.MX specific ones. 1437 */ 1438 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; 1439 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; 1440 1441 static struct nand_bbt_descr bbt_main_descr = { 1442 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 1443 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1444 .offs = 0, 1445 .len = 4, 1446 .veroffs = 4, 1447 .maxblocks = 4, 1448 .pattern = bbt_pattern, 1449 }; 1450 1451 static struct nand_bbt_descr bbt_mirror_descr = { 1452 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 1453 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1454 .offs = 0, 1455 .len = 4, 1456 .veroffs = 4, 1457 .maxblocks = 4, 1458 .pattern = mirror_pattern, 1459 }; 1460 1461 /* v1 + irqpending_quirk: i.MX21 */ 1462 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { 1463 .preset = preset_v1, 1464 .read_page = mxc_nand_read_page_v1, 1465 .send_cmd = send_cmd_v1_v2, 1466 .send_addr = send_addr_v1_v2, 1467 .send_page = send_page_v1, 1468 .send_read_id = send_read_id_v1_v2, 1469 .get_dev_status = get_dev_status_v1_v2, 1470 .check_int = check_int_v1_v2, 1471 .irq_control = irq_control_v1_v2, 1472 .get_ecc_status = get_ecc_status_v1, 1473 .ooblayout = &mxc_v1_ooblayout_ops, 1474 .select_chip = mxc_nand_select_chip_v1_v3, 1475 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1476 .irqpending_quirk = 1, 1477 .needs_ip = 0, 1478 .regs_offset = 0xe00, 1479 .spare0_offset = 0x800, 1480 .spare_len = 16, 1481 .eccbytes = 3, 1482 .eccsize = 1, 1483 }; 1484 1485 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ 1486 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { 1487 .preset = preset_v1, 1488 .read_page = mxc_nand_read_page_v1, 1489 .send_cmd = send_cmd_v1_v2, 1490 .send_addr = send_addr_v1_v2, 1491 .send_page = send_page_v1, 1492 .send_read_id = send_read_id_v1_v2, 1493 .get_dev_status = get_dev_status_v1_v2, 1494 .check_int = check_int_v1_v2, 1495 .irq_control = irq_control_v1_v2, 1496 .get_ecc_status = get_ecc_status_v1, 1497 .ooblayout = &mxc_v1_ooblayout_ops, 1498 .select_chip = mxc_nand_select_chip_v1_v3, 1499 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1500 .irqpending_quirk = 0, 1501 .needs_ip = 0, 1502 .regs_offset = 0xe00, 1503 .spare0_offset = 0x800, 1504 .axi_offset = 0, 1505 .spare_len = 16, 1506 .eccbytes = 3, 1507 .eccsize = 1, 1508 }; 1509 1510 /* v21: i.MX25, i.MX35 */ 1511 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { 1512 .preset = preset_v2, 1513 .read_page = mxc_nand_read_page_v2_v3, 1514 .send_cmd = send_cmd_v1_v2, 1515 .send_addr = send_addr_v1_v2, 1516 .send_page = send_page_v2, 1517 .send_read_id = send_read_id_v1_v2, 1518 .get_dev_status = get_dev_status_v1_v2, 1519 .check_int = check_int_v1_v2, 1520 .irq_control = irq_control_v1_v2, 1521 .get_ecc_status = get_ecc_status_v2, 1522 .ooblayout = &mxc_v2_ooblayout_ops, 1523 .select_chip = mxc_nand_select_chip_v2, 1524 .setup_data_interface = mxc_nand_v2_setup_data_interface, 1525 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2, 1526 .irqpending_quirk = 0, 1527 .needs_ip = 0, 1528 .regs_offset = 0x1e00, 1529 .spare0_offset = 0x1000, 1530 .axi_offset = 0, 1531 .spare_len = 64, 1532 .eccbytes = 9, 1533 .eccsize = 0, 1534 }; 1535 1536 /* v3.2a: i.MX51 */ 1537 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { 1538 .preset = preset_v3, 1539 .read_page = mxc_nand_read_page_v2_v3, 1540 .send_cmd = send_cmd_v3, 1541 .send_addr = send_addr_v3, 1542 .send_page = send_page_v3, 1543 .send_read_id = send_read_id_v3, 1544 .get_dev_status = get_dev_status_v3, 1545 .check_int = check_int_v3, 1546 .irq_control = irq_control_v3, 1547 .get_ecc_status = get_ecc_status_v3, 1548 .ooblayout = &mxc_v2_ooblayout_ops, 1549 .select_chip = mxc_nand_select_chip_v1_v3, 1550 .enable_hwecc = mxc_nand_enable_hwecc_v3, 1551 .irqpending_quirk = 0, 1552 .needs_ip = 1, 1553 .regs_offset = 0, 1554 .spare0_offset = 0x1000, 1555 .axi_offset = 0x1e00, 1556 .spare_len = 64, 1557 .eccbytes = 0, 1558 .eccsize = 0, 1559 .ppb_shift = 7, 1560 }; 1561 1562 /* v3.2b: i.MX53 */ 1563 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = { 1564 .preset = preset_v3, 1565 .read_page = mxc_nand_read_page_v2_v3, 1566 .send_cmd = send_cmd_v3, 1567 .send_addr = send_addr_v3, 1568 .send_page = send_page_v3, 1569 .send_read_id = send_read_id_v3, 1570 .get_dev_status = get_dev_status_v3, 1571 .check_int = check_int_v3, 1572 .irq_control = irq_control_v3, 1573 .get_ecc_status = get_ecc_status_v3, 1574 .ooblayout = &mxc_v2_ooblayout_ops, 1575 .select_chip = mxc_nand_select_chip_v1_v3, 1576 .enable_hwecc = mxc_nand_enable_hwecc_v3, 1577 .irqpending_quirk = 0, 1578 .needs_ip = 1, 1579 .regs_offset = 0, 1580 .spare0_offset = 0x1000, 1581 .axi_offset = 0x1e00, 1582 .spare_len = 64, 1583 .eccbytes = 0, 1584 .eccsize = 0, 1585 .ppb_shift = 8, 1586 }; 1587 1588 static inline int is_imx21_nfc(struct mxc_nand_host *host) 1589 { 1590 return host->devtype_data == &imx21_nand_devtype_data; 1591 } 1592 1593 static inline int is_imx27_nfc(struct mxc_nand_host *host) 1594 { 1595 return host->devtype_data == &imx27_nand_devtype_data; 1596 } 1597 1598 static inline int is_imx25_nfc(struct mxc_nand_host *host) 1599 { 1600 return host->devtype_data == &imx25_nand_devtype_data; 1601 } 1602 1603 static inline int is_imx51_nfc(struct mxc_nand_host *host) 1604 { 1605 return host->devtype_data == &imx51_nand_devtype_data; 1606 } 1607 1608 static inline int is_imx53_nfc(struct mxc_nand_host *host) 1609 { 1610 return host->devtype_data == &imx53_nand_devtype_data; 1611 } 1612 1613 static const struct platform_device_id mxcnd_devtype[] = { 1614 { 1615 .name = "imx21-nand", 1616 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data, 1617 }, { 1618 .name = "imx27-nand", 1619 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data, 1620 }, { 1621 .name = "imx25-nand", 1622 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data, 1623 }, { 1624 .name = "imx51-nand", 1625 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data, 1626 }, { 1627 .name = "imx53-nand", 1628 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data, 1629 }, { 1630 /* sentinel */ 1631 } 1632 }; 1633 MODULE_DEVICE_TABLE(platform, mxcnd_devtype); 1634 1635 #ifdef CONFIG_OF 1636 static const struct of_device_id mxcnd_dt_ids[] = { 1637 { 1638 .compatible = "fsl,imx21-nand", 1639 .data = &imx21_nand_devtype_data, 1640 }, { 1641 .compatible = "fsl,imx27-nand", 1642 .data = &imx27_nand_devtype_data, 1643 }, { 1644 .compatible = "fsl,imx25-nand", 1645 .data = &imx25_nand_devtype_data, 1646 }, { 1647 .compatible = "fsl,imx51-nand", 1648 .data = &imx51_nand_devtype_data, 1649 }, { 1650 .compatible = "fsl,imx53-nand", 1651 .data = &imx53_nand_devtype_data, 1652 }, 1653 { /* sentinel */ } 1654 }; 1655 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids); 1656 1657 static int mxcnd_probe_dt(struct mxc_nand_host *host) 1658 { 1659 struct device_node *np = host->dev->of_node; 1660 const struct of_device_id *of_id = 1661 of_match_device(mxcnd_dt_ids, host->dev); 1662 1663 if (!np) 1664 return 1; 1665 1666 host->devtype_data = of_id->data; 1667 1668 return 0; 1669 } 1670 #else 1671 static int mxcnd_probe_dt(struct mxc_nand_host *host) 1672 { 1673 return 1; 1674 } 1675 #endif 1676 1677 static int mxcnd_attach_chip(struct nand_chip *chip) 1678 { 1679 struct mtd_info *mtd = nand_to_mtd(chip); 1680 struct mxc_nand_host *host = nand_get_controller_data(chip); 1681 struct device *dev = mtd->dev.parent; 1682 1683 switch (chip->ecc.mode) { 1684 case NAND_ECC_HW: 1685 chip->ecc.read_page = mxc_nand_read_page; 1686 chip->ecc.read_page_raw = mxc_nand_read_page_raw; 1687 chip->ecc.read_oob = mxc_nand_read_oob; 1688 chip->ecc.write_page = mxc_nand_write_page_ecc; 1689 chip->ecc.write_page_raw = mxc_nand_write_page_raw; 1690 chip->ecc.write_oob = mxc_nand_write_oob; 1691 break; 1692 1693 case NAND_ECC_SOFT: 1694 break; 1695 1696 default: 1697 return -EINVAL; 1698 } 1699 1700 if (chip->bbt_options & NAND_BBT_USE_FLASH) { 1701 chip->bbt_td = &bbt_main_descr; 1702 chip->bbt_md = &bbt_mirror_descr; 1703 } 1704 1705 /* Allocate the right size buffer now */ 1706 devm_kfree(dev, (void *)host->data_buf); 1707 host->data_buf = devm_kzalloc(dev, mtd->writesize + mtd->oobsize, 1708 GFP_KERNEL); 1709 if (!host->data_buf) 1710 return -ENOMEM; 1711 1712 /* Call preset again, with correct writesize chip time */ 1713 host->devtype_data->preset(mtd); 1714 1715 if (!chip->ecc.bytes) { 1716 if (host->eccsize == 8) 1717 chip->ecc.bytes = 18; 1718 else if (host->eccsize == 4) 1719 chip->ecc.bytes = 9; 1720 } 1721 1722 /* 1723 * Experimentation shows that i.MX NFC can only handle up to 218 oob 1724 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare() 1725 * into copying invalid data to/from the spare IO buffer, as this 1726 * might cause ECC data corruption when doing sub-page write to a 1727 * partially written page. 1728 */ 1729 host->used_oobsize = min(mtd->oobsize, 218U); 1730 1731 if (chip->ecc.mode == NAND_ECC_HW) { 1732 if (is_imx21_nfc(host) || is_imx27_nfc(host)) 1733 chip->ecc.strength = 1; 1734 else 1735 chip->ecc.strength = (host->eccsize == 4) ? 4 : 8; 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int mxcnd_setup_data_interface(struct nand_chip *chip, int chipnr, 1742 const struct nand_data_interface *conf) 1743 { 1744 struct mxc_nand_host *host = nand_get_controller_data(chip); 1745 1746 return host->devtype_data->setup_data_interface(chip, chipnr, conf); 1747 } 1748 1749 static const struct nand_controller_ops mxcnd_controller_ops = { 1750 .attach_chip = mxcnd_attach_chip, 1751 .setup_data_interface = mxcnd_setup_data_interface, 1752 }; 1753 1754 static int mxcnd_probe(struct platform_device *pdev) 1755 { 1756 struct nand_chip *this; 1757 struct mtd_info *mtd; 1758 struct mxc_nand_host *host; 1759 struct resource *res; 1760 int err = 0; 1761 1762 /* Allocate memory for MTD device structure and private data */ 1763 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host), 1764 GFP_KERNEL); 1765 if (!host) 1766 return -ENOMEM; 1767 1768 /* allocate a temporary buffer for the nand_scan_ident() */ 1769 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL); 1770 if (!host->data_buf) 1771 return -ENOMEM; 1772 1773 host->dev = &pdev->dev; 1774 /* structures must be linked */ 1775 this = &host->nand; 1776 mtd = nand_to_mtd(this); 1777 mtd->dev.parent = &pdev->dev; 1778 mtd->name = DRIVER_NAME; 1779 1780 /* 50 us command delay time */ 1781 this->legacy.chip_delay = 5; 1782 1783 nand_set_controller_data(this, host); 1784 nand_set_flash_node(this, pdev->dev.of_node), 1785 this->legacy.dev_ready = mxc_nand_dev_ready; 1786 this->legacy.cmdfunc = mxc_nand_command; 1787 this->legacy.read_byte = mxc_nand_read_byte; 1788 this->legacy.write_buf = mxc_nand_write_buf; 1789 this->legacy.read_buf = mxc_nand_read_buf; 1790 this->legacy.set_features = mxc_nand_set_features; 1791 this->legacy.get_features = mxc_nand_get_features; 1792 1793 host->clk = devm_clk_get(&pdev->dev, NULL); 1794 if (IS_ERR(host->clk)) 1795 return PTR_ERR(host->clk); 1796 1797 err = mxcnd_probe_dt(host); 1798 if (err > 0) { 1799 struct mxc_nand_platform_data *pdata = 1800 dev_get_platdata(&pdev->dev); 1801 if (pdata) { 1802 host->pdata = *pdata; 1803 host->devtype_data = (struct mxc_nand_devtype_data *) 1804 pdev->id_entry->driver_data; 1805 } else { 1806 err = -ENODEV; 1807 } 1808 } 1809 if (err < 0) 1810 return err; 1811 1812 if (!host->devtype_data->setup_data_interface) 1813 this->options |= NAND_KEEP_TIMINGS; 1814 1815 if (host->devtype_data->needs_ip) { 1816 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1817 host->regs_ip = devm_ioremap_resource(&pdev->dev, res); 1818 if (IS_ERR(host->regs_ip)) 1819 return PTR_ERR(host->regs_ip); 1820 1821 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1822 } else { 1823 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1824 } 1825 1826 host->base = devm_ioremap_resource(&pdev->dev, res); 1827 if (IS_ERR(host->base)) 1828 return PTR_ERR(host->base); 1829 1830 host->main_area0 = host->base; 1831 1832 if (host->devtype_data->regs_offset) 1833 host->regs = host->base + host->devtype_data->regs_offset; 1834 host->spare0 = host->base + host->devtype_data->spare0_offset; 1835 if (host->devtype_data->axi_offset) 1836 host->regs_axi = host->base + host->devtype_data->axi_offset; 1837 1838 this->ecc.bytes = host->devtype_data->eccbytes; 1839 host->eccsize = host->devtype_data->eccsize; 1840 1841 this->legacy.select_chip = host->devtype_data->select_chip; 1842 this->ecc.size = 512; 1843 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout); 1844 1845 if (host->pdata.hw_ecc) { 1846 this->ecc.mode = NAND_ECC_HW; 1847 } else { 1848 this->ecc.mode = NAND_ECC_SOFT; 1849 this->ecc.algo = NAND_ECC_HAMMING; 1850 } 1851 1852 /* NAND bus width determines access functions used by upper layer */ 1853 if (host->pdata.width == 2) 1854 this->options |= NAND_BUSWIDTH_16; 1855 1856 /* update flash based bbt */ 1857 if (host->pdata.flash_bbt) 1858 this->bbt_options |= NAND_BBT_USE_FLASH; 1859 1860 init_completion(&host->op_completion); 1861 1862 host->irq = platform_get_irq(pdev, 0); 1863 if (host->irq < 0) 1864 return host->irq; 1865 1866 /* 1867 * Use host->devtype_data->irq_control() here instead of irq_control() 1868 * because we must not disable_irq_nosync without having requested the 1869 * irq. 1870 */ 1871 host->devtype_data->irq_control(host, 0); 1872 1873 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq, 1874 0, DRIVER_NAME, host); 1875 if (err) 1876 return err; 1877 1878 err = clk_prepare_enable(host->clk); 1879 if (err) 1880 return err; 1881 host->clk_act = 1; 1882 1883 /* 1884 * Now that we "own" the interrupt make sure the interrupt mask bit is 1885 * cleared on i.MX21. Otherwise we can't read the interrupt status bit 1886 * on this machine. 1887 */ 1888 if (host->devtype_data->irqpending_quirk) { 1889 disable_irq_nosync(host->irq); 1890 host->devtype_data->irq_control(host, 1); 1891 } 1892 1893 /* Scan the NAND device */ 1894 this->legacy.dummy_controller.ops = &mxcnd_controller_ops; 1895 err = nand_scan(this, is_imx25_nfc(host) ? 4 : 1); 1896 if (err) 1897 goto escan; 1898 1899 /* Register the partitions */ 1900 err = mtd_device_parse_register(mtd, part_probes, NULL, 1901 host->pdata.parts, 1902 host->pdata.nr_parts); 1903 if (err) 1904 goto cleanup_nand; 1905 1906 platform_set_drvdata(pdev, host); 1907 1908 return 0; 1909 1910 cleanup_nand: 1911 nand_cleanup(this); 1912 escan: 1913 if (host->clk_act) 1914 clk_disable_unprepare(host->clk); 1915 1916 return err; 1917 } 1918 1919 static int mxcnd_remove(struct platform_device *pdev) 1920 { 1921 struct mxc_nand_host *host = platform_get_drvdata(pdev); 1922 1923 nand_release(&host->nand); 1924 if (host->clk_act) 1925 clk_disable_unprepare(host->clk); 1926 1927 return 0; 1928 } 1929 1930 static struct platform_driver mxcnd_driver = { 1931 .driver = { 1932 .name = DRIVER_NAME, 1933 .of_match_table = of_match_ptr(mxcnd_dt_ids), 1934 }, 1935 .id_table = mxcnd_devtype, 1936 .probe = mxcnd_probe, 1937 .remove = mxcnd_remove, 1938 }; 1939 module_platform_driver(mxcnd_driver); 1940 1941 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1942 MODULE_DESCRIPTION("MXC NAND MTD driver"); 1943 MODULE_LICENSE("GPL"); 1944