1 /* 2 * MTK NAND Flash controller driver. 3 * Copyright (C) 2016 MediaTek Inc. 4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com> 5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/platform_device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/clk.h> 22 #include <linux/mtd/rawnand.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/module.h> 25 #include <linux/iopoll.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include "mtk_ecc.h" 29 30 /* NAND controller register definition */ 31 #define NFI_CNFG (0x00) 32 #define CNFG_AHB BIT(0) 33 #define CNFG_READ_EN BIT(1) 34 #define CNFG_DMA_BURST_EN BIT(2) 35 #define CNFG_BYTE_RW BIT(6) 36 #define CNFG_HW_ECC_EN BIT(8) 37 #define CNFG_AUTO_FMT_EN BIT(9) 38 #define CNFG_OP_CUST (6 << 12) 39 #define NFI_PAGEFMT (0x04) 40 #define PAGEFMT_FDM_ECC_SHIFT (12) 41 #define PAGEFMT_FDM_SHIFT (8) 42 #define PAGEFMT_SEC_SEL_512 BIT(2) 43 #define PAGEFMT_512_2K (0) 44 #define PAGEFMT_2K_4K (1) 45 #define PAGEFMT_4K_8K (2) 46 #define PAGEFMT_8K_16K (3) 47 /* NFI control */ 48 #define NFI_CON (0x08) 49 #define CON_FIFO_FLUSH BIT(0) 50 #define CON_NFI_RST BIT(1) 51 #define CON_BRD BIT(8) /* burst read */ 52 #define CON_BWR BIT(9) /* burst write */ 53 #define CON_SEC_SHIFT (12) 54 /* Timming control register */ 55 #define NFI_ACCCON (0x0C) 56 #define NFI_INTR_EN (0x10) 57 #define INTR_AHB_DONE_EN BIT(6) 58 #define NFI_INTR_STA (0x14) 59 #define NFI_CMD (0x20) 60 #define NFI_ADDRNOB (0x30) 61 #define NFI_COLADDR (0x34) 62 #define NFI_ROWADDR (0x38) 63 #define NFI_STRDATA (0x40) 64 #define STAR_EN (1) 65 #define STAR_DE (0) 66 #define NFI_CNRNB (0x44) 67 #define NFI_DATAW (0x50) 68 #define NFI_DATAR (0x54) 69 #define NFI_PIO_DIRDY (0x58) 70 #define PIO_DI_RDY (0x01) 71 #define NFI_STA (0x60) 72 #define STA_CMD BIT(0) 73 #define STA_ADDR BIT(1) 74 #define STA_BUSY BIT(8) 75 #define STA_EMP_PAGE BIT(12) 76 #define NFI_FSM_CUSTDATA (0xe << 16) 77 #define NFI_FSM_MASK (0xf << 16) 78 #define NFI_ADDRCNTR (0x70) 79 #define CNTR_MASK GENMASK(16, 12) 80 #define ADDRCNTR_SEC_SHIFT (12) 81 #define ADDRCNTR_SEC(val) \ 82 (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT) 83 #define NFI_STRADDR (0x80) 84 #define NFI_BYTELEN (0x84) 85 #define NFI_CSEL (0x90) 86 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2) 87 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2) 88 #define NFI_FDM_MAX_SIZE (8) 89 #define NFI_FDM_MIN_SIZE (1) 90 #define NFI_MASTER_STA (0x224) 91 #define MASTER_STA_MASK (0x0FFF) 92 #define NFI_EMPTY_THRESH (0x23C) 93 94 #define MTK_NAME "mtk-nand" 95 #define KB(x) ((x) * 1024UL) 96 #define MB(x) (KB(x) * 1024UL) 97 98 #define MTK_TIMEOUT (500000) 99 #define MTK_RESET_TIMEOUT (1000000) 100 #define MTK_NAND_MAX_NSELS (2) 101 #define MTK_NFC_MIN_SPARE (16) 102 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \ 103 ((tpoecs) << 28 | (tprecs) << 22 | (tc2r) << 16 | \ 104 (tw2r) << 12 | (twh) << 8 | (twst) << 4 | (trlt)) 105 106 struct mtk_nfc_caps { 107 const u8 *spare_size; 108 u8 num_spare_size; 109 u8 pageformat_spare_shift; 110 u8 nfi_clk_div; 111 u8 max_sector; 112 u32 max_sector_size; 113 }; 114 115 struct mtk_nfc_bad_mark_ctl { 116 void (*bm_swap)(struct mtd_info *, u8 *buf, int raw); 117 u32 sec; 118 u32 pos; 119 }; 120 121 /* 122 * FDM: region used to store free OOB data 123 */ 124 struct mtk_nfc_fdm { 125 u32 reg_size; 126 u32 ecc_size; 127 }; 128 129 struct mtk_nfc_nand_chip { 130 struct list_head node; 131 struct nand_chip nand; 132 133 struct mtk_nfc_bad_mark_ctl bad_mark; 134 struct mtk_nfc_fdm fdm; 135 u32 spare_per_sector; 136 137 int nsels; 138 u8 sels[0]; 139 /* nothing after this field */ 140 }; 141 142 struct mtk_nfc_clk { 143 struct clk *nfi_clk; 144 struct clk *pad_clk; 145 }; 146 147 struct mtk_nfc { 148 struct nand_hw_control controller; 149 struct mtk_ecc_config ecc_cfg; 150 struct mtk_nfc_clk clk; 151 struct mtk_ecc *ecc; 152 153 struct device *dev; 154 const struct mtk_nfc_caps *caps; 155 void __iomem *regs; 156 157 struct completion done; 158 struct list_head chips; 159 160 u8 *buffer; 161 }; 162 163 /* 164 * supported spare size of each IP. 165 * order should be the same with the spare size bitfiled defination of 166 * register NFI_PAGEFMT. 167 */ 168 static const u8 spare_size_mt2701[] = { 169 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64 170 }; 171 172 static const u8 spare_size_mt2712[] = { 173 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, 174 74 175 }; 176 177 static const u8 spare_size_mt7622[] = { 178 16, 26, 27, 28 179 }; 180 181 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) 182 { 183 return container_of(nand, struct mtk_nfc_nand_chip, nand); 184 } 185 186 static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i) 187 { 188 return (u8 *)p + i * chip->ecc.size; 189 } 190 191 static inline u8 *oob_ptr(struct nand_chip *chip, int i) 192 { 193 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 194 u8 *poi; 195 196 /* map the sector's FDM data to free oob: 197 * the beginning of the oob area stores the FDM data of bad mark sectors 198 */ 199 200 if (i < mtk_nand->bad_mark.sec) 201 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; 202 else if (i == mtk_nand->bad_mark.sec) 203 poi = chip->oob_poi; 204 else 205 poi = chip->oob_poi + i * mtk_nand->fdm.reg_size; 206 207 return poi; 208 } 209 210 static inline int mtk_data_len(struct nand_chip *chip) 211 { 212 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 213 214 return chip->ecc.size + mtk_nand->spare_per_sector; 215 } 216 217 static inline u8 *mtk_data_ptr(struct nand_chip *chip, int i) 218 { 219 struct mtk_nfc *nfc = nand_get_controller_data(chip); 220 221 return nfc->buffer + i * mtk_data_len(chip); 222 } 223 224 static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i) 225 { 226 struct mtk_nfc *nfc = nand_get_controller_data(chip); 227 228 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size; 229 } 230 231 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg) 232 { 233 writel(val, nfc->regs + reg); 234 } 235 236 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg) 237 { 238 writew(val, nfc->regs + reg); 239 } 240 241 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg) 242 { 243 writeb(val, nfc->regs + reg); 244 } 245 246 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg) 247 { 248 return readl_relaxed(nfc->regs + reg); 249 } 250 251 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg) 252 { 253 return readw_relaxed(nfc->regs + reg); 254 } 255 256 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg) 257 { 258 return readb_relaxed(nfc->regs + reg); 259 } 260 261 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc) 262 { 263 struct device *dev = nfc->dev; 264 u32 val; 265 int ret; 266 267 /* reset all registers and force the NFI master to terminate */ 268 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); 269 270 /* wait for the master to finish the last transaction */ 271 ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val, 272 !(val & MASTER_STA_MASK), 50, 273 MTK_RESET_TIMEOUT); 274 if (ret) 275 dev_warn(dev, "master active in reset [0x%x] = 0x%x\n", 276 NFI_MASTER_STA, val); 277 278 /* ensure any status register affected by the NFI master is reset */ 279 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); 280 nfi_writew(nfc, STAR_DE, NFI_STRDATA); 281 } 282 283 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command) 284 { 285 struct device *dev = nfc->dev; 286 u32 val; 287 int ret; 288 289 nfi_writel(nfc, command, NFI_CMD); 290 291 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, 292 !(val & STA_CMD), 10, MTK_TIMEOUT); 293 if (ret) { 294 dev_warn(dev, "nfi core timed out entering command mode\n"); 295 return -EIO; 296 } 297 298 return 0; 299 } 300 301 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr) 302 { 303 struct device *dev = nfc->dev; 304 u32 val; 305 int ret; 306 307 nfi_writel(nfc, addr, NFI_COLADDR); 308 nfi_writel(nfc, 0, NFI_ROWADDR); 309 nfi_writew(nfc, 1, NFI_ADDRNOB); 310 311 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, 312 !(val & STA_ADDR), 10, MTK_TIMEOUT); 313 if (ret) { 314 dev_warn(dev, "nfi core timed out entering address mode\n"); 315 return -EIO; 316 } 317 318 return 0; 319 } 320 321 static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd) 322 { 323 struct nand_chip *chip = mtd_to_nand(mtd); 324 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 325 struct mtk_nfc *nfc = nand_get_controller_data(chip); 326 u32 fmt, spare, i; 327 328 if (!mtd->writesize) 329 return 0; 330 331 spare = mtk_nand->spare_per_sector; 332 333 switch (mtd->writesize) { 334 case 512: 335 fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512; 336 break; 337 case KB(2): 338 if (chip->ecc.size == 512) 339 fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512; 340 else 341 fmt = PAGEFMT_512_2K; 342 break; 343 case KB(4): 344 if (chip->ecc.size == 512) 345 fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512; 346 else 347 fmt = PAGEFMT_2K_4K; 348 break; 349 case KB(8): 350 if (chip->ecc.size == 512) 351 fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512; 352 else 353 fmt = PAGEFMT_4K_8K; 354 break; 355 case KB(16): 356 fmt = PAGEFMT_8K_16K; 357 break; 358 default: 359 dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize); 360 return -EINVAL; 361 } 362 363 /* 364 * the hardware will double the value for this eccsize, so we need to 365 * halve it 366 */ 367 if (chip->ecc.size == 1024) 368 spare >>= 1; 369 370 for (i = 0; i < nfc->caps->num_spare_size; i++) { 371 if (nfc->caps->spare_size[i] == spare) 372 break; 373 } 374 375 if (i == nfc->caps->num_spare_size) { 376 dev_err(nfc->dev, "invalid spare size %d\n", spare); 377 return -EINVAL; 378 } 379 380 fmt |= i << nfc->caps->pageformat_spare_shift; 381 382 fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT; 383 fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT; 384 nfi_writel(nfc, fmt, NFI_PAGEFMT); 385 386 nfc->ecc_cfg.strength = chip->ecc.strength; 387 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size; 388 389 return 0; 390 } 391 392 static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip) 393 { 394 struct nand_chip *nand = mtd_to_nand(mtd); 395 struct mtk_nfc *nfc = nand_get_controller_data(nand); 396 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand); 397 398 if (chip < 0) 399 return; 400 401 mtk_nfc_hw_runtime_config(mtd); 402 403 nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL); 404 } 405 406 static int mtk_nfc_dev_ready(struct mtd_info *mtd) 407 { 408 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); 409 410 if (nfi_readl(nfc, NFI_STA) & STA_BUSY) 411 return 0; 412 413 return 1; 414 } 415 416 static void mtk_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) 417 { 418 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); 419 420 if (ctrl & NAND_ALE) { 421 mtk_nfc_send_address(nfc, dat); 422 } else if (ctrl & NAND_CLE) { 423 mtk_nfc_hw_reset(nfc); 424 425 nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG); 426 mtk_nfc_send_command(nfc, dat); 427 } 428 } 429 430 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc) 431 { 432 int rc; 433 u8 val; 434 435 rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val, 436 val & PIO_DI_RDY, 10, MTK_TIMEOUT); 437 if (rc < 0) 438 dev_err(nfc->dev, "data not ready\n"); 439 } 440 441 static inline u8 mtk_nfc_read_byte(struct mtd_info *mtd) 442 { 443 struct nand_chip *chip = mtd_to_nand(mtd); 444 struct mtk_nfc *nfc = nand_get_controller_data(chip); 445 u32 reg; 446 447 /* after each byte read, the NFI_STA reg is reset by the hardware */ 448 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; 449 if (reg != NFI_FSM_CUSTDATA) { 450 reg = nfi_readw(nfc, NFI_CNFG); 451 reg |= CNFG_BYTE_RW | CNFG_READ_EN; 452 nfi_writew(nfc, reg, NFI_CNFG); 453 454 /* 455 * set to max sector to allow the HW to continue reading over 456 * unaligned accesses 457 */ 458 reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD; 459 nfi_writel(nfc, reg, NFI_CON); 460 461 /* trigger to fetch data */ 462 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 463 } 464 465 mtk_nfc_wait_ioready(nfc); 466 467 return nfi_readb(nfc, NFI_DATAR); 468 } 469 470 static void mtk_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len) 471 { 472 int i; 473 474 for (i = 0; i < len; i++) 475 buf[i] = mtk_nfc_read_byte(mtd); 476 } 477 478 static void mtk_nfc_write_byte(struct mtd_info *mtd, u8 byte) 479 { 480 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); 481 u32 reg; 482 483 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; 484 485 if (reg != NFI_FSM_CUSTDATA) { 486 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW; 487 nfi_writew(nfc, reg, NFI_CNFG); 488 489 reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR; 490 nfi_writel(nfc, reg, NFI_CON); 491 492 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 493 } 494 495 mtk_nfc_wait_ioready(nfc); 496 nfi_writeb(nfc, byte, NFI_DATAW); 497 } 498 499 static void mtk_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 500 { 501 int i; 502 503 for (i = 0; i < len; i++) 504 mtk_nfc_write_byte(mtd, buf[i]); 505 } 506 507 static int mtk_nfc_setup_data_interface(struct mtd_info *mtd, int csline, 508 const struct nand_data_interface *conf) 509 { 510 struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); 511 const struct nand_sdr_timings *timings; 512 u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt; 513 514 timings = nand_get_sdr_timings(conf); 515 if (IS_ERR(timings)) 516 return -ENOTSUPP; 517 518 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 519 return 0; 520 521 rate = clk_get_rate(nfc->clk.nfi_clk); 522 /* There is a frequency divider in some IPs */ 523 rate /= nfc->caps->nfi_clk_div; 524 525 /* turn clock rate into KHZ */ 526 rate /= 1000; 527 528 tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000; 529 tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000); 530 tpoecs &= 0xf; 531 532 tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000; 533 tprecs = DIV_ROUND_UP(tprecs * rate, 1000000); 534 tprecs &= 0x3f; 535 536 /* sdr interface has no tCR which means CE# low to RE# low */ 537 tc2r = 0; 538 539 tw2r = timings->tWHR_min / 1000; 540 tw2r = DIV_ROUND_UP(tw2r * rate, 1000000); 541 tw2r = DIV_ROUND_UP(tw2r - 1, 2); 542 tw2r &= 0xf; 543 544 twh = max(timings->tREH_min, timings->tWH_min) / 1000; 545 twh = DIV_ROUND_UP(twh * rate, 1000000) - 1; 546 twh &= 0xf; 547 548 twst = timings->tWP_min / 1000; 549 twst = DIV_ROUND_UP(twst * rate, 1000000) - 1; 550 twst &= 0xf; 551 552 trlt = max(timings->tREA_max, timings->tRP_min) / 1000; 553 trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1; 554 trlt &= 0xf; 555 556 /* 557 * ACCON: access timing control register 558 * ------------------------------------- 559 * 31:28: tpoecs, minimum required time for CS post pulling down after 560 * accessing the device 561 * 27:22: tprecs, minimum required time for CS pre pulling down before 562 * accessing the device 563 * 21:16: tc2r, minimum required time from NCEB low to NREB low 564 * 15:12: tw2r, minimum required time from NWEB high to NREB low. 565 * 11:08: twh, write enable hold time 566 * 07:04: twst, write wait states 567 * 03:00: trlt, read wait states 568 */ 569 trlt = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt); 570 nfi_writel(nfc, trlt, NFI_ACCCON); 571 572 return 0; 573 } 574 575 static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data) 576 { 577 struct mtk_nfc *nfc = nand_get_controller_data(chip); 578 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 579 int size = chip->ecc.size + mtk_nand->fdm.reg_size; 580 581 nfc->ecc_cfg.mode = ECC_DMA_MODE; 582 nfc->ecc_cfg.op = ECC_ENCODE; 583 584 return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size); 585 } 586 587 static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c) 588 { 589 /* nop */ 590 } 591 592 static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw) 593 { 594 struct nand_chip *chip = mtd_to_nand(mtd); 595 struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip); 596 u32 bad_pos = nand->bad_mark.pos; 597 598 if (raw) 599 bad_pos += nand->bad_mark.sec * mtk_data_len(chip); 600 else 601 bad_pos += nand->bad_mark.sec * chip->ecc.size; 602 603 swap(chip->oob_poi[0], buf[bad_pos]); 604 } 605 606 static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset, 607 u32 len, const u8 *buf) 608 { 609 struct nand_chip *chip = mtd_to_nand(mtd); 610 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 611 struct mtk_nfc *nfc = nand_get_controller_data(chip); 612 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 613 u32 start, end; 614 int i, ret; 615 616 start = offset / chip->ecc.size; 617 end = DIV_ROUND_UP(offset + len, chip->ecc.size); 618 619 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 620 for (i = 0; i < chip->ecc.steps; i++) { 621 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), 622 chip->ecc.size); 623 624 if (start > i || i >= end) 625 continue; 626 627 if (i == mtk_nand->bad_mark.sec) 628 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 629 630 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); 631 632 /* program the CRC back to the OOB */ 633 ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i)); 634 if (ret < 0) 635 return ret; 636 } 637 638 return 0; 639 } 640 641 static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf) 642 { 643 struct nand_chip *chip = mtd_to_nand(mtd); 644 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 645 struct mtk_nfc *nfc = nand_get_controller_data(chip); 646 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 647 u32 i; 648 649 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 650 for (i = 0; i < chip->ecc.steps; i++) { 651 if (buf) 652 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), 653 chip->ecc.size); 654 655 if (i == mtk_nand->bad_mark.sec) 656 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 657 658 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); 659 } 660 } 661 662 static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start, 663 u32 sectors) 664 { 665 struct mtk_nfc *nfc = nand_get_controller_data(chip); 666 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 667 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 668 u32 vall, valm; 669 u8 *oobptr; 670 int i, j; 671 672 for (i = 0; i < sectors; i++) { 673 oobptr = oob_ptr(chip, start + i); 674 vall = nfi_readl(nfc, NFI_FDML(i)); 675 valm = nfi_readl(nfc, NFI_FDMM(i)); 676 677 for (j = 0; j < fdm->reg_size; j++) 678 oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); 679 } 680 } 681 682 static inline void mtk_nfc_write_fdm(struct nand_chip *chip) 683 { 684 struct mtk_nfc *nfc = nand_get_controller_data(chip); 685 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 686 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 687 u32 vall, valm; 688 u8 *oobptr; 689 int i, j; 690 691 for (i = 0; i < chip->ecc.steps; i++) { 692 oobptr = oob_ptr(chip, i); 693 vall = 0; 694 valm = 0; 695 for (j = 0; j < 8; j++) { 696 if (j < 4) 697 vall |= (j < fdm->reg_size ? oobptr[j] : 0xff) 698 << (j * 8); 699 else 700 valm |= (j < fdm->reg_size ? oobptr[j] : 0xff) 701 << ((j - 4) * 8); 702 } 703 nfi_writel(nfc, vall, NFI_FDML(i)); 704 nfi_writel(nfc, valm, NFI_FDMM(i)); 705 } 706 } 707 708 static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip, 709 const u8 *buf, int page, int len) 710 { 711 struct mtk_nfc *nfc = nand_get_controller_data(chip); 712 struct device *dev = nfc->dev; 713 dma_addr_t addr; 714 u32 reg; 715 int ret; 716 717 addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE); 718 ret = dma_mapping_error(nfc->dev, addr); 719 if (ret) { 720 dev_err(nfc->dev, "dma mapping error\n"); 721 return -EINVAL; 722 } 723 724 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN; 725 nfi_writew(nfc, reg, NFI_CNFG); 726 727 nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON); 728 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); 729 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); 730 731 init_completion(&nfc->done); 732 733 reg = nfi_readl(nfc, NFI_CON) | CON_BWR; 734 nfi_writel(nfc, reg, NFI_CON); 735 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 736 737 ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); 738 if (!ret) { 739 dev_err(dev, "program ahb done timeout\n"); 740 nfi_writew(nfc, 0, NFI_INTR_EN); 741 ret = -ETIMEDOUT; 742 goto timeout; 743 } 744 745 ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg, 746 ADDRCNTR_SEC(reg) >= chip->ecc.steps, 747 10, MTK_TIMEOUT); 748 if (ret) 749 dev_err(dev, "hwecc write timeout\n"); 750 751 timeout: 752 753 dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE); 754 nfi_writel(nfc, 0, NFI_CON); 755 756 return ret; 757 } 758 759 static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 760 const u8 *buf, int page, int raw) 761 { 762 struct mtk_nfc *nfc = nand_get_controller_data(chip); 763 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 764 size_t len; 765 const u8 *bufpoi; 766 u32 reg; 767 int ret; 768 769 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 770 771 if (!raw) { 772 /* OOB => FDM: from register, ECC: from HW */ 773 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN; 774 nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG); 775 776 nfc->ecc_cfg.op = ECC_ENCODE; 777 nfc->ecc_cfg.mode = ECC_NFI_MODE; 778 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); 779 if (ret) { 780 /* clear NFI config */ 781 reg = nfi_readw(nfc, NFI_CNFG); 782 reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); 783 nfi_writew(nfc, reg, NFI_CNFG); 784 785 return ret; 786 } 787 788 memcpy(nfc->buffer, buf, mtd->writesize); 789 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw); 790 bufpoi = nfc->buffer; 791 792 /* write OOB into the FDM registers (OOB area in MTK NAND) */ 793 mtk_nfc_write_fdm(chip); 794 } else { 795 bufpoi = buf; 796 } 797 798 len = mtd->writesize + (raw ? mtd->oobsize : 0); 799 ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len); 800 801 if (!raw) 802 mtk_ecc_disable(nfc->ecc); 803 804 if (ret) 805 return ret; 806 807 return nand_prog_page_end_op(chip); 808 } 809 810 static int mtk_nfc_write_page_hwecc(struct mtd_info *mtd, 811 struct nand_chip *chip, const u8 *buf, 812 int oob_on, int page) 813 { 814 return mtk_nfc_write_page(mtd, chip, buf, page, 0); 815 } 816 817 static int mtk_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 818 const u8 *buf, int oob_on, int pg) 819 { 820 struct mtk_nfc *nfc = nand_get_controller_data(chip); 821 822 mtk_nfc_format_page(mtd, buf); 823 return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1); 824 } 825 826 static int mtk_nfc_write_subpage_hwecc(struct mtd_info *mtd, 827 struct nand_chip *chip, u32 offset, 828 u32 data_len, const u8 *buf, 829 int oob_on, int page) 830 { 831 struct mtk_nfc *nfc = nand_get_controller_data(chip); 832 int ret; 833 834 ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf); 835 if (ret < 0) 836 return ret; 837 838 /* use the data in the private buffer (now with FDM and CRC) */ 839 return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1); 840 } 841 842 static int mtk_nfc_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 843 int page) 844 { 845 return mtk_nfc_write_page_raw(mtd, chip, NULL, 1, page); 846 } 847 848 static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors) 849 { 850 struct nand_chip *chip = mtd_to_nand(mtd); 851 struct mtk_nfc *nfc = nand_get_controller_data(chip); 852 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 853 struct mtk_ecc_stats stats; 854 int rc, i; 855 856 rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE; 857 if (rc) { 858 memset(buf, 0xff, sectors * chip->ecc.size); 859 for (i = 0; i < sectors; i++) 860 memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size); 861 return 0; 862 } 863 864 mtk_ecc_get_stats(nfc->ecc, &stats, sectors); 865 mtd->ecc_stats.corrected += stats.corrected; 866 mtd->ecc_stats.failed += stats.failed; 867 868 return stats.bitflips; 869 } 870 871 static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, 872 u32 data_offs, u32 readlen, 873 u8 *bufpoi, int page, int raw) 874 { 875 struct mtk_nfc *nfc = nand_get_controller_data(chip); 876 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 877 u32 spare = mtk_nand->spare_per_sector; 878 u32 column, sectors, start, end, reg; 879 dma_addr_t addr; 880 int bitflips; 881 size_t len; 882 u8 *buf; 883 int rc; 884 885 start = data_offs / chip->ecc.size; 886 end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size); 887 888 sectors = end - start; 889 column = start * (chip->ecc.size + spare); 890 891 len = sectors * chip->ecc.size + (raw ? sectors * spare : 0); 892 buf = bufpoi + start * chip->ecc.size; 893 894 nand_read_page_op(chip, page, column, NULL, 0); 895 896 addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE); 897 rc = dma_mapping_error(nfc->dev, addr); 898 if (rc) { 899 dev_err(nfc->dev, "dma mapping error\n"); 900 901 return -EINVAL; 902 } 903 904 reg = nfi_readw(nfc, NFI_CNFG); 905 reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB; 906 if (!raw) { 907 reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN; 908 nfi_writew(nfc, reg, NFI_CNFG); 909 910 nfc->ecc_cfg.mode = ECC_NFI_MODE; 911 nfc->ecc_cfg.sectors = sectors; 912 nfc->ecc_cfg.op = ECC_DECODE; 913 rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); 914 if (rc) { 915 dev_err(nfc->dev, "ecc enable\n"); 916 /* clear NFI_CNFG */ 917 reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN | 918 CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); 919 nfi_writew(nfc, reg, NFI_CNFG); 920 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); 921 922 return rc; 923 } 924 } else { 925 nfi_writew(nfc, reg, NFI_CNFG); 926 } 927 928 nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON); 929 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); 930 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); 931 932 init_completion(&nfc->done); 933 reg = nfi_readl(nfc, NFI_CON) | CON_BRD; 934 nfi_writel(nfc, reg, NFI_CON); 935 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 936 937 rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); 938 if (!rc) 939 dev_warn(nfc->dev, "read ahb/dma done timeout\n"); 940 941 rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg, 942 ADDRCNTR_SEC(reg) >= sectors, 10, 943 MTK_TIMEOUT); 944 if (rc < 0) { 945 dev_err(nfc->dev, "subpage done timeout\n"); 946 bitflips = -EIO; 947 } else { 948 bitflips = 0; 949 if (!raw) { 950 rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE); 951 bitflips = rc < 0 ? -ETIMEDOUT : 952 mtk_nfc_update_ecc_stats(mtd, buf, sectors); 953 mtk_nfc_read_fdm(chip, start, sectors); 954 } 955 } 956 957 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); 958 959 if (raw) 960 goto done; 961 962 mtk_ecc_disable(nfc->ecc); 963 964 if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec) 965 mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw); 966 done: 967 nfi_writel(nfc, 0, NFI_CON); 968 969 return bitflips; 970 } 971 972 static int mtk_nfc_read_subpage_hwecc(struct mtd_info *mtd, 973 struct nand_chip *chip, u32 off, 974 u32 len, u8 *p, int pg) 975 { 976 return mtk_nfc_read_subpage(mtd, chip, off, len, p, pg, 0); 977 } 978 979 static int mtk_nfc_read_page_hwecc(struct mtd_info *mtd, 980 struct nand_chip *chip, u8 *p, 981 int oob_on, int pg) 982 { 983 return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0); 984 } 985 986 static int mtk_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 987 u8 *buf, int oob_on, int page) 988 { 989 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 990 struct mtk_nfc *nfc = nand_get_controller_data(chip); 991 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 992 int i, ret; 993 994 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 995 ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer, 996 page, 1); 997 if (ret < 0) 998 return ret; 999 1000 for (i = 0; i < chip->ecc.steps; i++) { 1001 memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size); 1002 1003 if (i == mtk_nand->bad_mark.sec) 1004 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 1005 1006 if (buf) 1007 memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i), 1008 chip->ecc.size); 1009 } 1010 1011 return ret; 1012 } 1013 1014 static int mtk_nfc_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1015 int page) 1016 { 1017 return mtk_nfc_read_page_raw(mtd, chip, NULL, 1, page); 1018 } 1019 1020 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc) 1021 { 1022 /* 1023 * CNRNB: nand ready/busy register 1024 * ------------------------------- 1025 * 7:4: timeout register for polling the NAND busy/ready signal 1026 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles. 1027 */ 1028 nfi_writew(nfc, 0xf1, NFI_CNRNB); 1029 nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT); 1030 1031 mtk_nfc_hw_reset(nfc); 1032 1033 nfi_readl(nfc, NFI_INTR_STA); 1034 nfi_writel(nfc, 0, NFI_INTR_EN); 1035 } 1036 1037 static irqreturn_t mtk_nfc_irq(int irq, void *id) 1038 { 1039 struct mtk_nfc *nfc = id; 1040 u16 sta, ien; 1041 1042 sta = nfi_readw(nfc, NFI_INTR_STA); 1043 ien = nfi_readw(nfc, NFI_INTR_EN); 1044 1045 if (!(sta & ien)) 1046 return IRQ_NONE; 1047 1048 nfi_writew(nfc, ~sta & ien, NFI_INTR_EN); 1049 complete(&nfc->done); 1050 1051 return IRQ_HANDLED; 1052 } 1053 1054 static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk) 1055 { 1056 int ret; 1057 1058 ret = clk_prepare_enable(clk->nfi_clk); 1059 if (ret) { 1060 dev_err(dev, "failed to enable nfi clk\n"); 1061 return ret; 1062 } 1063 1064 ret = clk_prepare_enable(clk->pad_clk); 1065 if (ret) { 1066 dev_err(dev, "failed to enable pad clk\n"); 1067 clk_disable_unprepare(clk->nfi_clk); 1068 return ret; 1069 } 1070 1071 return 0; 1072 } 1073 1074 static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk) 1075 { 1076 clk_disable_unprepare(clk->nfi_clk); 1077 clk_disable_unprepare(clk->pad_clk); 1078 } 1079 1080 static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section, 1081 struct mtd_oob_region *oob_region) 1082 { 1083 struct nand_chip *chip = mtd_to_nand(mtd); 1084 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1085 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 1086 u32 eccsteps; 1087 1088 eccsteps = mtd->writesize / chip->ecc.size; 1089 1090 if (section >= eccsteps) 1091 return -ERANGE; 1092 1093 oob_region->length = fdm->reg_size - fdm->ecc_size; 1094 oob_region->offset = section * fdm->reg_size + fdm->ecc_size; 1095 1096 return 0; 1097 } 1098 1099 static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, 1100 struct mtd_oob_region *oob_region) 1101 { 1102 struct nand_chip *chip = mtd_to_nand(mtd); 1103 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1104 u32 eccsteps; 1105 1106 if (section) 1107 return -ERANGE; 1108 1109 eccsteps = mtd->writesize / chip->ecc.size; 1110 oob_region->offset = mtk_nand->fdm.reg_size * eccsteps; 1111 oob_region->length = mtd->oobsize - oob_region->offset; 1112 1113 return 0; 1114 } 1115 1116 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = { 1117 .free = mtk_nfc_ooblayout_free, 1118 .ecc = mtk_nfc_ooblayout_ecc, 1119 }; 1120 1121 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd) 1122 { 1123 struct nand_chip *nand = mtd_to_nand(mtd); 1124 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand); 1125 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1126 u32 ecc_bytes; 1127 1128 ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * 1129 mtk_ecc_get_parity_bits(nfc->ecc), 8); 1130 1131 fdm->reg_size = chip->spare_per_sector - ecc_bytes; 1132 if (fdm->reg_size > NFI_FDM_MAX_SIZE) 1133 fdm->reg_size = NFI_FDM_MAX_SIZE; 1134 1135 /* bad block mark storage */ 1136 fdm->ecc_size = 1; 1137 } 1138 1139 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl, 1140 struct mtd_info *mtd) 1141 { 1142 struct nand_chip *nand = mtd_to_nand(mtd); 1143 1144 if (mtd->writesize == 512) { 1145 bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap; 1146 } else { 1147 bm_ctl->bm_swap = mtk_nfc_bad_mark_swap; 1148 bm_ctl->sec = mtd->writesize / mtk_data_len(nand); 1149 bm_ctl->pos = mtd->writesize % mtk_data_len(nand); 1150 } 1151 } 1152 1153 static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd) 1154 { 1155 struct nand_chip *nand = mtd_to_nand(mtd); 1156 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1157 const u8 *spare = nfc->caps->spare_size; 1158 u32 eccsteps, i, closest_spare = 0; 1159 1160 eccsteps = mtd->writesize / nand->ecc.size; 1161 *sps = mtd->oobsize / eccsteps; 1162 1163 if (nand->ecc.size == 1024) 1164 *sps >>= 1; 1165 1166 if (*sps < MTK_NFC_MIN_SPARE) 1167 return -EINVAL; 1168 1169 for (i = 0; i < nfc->caps->num_spare_size; i++) { 1170 if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) { 1171 closest_spare = i; 1172 if (*sps == spare[i]) 1173 break; 1174 } 1175 } 1176 1177 *sps = spare[closest_spare]; 1178 1179 if (nand->ecc.size == 1024) 1180 *sps <<= 1; 1181 1182 return 0; 1183 } 1184 1185 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd) 1186 { 1187 struct nand_chip *nand = mtd_to_nand(mtd); 1188 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1189 u32 spare; 1190 int free, ret; 1191 1192 /* support only ecc hw mode */ 1193 if (nand->ecc.mode != NAND_ECC_HW) { 1194 dev_err(dev, "ecc.mode not supported\n"); 1195 return -EINVAL; 1196 } 1197 1198 /* if optional dt settings not present */ 1199 if (!nand->ecc.size || !nand->ecc.strength) { 1200 /* use datasheet requirements */ 1201 nand->ecc.strength = nand->ecc_strength_ds; 1202 nand->ecc.size = nand->ecc_step_ds; 1203 1204 /* 1205 * align eccstrength and eccsize 1206 * this controller only supports 512 and 1024 sizes 1207 */ 1208 if (nand->ecc.size < 1024) { 1209 if (mtd->writesize > 512 && 1210 nfc->caps->max_sector_size > 512) { 1211 nand->ecc.size = 1024; 1212 nand->ecc.strength <<= 1; 1213 } else { 1214 nand->ecc.size = 512; 1215 } 1216 } else { 1217 nand->ecc.size = 1024; 1218 } 1219 1220 ret = mtk_nfc_set_spare_per_sector(&spare, mtd); 1221 if (ret) 1222 return ret; 1223 1224 /* calculate oob bytes except ecc parity data */ 1225 free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc) 1226 + 7) >> 3; 1227 free = spare - free; 1228 1229 /* 1230 * enhance ecc strength if oob left is bigger than max FDM size 1231 * or reduce ecc strength if oob size is not enough for ecc 1232 * parity data. 1233 */ 1234 if (free > NFI_FDM_MAX_SIZE) { 1235 spare -= NFI_FDM_MAX_SIZE; 1236 nand->ecc.strength = (spare << 3) / 1237 mtk_ecc_get_parity_bits(nfc->ecc); 1238 } else if (free < 0) { 1239 spare -= NFI_FDM_MIN_SIZE; 1240 nand->ecc.strength = (spare << 3) / 1241 mtk_ecc_get_parity_bits(nfc->ecc); 1242 } 1243 } 1244 1245 mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength); 1246 1247 dev_info(dev, "eccsize %d eccstrength %d\n", 1248 nand->ecc.size, nand->ecc.strength); 1249 1250 return 0; 1251 } 1252 1253 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc, 1254 struct device_node *np) 1255 { 1256 struct mtk_nfc_nand_chip *chip; 1257 struct nand_chip *nand; 1258 struct mtd_info *mtd; 1259 int nsels, len; 1260 u32 tmp; 1261 int ret; 1262 int i; 1263 1264 if (!of_get_property(np, "reg", &nsels)) 1265 return -ENODEV; 1266 1267 nsels /= sizeof(u32); 1268 if (!nsels || nsels > MTK_NAND_MAX_NSELS) { 1269 dev_err(dev, "invalid reg property size %d\n", nsels); 1270 return -EINVAL; 1271 } 1272 1273 chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8), 1274 GFP_KERNEL); 1275 if (!chip) 1276 return -ENOMEM; 1277 1278 chip->nsels = nsels; 1279 for (i = 0; i < nsels; i++) { 1280 ret = of_property_read_u32_index(np, "reg", i, &tmp); 1281 if (ret) { 1282 dev_err(dev, "reg property failure : %d\n", ret); 1283 return ret; 1284 } 1285 chip->sels[i] = tmp; 1286 } 1287 1288 nand = &chip->nand; 1289 nand->controller = &nfc->controller; 1290 1291 nand_set_flash_node(nand, np); 1292 nand_set_controller_data(nand, nfc); 1293 1294 nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ; 1295 nand->dev_ready = mtk_nfc_dev_ready; 1296 nand->select_chip = mtk_nfc_select_chip; 1297 nand->write_byte = mtk_nfc_write_byte; 1298 nand->write_buf = mtk_nfc_write_buf; 1299 nand->read_byte = mtk_nfc_read_byte; 1300 nand->read_buf = mtk_nfc_read_buf; 1301 nand->cmd_ctrl = mtk_nfc_cmd_ctrl; 1302 nand->setup_data_interface = mtk_nfc_setup_data_interface; 1303 1304 /* set default mode in case dt entry is missing */ 1305 nand->ecc.mode = NAND_ECC_HW; 1306 1307 nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc; 1308 nand->ecc.write_page_raw = mtk_nfc_write_page_raw; 1309 nand->ecc.write_page = mtk_nfc_write_page_hwecc; 1310 nand->ecc.write_oob_raw = mtk_nfc_write_oob_std; 1311 nand->ecc.write_oob = mtk_nfc_write_oob_std; 1312 1313 nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc; 1314 nand->ecc.read_page_raw = mtk_nfc_read_page_raw; 1315 nand->ecc.read_page = mtk_nfc_read_page_hwecc; 1316 nand->ecc.read_oob_raw = mtk_nfc_read_oob_std; 1317 nand->ecc.read_oob = mtk_nfc_read_oob_std; 1318 1319 mtd = nand_to_mtd(nand); 1320 mtd->owner = THIS_MODULE; 1321 mtd->dev.parent = dev; 1322 mtd->name = MTK_NAME; 1323 mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops); 1324 1325 mtk_nfc_hw_init(nfc); 1326 1327 ret = nand_scan_ident(mtd, nsels, NULL); 1328 if (ret) 1329 return ret; 1330 1331 /* store bbt magic in page, cause OOB is not protected */ 1332 if (nand->bbt_options & NAND_BBT_USE_FLASH) 1333 nand->bbt_options |= NAND_BBT_NO_OOB; 1334 1335 ret = mtk_nfc_ecc_init(dev, mtd); 1336 if (ret) 1337 return -EINVAL; 1338 1339 if (nand->options & NAND_BUSWIDTH_16) { 1340 dev_err(dev, "16bits buswidth not supported"); 1341 return -EINVAL; 1342 } 1343 1344 ret = mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, mtd); 1345 if (ret) 1346 return ret; 1347 1348 mtk_nfc_set_fdm(&chip->fdm, mtd); 1349 mtk_nfc_set_bad_mark_ctl(&chip->bad_mark, mtd); 1350 1351 len = mtd->writesize + mtd->oobsize; 1352 nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL); 1353 if (!nfc->buffer) 1354 return -ENOMEM; 1355 1356 ret = nand_scan_tail(mtd); 1357 if (ret) 1358 return ret; 1359 1360 ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0); 1361 if (ret) { 1362 dev_err(dev, "mtd parse partition error\n"); 1363 nand_release(mtd); 1364 return ret; 1365 } 1366 1367 list_add_tail(&chip->node, &nfc->chips); 1368 1369 return 0; 1370 } 1371 1372 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc) 1373 { 1374 struct device_node *np = dev->of_node; 1375 struct device_node *nand_np; 1376 int ret; 1377 1378 for_each_child_of_node(np, nand_np) { 1379 ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np); 1380 if (ret) { 1381 of_node_put(nand_np); 1382 return ret; 1383 } 1384 } 1385 1386 return 0; 1387 } 1388 1389 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = { 1390 .spare_size = spare_size_mt2701, 1391 .num_spare_size = 16, 1392 .pageformat_spare_shift = 4, 1393 .nfi_clk_div = 1, 1394 .max_sector = 16, 1395 .max_sector_size = 1024, 1396 }; 1397 1398 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = { 1399 .spare_size = spare_size_mt2712, 1400 .num_spare_size = 19, 1401 .pageformat_spare_shift = 16, 1402 .nfi_clk_div = 2, 1403 .max_sector = 16, 1404 .max_sector_size = 1024, 1405 }; 1406 1407 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = { 1408 .spare_size = spare_size_mt7622, 1409 .num_spare_size = 4, 1410 .pageformat_spare_shift = 4, 1411 .nfi_clk_div = 1, 1412 .max_sector = 8, 1413 .max_sector_size = 512, 1414 }; 1415 1416 static const struct of_device_id mtk_nfc_id_table[] = { 1417 { 1418 .compatible = "mediatek,mt2701-nfc", 1419 .data = &mtk_nfc_caps_mt2701, 1420 }, { 1421 .compatible = "mediatek,mt2712-nfc", 1422 .data = &mtk_nfc_caps_mt2712, 1423 }, { 1424 .compatible = "mediatek,mt7622-nfc", 1425 .data = &mtk_nfc_caps_mt7622, 1426 }, 1427 {} 1428 }; 1429 MODULE_DEVICE_TABLE(of, mtk_nfc_id_table); 1430 1431 static int mtk_nfc_probe(struct platform_device *pdev) 1432 { 1433 struct device *dev = &pdev->dev; 1434 struct device_node *np = dev->of_node; 1435 struct mtk_nfc *nfc; 1436 struct resource *res; 1437 int ret, irq; 1438 1439 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1440 if (!nfc) 1441 return -ENOMEM; 1442 1443 spin_lock_init(&nfc->controller.lock); 1444 init_waitqueue_head(&nfc->controller.wq); 1445 INIT_LIST_HEAD(&nfc->chips); 1446 1447 /* probe defer if not ready */ 1448 nfc->ecc = of_mtk_ecc_get(np); 1449 if (IS_ERR(nfc->ecc)) 1450 return PTR_ERR(nfc->ecc); 1451 else if (!nfc->ecc) 1452 return -ENODEV; 1453 1454 nfc->caps = of_device_get_match_data(dev); 1455 nfc->dev = dev; 1456 1457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1458 nfc->regs = devm_ioremap_resource(dev, res); 1459 if (IS_ERR(nfc->regs)) { 1460 ret = PTR_ERR(nfc->regs); 1461 goto release_ecc; 1462 } 1463 1464 nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk"); 1465 if (IS_ERR(nfc->clk.nfi_clk)) { 1466 dev_err(dev, "no clk\n"); 1467 ret = PTR_ERR(nfc->clk.nfi_clk); 1468 goto release_ecc; 1469 } 1470 1471 nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk"); 1472 if (IS_ERR(nfc->clk.pad_clk)) { 1473 dev_err(dev, "no pad clk\n"); 1474 ret = PTR_ERR(nfc->clk.pad_clk); 1475 goto release_ecc; 1476 } 1477 1478 ret = mtk_nfc_enable_clk(dev, &nfc->clk); 1479 if (ret) 1480 goto release_ecc; 1481 1482 irq = platform_get_irq(pdev, 0); 1483 if (irq < 0) { 1484 dev_err(dev, "no nfi irq resource\n"); 1485 ret = -EINVAL; 1486 goto clk_disable; 1487 } 1488 1489 ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc); 1490 if (ret) { 1491 dev_err(dev, "failed to request nfi irq\n"); 1492 goto clk_disable; 1493 } 1494 1495 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 1496 if (ret) { 1497 dev_err(dev, "failed to set dma mask\n"); 1498 goto clk_disable; 1499 } 1500 1501 platform_set_drvdata(pdev, nfc); 1502 1503 ret = mtk_nfc_nand_chips_init(dev, nfc); 1504 if (ret) { 1505 dev_err(dev, "failed to init nand chips\n"); 1506 goto clk_disable; 1507 } 1508 1509 return 0; 1510 1511 clk_disable: 1512 mtk_nfc_disable_clk(&nfc->clk); 1513 1514 release_ecc: 1515 mtk_ecc_release(nfc->ecc); 1516 1517 return ret; 1518 } 1519 1520 static int mtk_nfc_remove(struct platform_device *pdev) 1521 { 1522 struct mtk_nfc *nfc = platform_get_drvdata(pdev); 1523 struct mtk_nfc_nand_chip *chip; 1524 1525 while (!list_empty(&nfc->chips)) { 1526 chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip, 1527 node); 1528 nand_release(nand_to_mtd(&chip->nand)); 1529 list_del(&chip->node); 1530 } 1531 1532 mtk_ecc_release(nfc->ecc); 1533 mtk_nfc_disable_clk(&nfc->clk); 1534 1535 return 0; 1536 } 1537 1538 #ifdef CONFIG_PM_SLEEP 1539 static int mtk_nfc_suspend(struct device *dev) 1540 { 1541 struct mtk_nfc *nfc = dev_get_drvdata(dev); 1542 1543 mtk_nfc_disable_clk(&nfc->clk); 1544 1545 return 0; 1546 } 1547 1548 static int mtk_nfc_resume(struct device *dev) 1549 { 1550 struct mtk_nfc *nfc = dev_get_drvdata(dev); 1551 struct mtk_nfc_nand_chip *chip; 1552 struct nand_chip *nand; 1553 int ret; 1554 u32 i; 1555 1556 udelay(200); 1557 1558 ret = mtk_nfc_enable_clk(dev, &nfc->clk); 1559 if (ret) 1560 return ret; 1561 1562 /* reset NAND chip if VCC was powered off */ 1563 list_for_each_entry(chip, &nfc->chips, node) { 1564 nand = &chip->nand; 1565 for (i = 0; i < chip->nsels; i++) 1566 nand_reset(nand, i); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume); 1573 #endif 1574 1575 static struct platform_driver mtk_nfc_driver = { 1576 .probe = mtk_nfc_probe, 1577 .remove = mtk_nfc_remove, 1578 .driver = { 1579 .name = MTK_NAME, 1580 .of_match_table = mtk_nfc_id_table, 1581 #ifdef CONFIG_PM_SLEEP 1582 .pm = &mtk_nfc_pm_ops, 1583 #endif 1584 }, 1585 }; 1586 1587 module_platform_driver(mtk_nfc_driver); 1588 1589 MODULE_LICENSE("GPL"); 1590 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>"); 1591 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver"); 1592