1 /* 2 * MTK NAND Flash controller driver. 3 * Copyright (C) 2016 MediaTek Inc. 4 * Authors: Xiaolei Li <xiaolei.li@mediatek.com> 5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/platform_device.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/clk.h> 22 #include <linux/mtd/rawnand.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/module.h> 25 #include <linux/iopoll.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include "mtk_ecc.h" 29 30 /* NAND controller register definition */ 31 #define NFI_CNFG (0x00) 32 #define CNFG_AHB BIT(0) 33 #define CNFG_READ_EN BIT(1) 34 #define CNFG_DMA_BURST_EN BIT(2) 35 #define CNFG_BYTE_RW BIT(6) 36 #define CNFG_HW_ECC_EN BIT(8) 37 #define CNFG_AUTO_FMT_EN BIT(9) 38 #define CNFG_OP_CUST (6 << 12) 39 #define NFI_PAGEFMT (0x04) 40 #define PAGEFMT_FDM_ECC_SHIFT (12) 41 #define PAGEFMT_FDM_SHIFT (8) 42 #define PAGEFMT_SEC_SEL_512 BIT(2) 43 #define PAGEFMT_512_2K (0) 44 #define PAGEFMT_2K_4K (1) 45 #define PAGEFMT_4K_8K (2) 46 #define PAGEFMT_8K_16K (3) 47 /* NFI control */ 48 #define NFI_CON (0x08) 49 #define CON_FIFO_FLUSH BIT(0) 50 #define CON_NFI_RST BIT(1) 51 #define CON_BRD BIT(8) /* burst read */ 52 #define CON_BWR BIT(9) /* burst write */ 53 #define CON_SEC_SHIFT (12) 54 /* Timming control register */ 55 #define NFI_ACCCON (0x0C) 56 #define NFI_INTR_EN (0x10) 57 #define INTR_AHB_DONE_EN BIT(6) 58 #define NFI_INTR_STA (0x14) 59 #define NFI_CMD (0x20) 60 #define NFI_ADDRNOB (0x30) 61 #define NFI_COLADDR (0x34) 62 #define NFI_ROWADDR (0x38) 63 #define NFI_STRDATA (0x40) 64 #define STAR_EN (1) 65 #define STAR_DE (0) 66 #define NFI_CNRNB (0x44) 67 #define NFI_DATAW (0x50) 68 #define NFI_DATAR (0x54) 69 #define NFI_PIO_DIRDY (0x58) 70 #define PIO_DI_RDY (0x01) 71 #define NFI_STA (0x60) 72 #define STA_CMD BIT(0) 73 #define STA_ADDR BIT(1) 74 #define STA_BUSY BIT(8) 75 #define STA_EMP_PAGE BIT(12) 76 #define NFI_FSM_CUSTDATA (0xe << 16) 77 #define NFI_FSM_MASK (0xf << 16) 78 #define NFI_ADDRCNTR (0x70) 79 #define CNTR_MASK GENMASK(16, 12) 80 #define ADDRCNTR_SEC_SHIFT (12) 81 #define ADDRCNTR_SEC(val) \ 82 (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT) 83 #define NFI_STRADDR (0x80) 84 #define NFI_BYTELEN (0x84) 85 #define NFI_CSEL (0x90) 86 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2) 87 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2) 88 #define NFI_FDM_MAX_SIZE (8) 89 #define NFI_FDM_MIN_SIZE (1) 90 #define NFI_MASTER_STA (0x224) 91 #define MASTER_STA_MASK (0x0FFF) 92 #define NFI_EMPTY_THRESH (0x23C) 93 94 #define MTK_NAME "mtk-nand" 95 #define KB(x) ((x) * 1024UL) 96 #define MB(x) (KB(x) * 1024UL) 97 98 #define MTK_TIMEOUT (500000) 99 #define MTK_RESET_TIMEOUT (1000000) 100 #define MTK_NAND_MAX_NSELS (2) 101 #define MTK_NFC_MIN_SPARE (16) 102 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \ 103 ((tpoecs) << 28 | (tprecs) << 22 | (tc2r) << 16 | \ 104 (tw2r) << 12 | (twh) << 8 | (twst) << 4 | (trlt)) 105 106 struct mtk_nfc_caps { 107 const u8 *spare_size; 108 u8 num_spare_size; 109 u8 pageformat_spare_shift; 110 u8 nfi_clk_div; 111 u8 max_sector; 112 u32 max_sector_size; 113 }; 114 115 struct mtk_nfc_bad_mark_ctl { 116 void (*bm_swap)(struct mtd_info *, u8 *buf, int raw); 117 u32 sec; 118 u32 pos; 119 }; 120 121 /* 122 * FDM: region used to store free OOB data 123 */ 124 struct mtk_nfc_fdm { 125 u32 reg_size; 126 u32 ecc_size; 127 }; 128 129 struct mtk_nfc_nand_chip { 130 struct list_head node; 131 struct nand_chip nand; 132 133 struct mtk_nfc_bad_mark_ctl bad_mark; 134 struct mtk_nfc_fdm fdm; 135 u32 spare_per_sector; 136 137 int nsels; 138 u8 sels[0]; 139 /* nothing after this field */ 140 }; 141 142 struct mtk_nfc_clk { 143 struct clk *nfi_clk; 144 struct clk *pad_clk; 145 }; 146 147 struct mtk_nfc { 148 struct nand_controller controller; 149 struct mtk_ecc_config ecc_cfg; 150 struct mtk_nfc_clk clk; 151 struct mtk_ecc *ecc; 152 153 struct device *dev; 154 const struct mtk_nfc_caps *caps; 155 void __iomem *regs; 156 157 struct completion done; 158 struct list_head chips; 159 160 u8 *buffer; 161 }; 162 163 /* 164 * supported spare size of each IP. 165 * order should be the same with the spare size bitfiled defination of 166 * register NFI_PAGEFMT. 167 */ 168 static const u8 spare_size_mt2701[] = { 169 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64 170 }; 171 172 static const u8 spare_size_mt2712[] = { 173 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, 174 74 175 }; 176 177 static const u8 spare_size_mt7622[] = { 178 16, 26, 27, 28 179 }; 180 181 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) 182 { 183 return container_of(nand, struct mtk_nfc_nand_chip, nand); 184 } 185 186 static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i) 187 { 188 return (u8 *)p + i * chip->ecc.size; 189 } 190 191 static inline u8 *oob_ptr(struct nand_chip *chip, int i) 192 { 193 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 194 u8 *poi; 195 196 /* map the sector's FDM data to free oob: 197 * the beginning of the oob area stores the FDM data of bad mark sectors 198 */ 199 200 if (i < mtk_nand->bad_mark.sec) 201 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; 202 else if (i == mtk_nand->bad_mark.sec) 203 poi = chip->oob_poi; 204 else 205 poi = chip->oob_poi + i * mtk_nand->fdm.reg_size; 206 207 return poi; 208 } 209 210 static inline int mtk_data_len(struct nand_chip *chip) 211 { 212 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 213 214 return chip->ecc.size + mtk_nand->spare_per_sector; 215 } 216 217 static inline u8 *mtk_data_ptr(struct nand_chip *chip, int i) 218 { 219 struct mtk_nfc *nfc = nand_get_controller_data(chip); 220 221 return nfc->buffer + i * mtk_data_len(chip); 222 } 223 224 static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i) 225 { 226 struct mtk_nfc *nfc = nand_get_controller_data(chip); 227 228 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size; 229 } 230 231 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg) 232 { 233 writel(val, nfc->regs + reg); 234 } 235 236 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg) 237 { 238 writew(val, nfc->regs + reg); 239 } 240 241 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg) 242 { 243 writeb(val, nfc->regs + reg); 244 } 245 246 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg) 247 { 248 return readl_relaxed(nfc->regs + reg); 249 } 250 251 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg) 252 { 253 return readw_relaxed(nfc->regs + reg); 254 } 255 256 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg) 257 { 258 return readb_relaxed(nfc->regs + reg); 259 } 260 261 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc) 262 { 263 struct device *dev = nfc->dev; 264 u32 val; 265 int ret; 266 267 /* reset all registers and force the NFI master to terminate */ 268 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); 269 270 /* wait for the master to finish the last transaction */ 271 ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val, 272 !(val & MASTER_STA_MASK), 50, 273 MTK_RESET_TIMEOUT); 274 if (ret) 275 dev_warn(dev, "master active in reset [0x%x] = 0x%x\n", 276 NFI_MASTER_STA, val); 277 278 /* ensure any status register affected by the NFI master is reset */ 279 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); 280 nfi_writew(nfc, STAR_DE, NFI_STRDATA); 281 } 282 283 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command) 284 { 285 struct device *dev = nfc->dev; 286 u32 val; 287 int ret; 288 289 nfi_writel(nfc, command, NFI_CMD); 290 291 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, 292 !(val & STA_CMD), 10, MTK_TIMEOUT); 293 if (ret) { 294 dev_warn(dev, "nfi core timed out entering command mode\n"); 295 return -EIO; 296 } 297 298 return 0; 299 } 300 301 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr) 302 { 303 struct device *dev = nfc->dev; 304 u32 val; 305 int ret; 306 307 nfi_writel(nfc, addr, NFI_COLADDR); 308 nfi_writel(nfc, 0, NFI_ROWADDR); 309 nfi_writew(nfc, 1, NFI_ADDRNOB); 310 311 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, 312 !(val & STA_ADDR), 10, MTK_TIMEOUT); 313 if (ret) { 314 dev_warn(dev, "nfi core timed out entering address mode\n"); 315 return -EIO; 316 } 317 318 return 0; 319 } 320 321 static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd) 322 { 323 struct nand_chip *chip = mtd_to_nand(mtd); 324 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 325 struct mtk_nfc *nfc = nand_get_controller_data(chip); 326 u32 fmt, spare, i; 327 328 if (!mtd->writesize) 329 return 0; 330 331 spare = mtk_nand->spare_per_sector; 332 333 switch (mtd->writesize) { 334 case 512: 335 fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512; 336 break; 337 case KB(2): 338 if (chip->ecc.size == 512) 339 fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512; 340 else 341 fmt = PAGEFMT_512_2K; 342 break; 343 case KB(4): 344 if (chip->ecc.size == 512) 345 fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512; 346 else 347 fmt = PAGEFMT_2K_4K; 348 break; 349 case KB(8): 350 if (chip->ecc.size == 512) 351 fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512; 352 else 353 fmt = PAGEFMT_4K_8K; 354 break; 355 case KB(16): 356 fmt = PAGEFMT_8K_16K; 357 break; 358 default: 359 dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize); 360 return -EINVAL; 361 } 362 363 /* 364 * the hardware will double the value for this eccsize, so we need to 365 * halve it 366 */ 367 if (chip->ecc.size == 1024) 368 spare >>= 1; 369 370 for (i = 0; i < nfc->caps->num_spare_size; i++) { 371 if (nfc->caps->spare_size[i] == spare) 372 break; 373 } 374 375 if (i == nfc->caps->num_spare_size) { 376 dev_err(nfc->dev, "invalid spare size %d\n", spare); 377 return -EINVAL; 378 } 379 380 fmt |= i << nfc->caps->pageformat_spare_shift; 381 382 fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT; 383 fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT; 384 nfi_writel(nfc, fmt, NFI_PAGEFMT); 385 386 nfc->ecc_cfg.strength = chip->ecc.strength; 387 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size; 388 389 return 0; 390 } 391 392 static void mtk_nfc_select_chip(struct nand_chip *nand, int chip) 393 { 394 struct mtk_nfc *nfc = nand_get_controller_data(nand); 395 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand); 396 397 if (chip < 0) 398 return; 399 400 mtk_nfc_hw_runtime_config(nand_to_mtd(nand)); 401 402 nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL); 403 } 404 405 static int mtk_nfc_dev_ready(struct nand_chip *nand) 406 { 407 struct mtk_nfc *nfc = nand_get_controller_data(nand); 408 409 if (nfi_readl(nfc, NFI_STA) & STA_BUSY) 410 return 0; 411 412 return 1; 413 } 414 415 static void mtk_nfc_cmd_ctrl(struct nand_chip *chip, int dat, 416 unsigned int ctrl) 417 { 418 struct mtk_nfc *nfc = nand_get_controller_data(chip); 419 420 if (ctrl & NAND_ALE) { 421 mtk_nfc_send_address(nfc, dat); 422 } else if (ctrl & NAND_CLE) { 423 mtk_nfc_hw_reset(nfc); 424 425 nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG); 426 mtk_nfc_send_command(nfc, dat); 427 } 428 } 429 430 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc) 431 { 432 int rc; 433 u8 val; 434 435 rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val, 436 val & PIO_DI_RDY, 10, MTK_TIMEOUT); 437 if (rc < 0) 438 dev_err(nfc->dev, "data not ready\n"); 439 } 440 441 static inline u8 mtk_nfc_read_byte(struct nand_chip *chip) 442 { 443 struct mtk_nfc *nfc = nand_get_controller_data(chip); 444 u32 reg; 445 446 /* after each byte read, the NFI_STA reg is reset by the hardware */ 447 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; 448 if (reg != NFI_FSM_CUSTDATA) { 449 reg = nfi_readw(nfc, NFI_CNFG); 450 reg |= CNFG_BYTE_RW | CNFG_READ_EN; 451 nfi_writew(nfc, reg, NFI_CNFG); 452 453 /* 454 * set to max sector to allow the HW to continue reading over 455 * unaligned accesses 456 */ 457 reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD; 458 nfi_writel(nfc, reg, NFI_CON); 459 460 /* trigger to fetch data */ 461 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 462 } 463 464 mtk_nfc_wait_ioready(nfc); 465 466 return nfi_readb(nfc, NFI_DATAR); 467 } 468 469 static void mtk_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len) 470 { 471 int i; 472 473 for (i = 0; i < len; i++) 474 buf[i] = mtk_nfc_read_byte(chip); 475 } 476 477 static void mtk_nfc_write_byte(struct nand_chip *chip, u8 byte) 478 { 479 struct mtk_nfc *nfc = nand_get_controller_data(chip); 480 u32 reg; 481 482 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; 483 484 if (reg != NFI_FSM_CUSTDATA) { 485 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW; 486 nfi_writew(nfc, reg, NFI_CNFG); 487 488 reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR; 489 nfi_writel(nfc, reg, NFI_CON); 490 491 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 492 } 493 494 mtk_nfc_wait_ioready(nfc); 495 nfi_writeb(nfc, byte, NFI_DATAW); 496 } 497 498 static void mtk_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len) 499 { 500 int i; 501 502 for (i = 0; i < len; i++) 503 mtk_nfc_write_byte(chip, buf[i]); 504 } 505 506 static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline, 507 const struct nand_data_interface *conf) 508 { 509 struct mtk_nfc *nfc = nand_get_controller_data(chip); 510 const struct nand_sdr_timings *timings; 511 u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt; 512 513 timings = nand_get_sdr_timings(conf); 514 if (IS_ERR(timings)) 515 return -ENOTSUPP; 516 517 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 518 return 0; 519 520 rate = clk_get_rate(nfc->clk.nfi_clk); 521 /* There is a frequency divider in some IPs */ 522 rate /= nfc->caps->nfi_clk_div; 523 524 /* turn clock rate into KHZ */ 525 rate /= 1000; 526 527 tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000; 528 tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000); 529 tpoecs &= 0xf; 530 531 tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000; 532 tprecs = DIV_ROUND_UP(tprecs * rate, 1000000); 533 tprecs &= 0x3f; 534 535 /* sdr interface has no tCR which means CE# low to RE# low */ 536 tc2r = 0; 537 538 tw2r = timings->tWHR_min / 1000; 539 tw2r = DIV_ROUND_UP(tw2r * rate, 1000000); 540 tw2r = DIV_ROUND_UP(tw2r - 1, 2); 541 tw2r &= 0xf; 542 543 twh = max(timings->tREH_min, timings->tWH_min) / 1000; 544 twh = DIV_ROUND_UP(twh * rate, 1000000) - 1; 545 twh &= 0xf; 546 547 twst = timings->tWP_min / 1000; 548 twst = DIV_ROUND_UP(twst * rate, 1000000) - 1; 549 twst &= 0xf; 550 551 trlt = max(timings->tREA_max, timings->tRP_min) / 1000; 552 trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1; 553 trlt &= 0xf; 554 555 /* 556 * ACCON: access timing control register 557 * ------------------------------------- 558 * 31:28: tpoecs, minimum required time for CS post pulling down after 559 * accessing the device 560 * 27:22: tprecs, minimum required time for CS pre pulling down before 561 * accessing the device 562 * 21:16: tc2r, minimum required time from NCEB low to NREB low 563 * 15:12: tw2r, minimum required time from NWEB high to NREB low. 564 * 11:08: twh, write enable hold time 565 * 07:04: twst, write wait states 566 * 03:00: trlt, read wait states 567 */ 568 trlt = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt); 569 nfi_writel(nfc, trlt, NFI_ACCCON); 570 571 return 0; 572 } 573 574 static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data) 575 { 576 struct mtk_nfc *nfc = nand_get_controller_data(chip); 577 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 578 int size = chip->ecc.size + mtk_nand->fdm.reg_size; 579 580 nfc->ecc_cfg.mode = ECC_DMA_MODE; 581 nfc->ecc_cfg.op = ECC_ENCODE; 582 583 return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size); 584 } 585 586 static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c) 587 { 588 /* nop */ 589 } 590 591 static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw) 592 { 593 struct nand_chip *chip = mtd_to_nand(mtd); 594 struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip); 595 u32 bad_pos = nand->bad_mark.pos; 596 597 if (raw) 598 bad_pos += nand->bad_mark.sec * mtk_data_len(chip); 599 else 600 bad_pos += nand->bad_mark.sec * chip->ecc.size; 601 602 swap(chip->oob_poi[0], buf[bad_pos]); 603 } 604 605 static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset, 606 u32 len, const u8 *buf) 607 { 608 struct nand_chip *chip = mtd_to_nand(mtd); 609 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 610 struct mtk_nfc *nfc = nand_get_controller_data(chip); 611 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 612 u32 start, end; 613 int i, ret; 614 615 start = offset / chip->ecc.size; 616 end = DIV_ROUND_UP(offset + len, chip->ecc.size); 617 618 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 619 for (i = 0; i < chip->ecc.steps; i++) { 620 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), 621 chip->ecc.size); 622 623 if (start > i || i >= end) 624 continue; 625 626 if (i == mtk_nand->bad_mark.sec) 627 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 628 629 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); 630 631 /* program the CRC back to the OOB */ 632 ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i)); 633 if (ret < 0) 634 return ret; 635 } 636 637 return 0; 638 } 639 640 static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf) 641 { 642 struct nand_chip *chip = mtd_to_nand(mtd); 643 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 644 struct mtk_nfc *nfc = nand_get_controller_data(chip); 645 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 646 u32 i; 647 648 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 649 for (i = 0; i < chip->ecc.steps; i++) { 650 if (buf) 651 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), 652 chip->ecc.size); 653 654 if (i == mtk_nand->bad_mark.sec) 655 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 656 657 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); 658 } 659 } 660 661 static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start, 662 u32 sectors) 663 { 664 struct mtk_nfc *nfc = nand_get_controller_data(chip); 665 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 666 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 667 u32 vall, valm; 668 u8 *oobptr; 669 int i, j; 670 671 for (i = 0; i < sectors; i++) { 672 oobptr = oob_ptr(chip, start + i); 673 vall = nfi_readl(nfc, NFI_FDML(i)); 674 valm = nfi_readl(nfc, NFI_FDMM(i)); 675 676 for (j = 0; j < fdm->reg_size; j++) 677 oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); 678 } 679 } 680 681 static inline void mtk_nfc_write_fdm(struct nand_chip *chip) 682 { 683 struct mtk_nfc *nfc = nand_get_controller_data(chip); 684 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 685 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 686 u32 vall, valm; 687 u8 *oobptr; 688 int i, j; 689 690 for (i = 0; i < chip->ecc.steps; i++) { 691 oobptr = oob_ptr(chip, i); 692 vall = 0; 693 valm = 0; 694 for (j = 0; j < 8; j++) { 695 if (j < 4) 696 vall |= (j < fdm->reg_size ? oobptr[j] : 0xff) 697 << (j * 8); 698 else 699 valm |= (j < fdm->reg_size ? oobptr[j] : 0xff) 700 << ((j - 4) * 8); 701 } 702 nfi_writel(nfc, vall, NFI_FDML(i)); 703 nfi_writel(nfc, valm, NFI_FDMM(i)); 704 } 705 } 706 707 static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip, 708 const u8 *buf, int page, int len) 709 { 710 struct mtk_nfc *nfc = nand_get_controller_data(chip); 711 struct device *dev = nfc->dev; 712 dma_addr_t addr; 713 u32 reg; 714 int ret; 715 716 addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE); 717 ret = dma_mapping_error(nfc->dev, addr); 718 if (ret) { 719 dev_err(nfc->dev, "dma mapping error\n"); 720 return -EINVAL; 721 } 722 723 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN; 724 nfi_writew(nfc, reg, NFI_CNFG); 725 726 nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON); 727 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); 728 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); 729 730 init_completion(&nfc->done); 731 732 reg = nfi_readl(nfc, NFI_CON) | CON_BWR; 733 nfi_writel(nfc, reg, NFI_CON); 734 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 735 736 ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); 737 if (!ret) { 738 dev_err(dev, "program ahb done timeout\n"); 739 nfi_writew(nfc, 0, NFI_INTR_EN); 740 ret = -ETIMEDOUT; 741 goto timeout; 742 } 743 744 ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg, 745 ADDRCNTR_SEC(reg) >= chip->ecc.steps, 746 10, MTK_TIMEOUT); 747 if (ret) 748 dev_err(dev, "hwecc write timeout\n"); 749 750 timeout: 751 752 dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE); 753 nfi_writel(nfc, 0, NFI_CON); 754 755 return ret; 756 } 757 758 static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 759 const u8 *buf, int page, int raw) 760 { 761 struct mtk_nfc *nfc = nand_get_controller_data(chip); 762 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 763 size_t len; 764 const u8 *bufpoi; 765 u32 reg; 766 int ret; 767 768 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 769 770 if (!raw) { 771 /* OOB => FDM: from register, ECC: from HW */ 772 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN; 773 nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG); 774 775 nfc->ecc_cfg.op = ECC_ENCODE; 776 nfc->ecc_cfg.mode = ECC_NFI_MODE; 777 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); 778 if (ret) { 779 /* clear NFI config */ 780 reg = nfi_readw(nfc, NFI_CNFG); 781 reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); 782 nfi_writew(nfc, reg, NFI_CNFG); 783 784 return ret; 785 } 786 787 memcpy(nfc->buffer, buf, mtd->writesize); 788 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw); 789 bufpoi = nfc->buffer; 790 791 /* write OOB into the FDM registers (OOB area in MTK NAND) */ 792 mtk_nfc_write_fdm(chip); 793 } else { 794 bufpoi = buf; 795 } 796 797 len = mtd->writesize + (raw ? mtd->oobsize : 0); 798 ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len); 799 800 if (!raw) 801 mtk_ecc_disable(nfc->ecc); 802 803 if (ret) 804 return ret; 805 806 return nand_prog_page_end_op(chip); 807 } 808 809 static int mtk_nfc_write_page_hwecc(struct nand_chip *chip, const u8 *buf, 810 int oob_on, int page) 811 { 812 return mtk_nfc_write_page(nand_to_mtd(chip), chip, buf, page, 0); 813 } 814 815 static int mtk_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf, 816 int oob_on, int pg) 817 { 818 struct mtd_info *mtd = nand_to_mtd(chip); 819 struct mtk_nfc *nfc = nand_get_controller_data(chip); 820 821 mtk_nfc_format_page(mtd, buf); 822 return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1); 823 } 824 825 static int mtk_nfc_write_subpage_hwecc(struct nand_chip *chip, u32 offset, 826 u32 data_len, const u8 *buf, 827 int oob_on, int page) 828 { 829 struct mtd_info *mtd = nand_to_mtd(chip); 830 struct mtk_nfc *nfc = nand_get_controller_data(chip); 831 int ret; 832 833 ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf); 834 if (ret < 0) 835 return ret; 836 837 /* use the data in the private buffer (now with FDM and CRC) */ 838 return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1); 839 } 840 841 static int mtk_nfc_write_oob_std(struct nand_chip *chip, int page) 842 { 843 return mtk_nfc_write_page_raw(chip, NULL, 1, page); 844 } 845 846 static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors) 847 { 848 struct nand_chip *chip = mtd_to_nand(mtd); 849 struct mtk_nfc *nfc = nand_get_controller_data(chip); 850 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 851 struct mtk_ecc_stats stats; 852 int rc, i; 853 854 rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE; 855 if (rc) { 856 memset(buf, 0xff, sectors * chip->ecc.size); 857 for (i = 0; i < sectors; i++) 858 memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size); 859 return 0; 860 } 861 862 mtk_ecc_get_stats(nfc->ecc, &stats, sectors); 863 mtd->ecc_stats.corrected += stats.corrected; 864 mtd->ecc_stats.failed += stats.failed; 865 866 return stats.bitflips; 867 } 868 869 static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, 870 u32 data_offs, u32 readlen, 871 u8 *bufpoi, int page, int raw) 872 { 873 struct mtk_nfc *nfc = nand_get_controller_data(chip); 874 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 875 u32 spare = mtk_nand->spare_per_sector; 876 u32 column, sectors, start, end, reg; 877 dma_addr_t addr; 878 int bitflips; 879 size_t len; 880 u8 *buf; 881 int rc; 882 883 start = data_offs / chip->ecc.size; 884 end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size); 885 886 sectors = end - start; 887 column = start * (chip->ecc.size + spare); 888 889 len = sectors * chip->ecc.size + (raw ? sectors * spare : 0); 890 buf = bufpoi + start * chip->ecc.size; 891 892 nand_read_page_op(chip, page, column, NULL, 0); 893 894 addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE); 895 rc = dma_mapping_error(nfc->dev, addr); 896 if (rc) { 897 dev_err(nfc->dev, "dma mapping error\n"); 898 899 return -EINVAL; 900 } 901 902 reg = nfi_readw(nfc, NFI_CNFG); 903 reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB; 904 if (!raw) { 905 reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN; 906 nfi_writew(nfc, reg, NFI_CNFG); 907 908 nfc->ecc_cfg.mode = ECC_NFI_MODE; 909 nfc->ecc_cfg.sectors = sectors; 910 nfc->ecc_cfg.op = ECC_DECODE; 911 rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); 912 if (rc) { 913 dev_err(nfc->dev, "ecc enable\n"); 914 /* clear NFI_CNFG */ 915 reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN | 916 CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); 917 nfi_writew(nfc, reg, NFI_CNFG); 918 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); 919 920 return rc; 921 } 922 } else { 923 nfi_writew(nfc, reg, NFI_CNFG); 924 } 925 926 nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON); 927 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); 928 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); 929 930 init_completion(&nfc->done); 931 reg = nfi_readl(nfc, NFI_CON) | CON_BRD; 932 nfi_writel(nfc, reg, NFI_CON); 933 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 934 935 rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); 936 if (!rc) 937 dev_warn(nfc->dev, "read ahb/dma done timeout\n"); 938 939 rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg, 940 ADDRCNTR_SEC(reg) >= sectors, 10, 941 MTK_TIMEOUT); 942 if (rc < 0) { 943 dev_err(nfc->dev, "subpage done timeout\n"); 944 bitflips = -EIO; 945 } else { 946 bitflips = 0; 947 if (!raw) { 948 rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE); 949 bitflips = rc < 0 ? -ETIMEDOUT : 950 mtk_nfc_update_ecc_stats(mtd, buf, sectors); 951 mtk_nfc_read_fdm(chip, start, sectors); 952 } 953 } 954 955 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); 956 957 if (raw) 958 goto done; 959 960 mtk_ecc_disable(nfc->ecc); 961 962 if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec) 963 mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw); 964 done: 965 nfi_writel(nfc, 0, NFI_CON); 966 967 return bitflips; 968 } 969 970 static int mtk_nfc_read_subpage_hwecc(struct nand_chip *chip, u32 off, 971 u32 len, u8 *p, int pg) 972 { 973 return mtk_nfc_read_subpage(nand_to_mtd(chip), chip, off, len, p, pg, 974 0); 975 } 976 977 static int mtk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *p, int oob_on, 978 int pg) 979 { 980 struct mtd_info *mtd = nand_to_mtd(chip); 981 982 return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0); 983 } 984 985 static int mtk_nfc_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_on, 986 int page) 987 { 988 struct mtd_info *mtd = nand_to_mtd(chip); 989 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 990 struct mtk_nfc *nfc = nand_get_controller_data(chip); 991 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 992 int i, ret; 993 994 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 995 ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer, 996 page, 1); 997 if (ret < 0) 998 return ret; 999 1000 for (i = 0; i < chip->ecc.steps; i++) { 1001 memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size); 1002 1003 if (i == mtk_nand->bad_mark.sec) 1004 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 1005 1006 if (buf) 1007 memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i), 1008 chip->ecc.size); 1009 } 1010 1011 return ret; 1012 } 1013 1014 static int mtk_nfc_read_oob_std(struct nand_chip *chip, int page) 1015 { 1016 return mtk_nfc_read_page_raw(chip, NULL, 1, page); 1017 } 1018 1019 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc) 1020 { 1021 /* 1022 * CNRNB: nand ready/busy register 1023 * ------------------------------- 1024 * 7:4: timeout register for polling the NAND busy/ready signal 1025 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles. 1026 */ 1027 nfi_writew(nfc, 0xf1, NFI_CNRNB); 1028 nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT); 1029 1030 mtk_nfc_hw_reset(nfc); 1031 1032 nfi_readl(nfc, NFI_INTR_STA); 1033 nfi_writel(nfc, 0, NFI_INTR_EN); 1034 } 1035 1036 static irqreturn_t mtk_nfc_irq(int irq, void *id) 1037 { 1038 struct mtk_nfc *nfc = id; 1039 u16 sta, ien; 1040 1041 sta = nfi_readw(nfc, NFI_INTR_STA); 1042 ien = nfi_readw(nfc, NFI_INTR_EN); 1043 1044 if (!(sta & ien)) 1045 return IRQ_NONE; 1046 1047 nfi_writew(nfc, ~sta & ien, NFI_INTR_EN); 1048 complete(&nfc->done); 1049 1050 return IRQ_HANDLED; 1051 } 1052 1053 static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk) 1054 { 1055 int ret; 1056 1057 ret = clk_prepare_enable(clk->nfi_clk); 1058 if (ret) { 1059 dev_err(dev, "failed to enable nfi clk\n"); 1060 return ret; 1061 } 1062 1063 ret = clk_prepare_enable(clk->pad_clk); 1064 if (ret) { 1065 dev_err(dev, "failed to enable pad clk\n"); 1066 clk_disable_unprepare(clk->nfi_clk); 1067 return ret; 1068 } 1069 1070 return 0; 1071 } 1072 1073 static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk) 1074 { 1075 clk_disable_unprepare(clk->nfi_clk); 1076 clk_disable_unprepare(clk->pad_clk); 1077 } 1078 1079 static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section, 1080 struct mtd_oob_region *oob_region) 1081 { 1082 struct nand_chip *chip = mtd_to_nand(mtd); 1083 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1084 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 1085 u32 eccsteps; 1086 1087 eccsteps = mtd->writesize / chip->ecc.size; 1088 1089 if (section >= eccsteps) 1090 return -ERANGE; 1091 1092 oob_region->length = fdm->reg_size - fdm->ecc_size; 1093 oob_region->offset = section * fdm->reg_size + fdm->ecc_size; 1094 1095 return 0; 1096 } 1097 1098 static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, 1099 struct mtd_oob_region *oob_region) 1100 { 1101 struct nand_chip *chip = mtd_to_nand(mtd); 1102 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1103 u32 eccsteps; 1104 1105 if (section) 1106 return -ERANGE; 1107 1108 eccsteps = mtd->writesize / chip->ecc.size; 1109 oob_region->offset = mtk_nand->fdm.reg_size * eccsteps; 1110 oob_region->length = mtd->oobsize - oob_region->offset; 1111 1112 return 0; 1113 } 1114 1115 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = { 1116 .free = mtk_nfc_ooblayout_free, 1117 .ecc = mtk_nfc_ooblayout_ecc, 1118 }; 1119 1120 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd) 1121 { 1122 struct nand_chip *nand = mtd_to_nand(mtd); 1123 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand); 1124 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1125 u32 ecc_bytes; 1126 1127 ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * 1128 mtk_ecc_get_parity_bits(nfc->ecc), 8); 1129 1130 fdm->reg_size = chip->spare_per_sector - ecc_bytes; 1131 if (fdm->reg_size > NFI_FDM_MAX_SIZE) 1132 fdm->reg_size = NFI_FDM_MAX_SIZE; 1133 1134 /* bad block mark storage */ 1135 fdm->ecc_size = 1; 1136 } 1137 1138 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl, 1139 struct mtd_info *mtd) 1140 { 1141 struct nand_chip *nand = mtd_to_nand(mtd); 1142 1143 if (mtd->writesize == 512) { 1144 bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap; 1145 } else { 1146 bm_ctl->bm_swap = mtk_nfc_bad_mark_swap; 1147 bm_ctl->sec = mtd->writesize / mtk_data_len(nand); 1148 bm_ctl->pos = mtd->writesize % mtk_data_len(nand); 1149 } 1150 } 1151 1152 static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd) 1153 { 1154 struct nand_chip *nand = mtd_to_nand(mtd); 1155 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1156 const u8 *spare = nfc->caps->spare_size; 1157 u32 eccsteps, i, closest_spare = 0; 1158 1159 eccsteps = mtd->writesize / nand->ecc.size; 1160 *sps = mtd->oobsize / eccsteps; 1161 1162 if (nand->ecc.size == 1024) 1163 *sps >>= 1; 1164 1165 if (*sps < MTK_NFC_MIN_SPARE) 1166 return -EINVAL; 1167 1168 for (i = 0; i < nfc->caps->num_spare_size; i++) { 1169 if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) { 1170 closest_spare = i; 1171 if (*sps == spare[i]) 1172 break; 1173 } 1174 } 1175 1176 *sps = spare[closest_spare]; 1177 1178 if (nand->ecc.size == 1024) 1179 *sps <<= 1; 1180 1181 return 0; 1182 } 1183 1184 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd) 1185 { 1186 struct nand_chip *nand = mtd_to_nand(mtd); 1187 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1188 u32 spare; 1189 int free, ret; 1190 1191 /* support only ecc hw mode */ 1192 if (nand->ecc.mode != NAND_ECC_HW) { 1193 dev_err(dev, "ecc.mode not supported\n"); 1194 return -EINVAL; 1195 } 1196 1197 /* if optional dt settings not present */ 1198 if (!nand->ecc.size || !nand->ecc.strength) { 1199 /* use datasheet requirements */ 1200 nand->ecc.strength = nand->ecc_strength_ds; 1201 nand->ecc.size = nand->ecc_step_ds; 1202 1203 /* 1204 * align eccstrength and eccsize 1205 * this controller only supports 512 and 1024 sizes 1206 */ 1207 if (nand->ecc.size < 1024) { 1208 if (mtd->writesize > 512 && 1209 nfc->caps->max_sector_size > 512) { 1210 nand->ecc.size = 1024; 1211 nand->ecc.strength <<= 1; 1212 } else { 1213 nand->ecc.size = 512; 1214 } 1215 } else { 1216 nand->ecc.size = 1024; 1217 } 1218 1219 ret = mtk_nfc_set_spare_per_sector(&spare, mtd); 1220 if (ret) 1221 return ret; 1222 1223 /* calculate oob bytes except ecc parity data */ 1224 free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc) 1225 + 7) >> 3; 1226 free = spare - free; 1227 1228 /* 1229 * enhance ecc strength if oob left is bigger than max FDM size 1230 * or reduce ecc strength if oob size is not enough for ecc 1231 * parity data. 1232 */ 1233 if (free > NFI_FDM_MAX_SIZE) { 1234 spare -= NFI_FDM_MAX_SIZE; 1235 nand->ecc.strength = (spare << 3) / 1236 mtk_ecc_get_parity_bits(nfc->ecc); 1237 } else if (free < 0) { 1238 spare -= NFI_FDM_MIN_SIZE; 1239 nand->ecc.strength = (spare << 3) / 1240 mtk_ecc_get_parity_bits(nfc->ecc); 1241 } 1242 } 1243 1244 mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength); 1245 1246 dev_info(dev, "eccsize %d eccstrength %d\n", 1247 nand->ecc.size, nand->ecc.strength); 1248 1249 return 0; 1250 } 1251 1252 static int mtk_nfc_attach_chip(struct nand_chip *chip) 1253 { 1254 struct mtd_info *mtd = nand_to_mtd(chip); 1255 struct device *dev = mtd->dev.parent; 1256 struct mtk_nfc *nfc = nand_get_controller_data(chip); 1257 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1258 int len; 1259 int ret; 1260 1261 if (chip->options & NAND_BUSWIDTH_16) { 1262 dev_err(dev, "16bits buswidth not supported"); 1263 return -EINVAL; 1264 } 1265 1266 /* store bbt magic in page, cause OOB is not protected */ 1267 if (chip->bbt_options & NAND_BBT_USE_FLASH) 1268 chip->bbt_options |= NAND_BBT_NO_OOB; 1269 1270 ret = mtk_nfc_ecc_init(dev, mtd); 1271 if (ret) 1272 return ret; 1273 1274 ret = mtk_nfc_set_spare_per_sector(&mtk_nand->spare_per_sector, mtd); 1275 if (ret) 1276 return ret; 1277 1278 mtk_nfc_set_fdm(&mtk_nand->fdm, mtd); 1279 mtk_nfc_set_bad_mark_ctl(&mtk_nand->bad_mark, mtd); 1280 1281 len = mtd->writesize + mtd->oobsize; 1282 nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL); 1283 if (!nfc->buffer) 1284 return -ENOMEM; 1285 1286 return 0; 1287 } 1288 1289 static const struct nand_controller_ops mtk_nfc_controller_ops = { 1290 .attach_chip = mtk_nfc_attach_chip, 1291 .setup_data_interface = mtk_nfc_setup_data_interface, 1292 }; 1293 1294 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc, 1295 struct device_node *np) 1296 { 1297 struct mtk_nfc_nand_chip *chip; 1298 struct nand_chip *nand; 1299 struct mtd_info *mtd; 1300 int nsels; 1301 u32 tmp; 1302 int ret; 1303 int i; 1304 1305 if (!of_get_property(np, "reg", &nsels)) 1306 return -ENODEV; 1307 1308 nsels /= sizeof(u32); 1309 if (!nsels || nsels > MTK_NAND_MAX_NSELS) { 1310 dev_err(dev, "invalid reg property size %d\n", nsels); 1311 return -EINVAL; 1312 } 1313 1314 chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8), 1315 GFP_KERNEL); 1316 if (!chip) 1317 return -ENOMEM; 1318 1319 chip->nsels = nsels; 1320 for (i = 0; i < nsels; i++) { 1321 ret = of_property_read_u32_index(np, "reg", i, &tmp); 1322 if (ret) { 1323 dev_err(dev, "reg property failure : %d\n", ret); 1324 return ret; 1325 } 1326 chip->sels[i] = tmp; 1327 } 1328 1329 nand = &chip->nand; 1330 nand->controller = &nfc->controller; 1331 1332 nand_set_flash_node(nand, np); 1333 nand_set_controller_data(nand, nfc); 1334 1335 nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ; 1336 nand->legacy.dev_ready = mtk_nfc_dev_ready; 1337 nand->legacy.select_chip = mtk_nfc_select_chip; 1338 nand->legacy.write_byte = mtk_nfc_write_byte; 1339 nand->legacy.write_buf = mtk_nfc_write_buf; 1340 nand->legacy.read_byte = mtk_nfc_read_byte; 1341 nand->legacy.read_buf = mtk_nfc_read_buf; 1342 nand->legacy.cmd_ctrl = mtk_nfc_cmd_ctrl; 1343 1344 /* set default mode in case dt entry is missing */ 1345 nand->ecc.mode = NAND_ECC_HW; 1346 1347 nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc; 1348 nand->ecc.write_page_raw = mtk_nfc_write_page_raw; 1349 nand->ecc.write_page = mtk_nfc_write_page_hwecc; 1350 nand->ecc.write_oob_raw = mtk_nfc_write_oob_std; 1351 nand->ecc.write_oob = mtk_nfc_write_oob_std; 1352 1353 nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc; 1354 nand->ecc.read_page_raw = mtk_nfc_read_page_raw; 1355 nand->ecc.read_page = mtk_nfc_read_page_hwecc; 1356 nand->ecc.read_oob_raw = mtk_nfc_read_oob_std; 1357 nand->ecc.read_oob = mtk_nfc_read_oob_std; 1358 1359 mtd = nand_to_mtd(nand); 1360 mtd->owner = THIS_MODULE; 1361 mtd->dev.parent = dev; 1362 mtd->name = MTK_NAME; 1363 mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops); 1364 1365 mtk_nfc_hw_init(nfc); 1366 1367 ret = nand_scan(nand, nsels); 1368 if (ret) 1369 return ret; 1370 1371 ret = mtd_device_register(mtd, NULL, 0); 1372 if (ret) { 1373 dev_err(dev, "mtd parse partition error\n"); 1374 nand_release(nand); 1375 return ret; 1376 } 1377 1378 list_add_tail(&chip->node, &nfc->chips); 1379 1380 return 0; 1381 } 1382 1383 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc) 1384 { 1385 struct device_node *np = dev->of_node; 1386 struct device_node *nand_np; 1387 int ret; 1388 1389 for_each_child_of_node(np, nand_np) { 1390 ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np); 1391 if (ret) { 1392 of_node_put(nand_np); 1393 return ret; 1394 } 1395 } 1396 1397 return 0; 1398 } 1399 1400 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = { 1401 .spare_size = spare_size_mt2701, 1402 .num_spare_size = 16, 1403 .pageformat_spare_shift = 4, 1404 .nfi_clk_div = 1, 1405 .max_sector = 16, 1406 .max_sector_size = 1024, 1407 }; 1408 1409 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = { 1410 .spare_size = spare_size_mt2712, 1411 .num_spare_size = 19, 1412 .pageformat_spare_shift = 16, 1413 .nfi_clk_div = 2, 1414 .max_sector = 16, 1415 .max_sector_size = 1024, 1416 }; 1417 1418 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = { 1419 .spare_size = spare_size_mt7622, 1420 .num_spare_size = 4, 1421 .pageformat_spare_shift = 4, 1422 .nfi_clk_div = 1, 1423 .max_sector = 8, 1424 .max_sector_size = 512, 1425 }; 1426 1427 static const struct of_device_id mtk_nfc_id_table[] = { 1428 { 1429 .compatible = "mediatek,mt2701-nfc", 1430 .data = &mtk_nfc_caps_mt2701, 1431 }, { 1432 .compatible = "mediatek,mt2712-nfc", 1433 .data = &mtk_nfc_caps_mt2712, 1434 }, { 1435 .compatible = "mediatek,mt7622-nfc", 1436 .data = &mtk_nfc_caps_mt7622, 1437 }, 1438 {} 1439 }; 1440 MODULE_DEVICE_TABLE(of, mtk_nfc_id_table); 1441 1442 static int mtk_nfc_probe(struct platform_device *pdev) 1443 { 1444 struct device *dev = &pdev->dev; 1445 struct device_node *np = dev->of_node; 1446 struct mtk_nfc *nfc; 1447 struct resource *res; 1448 int ret, irq; 1449 1450 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1451 if (!nfc) 1452 return -ENOMEM; 1453 1454 spin_lock_init(&nfc->controller.lock); 1455 init_waitqueue_head(&nfc->controller.wq); 1456 INIT_LIST_HEAD(&nfc->chips); 1457 nfc->controller.ops = &mtk_nfc_controller_ops; 1458 1459 /* probe defer if not ready */ 1460 nfc->ecc = of_mtk_ecc_get(np); 1461 if (IS_ERR(nfc->ecc)) 1462 return PTR_ERR(nfc->ecc); 1463 else if (!nfc->ecc) 1464 return -ENODEV; 1465 1466 nfc->caps = of_device_get_match_data(dev); 1467 nfc->dev = dev; 1468 1469 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1470 nfc->regs = devm_ioremap_resource(dev, res); 1471 if (IS_ERR(nfc->regs)) { 1472 ret = PTR_ERR(nfc->regs); 1473 goto release_ecc; 1474 } 1475 1476 nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk"); 1477 if (IS_ERR(nfc->clk.nfi_clk)) { 1478 dev_err(dev, "no clk\n"); 1479 ret = PTR_ERR(nfc->clk.nfi_clk); 1480 goto release_ecc; 1481 } 1482 1483 nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk"); 1484 if (IS_ERR(nfc->clk.pad_clk)) { 1485 dev_err(dev, "no pad clk\n"); 1486 ret = PTR_ERR(nfc->clk.pad_clk); 1487 goto release_ecc; 1488 } 1489 1490 ret = mtk_nfc_enable_clk(dev, &nfc->clk); 1491 if (ret) 1492 goto release_ecc; 1493 1494 irq = platform_get_irq(pdev, 0); 1495 if (irq < 0) { 1496 dev_err(dev, "no nfi irq resource\n"); 1497 ret = -EINVAL; 1498 goto clk_disable; 1499 } 1500 1501 ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc); 1502 if (ret) { 1503 dev_err(dev, "failed to request nfi irq\n"); 1504 goto clk_disable; 1505 } 1506 1507 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 1508 if (ret) { 1509 dev_err(dev, "failed to set dma mask\n"); 1510 goto clk_disable; 1511 } 1512 1513 platform_set_drvdata(pdev, nfc); 1514 1515 ret = mtk_nfc_nand_chips_init(dev, nfc); 1516 if (ret) { 1517 dev_err(dev, "failed to init nand chips\n"); 1518 goto clk_disable; 1519 } 1520 1521 return 0; 1522 1523 clk_disable: 1524 mtk_nfc_disable_clk(&nfc->clk); 1525 1526 release_ecc: 1527 mtk_ecc_release(nfc->ecc); 1528 1529 return ret; 1530 } 1531 1532 static int mtk_nfc_remove(struct platform_device *pdev) 1533 { 1534 struct mtk_nfc *nfc = platform_get_drvdata(pdev); 1535 struct mtk_nfc_nand_chip *chip; 1536 1537 while (!list_empty(&nfc->chips)) { 1538 chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip, 1539 node); 1540 nand_release(&chip->nand); 1541 list_del(&chip->node); 1542 } 1543 1544 mtk_ecc_release(nfc->ecc); 1545 mtk_nfc_disable_clk(&nfc->clk); 1546 1547 return 0; 1548 } 1549 1550 #ifdef CONFIG_PM_SLEEP 1551 static int mtk_nfc_suspend(struct device *dev) 1552 { 1553 struct mtk_nfc *nfc = dev_get_drvdata(dev); 1554 1555 mtk_nfc_disable_clk(&nfc->clk); 1556 1557 return 0; 1558 } 1559 1560 static int mtk_nfc_resume(struct device *dev) 1561 { 1562 struct mtk_nfc *nfc = dev_get_drvdata(dev); 1563 struct mtk_nfc_nand_chip *chip; 1564 struct nand_chip *nand; 1565 int ret; 1566 u32 i; 1567 1568 udelay(200); 1569 1570 ret = mtk_nfc_enable_clk(dev, &nfc->clk); 1571 if (ret) 1572 return ret; 1573 1574 /* reset NAND chip if VCC was powered off */ 1575 list_for_each_entry(chip, &nfc->chips, node) { 1576 nand = &chip->nand; 1577 for (i = 0; i < chip->nsels; i++) 1578 nand_reset(nand, i); 1579 } 1580 1581 return 0; 1582 } 1583 1584 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume); 1585 #endif 1586 1587 static struct platform_driver mtk_nfc_driver = { 1588 .probe = mtk_nfc_probe, 1589 .remove = mtk_nfc_remove, 1590 .driver = { 1591 .name = MTK_NAME, 1592 .of_match_table = mtk_nfc_id_table, 1593 #ifdef CONFIG_PM_SLEEP 1594 .pm = &mtk_nfc_pm_ops, 1595 #endif 1596 }, 1597 }; 1598 1599 module_platform_driver(mtk_nfc_driver); 1600 1601 MODULE_LICENSE("GPL"); 1602 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>"); 1603 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver"); 1604