1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MTK NAND Flash controller driver. 4 * Copyright (C) 2016 MediaTek Inc. 5 * Authors: Xiaolei Li <xiaolei.li@mediatek.com> 6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/delay.h> 13 #include <linux/clk.h> 14 #include <linux/mtd/rawnand.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/module.h> 17 #include <linux/iopoll.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include "mtk_ecc.h" 21 22 /* NAND controller register definition */ 23 #define NFI_CNFG (0x00) 24 #define CNFG_AHB BIT(0) 25 #define CNFG_READ_EN BIT(1) 26 #define CNFG_DMA_BURST_EN BIT(2) 27 #define CNFG_BYTE_RW BIT(6) 28 #define CNFG_HW_ECC_EN BIT(8) 29 #define CNFG_AUTO_FMT_EN BIT(9) 30 #define CNFG_OP_CUST (6 << 12) 31 #define NFI_PAGEFMT (0x04) 32 #define PAGEFMT_FDM_ECC_SHIFT (12) 33 #define PAGEFMT_FDM_SHIFT (8) 34 #define PAGEFMT_SEC_SEL_512 BIT(2) 35 #define PAGEFMT_512_2K (0) 36 #define PAGEFMT_2K_4K (1) 37 #define PAGEFMT_4K_8K (2) 38 #define PAGEFMT_8K_16K (3) 39 /* NFI control */ 40 #define NFI_CON (0x08) 41 #define CON_FIFO_FLUSH BIT(0) 42 #define CON_NFI_RST BIT(1) 43 #define CON_BRD BIT(8) /* burst read */ 44 #define CON_BWR BIT(9) /* burst write */ 45 #define CON_SEC_SHIFT (12) 46 /* Timming control register */ 47 #define NFI_ACCCON (0x0C) 48 #define NFI_INTR_EN (0x10) 49 #define INTR_AHB_DONE_EN BIT(6) 50 #define NFI_INTR_STA (0x14) 51 #define NFI_CMD (0x20) 52 #define NFI_ADDRNOB (0x30) 53 #define NFI_COLADDR (0x34) 54 #define NFI_ROWADDR (0x38) 55 #define NFI_STRDATA (0x40) 56 #define STAR_EN (1) 57 #define STAR_DE (0) 58 #define NFI_CNRNB (0x44) 59 #define NFI_DATAW (0x50) 60 #define NFI_DATAR (0x54) 61 #define NFI_PIO_DIRDY (0x58) 62 #define PIO_DI_RDY (0x01) 63 #define NFI_STA (0x60) 64 #define STA_CMD BIT(0) 65 #define STA_ADDR BIT(1) 66 #define STA_BUSY BIT(8) 67 #define STA_EMP_PAGE BIT(12) 68 #define NFI_FSM_CUSTDATA (0xe << 16) 69 #define NFI_FSM_MASK (0xf << 16) 70 #define NFI_ADDRCNTR (0x70) 71 #define CNTR_MASK GENMASK(16, 12) 72 #define ADDRCNTR_SEC_SHIFT (12) 73 #define ADDRCNTR_SEC(val) \ 74 (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT) 75 #define NFI_STRADDR (0x80) 76 #define NFI_BYTELEN (0x84) 77 #define NFI_CSEL (0x90) 78 #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2) 79 #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2) 80 #define NFI_FDM_MAX_SIZE (8) 81 #define NFI_FDM_MIN_SIZE (1) 82 #define NFI_DEBUG_CON1 (0x220) 83 #define STROBE_MASK GENMASK(4, 3) 84 #define STROBE_SHIFT (3) 85 #define MAX_STROBE_DLY (3) 86 #define NFI_MASTER_STA (0x224) 87 #define MASTER_STA_MASK (0x0FFF) 88 #define NFI_EMPTY_THRESH (0x23C) 89 90 #define MTK_NAME "mtk-nand" 91 #define KB(x) ((x) * 1024UL) 92 #define MB(x) (KB(x) * 1024UL) 93 94 #define MTK_TIMEOUT (500000) 95 #define MTK_RESET_TIMEOUT (1000000) 96 #define MTK_NAND_MAX_NSELS (2) 97 #define MTK_NFC_MIN_SPARE (16) 98 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \ 99 ((tpoecs) << 28 | (tprecs) << 22 | (tc2r) << 16 | \ 100 (tw2r) << 12 | (twh) << 8 | (twst) << 4 | (trlt)) 101 102 struct mtk_nfc_caps { 103 const u8 *spare_size; 104 u8 num_spare_size; 105 u8 pageformat_spare_shift; 106 u8 nfi_clk_div; 107 u8 max_sector; 108 u32 max_sector_size; 109 }; 110 111 struct mtk_nfc_bad_mark_ctl { 112 void (*bm_swap)(struct mtd_info *, u8 *buf, int raw); 113 u32 sec; 114 u32 pos; 115 }; 116 117 /* 118 * FDM: region used to store free OOB data 119 */ 120 struct mtk_nfc_fdm { 121 u32 reg_size; 122 u32 ecc_size; 123 }; 124 125 struct mtk_nfc_nand_chip { 126 struct list_head node; 127 struct nand_chip nand; 128 129 struct mtk_nfc_bad_mark_ctl bad_mark; 130 struct mtk_nfc_fdm fdm; 131 u32 spare_per_sector; 132 133 int nsels; 134 u8 sels[0]; 135 /* nothing after this field */ 136 }; 137 138 struct mtk_nfc_clk { 139 struct clk *nfi_clk; 140 struct clk *pad_clk; 141 }; 142 143 struct mtk_nfc { 144 struct nand_controller controller; 145 struct mtk_ecc_config ecc_cfg; 146 struct mtk_nfc_clk clk; 147 struct mtk_ecc *ecc; 148 149 struct device *dev; 150 const struct mtk_nfc_caps *caps; 151 void __iomem *regs; 152 153 struct completion done; 154 struct list_head chips; 155 156 u8 *buffer; 157 }; 158 159 /* 160 * supported spare size of each IP. 161 * order should be the same with the spare size bitfiled defination of 162 * register NFI_PAGEFMT. 163 */ 164 static const u8 spare_size_mt2701[] = { 165 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64 166 }; 167 168 static const u8 spare_size_mt2712[] = { 169 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, 170 74 171 }; 172 173 static const u8 spare_size_mt7622[] = { 174 16, 26, 27, 28 175 }; 176 177 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) 178 { 179 return container_of(nand, struct mtk_nfc_nand_chip, nand); 180 } 181 182 static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i) 183 { 184 return (u8 *)p + i * chip->ecc.size; 185 } 186 187 static inline u8 *oob_ptr(struct nand_chip *chip, int i) 188 { 189 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 190 u8 *poi; 191 192 /* map the sector's FDM data to free oob: 193 * the beginning of the oob area stores the FDM data of bad mark sectors 194 */ 195 196 if (i < mtk_nand->bad_mark.sec) 197 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; 198 else if (i == mtk_nand->bad_mark.sec) 199 poi = chip->oob_poi; 200 else 201 poi = chip->oob_poi + i * mtk_nand->fdm.reg_size; 202 203 return poi; 204 } 205 206 static inline int mtk_data_len(struct nand_chip *chip) 207 { 208 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 209 210 return chip->ecc.size + mtk_nand->spare_per_sector; 211 } 212 213 static inline u8 *mtk_data_ptr(struct nand_chip *chip, int i) 214 { 215 struct mtk_nfc *nfc = nand_get_controller_data(chip); 216 217 return nfc->buffer + i * mtk_data_len(chip); 218 } 219 220 static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i) 221 { 222 struct mtk_nfc *nfc = nand_get_controller_data(chip); 223 224 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size; 225 } 226 227 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg) 228 { 229 writel(val, nfc->regs + reg); 230 } 231 232 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg) 233 { 234 writew(val, nfc->regs + reg); 235 } 236 237 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg) 238 { 239 writeb(val, nfc->regs + reg); 240 } 241 242 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg) 243 { 244 return readl_relaxed(nfc->regs + reg); 245 } 246 247 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg) 248 { 249 return readw_relaxed(nfc->regs + reg); 250 } 251 252 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg) 253 { 254 return readb_relaxed(nfc->regs + reg); 255 } 256 257 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc) 258 { 259 struct device *dev = nfc->dev; 260 u32 val; 261 int ret; 262 263 /* reset all registers and force the NFI master to terminate */ 264 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); 265 266 /* wait for the master to finish the last transaction */ 267 ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val, 268 !(val & MASTER_STA_MASK), 50, 269 MTK_RESET_TIMEOUT); 270 if (ret) 271 dev_warn(dev, "master active in reset [0x%x] = 0x%x\n", 272 NFI_MASTER_STA, val); 273 274 /* ensure any status register affected by the NFI master is reset */ 275 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); 276 nfi_writew(nfc, STAR_DE, NFI_STRDATA); 277 } 278 279 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command) 280 { 281 struct device *dev = nfc->dev; 282 u32 val; 283 int ret; 284 285 nfi_writel(nfc, command, NFI_CMD); 286 287 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, 288 !(val & STA_CMD), 10, MTK_TIMEOUT); 289 if (ret) { 290 dev_warn(dev, "nfi core timed out entering command mode\n"); 291 return -EIO; 292 } 293 294 return 0; 295 } 296 297 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr) 298 { 299 struct device *dev = nfc->dev; 300 u32 val; 301 int ret; 302 303 nfi_writel(nfc, addr, NFI_COLADDR); 304 nfi_writel(nfc, 0, NFI_ROWADDR); 305 nfi_writew(nfc, 1, NFI_ADDRNOB); 306 307 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, 308 !(val & STA_ADDR), 10, MTK_TIMEOUT); 309 if (ret) { 310 dev_warn(dev, "nfi core timed out entering address mode\n"); 311 return -EIO; 312 } 313 314 return 0; 315 } 316 317 static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd) 318 { 319 struct nand_chip *chip = mtd_to_nand(mtd); 320 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 321 struct mtk_nfc *nfc = nand_get_controller_data(chip); 322 u32 fmt, spare, i; 323 324 if (!mtd->writesize) 325 return 0; 326 327 spare = mtk_nand->spare_per_sector; 328 329 switch (mtd->writesize) { 330 case 512: 331 fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512; 332 break; 333 case KB(2): 334 if (chip->ecc.size == 512) 335 fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512; 336 else 337 fmt = PAGEFMT_512_2K; 338 break; 339 case KB(4): 340 if (chip->ecc.size == 512) 341 fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512; 342 else 343 fmt = PAGEFMT_2K_4K; 344 break; 345 case KB(8): 346 if (chip->ecc.size == 512) 347 fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512; 348 else 349 fmt = PAGEFMT_4K_8K; 350 break; 351 case KB(16): 352 fmt = PAGEFMT_8K_16K; 353 break; 354 default: 355 dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize); 356 return -EINVAL; 357 } 358 359 /* 360 * the hardware will double the value for this eccsize, so we need to 361 * halve it 362 */ 363 if (chip->ecc.size == 1024) 364 spare >>= 1; 365 366 for (i = 0; i < nfc->caps->num_spare_size; i++) { 367 if (nfc->caps->spare_size[i] == spare) 368 break; 369 } 370 371 if (i == nfc->caps->num_spare_size) { 372 dev_err(nfc->dev, "invalid spare size %d\n", spare); 373 return -EINVAL; 374 } 375 376 fmt |= i << nfc->caps->pageformat_spare_shift; 377 378 fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT; 379 fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT; 380 nfi_writel(nfc, fmt, NFI_PAGEFMT); 381 382 nfc->ecc_cfg.strength = chip->ecc.strength; 383 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size; 384 385 return 0; 386 } 387 388 static void mtk_nfc_select_chip(struct nand_chip *nand, int chip) 389 { 390 struct mtk_nfc *nfc = nand_get_controller_data(nand); 391 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand); 392 393 if (chip < 0) 394 return; 395 396 mtk_nfc_hw_runtime_config(nand_to_mtd(nand)); 397 398 nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL); 399 } 400 401 static int mtk_nfc_dev_ready(struct nand_chip *nand) 402 { 403 struct mtk_nfc *nfc = nand_get_controller_data(nand); 404 405 if (nfi_readl(nfc, NFI_STA) & STA_BUSY) 406 return 0; 407 408 return 1; 409 } 410 411 static void mtk_nfc_cmd_ctrl(struct nand_chip *chip, int dat, 412 unsigned int ctrl) 413 { 414 struct mtk_nfc *nfc = nand_get_controller_data(chip); 415 416 if (ctrl & NAND_ALE) { 417 mtk_nfc_send_address(nfc, dat); 418 } else if (ctrl & NAND_CLE) { 419 mtk_nfc_hw_reset(nfc); 420 421 nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG); 422 mtk_nfc_send_command(nfc, dat); 423 } 424 } 425 426 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc) 427 { 428 int rc; 429 u8 val; 430 431 rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val, 432 val & PIO_DI_RDY, 10, MTK_TIMEOUT); 433 if (rc < 0) 434 dev_err(nfc->dev, "data not ready\n"); 435 } 436 437 static inline u8 mtk_nfc_read_byte(struct nand_chip *chip) 438 { 439 struct mtk_nfc *nfc = nand_get_controller_data(chip); 440 u32 reg; 441 442 /* after each byte read, the NFI_STA reg is reset by the hardware */ 443 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; 444 if (reg != NFI_FSM_CUSTDATA) { 445 reg = nfi_readw(nfc, NFI_CNFG); 446 reg |= CNFG_BYTE_RW | CNFG_READ_EN; 447 nfi_writew(nfc, reg, NFI_CNFG); 448 449 /* 450 * set to max sector to allow the HW to continue reading over 451 * unaligned accesses 452 */ 453 reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD; 454 nfi_writel(nfc, reg, NFI_CON); 455 456 /* trigger to fetch data */ 457 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 458 } 459 460 mtk_nfc_wait_ioready(nfc); 461 462 return nfi_readb(nfc, NFI_DATAR); 463 } 464 465 static void mtk_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len) 466 { 467 int i; 468 469 for (i = 0; i < len; i++) 470 buf[i] = mtk_nfc_read_byte(chip); 471 } 472 473 static void mtk_nfc_write_byte(struct nand_chip *chip, u8 byte) 474 { 475 struct mtk_nfc *nfc = nand_get_controller_data(chip); 476 u32 reg; 477 478 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; 479 480 if (reg != NFI_FSM_CUSTDATA) { 481 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW; 482 nfi_writew(nfc, reg, NFI_CNFG); 483 484 reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR; 485 nfi_writel(nfc, reg, NFI_CON); 486 487 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 488 } 489 490 mtk_nfc_wait_ioready(nfc); 491 nfi_writeb(nfc, byte, NFI_DATAW); 492 } 493 494 static void mtk_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len) 495 { 496 int i; 497 498 for (i = 0; i < len; i++) 499 mtk_nfc_write_byte(chip, buf[i]); 500 } 501 502 static int mtk_nfc_setup_data_interface(struct nand_chip *chip, int csline, 503 const struct nand_data_interface *conf) 504 { 505 struct mtk_nfc *nfc = nand_get_controller_data(chip); 506 const struct nand_sdr_timings *timings; 507 u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst = 0, trlt = 0; 508 u32 temp, tsel = 0; 509 510 timings = nand_get_sdr_timings(conf); 511 if (IS_ERR(timings)) 512 return -ENOTSUPP; 513 514 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 515 return 0; 516 517 rate = clk_get_rate(nfc->clk.nfi_clk); 518 /* There is a frequency divider in some IPs */ 519 rate /= nfc->caps->nfi_clk_div; 520 521 /* turn clock rate into KHZ */ 522 rate /= 1000; 523 524 tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000; 525 tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000); 526 tpoecs &= 0xf; 527 528 tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000; 529 tprecs = DIV_ROUND_UP(tprecs * rate, 1000000); 530 tprecs &= 0x3f; 531 532 /* sdr interface has no tCR which means CE# low to RE# low */ 533 tc2r = 0; 534 535 tw2r = timings->tWHR_min / 1000; 536 tw2r = DIV_ROUND_UP(tw2r * rate, 1000000); 537 tw2r = DIV_ROUND_UP(tw2r - 1, 2); 538 tw2r &= 0xf; 539 540 twh = max(timings->tREH_min, timings->tWH_min) / 1000; 541 twh = DIV_ROUND_UP(twh * rate, 1000000) - 1; 542 twh &= 0xf; 543 544 /* Calculate real WE#/RE# hold time in nanosecond */ 545 temp = (twh + 1) * 1000000 / rate; 546 /* nanosecond to picosecond */ 547 temp *= 1000; 548 549 /* 550 * WE# low level time should be expaned to meet WE# pulse time 551 * and WE# cycle time at the same time. 552 */ 553 if (temp < timings->tWC_min) 554 twst = timings->tWC_min - temp; 555 twst = max(timings->tWP_min, twst) / 1000; 556 twst = DIV_ROUND_UP(twst * rate, 1000000) - 1; 557 twst &= 0xf; 558 559 /* 560 * RE# low level time should be expaned to meet RE# pulse time 561 * and RE# cycle time at the same time. 562 */ 563 if (temp < timings->tRC_min) 564 trlt = timings->tRC_min - temp; 565 trlt = max(trlt, timings->tRP_min) / 1000; 566 trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1; 567 trlt &= 0xf; 568 569 /* Calculate RE# pulse time in nanosecond. */ 570 temp = (trlt + 1) * 1000000 / rate; 571 /* nanosecond to picosecond */ 572 temp *= 1000; 573 /* 574 * If RE# access time is bigger than RE# pulse time, 575 * delay sampling data timing. 576 */ 577 if (temp < timings->tREA_max) { 578 tsel = timings->tREA_max / 1000; 579 tsel = DIV_ROUND_UP(tsel * rate, 1000000); 580 tsel -= (trlt + 1); 581 if (tsel > MAX_STROBE_DLY) { 582 trlt += tsel - MAX_STROBE_DLY; 583 tsel = MAX_STROBE_DLY; 584 } 585 } 586 temp = nfi_readl(nfc, NFI_DEBUG_CON1); 587 temp &= ~STROBE_MASK; 588 temp |= tsel << STROBE_SHIFT; 589 nfi_writel(nfc, temp, NFI_DEBUG_CON1); 590 591 /* 592 * ACCON: access timing control register 593 * ------------------------------------- 594 * 31:28: tpoecs, minimum required time for CS post pulling down after 595 * accessing the device 596 * 27:22: tprecs, minimum required time for CS pre pulling down before 597 * accessing the device 598 * 21:16: tc2r, minimum required time from NCEB low to NREB low 599 * 15:12: tw2r, minimum required time from NWEB high to NREB low. 600 * 11:08: twh, write enable hold time 601 * 07:04: twst, write wait states 602 * 03:00: trlt, read wait states 603 */ 604 trlt = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt); 605 nfi_writel(nfc, trlt, NFI_ACCCON); 606 607 return 0; 608 } 609 610 static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data) 611 { 612 struct mtk_nfc *nfc = nand_get_controller_data(chip); 613 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 614 int size = chip->ecc.size + mtk_nand->fdm.reg_size; 615 616 nfc->ecc_cfg.mode = ECC_DMA_MODE; 617 nfc->ecc_cfg.op = ECC_ENCODE; 618 619 return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size); 620 } 621 622 static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c) 623 { 624 /* nop */ 625 } 626 627 static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw) 628 { 629 struct nand_chip *chip = mtd_to_nand(mtd); 630 struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip); 631 u32 bad_pos = nand->bad_mark.pos; 632 633 if (raw) 634 bad_pos += nand->bad_mark.sec * mtk_data_len(chip); 635 else 636 bad_pos += nand->bad_mark.sec * chip->ecc.size; 637 638 swap(chip->oob_poi[0], buf[bad_pos]); 639 } 640 641 static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset, 642 u32 len, const u8 *buf) 643 { 644 struct nand_chip *chip = mtd_to_nand(mtd); 645 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 646 struct mtk_nfc *nfc = nand_get_controller_data(chip); 647 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 648 u32 start, end; 649 int i, ret; 650 651 start = offset / chip->ecc.size; 652 end = DIV_ROUND_UP(offset + len, chip->ecc.size); 653 654 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 655 for (i = 0; i < chip->ecc.steps; i++) { 656 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), 657 chip->ecc.size); 658 659 if (start > i || i >= end) 660 continue; 661 662 if (i == mtk_nand->bad_mark.sec) 663 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 664 665 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); 666 667 /* program the CRC back to the OOB */ 668 ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i)); 669 if (ret < 0) 670 return ret; 671 } 672 673 return 0; 674 } 675 676 static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf) 677 { 678 struct nand_chip *chip = mtd_to_nand(mtd); 679 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 680 struct mtk_nfc *nfc = nand_get_controller_data(chip); 681 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 682 u32 i; 683 684 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 685 for (i = 0; i < chip->ecc.steps; i++) { 686 if (buf) 687 memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), 688 chip->ecc.size); 689 690 if (i == mtk_nand->bad_mark.sec) 691 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 692 693 memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); 694 } 695 } 696 697 static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start, 698 u32 sectors) 699 { 700 struct mtk_nfc *nfc = nand_get_controller_data(chip); 701 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 702 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 703 u32 vall, valm; 704 u8 *oobptr; 705 int i, j; 706 707 for (i = 0; i < sectors; i++) { 708 oobptr = oob_ptr(chip, start + i); 709 vall = nfi_readl(nfc, NFI_FDML(i)); 710 valm = nfi_readl(nfc, NFI_FDMM(i)); 711 712 for (j = 0; j < fdm->reg_size; j++) 713 oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); 714 } 715 } 716 717 static inline void mtk_nfc_write_fdm(struct nand_chip *chip) 718 { 719 struct mtk_nfc *nfc = nand_get_controller_data(chip); 720 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 721 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 722 u32 vall, valm; 723 u8 *oobptr; 724 int i, j; 725 726 for (i = 0; i < chip->ecc.steps; i++) { 727 oobptr = oob_ptr(chip, i); 728 vall = 0; 729 valm = 0; 730 for (j = 0; j < 8; j++) { 731 if (j < 4) 732 vall |= (j < fdm->reg_size ? oobptr[j] : 0xff) 733 << (j * 8); 734 else 735 valm |= (j < fdm->reg_size ? oobptr[j] : 0xff) 736 << ((j - 4) * 8); 737 } 738 nfi_writel(nfc, vall, NFI_FDML(i)); 739 nfi_writel(nfc, valm, NFI_FDMM(i)); 740 } 741 } 742 743 static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip, 744 const u8 *buf, int page, int len) 745 { 746 struct mtk_nfc *nfc = nand_get_controller_data(chip); 747 struct device *dev = nfc->dev; 748 dma_addr_t addr; 749 u32 reg; 750 int ret; 751 752 addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE); 753 ret = dma_mapping_error(nfc->dev, addr); 754 if (ret) { 755 dev_err(nfc->dev, "dma mapping error\n"); 756 return -EINVAL; 757 } 758 759 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN; 760 nfi_writew(nfc, reg, NFI_CNFG); 761 762 nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON); 763 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); 764 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); 765 766 init_completion(&nfc->done); 767 768 reg = nfi_readl(nfc, NFI_CON) | CON_BWR; 769 nfi_writel(nfc, reg, NFI_CON); 770 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 771 772 ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); 773 if (!ret) { 774 dev_err(dev, "program ahb done timeout\n"); 775 nfi_writew(nfc, 0, NFI_INTR_EN); 776 ret = -ETIMEDOUT; 777 goto timeout; 778 } 779 780 ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg, 781 ADDRCNTR_SEC(reg) >= chip->ecc.steps, 782 10, MTK_TIMEOUT); 783 if (ret) 784 dev_err(dev, "hwecc write timeout\n"); 785 786 timeout: 787 788 dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE); 789 nfi_writel(nfc, 0, NFI_CON); 790 791 return ret; 792 } 793 794 static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 795 const u8 *buf, int page, int raw) 796 { 797 struct mtk_nfc *nfc = nand_get_controller_data(chip); 798 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 799 size_t len; 800 const u8 *bufpoi; 801 u32 reg; 802 int ret; 803 804 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 805 806 if (!raw) { 807 /* OOB => FDM: from register, ECC: from HW */ 808 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN; 809 nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG); 810 811 nfc->ecc_cfg.op = ECC_ENCODE; 812 nfc->ecc_cfg.mode = ECC_NFI_MODE; 813 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); 814 if (ret) { 815 /* clear NFI config */ 816 reg = nfi_readw(nfc, NFI_CNFG); 817 reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); 818 nfi_writew(nfc, reg, NFI_CNFG); 819 820 return ret; 821 } 822 823 memcpy(nfc->buffer, buf, mtd->writesize); 824 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw); 825 bufpoi = nfc->buffer; 826 827 /* write OOB into the FDM registers (OOB area in MTK NAND) */ 828 mtk_nfc_write_fdm(chip); 829 } else { 830 bufpoi = buf; 831 } 832 833 len = mtd->writesize + (raw ? mtd->oobsize : 0); 834 ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len); 835 836 if (!raw) 837 mtk_ecc_disable(nfc->ecc); 838 839 if (ret) 840 return ret; 841 842 return nand_prog_page_end_op(chip); 843 } 844 845 static int mtk_nfc_write_page_hwecc(struct nand_chip *chip, const u8 *buf, 846 int oob_on, int page) 847 { 848 return mtk_nfc_write_page(nand_to_mtd(chip), chip, buf, page, 0); 849 } 850 851 static int mtk_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf, 852 int oob_on, int pg) 853 { 854 struct mtd_info *mtd = nand_to_mtd(chip); 855 struct mtk_nfc *nfc = nand_get_controller_data(chip); 856 857 mtk_nfc_format_page(mtd, buf); 858 return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1); 859 } 860 861 static int mtk_nfc_write_subpage_hwecc(struct nand_chip *chip, u32 offset, 862 u32 data_len, const u8 *buf, 863 int oob_on, int page) 864 { 865 struct mtd_info *mtd = nand_to_mtd(chip); 866 struct mtk_nfc *nfc = nand_get_controller_data(chip); 867 int ret; 868 869 ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf); 870 if (ret < 0) 871 return ret; 872 873 /* use the data in the private buffer (now with FDM and CRC) */ 874 return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1); 875 } 876 877 static int mtk_nfc_write_oob_std(struct nand_chip *chip, int page) 878 { 879 return mtk_nfc_write_page_raw(chip, NULL, 1, page); 880 } 881 882 static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors) 883 { 884 struct nand_chip *chip = mtd_to_nand(mtd); 885 struct mtk_nfc *nfc = nand_get_controller_data(chip); 886 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 887 struct mtk_ecc_stats stats; 888 int rc, i; 889 890 rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE; 891 if (rc) { 892 memset(buf, 0xff, sectors * chip->ecc.size); 893 for (i = 0; i < sectors; i++) 894 memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size); 895 return 0; 896 } 897 898 mtk_ecc_get_stats(nfc->ecc, &stats, sectors); 899 mtd->ecc_stats.corrected += stats.corrected; 900 mtd->ecc_stats.failed += stats.failed; 901 902 return stats.bitflips; 903 } 904 905 static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, 906 u32 data_offs, u32 readlen, 907 u8 *bufpoi, int page, int raw) 908 { 909 struct mtk_nfc *nfc = nand_get_controller_data(chip); 910 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 911 u32 spare = mtk_nand->spare_per_sector; 912 u32 column, sectors, start, end, reg; 913 dma_addr_t addr; 914 int bitflips; 915 size_t len; 916 u8 *buf; 917 int rc; 918 919 start = data_offs / chip->ecc.size; 920 end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size); 921 922 sectors = end - start; 923 column = start * (chip->ecc.size + spare); 924 925 len = sectors * chip->ecc.size + (raw ? sectors * spare : 0); 926 buf = bufpoi + start * chip->ecc.size; 927 928 nand_read_page_op(chip, page, column, NULL, 0); 929 930 addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE); 931 rc = dma_mapping_error(nfc->dev, addr); 932 if (rc) { 933 dev_err(nfc->dev, "dma mapping error\n"); 934 935 return -EINVAL; 936 } 937 938 reg = nfi_readw(nfc, NFI_CNFG); 939 reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB; 940 if (!raw) { 941 reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN; 942 nfi_writew(nfc, reg, NFI_CNFG); 943 944 nfc->ecc_cfg.mode = ECC_NFI_MODE; 945 nfc->ecc_cfg.sectors = sectors; 946 nfc->ecc_cfg.op = ECC_DECODE; 947 rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); 948 if (rc) { 949 dev_err(nfc->dev, "ecc enable\n"); 950 /* clear NFI_CNFG */ 951 reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN | 952 CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); 953 nfi_writew(nfc, reg, NFI_CNFG); 954 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); 955 956 return rc; 957 } 958 } else { 959 nfi_writew(nfc, reg, NFI_CNFG); 960 } 961 962 nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON); 963 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); 964 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); 965 966 init_completion(&nfc->done); 967 reg = nfi_readl(nfc, NFI_CON) | CON_BRD; 968 nfi_writel(nfc, reg, NFI_CON); 969 nfi_writew(nfc, STAR_EN, NFI_STRDATA); 970 971 rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); 972 if (!rc) 973 dev_warn(nfc->dev, "read ahb/dma done timeout\n"); 974 975 rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg, 976 ADDRCNTR_SEC(reg) >= sectors, 10, 977 MTK_TIMEOUT); 978 if (rc < 0) { 979 dev_err(nfc->dev, "subpage done timeout\n"); 980 bitflips = -EIO; 981 } else { 982 bitflips = 0; 983 if (!raw) { 984 rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE); 985 bitflips = rc < 0 ? -ETIMEDOUT : 986 mtk_nfc_update_ecc_stats(mtd, buf, sectors); 987 mtk_nfc_read_fdm(chip, start, sectors); 988 } 989 } 990 991 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); 992 993 if (raw) 994 goto done; 995 996 mtk_ecc_disable(nfc->ecc); 997 998 if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec) 999 mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw); 1000 done: 1001 nfi_writel(nfc, 0, NFI_CON); 1002 1003 return bitflips; 1004 } 1005 1006 static int mtk_nfc_read_subpage_hwecc(struct nand_chip *chip, u32 off, 1007 u32 len, u8 *p, int pg) 1008 { 1009 return mtk_nfc_read_subpage(nand_to_mtd(chip), chip, off, len, p, pg, 1010 0); 1011 } 1012 1013 static int mtk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *p, int oob_on, 1014 int pg) 1015 { 1016 struct mtd_info *mtd = nand_to_mtd(chip); 1017 1018 return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0); 1019 } 1020 1021 static int mtk_nfc_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_on, 1022 int page) 1023 { 1024 struct mtd_info *mtd = nand_to_mtd(chip); 1025 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1026 struct mtk_nfc *nfc = nand_get_controller_data(chip); 1027 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 1028 int i, ret; 1029 1030 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); 1031 ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer, 1032 page, 1); 1033 if (ret < 0) 1034 return ret; 1035 1036 for (i = 0; i < chip->ecc.steps; i++) { 1037 memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size); 1038 1039 if (i == mtk_nand->bad_mark.sec) 1040 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); 1041 1042 if (buf) 1043 memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i), 1044 chip->ecc.size); 1045 } 1046 1047 return ret; 1048 } 1049 1050 static int mtk_nfc_read_oob_std(struct nand_chip *chip, int page) 1051 { 1052 return mtk_nfc_read_page_raw(chip, NULL, 1, page); 1053 } 1054 1055 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc) 1056 { 1057 /* 1058 * CNRNB: nand ready/busy register 1059 * ------------------------------- 1060 * 7:4: timeout register for polling the NAND busy/ready signal 1061 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles. 1062 */ 1063 nfi_writew(nfc, 0xf1, NFI_CNRNB); 1064 nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT); 1065 1066 mtk_nfc_hw_reset(nfc); 1067 1068 nfi_readl(nfc, NFI_INTR_STA); 1069 nfi_writel(nfc, 0, NFI_INTR_EN); 1070 } 1071 1072 static irqreturn_t mtk_nfc_irq(int irq, void *id) 1073 { 1074 struct mtk_nfc *nfc = id; 1075 u16 sta, ien; 1076 1077 sta = nfi_readw(nfc, NFI_INTR_STA); 1078 ien = nfi_readw(nfc, NFI_INTR_EN); 1079 1080 if (!(sta & ien)) 1081 return IRQ_NONE; 1082 1083 nfi_writew(nfc, ~sta & ien, NFI_INTR_EN); 1084 complete(&nfc->done); 1085 1086 return IRQ_HANDLED; 1087 } 1088 1089 static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk) 1090 { 1091 int ret; 1092 1093 ret = clk_prepare_enable(clk->nfi_clk); 1094 if (ret) { 1095 dev_err(dev, "failed to enable nfi clk\n"); 1096 return ret; 1097 } 1098 1099 ret = clk_prepare_enable(clk->pad_clk); 1100 if (ret) { 1101 dev_err(dev, "failed to enable pad clk\n"); 1102 clk_disable_unprepare(clk->nfi_clk); 1103 return ret; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk) 1110 { 1111 clk_disable_unprepare(clk->nfi_clk); 1112 clk_disable_unprepare(clk->pad_clk); 1113 } 1114 1115 static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section, 1116 struct mtd_oob_region *oob_region) 1117 { 1118 struct nand_chip *chip = mtd_to_nand(mtd); 1119 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1120 struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; 1121 u32 eccsteps; 1122 1123 eccsteps = mtd->writesize / chip->ecc.size; 1124 1125 if (section >= eccsteps) 1126 return -ERANGE; 1127 1128 oob_region->length = fdm->reg_size - fdm->ecc_size; 1129 oob_region->offset = section * fdm->reg_size + fdm->ecc_size; 1130 1131 return 0; 1132 } 1133 1134 static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, 1135 struct mtd_oob_region *oob_region) 1136 { 1137 struct nand_chip *chip = mtd_to_nand(mtd); 1138 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1139 u32 eccsteps; 1140 1141 if (section) 1142 return -ERANGE; 1143 1144 eccsteps = mtd->writesize / chip->ecc.size; 1145 oob_region->offset = mtk_nand->fdm.reg_size * eccsteps; 1146 oob_region->length = mtd->oobsize - oob_region->offset; 1147 1148 return 0; 1149 } 1150 1151 static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = { 1152 .free = mtk_nfc_ooblayout_free, 1153 .ecc = mtk_nfc_ooblayout_ecc, 1154 }; 1155 1156 static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd) 1157 { 1158 struct nand_chip *nand = mtd_to_nand(mtd); 1159 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand); 1160 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1161 u32 ecc_bytes; 1162 1163 ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * 1164 mtk_ecc_get_parity_bits(nfc->ecc), 8); 1165 1166 fdm->reg_size = chip->spare_per_sector - ecc_bytes; 1167 if (fdm->reg_size > NFI_FDM_MAX_SIZE) 1168 fdm->reg_size = NFI_FDM_MAX_SIZE; 1169 1170 /* bad block mark storage */ 1171 fdm->ecc_size = 1; 1172 } 1173 1174 static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl, 1175 struct mtd_info *mtd) 1176 { 1177 struct nand_chip *nand = mtd_to_nand(mtd); 1178 1179 if (mtd->writesize == 512) { 1180 bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap; 1181 } else { 1182 bm_ctl->bm_swap = mtk_nfc_bad_mark_swap; 1183 bm_ctl->sec = mtd->writesize / mtk_data_len(nand); 1184 bm_ctl->pos = mtd->writesize % mtk_data_len(nand); 1185 } 1186 } 1187 1188 static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd) 1189 { 1190 struct nand_chip *nand = mtd_to_nand(mtd); 1191 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1192 const u8 *spare = nfc->caps->spare_size; 1193 u32 eccsteps, i, closest_spare = 0; 1194 1195 eccsteps = mtd->writesize / nand->ecc.size; 1196 *sps = mtd->oobsize / eccsteps; 1197 1198 if (nand->ecc.size == 1024) 1199 *sps >>= 1; 1200 1201 if (*sps < MTK_NFC_MIN_SPARE) 1202 return -EINVAL; 1203 1204 for (i = 0; i < nfc->caps->num_spare_size; i++) { 1205 if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) { 1206 closest_spare = i; 1207 if (*sps == spare[i]) 1208 break; 1209 } 1210 } 1211 1212 *sps = spare[closest_spare]; 1213 1214 if (nand->ecc.size == 1024) 1215 *sps <<= 1; 1216 1217 return 0; 1218 } 1219 1220 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd) 1221 { 1222 struct nand_chip *nand = mtd_to_nand(mtd); 1223 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1224 u32 spare; 1225 int free, ret; 1226 1227 /* support only ecc hw mode */ 1228 if (nand->ecc.mode != NAND_ECC_HW) { 1229 dev_err(dev, "ecc.mode not supported\n"); 1230 return -EINVAL; 1231 } 1232 1233 /* if optional dt settings not present */ 1234 if (!nand->ecc.size || !nand->ecc.strength) { 1235 /* use datasheet requirements */ 1236 nand->ecc.strength = nand->base.eccreq.strength; 1237 nand->ecc.size = nand->base.eccreq.step_size; 1238 1239 /* 1240 * align eccstrength and eccsize 1241 * this controller only supports 512 and 1024 sizes 1242 */ 1243 if (nand->ecc.size < 1024) { 1244 if (mtd->writesize > 512 && 1245 nfc->caps->max_sector_size > 512) { 1246 nand->ecc.size = 1024; 1247 nand->ecc.strength <<= 1; 1248 } else { 1249 nand->ecc.size = 512; 1250 } 1251 } else { 1252 nand->ecc.size = 1024; 1253 } 1254 1255 ret = mtk_nfc_set_spare_per_sector(&spare, mtd); 1256 if (ret) 1257 return ret; 1258 1259 /* calculate oob bytes except ecc parity data */ 1260 free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc) 1261 + 7) >> 3; 1262 free = spare - free; 1263 1264 /* 1265 * enhance ecc strength if oob left is bigger than max FDM size 1266 * or reduce ecc strength if oob size is not enough for ecc 1267 * parity data. 1268 */ 1269 if (free > NFI_FDM_MAX_SIZE) { 1270 spare -= NFI_FDM_MAX_SIZE; 1271 nand->ecc.strength = (spare << 3) / 1272 mtk_ecc_get_parity_bits(nfc->ecc); 1273 } else if (free < 0) { 1274 spare -= NFI_FDM_MIN_SIZE; 1275 nand->ecc.strength = (spare << 3) / 1276 mtk_ecc_get_parity_bits(nfc->ecc); 1277 } 1278 } 1279 1280 mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength); 1281 1282 dev_info(dev, "eccsize %d eccstrength %d\n", 1283 nand->ecc.size, nand->ecc.strength); 1284 1285 return 0; 1286 } 1287 1288 static int mtk_nfc_attach_chip(struct nand_chip *chip) 1289 { 1290 struct mtd_info *mtd = nand_to_mtd(chip); 1291 struct device *dev = mtd->dev.parent; 1292 struct mtk_nfc *nfc = nand_get_controller_data(chip); 1293 struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); 1294 int len; 1295 int ret; 1296 1297 if (chip->options & NAND_BUSWIDTH_16) { 1298 dev_err(dev, "16bits buswidth not supported"); 1299 return -EINVAL; 1300 } 1301 1302 /* store bbt magic in page, cause OOB is not protected */ 1303 if (chip->bbt_options & NAND_BBT_USE_FLASH) 1304 chip->bbt_options |= NAND_BBT_NO_OOB; 1305 1306 ret = mtk_nfc_ecc_init(dev, mtd); 1307 if (ret) 1308 return ret; 1309 1310 ret = mtk_nfc_set_spare_per_sector(&mtk_nand->spare_per_sector, mtd); 1311 if (ret) 1312 return ret; 1313 1314 mtk_nfc_set_fdm(&mtk_nand->fdm, mtd); 1315 mtk_nfc_set_bad_mark_ctl(&mtk_nand->bad_mark, mtd); 1316 1317 len = mtd->writesize + mtd->oobsize; 1318 nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL); 1319 if (!nfc->buffer) 1320 return -ENOMEM; 1321 1322 return 0; 1323 } 1324 1325 static const struct nand_controller_ops mtk_nfc_controller_ops = { 1326 .attach_chip = mtk_nfc_attach_chip, 1327 .setup_data_interface = mtk_nfc_setup_data_interface, 1328 }; 1329 1330 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc, 1331 struct device_node *np) 1332 { 1333 struct mtk_nfc_nand_chip *chip; 1334 struct nand_chip *nand; 1335 struct mtd_info *mtd; 1336 int nsels; 1337 u32 tmp; 1338 int ret; 1339 int i; 1340 1341 if (!of_get_property(np, "reg", &nsels)) 1342 return -ENODEV; 1343 1344 nsels /= sizeof(u32); 1345 if (!nsels || nsels > MTK_NAND_MAX_NSELS) { 1346 dev_err(dev, "invalid reg property size %d\n", nsels); 1347 return -EINVAL; 1348 } 1349 1350 chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8), 1351 GFP_KERNEL); 1352 if (!chip) 1353 return -ENOMEM; 1354 1355 chip->nsels = nsels; 1356 for (i = 0; i < nsels; i++) { 1357 ret = of_property_read_u32_index(np, "reg", i, &tmp); 1358 if (ret) { 1359 dev_err(dev, "reg property failure : %d\n", ret); 1360 return ret; 1361 } 1362 chip->sels[i] = tmp; 1363 } 1364 1365 nand = &chip->nand; 1366 nand->controller = &nfc->controller; 1367 1368 nand_set_flash_node(nand, np); 1369 nand_set_controller_data(nand, nfc); 1370 1371 nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ; 1372 nand->legacy.dev_ready = mtk_nfc_dev_ready; 1373 nand->legacy.select_chip = mtk_nfc_select_chip; 1374 nand->legacy.write_byte = mtk_nfc_write_byte; 1375 nand->legacy.write_buf = mtk_nfc_write_buf; 1376 nand->legacy.read_byte = mtk_nfc_read_byte; 1377 nand->legacy.read_buf = mtk_nfc_read_buf; 1378 nand->legacy.cmd_ctrl = mtk_nfc_cmd_ctrl; 1379 1380 /* set default mode in case dt entry is missing */ 1381 nand->ecc.mode = NAND_ECC_HW; 1382 1383 nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc; 1384 nand->ecc.write_page_raw = mtk_nfc_write_page_raw; 1385 nand->ecc.write_page = mtk_nfc_write_page_hwecc; 1386 nand->ecc.write_oob_raw = mtk_nfc_write_oob_std; 1387 nand->ecc.write_oob = mtk_nfc_write_oob_std; 1388 1389 nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc; 1390 nand->ecc.read_page_raw = mtk_nfc_read_page_raw; 1391 nand->ecc.read_page = mtk_nfc_read_page_hwecc; 1392 nand->ecc.read_oob_raw = mtk_nfc_read_oob_std; 1393 nand->ecc.read_oob = mtk_nfc_read_oob_std; 1394 1395 mtd = nand_to_mtd(nand); 1396 mtd->owner = THIS_MODULE; 1397 mtd->dev.parent = dev; 1398 mtd->name = MTK_NAME; 1399 mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops); 1400 1401 mtk_nfc_hw_init(nfc); 1402 1403 ret = nand_scan(nand, nsels); 1404 if (ret) 1405 return ret; 1406 1407 ret = mtd_device_register(mtd, NULL, 0); 1408 if (ret) { 1409 dev_err(dev, "mtd parse partition error\n"); 1410 nand_release(nand); 1411 return ret; 1412 } 1413 1414 list_add_tail(&chip->node, &nfc->chips); 1415 1416 return 0; 1417 } 1418 1419 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc) 1420 { 1421 struct device_node *np = dev->of_node; 1422 struct device_node *nand_np; 1423 int ret; 1424 1425 for_each_child_of_node(np, nand_np) { 1426 ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np); 1427 if (ret) { 1428 of_node_put(nand_np); 1429 return ret; 1430 } 1431 } 1432 1433 return 0; 1434 } 1435 1436 static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = { 1437 .spare_size = spare_size_mt2701, 1438 .num_spare_size = 16, 1439 .pageformat_spare_shift = 4, 1440 .nfi_clk_div = 1, 1441 .max_sector = 16, 1442 .max_sector_size = 1024, 1443 }; 1444 1445 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = { 1446 .spare_size = spare_size_mt2712, 1447 .num_spare_size = 19, 1448 .pageformat_spare_shift = 16, 1449 .nfi_clk_div = 2, 1450 .max_sector = 16, 1451 .max_sector_size = 1024, 1452 }; 1453 1454 static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = { 1455 .spare_size = spare_size_mt7622, 1456 .num_spare_size = 4, 1457 .pageformat_spare_shift = 4, 1458 .nfi_clk_div = 1, 1459 .max_sector = 8, 1460 .max_sector_size = 512, 1461 }; 1462 1463 static const struct of_device_id mtk_nfc_id_table[] = { 1464 { 1465 .compatible = "mediatek,mt2701-nfc", 1466 .data = &mtk_nfc_caps_mt2701, 1467 }, { 1468 .compatible = "mediatek,mt2712-nfc", 1469 .data = &mtk_nfc_caps_mt2712, 1470 }, { 1471 .compatible = "mediatek,mt7622-nfc", 1472 .data = &mtk_nfc_caps_mt7622, 1473 }, 1474 {} 1475 }; 1476 MODULE_DEVICE_TABLE(of, mtk_nfc_id_table); 1477 1478 static int mtk_nfc_probe(struct platform_device *pdev) 1479 { 1480 struct device *dev = &pdev->dev; 1481 struct device_node *np = dev->of_node; 1482 struct mtk_nfc *nfc; 1483 struct resource *res; 1484 int ret, irq; 1485 1486 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1487 if (!nfc) 1488 return -ENOMEM; 1489 1490 nand_controller_init(&nfc->controller); 1491 INIT_LIST_HEAD(&nfc->chips); 1492 nfc->controller.ops = &mtk_nfc_controller_ops; 1493 1494 /* probe defer if not ready */ 1495 nfc->ecc = of_mtk_ecc_get(np); 1496 if (IS_ERR(nfc->ecc)) 1497 return PTR_ERR(nfc->ecc); 1498 else if (!nfc->ecc) 1499 return -ENODEV; 1500 1501 nfc->caps = of_device_get_match_data(dev); 1502 nfc->dev = dev; 1503 1504 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1505 nfc->regs = devm_ioremap_resource(dev, res); 1506 if (IS_ERR(nfc->regs)) { 1507 ret = PTR_ERR(nfc->regs); 1508 goto release_ecc; 1509 } 1510 1511 nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk"); 1512 if (IS_ERR(nfc->clk.nfi_clk)) { 1513 dev_err(dev, "no clk\n"); 1514 ret = PTR_ERR(nfc->clk.nfi_clk); 1515 goto release_ecc; 1516 } 1517 1518 nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk"); 1519 if (IS_ERR(nfc->clk.pad_clk)) { 1520 dev_err(dev, "no pad clk\n"); 1521 ret = PTR_ERR(nfc->clk.pad_clk); 1522 goto release_ecc; 1523 } 1524 1525 ret = mtk_nfc_enable_clk(dev, &nfc->clk); 1526 if (ret) 1527 goto release_ecc; 1528 1529 irq = platform_get_irq(pdev, 0); 1530 if (irq < 0) { 1531 dev_err(dev, "no nfi irq resource\n"); 1532 ret = -EINVAL; 1533 goto clk_disable; 1534 } 1535 1536 ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc); 1537 if (ret) { 1538 dev_err(dev, "failed to request nfi irq\n"); 1539 goto clk_disable; 1540 } 1541 1542 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 1543 if (ret) { 1544 dev_err(dev, "failed to set dma mask\n"); 1545 goto clk_disable; 1546 } 1547 1548 platform_set_drvdata(pdev, nfc); 1549 1550 ret = mtk_nfc_nand_chips_init(dev, nfc); 1551 if (ret) { 1552 dev_err(dev, "failed to init nand chips\n"); 1553 goto clk_disable; 1554 } 1555 1556 return 0; 1557 1558 clk_disable: 1559 mtk_nfc_disable_clk(&nfc->clk); 1560 1561 release_ecc: 1562 mtk_ecc_release(nfc->ecc); 1563 1564 return ret; 1565 } 1566 1567 static int mtk_nfc_remove(struct platform_device *pdev) 1568 { 1569 struct mtk_nfc *nfc = platform_get_drvdata(pdev); 1570 struct mtk_nfc_nand_chip *chip; 1571 1572 while (!list_empty(&nfc->chips)) { 1573 chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip, 1574 node); 1575 nand_release(&chip->nand); 1576 list_del(&chip->node); 1577 } 1578 1579 mtk_ecc_release(nfc->ecc); 1580 mtk_nfc_disable_clk(&nfc->clk); 1581 1582 return 0; 1583 } 1584 1585 #ifdef CONFIG_PM_SLEEP 1586 static int mtk_nfc_suspend(struct device *dev) 1587 { 1588 struct mtk_nfc *nfc = dev_get_drvdata(dev); 1589 1590 mtk_nfc_disable_clk(&nfc->clk); 1591 1592 return 0; 1593 } 1594 1595 static int mtk_nfc_resume(struct device *dev) 1596 { 1597 struct mtk_nfc *nfc = dev_get_drvdata(dev); 1598 struct mtk_nfc_nand_chip *chip; 1599 struct nand_chip *nand; 1600 int ret; 1601 u32 i; 1602 1603 udelay(200); 1604 1605 ret = mtk_nfc_enable_clk(dev, &nfc->clk); 1606 if (ret) 1607 return ret; 1608 1609 /* reset NAND chip if VCC was powered off */ 1610 list_for_each_entry(chip, &nfc->chips, node) { 1611 nand = &chip->nand; 1612 for (i = 0; i < chip->nsels; i++) 1613 nand_reset(nand, i); 1614 } 1615 1616 return 0; 1617 } 1618 1619 static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume); 1620 #endif 1621 1622 static struct platform_driver mtk_nfc_driver = { 1623 .probe = mtk_nfc_probe, 1624 .remove = mtk_nfc_remove, 1625 .driver = { 1626 .name = MTK_NAME, 1627 .of_match_table = mtk_nfc_id_table, 1628 #ifdef CONFIG_PM_SLEEP 1629 .pm = &mtk_nfc_pm_ops, 1630 #endif 1631 }, 1632 }; 1633 1634 module_platform_driver(mtk_nfc_driver); 1635 1636 MODULE_LICENSE("GPL"); 1637 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>"); 1638 MODULE_DESCRIPTION("MTK Nand Flash Controller Driver"); 1639