1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * Copyright 2009 Semihalf. 5 * 6 * Approved as OSADL project by a majority of OSADL members and funded 7 * by OSADL membership fees in 2009; for details see www.osadl.org. 8 * 9 * Based on original driver from Freescale Semiconductor 10 * written by John Rigby <jrigby@freescale.com> on basis of mxc_nand.c. 11 * Reworked and extended by Piotr Ziecik <kosmo@semihalf.com>. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/gfp.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/rawnand.h> 23 #include <linux/mtd/partitions.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 29 #include <asm/mpc5121.h> 30 31 /* Addresses for NFC MAIN RAM BUFFER areas */ 32 #define NFC_MAIN_AREA(n) ((n) * 0x200) 33 34 /* Addresses for NFC SPARE BUFFER areas */ 35 #define NFC_SPARE_BUFFERS 8 36 #define NFC_SPARE_LEN 0x40 37 #define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN)) 38 39 /* MPC5121 NFC registers */ 40 #define NFC_BUF_ADDR 0x1E04 41 #define NFC_FLASH_ADDR 0x1E06 42 #define NFC_FLASH_CMD 0x1E08 43 #define NFC_CONFIG 0x1E0A 44 #define NFC_ECC_STATUS1 0x1E0C 45 #define NFC_ECC_STATUS2 0x1E0E 46 #define NFC_SPAS 0x1E10 47 #define NFC_WRPROT 0x1E12 48 #define NFC_NF_WRPRST 0x1E18 49 #define NFC_CONFIG1 0x1E1A 50 #define NFC_CONFIG2 0x1E1C 51 #define NFC_UNLOCKSTART_BLK0 0x1E20 52 #define NFC_UNLOCKEND_BLK0 0x1E22 53 #define NFC_UNLOCKSTART_BLK1 0x1E24 54 #define NFC_UNLOCKEND_BLK1 0x1E26 55 #define NFC_UNLOCKSTART_BLK2 0x1E28 56 #define NFC_UNLOCKEND_BLK2 0x1E2A 57 #define NFC_UNLOCKSTART_BLK3 0x1E2C 58 #define NFC_UNLOCKEND_BLK3 0x1E2E 59 60 /* Bit Definitions: NFC_BUF_ADDR */ 61 #define NFC_RBA_MASK (7 << 0) 62 #define NFC_ACTIVE_CS_SHIFT 5 63 #define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT) 64 65 /* Bit Definitions: NFC_CONFIG */ 66 #define NFC_BLS_UNLOCKED (1 << 1) 67 68 /* Bit Definitions: NFC_CONFIG1 */ 69 #define NFC_ECC_4BIT (1 << 0) 70 #define NFC_FULL_PAGE_DMA (1 << 1) 71 #define NFC_SPARE_ONLY (1 << 2) 72 #define NFC_ECC_ENABLE (1 << 3) 73 #define NFC_INT_MASK (1 << 4) 74 #define NFC_BIG_ENDIAN (1 << 5) 75 #define NFC_RESET (1 << 6) 76 #define NFC_CE (1 << 7) 77 #define NFC_ONE_CYCLE (1 << 8) 78 #define NFC_PPB_32 (0 << 9) 79 #define NFC_PPB_64 (1 << 9) 80 #define NFC_PPB_128 (2 << 9) 81 #define NFC_PPB_256 (3 << 9) 82 #define NFC_PPB_MASK (3 << 9) 83 #define NFC_FULL_PAGE_INT (1 << 11) 84 85 /* Bit Definitions: NFC_CONFIG2 */ 86 #define NFC_COMMAND (1 << 0) 87 #define NFC_ADDRESS (1 << 1) 88 #define NFC_INPUT (1 << 2) 89 #define NFC_OUTPUT (1 << 3) 90 #define NFC_ID (1 << 4) 91 #define NFC_STATUS (1 << 5) 92 #define NFC_CMD_FAIL (1 << 15) 93 #define NFC_INT (1 << 15) 94 95 /* Bit Definitions: NFC_WRPROT */ 96 #define NFC_WPC_LOCK_TIGHT (1 << 0) 97 #define NFC_WPC_LOCK (1 << 1) 98 #define NFC_WPC_UNLOCK (1 << 2) 99 100 #define DRV_NAME "mpc5121_nfc" 101 102 /* Timeouts */ 103 #define NFC_RESET_TIMEOUT 1000 /* 1 ms */ 104 #define NFC_TIMEOUT (HZ / 10) /* 1/10 s */ 105 106 struct mpc5121_nfc_prv { 107 struct nand_controller controller; 108 struct nand_chip chip; 109 int irq; 110 void __iomem *regs; 111 struct clk *clk; 112 wait_queue_head_t irq_waitq; 113 uint column; 114 int spareonly; 115 void __iomem *csreg; 116 struct device *dev; 117 }; 118 119 static void mpc5121_nfc_done(struct mtd_info *mtd); 120 121 /* Read NFC register */ 122 static inline u16 nfc_read(struct mtd_info *mtd, uint reg) 123 { 124 struct nand_chip *chip = mtd_to_nand(mtd); 125 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 126 127 return in_be16(prv->regs + reg); 128 } 129 130 /* Write NFC register */ 131 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val) 132 { 133 struct nand_chip *chip = mtd_to_nand(mtd); 134 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 135 136 out_be16(prv->regs + reg, val); 137 } 138 139 /* Set bits in NFC register */ 140 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits) 141 { 142 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits); 143 } 144 145 /* Clear bits in NFC register */ 146 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits) 147 { 148 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits); 149 } 150 151 /* Invoke address cycle */ 152 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr) 153 { 154 nfc_write(mtd, NFC_FLASH_ADDR, addr); 155 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS); 156 mpc5121_nfc_done(mtd); 157 } 158 159 /* Invoke command cycle */ 160 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd) 161 { 162 nfc_write(mtd, NFC_FLASH_CMD, cmd); 163 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND); 164 mpc5121_nfc_done(mtd); 165 } 166 167 /* Send data from NFC buffers to NAND flash */ 168 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd) 169 { 170 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 171 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT); 172 mpc5121_nfc_done(mtd); 173 } 174 175 /* Receive data from NAND flash */ 176 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd) 177 { 178 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 179 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT); 180 mpc5121_nfc_done(mtd); 181 } 182 183 /* Receive ID from NAND flash */ 184 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd) 185 { 186 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 187 nfc_write(mtd, NFC_CONFIG2, NFC_ID); 188 mpc5121_nfc_done(mtd); 189 } 190 191 /* Receive status from NAND flash */ 192 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd) 193 { 194 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 195 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS); 196 mpc5121_nfc_done(mtd); 197 } 198 199 /* NFC interrupt handler */ 200 static irqreturn_t mpc5121_nfc_irq(int irq, void *data) 201 { 202 struct mtd_info *mtd = data; 203 struct nand_chip *chip = mtd_to_nand(mtd); 204 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 205 206 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK); 207 wake_up(&prv->irq_waitq); 208 209 return IRQ_HANDLED; 210 } 211 212 /* Wait for operation complete */ 213 static void mpc5121_nfc_done(struct mtd_info *mtd) 214 { 215 struct nand_chip *chip = mtd_to_nand(mtd); 216 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 217 int rv; 218 219 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) { 220 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK); 221 rv = wait_event_timeout(prv->irq_waitq, 222 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT); 223 224 if (!rv) 225 dev_warn(prv->dev, 226 "Timeout while waiting for interrupt.\n"); 227 } 228 229 nfc_clear(mtd, NFC_CONFIG2, NFC_INT); 230 } 231 232 /* Do address cycle(s) */ 233 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) 234 { 235 struct nand_chip *chip = mtd_to_nand(mtd); 236 u32 pagemask = chip->pagemask; 237 238 if (column != -1) { 239 mpc5121_nfc_send_addr(mtd, column); 240 if (mtd->writesize > 512) 241 mpc5121_nfc_send_addr(mtd, column >> 8); 242 } 243 244 if (page != -1) { 245 do { 246 mpc5121_nfc_send_addr(mtd, page & 0xFF); 247 page >>= 8; 248 pagemask >>= 8; 249 } while (pagemask); 250 } 251 } 252 253 /* Control chip select signals */ 254 static void mpc5121_nfc_select_chip(struct nand_chip *nand, int chip) 255 { 256 struct mtd_info *mtd = nand_to_mtd(nand); 257 258 if (chip < 0) { 259 nfc_clear(mtd, NFC_CONFIG1, NFC_CE); 260 return; 261 } 262 263 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK); 264 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) & 265 NFC_ACTIVE_CS_MASK); 266 nfc_set(mtd, NFC_CONFIG1, NFC_CE); 267 } 268 269 /* Init external chip select logic on ADS5121 board */ 270 static int ads5121_chipselect_init(struct mtd_info *mtd) 271 { 272 struct nand_chip *chip = mtd_to_nand(mtd); 273 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 274 struct device_node *dn; 275 276 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld"); 277 if (dn) { 278 prv->csreg = of_iomap(dn, 0); 279 of_node_put(dn); 280 if (!prv->csreg) 281 return -ENOMEM; 282 283 /* CPLD Register 9 controls NAND /CE Lines */ 284 prv->csreg += 9; 285 return 0; 286 } 287 288 return -EINVAL; 289 } 290 291 /* Control chips select signal on ADS5121 board */ 292 static void ads5121_select_chip(struct nand_chip *nand, int chip) 293 { 294 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand); 295 u8 v; 296 297 v = in_8(prv->csreg); 298 v |= 0x0F; 299 300 if (chip >= 0) { 301 mpc5121_nfc_select_chip(nand, 0); 302 v &= ~(1 << chip); 303 } else 304 mpc5121_nfc_select_chip(nand, -1); 305 306 out_8(prv->csreg, v); 307 } 308 309 /* Read NAND Ready/Busy signal */ 310 static int mpc5121_nfc_dev_ready(struct nand_chip *nand) 311 { 312 /* 313 * NFC handles ready/busy signal internally. Therefore, this function 314 * always returns status as ready. 315 */ 316 return 1; 317 } 318 319 /* Write command to NAND flash */ 320 static void mpc5121_nfc_command(struct nand_chip *chip, unsigned command, 321 int column, int page) 322 { 323 struct mtd_info *mtd = nand_to_mtd(chip); 324 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 325 326 prv->column = (column >= 0) ? column : 0; 327 prv->spareonly = 0; 328 329 switch (command) { 330 case NAND_CMD_PAGEPROG: 331 mpc5121_nfc_send_prog_page(mtd); 332 break; 333 /* 334 * NFC does not support sub-page reads and writes, 335 * so emulate them using full page transfers. 336 */ 337 case NAND_CMD_READ0: 338 column = 0; 339 break; 340 341 case NAND_CMD_READ1: 342 prv->column += 256; 343 command = NAND_CMD_READ0; 344 column = 0; 345 break; 346 347 case NAND_CMD_READOOB: 348 prv->spareonly = 1; 349 command = NAND_CMD_READ0; 350 column = 0; 351 break; 352 353 case NAND_CMD_SEQIN: 354 mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page); 355 column = 0; 356 break; 357 358 case NAND_CMD_ERASE1: 359 case NAND_CMD_ERASE2: 360 case NAND_CMD_READID: 361 case NAND_CMD_STATUS: 362 break; 363 364 default: 365 return; 366 } 367 368 mpc5121_nfc_send_cmd(mtd, command); 369 mpc5121_nfc_addr_cycle(mtd, column, page); 370 371 switch (command) { 372 case NAND_CMD_READ0: 373 if (mtd->writesize > 512) 374 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART); 375 mpc5121_nfc_send_read_page(mtd); 376 break; 377 378 case NAND_CMD_READID: 379 mpc5121_nfc_send_read_id(mtd); 380 break; 381 382 case NAND_CMD_STATUS: 383 mpc5121_nfc_send_read_status(mtd); 384 if (chip->options & NAND_BUSWIDTH_16) 385 prv->column = 1; 386 else 387 prv->column = 0; 388 break; 389 } 390 } 391 392 /* Copy data from/to NFC spare buffers. */ 393 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset, 394 u8 *buffer, uint size, int wr) 395 { 396 struct nand_chip *nand = mtd_to_nand(mtd); 397 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand); 398 uint o, s, sbsize, blksize; 399 400 /* 401 * NAND spare area is available through NFC spare buffers. 402 * The NFC divides spare area into (page_size / 512) chunks. 403 * Each chunk is placed into separate spare memory area, using 404 * first (spare_size / num_of_chunks) bytes of the buffer. 405 * 406 * For NAND device in which the spare area is not divided fully 407 * by the number of chunks, number of used bytes in each spare 408 * buffer is rounded down to the nearest even number of bytes, 409 * and all remaining bytes are added to the last used spare area. 410 * 411 * For more information read section 26.6.10 of MPC5121e 412 * Microcontroller Reference Manual, Rev. 3. 413 */ 414 415 /* Calculate number of valid bytes in each spare buffer */ 416 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1; 417 418 while (size) { 419 /* Calculate spare buffer number */ 420 s = offset / sbsize; 421 if (s > NFC_SPARE_BUFFERS - 1) 422 s = NFC_SPARE_BUFFERS - 1; 423 424 /* 425 * Calculate offset to requested data block in selected spare 426 * buffer and its size. 427 */ 428 o = offset - (s * sbsize); 429 blksize = min(sbsize - o, size); 430 431 if (wr) 432 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o, 433 buffer, blksize); 434 else 435 memcpy_fromio(buffer, 436 prv->regs + NFC_SPARE_AREA(s) + o, blksize); 437 438 buffer += blksize; 439 offset += blksize; 440 size -= blksize; 441 } 442 } 443 444 /* Copy data from/to NFC main and spare buffers */ 445 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len, 446 int wr) 447 { 448 struct nand_chip *chip = mtd_to_nand(mtd); 449 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 450 uint c = prv->column; 451 uint l; 452 453 /* Handle spare area access */ 454 if (prv->spareonly || c >= mtd->writesize) { 455 /* Calculate offset from beginning of spare area */ 456 if (c >= mtd->writesize) 457 c -= mtd->writesize; 458 459 prv->column += len; 460 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr); 461 return; 462 } 463 464 /* 465 * Handle main area access - limit copy length to prevent 466 * crossing main/spare boundary. 467 */ 468 l = min((uint)len, mtd->writesize - c); 469 prv->column += l; 470 471 if (wr) 472 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l); 473 else 474 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l); 475 476 /* Handle crossing main/spare boundary */ 477 if (l != len) { 478 buf += l; 479 len -= l; 480 mpc5121_nfc_buf_copy(mtd, buf, len, wr); 481 } 482 } 483 484 /* Read data from NFC buffers */ 485 static void mpc5121_nfc_read_buf(struct nand_chip *chip, u_char *buf, int len) 486 { 487 mpc5121_nfc_buf_copy(nand_to_mtd(chip), buf, len, 0); 488 } 489 490 /* Write data to NFC buffers */ 491 static void mpc5121_nfc_write_buf(struct nand_chip *chip, const u_char *buf, 492 int len) 493 { 494 mpc5121_nfc_buf_copy(nand_to_mtd(chip), (u_char *)buf, len, 1); 495 } 496 497 /* Read byte from NFC buffers */ 498 static u8 mpc5121_nfc_read_byte(struct nand_chip *chip) 499 { 500 u8 tmp; 501 502 mpc5121_nfc_read_buf(chip, &tmp, sizeof(tmp)); 503 504 return tmp; 505 } 506 507 /* 508 * Read NFC configuration from Reset Config Word 509 * 510 * NFC is configured during reset in basis of information stored 511 * in Reset Config Word. There is no other way to set NAND block 512 * size, spare size and bus width. 513 */ 514 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd) 515 { 516 struct nand_chip *chip = mtd_to_nand(mtd); 517 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 518 struct mpc512x_reset_module *rm; 519 struct device_node *rmnode; 520 uint rcw_pagesize = 0; 521 uint rcw_sparesize = 0; 522 uint rcw_width; 523 uint rcwh; 524 uint romloc, ps; 525 int ret = 0; 526 527 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset"); 528 if (!rmnode) { 529 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' " 530 "node in device tree!\n"); 531 return -ENODEV; 532 } 533 534 rm = of_iomap(rmnode, 0); 535 if (!rm) { 536 dev_err(prv->dev, "Error mapping reset module node!\n"); 537 ret = -EBUSY; 538 goto out; 539 } 540 541 rcwh = in_be32(&rm->rcwhr); 542 543 /* Bit 6: NFC bus width */ 544 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1; 545 546 /* Bit 7: NFC Page/Spare size */ 547 ps = (rcwh >> 7) & 0x1; 548 549 /* Bits [22:21]: ROM Location */ 550 romloc = (rcwh >> 21) & 0x3; 551 552 /* Decode RCW bits */ 553 switch ((ps << 2) | romloc) { 554 case 0x00: 555 case 0x01: 556 rcw_pagesize = 512; 557 rcw_sparesize = 16; 558 break; 559 case 0x02: 560 case 0x03: 561 rcw_pagesize = 4096; 562 rcw_sparesize = 128; 563 break; 564 case 0x04: 565 case 0x05: 566 rcw_pagesize = 2048; 567 rcw_sparesize = 64; 568 break; 569 case 0x06: 570 case 0x07: 571 rcw_pagesize = 4096; 572 rcw_sparesize = 218; 573 break; 574 } 575 576 mtd->writesize = rcw_pagesize; 577 mtd->oobsize = rcw_sparesize; 578 if (rcw_width == 2) 579 chip->options |= NAND_BUSWIDTH_16; 580 581 dev_notice(prv->dev, "Configured for " 582 "%u-bit NAND, page size %u " 583 "with %u spare.\n", 584 rcw_width * 8, rcw_pagesize, 585 rcw_sparesize); 586 iounmap(rm); 587 out: 588 of_node_put(rmnode); 589 return ret; 590 } 591 592 /* Free driver resources */ 593 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd) 594 { 595 struct nand_chip *chip = mtd_to_nand(mtd); 596 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 597 598 clk_disable_unprepare(prv->clk); 599 600 if (prv->csreg) 601 iounmap(prv->csreg); 602 } 603 604 static int mpc5121_nfc_attach_chip(struct nand_chip *chip) 605 { 606 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 607 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) 608 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 609 610 return 0; 611 } 612 613 static const struct nand_controller_ops mpc5121_nfc_ops = { 614 .attach_chip = mpc5121_nfc_attach_chip, 615 }; 616 617 static int mpc5121_nfc_probe(struct platform_device *op) 618 { 619 struct device_node *dn = op->dev.of_node; 620 struct clk *clk; 621 struct device *dev = &op->dev; 622 struct mpc5121_nfc_prv *prv; 623 struct resource res; 624 struct mtd_info *mtd; 625 struct nand_chip *chip; 626 unsigned long regs_paddr, regs_size; 627 const __be32 *chips_no; 628 int resettime = 0; 629 int retval = 0; 630 int rev, len; 631 632 /* 633 * Check SoC revision. This driver supports only NFC 634 * in MPC5121 revision 2 and MPC5123 revision 3. 635 */ 636 rev = (mfspr(SPRN_SVR) >> 4) & 0xF; 637 if ((rev != 2) && (rev != 3)) { 638 dev_err(dev, "SoC revision %u is not supported!\n", rev); 639 return -ENXIO; 640 } 641 642 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL); 643 if (!prv) 644 return -ENOMEM; 645 646 chip = &prv->chip; 647 mtd = nand_to_mtd(chip); 648 649 nand_controller_init(&prv->controller); 650 prv->controller.ops = &mpc5121_nfc_ops; 651 chip->controller = &prv->controller; 652 653 mtd->dev.parent = dev; 654 nand_set_controller_data(chip, prv); 655 nand_set_flash_node(chip, dn); 656 prv->dev = dev; 657 658 /* Read NFC configuration from Reset Config Word */ 659 retval = mpc5121_nfc_read_hw_config(mtd); 660 if (retval) { 661 dev_err(dev, "Unable to read NFC config!\n"); 662 return retval; 663 } 664 665 prv->irq = irq_of_parse_and_map(dn, 0); 666 if (prv->irq == NO_IRQ) { 667 dev_err(dev, "Error mapping IRQ!\n"); 668 return -EINVAL; 669 } 670 671 retval = of_address_to_resource(dn, 0, &res); 672 if (retval) { 673 dev_err(dev, "Error parsing memory region!\n"); 674 return retval; 675 } 676 677 chips_no = of_get_property(dn, "chips", &len); 678 if (!chips_no || len != sizeof(*chips_no)) { 679 dev_err(dev, "Invalid/missing 'chips' property!\n"); 680 return -EINVAL; 681 } 682 683 regs_paddr = res.start; 684 regs_size = resource_size(&res); 685 686 if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) { 687 dev_err(dev, "Error requesting memory region!\n"); 688 return -EBUSY; 689 } 690 691 prv->regs = devm_ioremap(dev, regs_paddr, regs_size); 692 if (!prv->regs) { 693 dev_err(dev, "Error mapping memory region!\n"); 694 return -ENOMEM; 695 } 696 697 mtd->name = "MPC5121 NAND"; 698 chip->legacy.dev_ready = mpc5121_nfc_dev_ready; 699 chip->legacy.cmdfunc = mpc5121_nfc_command; 700 chip->legacy.read_byte = mpc5121_nfc_read_byte; 701 chip->legacy.read_buf = mpc5121_nfc_read_buf; 702 chip->legacy.write_buf = mpc5121_nfc_write_buf; 703 chip->legacy.select_chip = mpc5121_nfc_select_chip; 704 chip->legacy.set_features = nand_get_set_features_notsupp; 705 chip->legacy.get_features = nand_get_set_features_notsupp; 706 chip->bbt_options = NAND_BBT_USE_FLASH; 707 708 /* Support external chip-select logic on ADS5121 board */ 709 if (of_machine_is_compatible("fsl,mpc5121ads")) { 710 retval = ads5121_chipselect_init(mtd); 711 if (retval) { 712 dev_err(dev, "Chipselect init error!\n"); 713 return retval; 714 } 715 716 chip->legacy.select_chip = ads5121_select_chip; 717 } 718 719 /* Enable NFC clock */ 720 clk = devm_clk_get(dev, "ipg"); 721 if (IS_ERR(clk)) { 722 dev_err(dev, "Unable to acquire NFC clock!\n"); 723 retval = PTR_ERR(clk); 724 goto error; 725 } 726 retval = clk_prepare_enable(clk); 727 if (retval) { 728 dev_err(dev, "Unable to enable NFC clock!\n"); 729 goto error; 730 } 731 prv->clk = clk; 732 733 /* Reset NAND Flash controller */ 734 nfc_set(mtd, NFC_CONFIG1, NFC_RESET); 735 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) { 736 if (resettime++ >= NFC_RESET_TIMEOUT) { 737 dev_err(dev, "Timeout while resetting NFC!\n"); 738 retval = -EINVAL; 739 goto error; 740 } 741 742 udelay(1); 743 } 744 745 /* Enable write to NFC memory */ 746 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED); 747 748 /* Enable write to all NAND pages */ 749 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000); 750 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF); 751 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK); 752 753 /* 754 * Setup NFC: 755 * - Big Endian transfers, 756 * - Interrupt after full page read/write. 757 */ 758 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK | 759 NFC_FULL_PAGE_INT); 760 761 /* Set spare area size */ 762 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1); 763 764 init_waitqueue_head(&prv->irq_waitq); 765 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME, 766 mtd); 767 if (retval) { 768 dev_err(dev, "Error requesting IRQ!\n"); 769 goto error; 770 } 771 772 /* 773 * This driver assumes that the default ECC engine should be TYPE_SOFT. 774 * Set ->engine_type before registering the NAND devices in order to 775 * provide a driver specific default value. 776 */ 777 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 778 779 /* Detect NAND chips */ 780 retval = nand_scan(chip, be32_to_cpup(chips_no)); 781 if (retval) { 782 dev_err(dev, "NAND Flash not found !\n"); 783 goto error; 784 } 785 786 /* Set erase block size */ 787 switch (mtd->erasesize / mtd->writesize) { 788 case 32: 789 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32); 790 break; 791 792 case 64: 793 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64); 794 break; 795 796 case 128: 797 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128); 798 break; 799 800 case 256: 801 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256); 802 break; 803 804 default: 805 dev_err(dev, "Unsupported NAND flash!\n"); 806 retval = -ENXIO; 807 goto error; 808 } 809 810 dev_set_drvdata(dev, mtd); 811 812 /* Register device in MTD */ 813 retval = mtd_device_register(mtd, NULL, 0); 814 if (retval) { 815 dev_err(dev, "Error adding MTD device!\n"); 816 goto error; 817 } 818 819 return 0; 820 error: 821 mpc5121_nfc_free(dev, mtd); 822 return retval; 823 } 824 825 static int mpc5121_nfc_remove(struct platform_device *op) 826 { 827 struct device *dev = &op->dev; 828 struct mtd_info *mtd = dev_get_drvdata(dev); 829 int ret; 830 831 ret = mtd_device_unregister(mtd); 832 WARN_ON(ret); 833 nand_cleanup(mtd_to_nand(mtd)); 834 mpc5121_nfc_free(dev, mtd); 835 836 return 0; 837 } 838 839 static const struct of_device_id mpc5121_nfc_match[] = { 840 { .compatible = "fsl,mpc5121-nfc", }, 841 {}, 842 }; 843 MODULE_DEVICE_TABLE(of, mpc5121_nfc_match); 844 845 static struct platform_driver mpc5121_nfc_driver = { 846 .probe = mpc5121_nfc_probe, 847 .remove = mpc5121_nfc_remove, 848 .driver = { 849 .name = DRV_NAME, 850 .of_match_table = mpc5121_nfc_match, 851 }, 852 }; 853 854 module_platform_driver(mpc5121_nfc_driver); 855 856 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 857 MODULE_DESCRIPTION("MPC5121 NAND MTD driver"); 858 MODULE_LICENSE("GPL"); 859