xref: /openbmc/linux/drivers/mtd/nand/raw/mpc5121_nfc.c (revision 151f4e2b)
1 /*
2  * Copyright 2004-2008 Freescale Semiconductor, Inc.
3  * Copyright 2009 Semihalf.
4  *
5  * Approved as OSADL project by a majority of OSADL members and funded
6  * by OSADL membership fees in 2009;  for details see www.osadl.org.
7  *
8  * Based on original driver from Freescale Semiconductor
9  * written by John Rigby <jrigby@freescale.com> on basis of mxc_nand.c.
10  * Reworked and extended by Piotr Ziecik <kosmo@semihalf.com>.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License
14  * as published by the Free Software Foundation; either version 2
15  * of the License, or (at your option) any later version.
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24  * MA 02110-1301, USA.
25  */
26 
27 #include <linux/module.h>
28 #include <linux/clk.h>
29 #include <linux/gfp.h>
30 #include <linux/delay.h>
31 #include <linux/err.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/rawnand.h>
36 #include <linux/mtd/partitions.h>
37 #include <linux/of_address.h>
38 #include <linux/of_device.h>
39 #include <linux/of_irq.h>
40 #include <linux/of_platform.h>
41 
42 #include <asm/mpc5121.h>
43 
44 /* Addresses for NFC MAIN RAM BUFFER areas */
45 #define NFC_MAIN_AREA(n)	((n) *  0x200)
46 
47 /* Addresses for NFC SPARE BUFFER areas */
48 #define NFC_SPARE_BUFFERS	8
49 #define NFC_SPARE_LEN		0x40
50 #define NFC_SPARE_AREA(n)	(0x1000 + ((n) * NFC_SPARE_LEN))
51 
52 /* MPC5121 NFC registers */
53 #define NFC_BUF_ADDR		0x1E04
54 #define NFC_FLASH_ADDR		0x1E06
55 #define NFC_FLASH_CMD		0x1E08
56 #define NFC_CONFIG		0x1E0A
57 #define NFC_ECC_STATUS1		0x1E0C
58 #define NFC_ECC_STATUS2		0x1E0E
59 #define NFC_SPAS		0x1E10
60 #define NFC_WRPROT		0x1E12
61 #define NFC_NF_WRPRST		0x1E18
62 #define NFC_CONFIG1		0x1E1A
63 #define NFC_CONFIG2		0x1E1C
64 #define NFC_UNLOCKSTART_BLK0	0x1E20
65 #define NFC_UNLOCKEND_BLK0	0x1E22
66 #define NFC_UNLOCKSTART_BLK1	0x1E24
67 #define NFC_UNLOCKEND_BLK1	0x1E26
68 #define NFC_UNLOCKSTART_BLK2	0x1E28
69 #define NFC_UNLOCKEND_BLK2	0x1E2A
70 #define NFC_UNLOCKSTART_BLK3	0x1E2C
71 #define NFC_UNLOCKEND_BLK3	0x1E2E
72 
73 /* Bit Definitions: NFC_BUF_ADDR */
74 #define NFC_RBA_MASK		(7 << 0)
75 #define NFC_ACTIVE_CS_SHIFT	5
76 #define NFC_ACTIVE_CS_MASK	(3 << NFC_ACTIVE_CS_SHIFT)
77 
78 /* Bit Definitions: NFC_CONFIG */
79 #define NFC_BLS_UNLOCKED	(1 << 1)
80 
81 /* Bit Definitions: NFC_CONFIG1 */
82 #define NFC_ECC_4BIT		(1 << 0)
83 #define NFC_FULL_PAGE_DMA	(1 << 1)
84 #define NFC_SPARE_ONLY		(1 << 2)
85 #define NFC_ECC_ENABLE		(1 << 3)
86 #define NFC_INT_MASK		(1 << 4)
87 #define NFC_BIG_ENDIAN		(1 << 5)
88 #define NFC_RESET		(1 << 6)
89 #define NFC_CE			(1 << 7)
90 #define NFC_ONE_CYCLE		(1 << 8)
91 #define NFC_PPB_32		(0 << 9)
92 #define NFC_PPB_64		(1 << 9)
93 #define NFC_PPB_128		(2 << 9)
94 #define NFC_PPB_256		(3 << 9)
95 #define NFC_PPB_MASK		(3 << 9)
96 #define NFC_FULL_PAGE_INT	(1 << 11)
97 
98 /* Bit Definitions: NFC_CONFIG2 */
99 #define NFC_COMMAND		(1 << 0)
100 #define NFC_ADDRESS		(1 << 1)
101 #define NFC_INPUT		(1 << 2)
102 #define NFC_OUTPUT		(1 << 3)
103 #define NFC_ID			(1 << 4)
104 #define NFC_STATUS		(1 << 5)
105 #define NFC_CMD_FAIL		(1 << 15)
106 #define NFC_INT			(1 << 15)
107 
108 /* Bit Definitions: NFC_WRPROT */
109 #define NFC_WPC_LOCK_TIGHT	(1 << 0)
110 #define NFC_WPC_LOCK		(1 << 1)
111 #define NFC_WPC_UNLOCK		(1 << 2)
112 
113 #define	DRV_NAME		"mpc5121_nfc"
114 
115 /* Timeouts */
116 #define NFC_RESET_TIMEOUT	1000		/* 1 ms */
117 #define NFC_TIMEOUT		(HZ / 10)	/* 1/10 s */
118 
119 struct mpc5121_nfc_prv {
120 	struct nand_chip	chip;
121 	int			irq;
122 	void __iomem		*regs;
123 	struct clk		*clk;
124 	wait_queue_head_t	irq_waitq;
125 	uint			column;
126 	int			spareonly;
127 	void __iomem		*csreg;
128 	struct device		*dev;
129 };
130 
131 static void mpc5121_nfc_done(struct mtd_info *mtd);
132 
133 /* Read NFC register */
134 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
135 {
136 	struct nand_chip *chip = mtd_to_nand(mtd);
137 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
138 
139 	return in_be16(prv->regs + reg);
140 }
141 
142 /* Write NFC register */
143 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
144 {
145 	struct nand_chip *chip = mtd_to_nand(mtd);
146 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
147 
148 	out_be16(prv->regs + reg, val);
149 }
150 
151 /* Set bits in NFC register */
152 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
153 {
154 	nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
155 }
156 
157 /* Clear bits in NFC register */
158 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
159 {
160 	nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
161 }
162 
163 /* Invoke address cycle */
164 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
165 {
166 	nfc_write(mtd, NFC_FLASH_ADDR, addr);
167 	nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
168 	mpc5121_nfc_done(mtd);
169 }
170 
171 /* Invoke command cycle */
172 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
173 {
174 	nfc_write(mtd, NFC_FLASH_CMD, cmd);
175 	nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
176 	mpc5121_nfc_done(mtd);
177 }
178 
179 /* Send data from NFC buffers to NAND flash */
180 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
181 {
182 	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
183 	nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
184 	mpc5121_nfc_done(mtd);
185 }
186 
187 /* Receive data from NAND flash */
188 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
189 {
190 	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
191 	nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
192 	mpc5121_nfc_done(mtd);
193 }
194 
195 /* Receive ID from NAND flash */
196 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
197 {
198 	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
199 	nfc_write(mtd, NFC_CONFIG2, NFC_ID);
200 	mpc5121_nfc_done(mtd);
201 }
202 
203 /* Receive status from NAND flash */
204 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
205 {
206 	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
207 	nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
208 	mpc5121_nfc_done(mtd);
209 }
210 
211 /* NFC interrupt handler */
212 static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
213 {
214 	struct mtd_info *mtd = data;
215 	struct nand_chip *chip = mtd_to_nand(mtd);
216 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
217 
218 	nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
219 	wake_up(&prv->irq_waitq);
220 
221 	return IRQ_HANDLED;
222 }
223 
224 /* Wait for operation complete */
225 static void mpc5121_nfc_done(struct mtd_info *mtd)
226 {
227 	struct nand_chip *chip = mtd_to_nand(mtd);
228 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
229 	int rv;
230 
231 	if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
232 		nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
233 		rv = wait_event_timeout(prv->irq_waitq,
234 			(nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
235 
236 		if (!rv)
237 			dev_warn(prv->dev,
238 				"Timeout while waiting for interrupt.\n");
239 	}
240 
241 	nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
242 }
243 
244 /* Do address cycle(s) */
245 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
246 {
247 	struct nand_chip *chip = mtd_to_nand(mtd);
248 	u32 pagemask = chip->pagemask;
249 
250 	if (column != -1) {
251 		mpc5121_nfc_send_addr(mtd, column);
252 		if (mtd->writesize > 512)
253 			mpc5121_nfc_send_addr(mtd, column >> 8);
254 	}
255 
256 	if (page != -1) {
257 		do {
258 			mpc5121_nfc_send_addr(mtd, page & 0xFF);
259 			page >>= 8;
260 			pagemask >>= 8;
261 		} while (pagemask);
262 	}
263 }
264 
265 /* Control chip select signals */
266 static void mpc5121_nfc_select_chip(struct nand_chip *nand, int chip)
267 {
268 	struct mtd_info *mtd = nand_to_mtd(nand);
269 
270 	if (chip < 0) {
271 		nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
272 		return;
273 	}
274 
275 	nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
276 	nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
277 							NFC_ACTIVE_CS_MASK);
278 	nfc_set(mtd, NFC_CONFIG1, NFC_CE);
279 }
280 
281 /* Init external chip select logic on ADS5121 board */
282 static int ads5121_chipselect_init(struct mtd_info *mtd)
283 {
284 	struct nand_chip *chip = mtd_to_nand(mtd);
285 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
286 	struct device_node *dn;
287 
288 	dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
289 	if (dn) {
290 		prv->csreg = of_iomap(dn, 0);
291 		of_node_put(dn);
292 		if (!prv->csreg)
293 			return -ENOMEM;
294 
295 		/* CPLD Register 9 controls NAND /CE Lines */
296 		prv->csreg += 9;
297 		return 0;
298 	}
299 
300 	return -EINVAL;
301 }
302 
303 /* Control chips select signal on ADS5121 board */
304 static void ads5121_select_chip(struct nand_chip *nand, int chip)
305 {
306 	struct mtd_info *mtd = nand_to_mtd(nand);
307 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
308 	u8 v;
309 
310 	v = in_8(prv->csreg);
311 	v |= 0x0F;
312 
313 	if (chip >= 0) {
314 		mpc5121_nfc_select_chip(nand, 0);
315 		v &= ~(1 << chip);
316 	} else
317 		mpc5121_nfc_select_chip(nand, -1);
318 
319 	out_8(prv->csreg, v);
320 }
321 
322 /* Read NAND Ready/Busy signal */
323 static int mpc5121_nfc_dev_ready(struct nand_chip *nand)
324 {
325 	/*
326 	 * NFC handles ready/busy signal internally. Therefore, this function
327 	 * always returns status as ready.
328 	 */
329 	return 1;
330 }
331 
332 /* Write command to NAND flash */
333 static void mpc5121_nfc_command(struct nand_chip *chip, unsigned command,
334 				int column, int page)
335 {
336 	struct mtd_info *mtd = nand_to_mtd(chip);
337 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
338 
339 	prv->column = (column >= 0) ? column : 0;
340 	prv->spareonly = 0;
341 
342 	switch (command) {
343 	case NAND_CMD_PAGEPROG:
344 		mpc5121_nfc_send_prog_page(mtd);
345 		break;
346 	/*
347 	 * NFC does not support sub-page reads and writes,
348 	 * so emulate them using full page transfers.
349 	 */
350 	case NAND_CMD_READ0:
351 		column = 0;
352 		break;
353 
354 	case NAND_CMD_READ1:
355 		prv->column += 256;
356 		command = NAND_CMD_READ0;
357 		column = 0;
358 		break;
359 
360 	case NAND_CMD_READOOB:
361 		prv->spareonly = 1;
362 		command = NAND_CMD_READ0;
363 		column = 0;
364 		break;
365 
366 	case NAND_CMD_SEQIN:
367 		mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page);
368 		column = 0;
369 		break;
370 
371 	case NAND_CMD_ERASE1:
372 	case NAND_CMD_ERASE2:
373 	case NAND_CMD_READID:
374 	case NAND_CMD_STATUS:
375 		break;
376 
377 	default:
378 		return;
379 	}
380 
381 	mpc5121_nfc_send_cmd(mtd, command);
382 	mpc5121_nfc_addr_cycle(mtd, column, page);
383 
384 	switch (command) {
385 	case NAND_CMD_READ0:
386 		if (mtd->writesize > 512)
387 			mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
388 		mpc5121_nfc_send_read_page(mtd);
389 		break;
390 
391 	case NAND_CMD_READID:
392 		mpc5121_nfc_send_read_id(mtd);
393 		break;
394 
395 	case NAND_CMD_STATUS:
396 		mpc5121_nfc_send_read_status(mtd);
397 		if (chip->options & NAND_BUSWIDTH_16)
398 			prv->column = 1;
399 		else
400 			prv->column = 0;
401 		break;
402 	}
403 }
404 
405 /* Copy data from/to NFC spare buffers. */
406 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
407 						u8 *buffer, uint size, int wr)
408 {
409 	struct nand_chip *nand = mtd_to_nand(mtd);
410 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
411 	uint o, s, sbsize, blksize;
412 
413 	/*
414 	 * NAND spare area is available through NFC spare buffers.
415 	 * The NFC divides spare area into (page_size / 512) chunks.
416 	 * Each chunk is placed into separate spare memory area, using
417 	 * first (spare_size / num_of_chunks) bytes of the buffer.
418 	 *
419 	 * For NAND device in which the spare area is not divided fully
420 	 * by the number of chunks, number of used bytes in each spare
421 	 * buffer is rounded down to the nearest even number of bytes,
422 	 * and all remaining bytes are added to the last used spare area.
423 	 *
424 	 * For more information read section 26.6.10 of MPC5121e
425 	 * Microcontroller Reference Manual, Rev. 3.
426 	 */
427 
428 	/* Calculate number of valid bytes in each spare buffer */
429 	sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
430 
431 	while (size) {
432 		/* Calculate spare buffer number */
433 		s = offset / sbsize;
434 		if (s > NFC_SPARE_BUFFERS - 1)
435 			s = NFC_SPARE_BUFFERS - 1;
436 
437 		/*
438 		 * Calculate offset to requested data block in selected spare
439 		 * buffer and its size.
440 		 */
441 		o = offset - (s * sbsize);
442 		blksize = min(sbsize - o, size);
443 
444 		if (wr)
445 			memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
446 							buffer, blksize);
447 		else
448 			memcpy_fromio(buffer,
449 				prv->regs + NFC_SPARE_AREA(s) + o, blksize);
450 
451 		buffer += blksize;
452 		offset += blksize;
453 		size -= blksize;
454 	};
455 }
456 
457 /* Copy data from/to NFC main and spare buffers */
458 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
459 									int wr)
460 {
461 	struct nand_chip *chip = mtd_to_nand(mtd);
462 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
463 	uint c = prv->column;
464 	uint l;
465 
466 	/* Handle spare area access */
467 	if (prv->spareonly || c >= mtd->writesize) {
468 		/* Calculate offset from beginning of spare area */
469 		if (c >= mtd->writesize)
470 			c -= mtd->writesize;
471 
472 		prv->column += len;
473 		mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
474 		return;
475 	}
476 
477 	/*
478 	 * Handle main area access - limit copy length to prevent
479 	 * crossing main/spare boundary.
480 	 */
481 	l = min((uint)len, mtd->writesize - c);
482 	prv->column += l;
483 
484 	if (wr)
485 		memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
486 	else
487 		memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
488 
489 	/* Handle crossing main/spare boundary */
490 	if (l != len) {
491 		buf += l;
492 		len -= l;
493 		mpc5121_nfc_buf_copy(mtd, buf, len, wr);
494 	}
495 }
496 
497 /* Read data from NFC buffers */
498 static void mpc5121_nfc_read_buf(struct nand_chip *chip, u_char *buf, int len)
499 {
500 	mpc5121_nfc_buf_copy(nand_to_mtd(chip), buf, len, 0);
501 }
502 
503 /* Write data to NFC buffers */
504 static void mpc5121_nfc_write_buf(struct nand_chip *chip, const u_char *buf,
505 				  int len)
506 {
507 	mpc5121_nfc_buf_copy(nand_to_mtd(chip), (u_char *)buf, len, 1);
508 }
509 
510 /* Read byte from NFC buffers */
511 static u8 mpc5121_nfc_read_byte(struct nand_chip *chip)
512 {
513 	u8 tmp;
514 
515 	mpc5121_nfc_read_buf(chip, &tmp, sizeof(tmp));
516 
517 	return tmp;
518 }
519 
520 /*
521  * Read NFC configuration from Reset Config Word
522  *
523  * NFC is configured during reset in basis of information stored
524  * in Reset Config Word. There is no other way to set NAND block
525  * size, spare size and bus width.
526  */
527 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
528 {
529 	struct nand_chip *chip = mtd_to_nand(mtd);
530 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
531 	struct mpc512x_reset_module *rm;
532 	struct device_node *rmnode;
533 	uint rcw_pagesize = 0;
534 	uint rcw_sparesize = 0;
535 	uint rcw_width;
536 	uint rcwh;
537 	uint romloc, ps;
538 	int ret = 0;
539 
540 	rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
541 	if (!rmnode) {
542 		dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
543 					"node in device tree!\n");
544 		return -ENODEV;
545 	}
546 
547 	rm = of_iomap(rmnode, 0);
548 	if (!rm) {
549 		dev_err(prv->dev, "Error mapping reset module node!\n");
550 		ret = -EBUSY;
551 		goto out;
552 	}
553 
554 	rcwh = in_be32(&rm->rcwhr);
555 
556 	/* Bit 6: NFC bus width */
557 	rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
558 
559 	/* Bit 7: NFC Page/Spare size */
560 	ps = (rcwh >> 7) & 0x1;
561 
562 	/* Bits [22:21]: ROM Location */
563 	romloc = (rcwh >> 21) & 0x3;
564 
565 	/* Decode RCW bits */
566 	switch ((ps << 2) | romloc) {
567 	case 0x00:
568 	case 0x01:
569 		rcw_pagesize = 512;
570 		rcw_sparesize = 16;
571 		break;
572 	case 0x02:
573 	case 0x03:
574 		rcw_pagesize = 4096;
575 		rcw_sparesize = 128;
576 		break;
577 	case 0x04:
578 	case 0x05:
579 		rcw_pagesize = 2048;
580 		rcw_sparesize = 64;
581 		break;
582 	case 0x06:
583 	case 0x07:
584 		rcw_pagesize = 4096;
585 		rcw_sparesize = 218;
586 		break;
587 	}
588 
589 	mtd->writesize = rcw_pagesize;
590 	mtd->oobsize = rcw_sparesize;
591 	if (rcw_width == 2)
592 		chip->options |= NAND_BUSWIDTH_16;
593 
594 	dev_notice(prv->dev, "Configured for "
595 				"%u-bit NAND, page size %u "
596 				"with %u spare.\n",
597 				rcw_width * 8, rcw_pagesize,
598 				rcw_sparesize);
599 	iounmap(rm);
600 out:
601 	of_node_put(rmnode);
602 	return ret;
603 }
604 
605 /* Free driver resources */
606 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
607 {
608 	struct nand_chip *chip = mtd_to_nand(mtd);
609 	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
610 
611 	if (prv->clk)
612 		clk_disable_unprepare(prv->clk);
613 
614 	if (prv->csreg)
615 		iounmap(prv->csreg);
616 }
617 
618 static int mpc5121_nfc_probe(struct platform_device *op)
619 {
620 	struct device_node *dn = op->dev.of_node;
621 	struct clk *clk;
622 	struct device *dev = &op->dev;
623 	struct mpc5121_nfc_prv *prv;
624 	struct resource res;
625 	struct mtd_info *mtd;
626 	struct nand_chip *chip;
627 	unsigned long regs_paddr, regs_size;
628 	const __be32 *chips_no;
629 	int resettime = 0;
630 	int retval = 0;
631 	int rev, len;
632 
633 	/*
634 	 * Check SoC revision. This driver supports only NFC
635 	 * in MPC5121 revision 2 and MPC5123 revision 3.
636 	 */
637 	rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
638 	if ((rev != 2) && (rev != 3)) {
639 		dev_err(dev, "SoC revision %u is not supported!\n", rev);
640 		return -ENXIO;
641 	}
642 
643 	prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
644 	if (!prv)
645 		return -ENOMEM;
646 
647 	chip = &prv->chip;
648 	mtd = nand_to_mtd(chip);
649 
650 	mtd->dev.parent = dev;
651 	nand_set_controller_data(chip, prv);
652 	nand_set_flash_node(chip, dn);
653 	prv->dev = dev;
654 
655 	/* Read NFC configuration from Reset Config Word */
656 	retval = mpc5121_nfc_read_hw_config(mtd);
657 	if (retval) {
658 		dev_err(dev, "Unable to read NFC config!\n");
659 		return retval;
660 	}
661 
662 	prv->irq = irq_of_parse_and_map(dn, 0);
663 	if (prv->irq == NO_IRQ) {
664 		dev_err(dev, "Error mapping IRQ!\n");
665 		return -EINVAL;
666 	}
667 
668 	retval = of_address_to_resource(dn, 0, &res);
669 	if (retval) {
670 		dev_err(dev, "Error parsing memory region!\n");
671 		return retval;
672 	}
673 
674 	chips_no = of_get_property(dn, "chips", &len);
675 	if (!chips_no || len != sizeof(*chips_no)) {
676 		dev_err(dev, "Invalid/missing 'chips' property!\n");
677 		return -EINVAL;
678 	}
679 
680 	regs_paddr = res.start;
681 	regs_size = resource_size(&res);
682 
683 	if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
684 		dev_err(dev, "Error requesting memory region!\n");
685 		return -EBUSY;
686 	}
687 
688 	prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
689 	if (!prv->regs) {
690 		dev_err(dev, "Error mapping memory region!\n");
691 		return -ENOMEM;
692 	}
693 
694 	mtd->name = "MPC5121 NAND";
695 	chip->legacy.dev_ready = mpc5121_nfc_dev_ready;
696 	chip->legacy.cmdfunc = mpc5121_nfc_command;
697 	chip->legacy.read_byte = mpc5121_nfc_read_byte;
698 	chip->legacy.read_buf = mpc5121_nfc_read_buf;
699 	chip->legacy.write_buf = mpc5121_nfc_write_buf;
700 	chip->legacy.select_chip = mpc5121_nfc_select_chip;
701 	chip->legacy.set_features = nand_get_set_features_notsupp;
702 	chip->legacy.get_features = nand_get_set_features_notsupp;
703 	chip->bbt_options = NAND_BBT_USE_FLASH;
704 	chip->ecc.mode = NAND_ECC_SOFT;
705 	chip->ecc.algo = NAND_ECC_HAMMING;
706 
707 	/* Support external chip-select logic on ADS5121 board */
708 	if (of_machine_is_compatible("fsl,mpc5121ads")) {
709 		retval = ads5121_chipselect_init(mtd);
710 		if (retval) {
711 			dev_err(dev, "Chipselect init error!\n");
712 			return retval;
713 		}
714 
715 		chip->legacy.select_chip = ads5121_select_chip;
716 	}
717 
718 	/* Enable NFC clock */
719 	clk = devm_clk_get(dev, "ipg");
720 	if (IS_ERR(clk)) {
721 		dev_err(dev, "Unable to acquire NFC clock!\n");
722 		retval = PTR_ERR(clk);
723 		goto error;
724 	}
725 	retval = clk_prepare_enable(clk);
726 	if (retval) {
727 		dev_err(dev, "Unable to enable NFC clock!\n");
728 		goto error;
729 	}
730 	prv->clk = clk;
731 
732 	/* Reset NAND Flash controller */
733 	nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
734 	while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
735 		if (resettime++ >= NFC_RESET_TIMEOUT) {
736 			dev_err(dev, "Timeout while resetting NFC!\n");
737 			retval = -EINVAL;
738 			goto error;
739 		}
740 
741 		udelay(1);
742 	}
743 
744 	/* Enable write to NFC memory */
745 	nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
746 
747 	/* Enable write to all NAND pages */
748 	nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
749 	nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
750 	nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
751 
752 	/*
753 	 * Setup NFC:
754 	 *	- Big Endian transfers,
755 	 *	- Interrupt after full page read/write.
756 	 */
757 	nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
758 							NFC_FULL_PAGE_INT);
759 
760 	/* Set spare area size */
761 	nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
762 
763 	init_waitqueue_head(&prv->irq_waitq);
764 	retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
765 									mtd);
766 	if (retval) {
767 		dev_err(dev, "Error requesting IRQ!\n");
768 		goto error;
769 	}
770 
771 	/* Detect NAND chips */
772 	retval = nand_scan(chip, be32_to_cpup(chips_no));
773 	if (retval) {
774 		dev_err(dev, "NAND Flash not found !\n");
775 		goto error;
776 	}
777 
778 	/* Set erase block size */
779 	switch (mtd->erasesize / mtd->writesize) {
780 	case 32:
781 		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
782 		break;
783 
784 	case 64:
785 		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
786 		break;
787 
788 	case 128:
789 		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
790 		break;
791 
792 	case 256:
793 		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
794 		break;
795 
796 	default:
797 		dev_err(dev, "Unsupported NAND flash!\n");
798 		retval = -ENXIO;
799 		goto error;
800 	}
801 
802 	dev_set_drvdata(dev, mtd);
803 
804 	/* Register device in MTD */
805 	retval = mtd_device_register(mtd, NULL, 0);
806 	if (retval) {
807 		dev_err(dev, "Error adding MTD device!\n");
808 		goto error;
809 	}
810 
811 	return 0;
812 error:
813 	mpc5121_nfc_free(dev, mtd);
814 	return retval;
815 }
816 
817 static int mpc5121_nfc_remove(struct platform_device *op)
818 {
819 	struct device *dev = &op->dev;
820 	struct mtd_info *mtd = dev_get_drvdata(dev);
821 
822 	nand_release(mtd_to_nand(mtd));
823 	mpc5121_nfc_free(dev, mtd);
824 
825 	return 0;
826 }
827 
828 static const struct of_device_id mpc5121_nfc_match[] = {
829 	{ .compatible = "fsl,mpc5121-nfc", },
830 	{},
831 };
832 MODULE_DEVICE_TABLE(of, mpc5121_nfc_match);
833 
834 static struct platform_driver mpc5121_nfc_driver = {
835 	.probe		= mpc5121_nfc_probe,
836 	.remove		= mpc5121_nfc_remove,
837 	.driver		= {
838 		.name = DRV_NAME,
839 		.of_match_table = mpc5121_nfc_match,
840 	},
841 };
842 
843 module_platform_driver(mpc5121_nfc_driver);
844 
845 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
846 MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
847 MODULE_LICENSE("GPL");
848