1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Amlogic Meson Nand Flash Controller Driver 4 * 5 * Copyright (c) 2018 Amlogic, inc. 6 * Author: Liang Yang <liang.yang@amlogic.com> 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/clk.h> 13 #include <linux/mtd/rawnand.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/module.h> 19 #include <linux/iopoll.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/sched/task_stack.h> 23 24 #define NFC_REG_CMD 0x00 25 #define NFC_CMD_IDLE (0xc << 14) 26 #define NFC_CMD_CLE (0x5 << 14) 27 #define NFC_CMD_ALE (0x6 << 14) 28 #define NFC_CMD_ADL ((0 << 16) | (3 << 20)) 29 #define NFC_CMD_ADH ((1 << 16) | (3 << 20)) 30 #define NFC_CMD_AIL ((2 << 16) | (3 << 20)) 31 #define NFC_CMD_AIH ((3 << 16) | (3 << 20)) 32 #define NFC_CMD_SEED ((8 << 16) | (3 << 20)) 33 #define NFC_CMD_M2N ((0 << 17) | (2 << 20)) 34 #define NFC_CMD_N2M ((1 << 17) | (2 << 20)) 35 #define NFC_CMD_RB BIT(20) 36 #define NFC_CMD_SCRAMBLER_ENABLE BIT(19) 37 #define NFC_CMD_SCRAMBLER_DISABLE 0 38 #define NFC_CMD_SHORTMODE_DISABLE 0 39 #define NFC_CMD_RB_INT BIT(14) 40 41 #define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0)) 42 43 #define NFC_REG_CFG 0x04 44 #define NFC_REG_DADR 0x08 45 #define NFC_REG_IADR 0x0c 46 #define NFC_REG_BUF 0x10 47 #define NFC_REG_INFO 0x14 48 #define NFC_REG_DC 0x18 49 #define NFC_REG_ADR 0x1c 50 #define NFC_REG_DL 0x20 51 #define NFC_REG_DH 0x24 52 #define NFC_REG_CADR 0x28 53 #define NFC_REG_SADR 0x2c 54 #define NFC_REG_PINS 0x30 55 #define NFC_REG_VER 0x38 56 57 #define NFC_RB_IRQ_EN BIT(21) 58 59 #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ 60 ( \ 61 (cmd_dir) | \ 62 ((ran) << 19) | \ 63 ((bch) << 14) | \ 64 ((short_mode) << 13) | \ 65 (((page_size) & 0x7f) << 6) | \ 66 ((pages) & 0x3f) \ 67 ) 68 69 #define GENCMDDADDRL(adl, addr) ((adl) | ((addr) & 0xffff)) 70 #define GENCMDDADDRH(adh, addr) ((adh) | (((addr) >> 16) & 0xffff)) 71 #define GENCMDIADDRL(ail, addr) ((ail) | ((addr) & 0xffff)) 72 #define GENCMDIADDRH(aih, addr) ((aih) | (((addr) >> 16) & 0xffff)) 73 74 #define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) 75 76 #define ECC_CHECK_RETURN_FF (-1) 77 78 #define NAND_CE0 (0xe << 10) 79 #define NAND_CE1 (0xd << 10) 80 81 #define DMA_BUSY_TIMEOUT 0x100000 82 #define CMD_FIFO_EMPTY_TIMEOUT 1000 83 84 #define MAX_CE_NUM 2 85 86 /* eMMC clock register, misc control */ 87 #define CLK_SELECT_NAND BIT(31) 88 89 #define NFC_CLK_CYCLE 6 90 91 /* nand flash controller delay 3 ns */ 92 #define NFC_DEFAULT_DELAY 3000 93 94 #define ROW_ADDER(page, index) (((page) >> (8 * (index))) & 0xff) 95 #define MAX_CYCLE_ADDRS 5 96 #define DIRREAD 1 97 #define DIRWRITE 0 98 99 #define ECC_PARITY_BCH8_512B 14 100 #define ECC_COMPLETE BIT(31) 101 #define ECC_ERR_CNT(x) (((x) >> 24) & GENMASK(5, 0)) 102 #define ECC_ZERO_CNT(x) (((x) >> 16) & GENMASK(5, 0)) 103 #define ECC_UNCORRECTABLE 0x3f 104 105 #define PER_INFO_BYTE 8 106 107 struct meson_nfc_nand_chip { 108 struct list_head node; 109 struct nand_chip nand; 110 unsigned long clk_rate; 111 unsigned long level1_divider; 112 u32 bus_timing; 113 u32 twb; 114 u32 tadl; 115 u32 tbers_max; 116 117 u32 bch_mode; 118 u8 *data_buf; 119 __le64 *info_buf; 120 u32 nsels; 121 u8 sels[0]; 122 }; 123 124 struct meson_nand_ecc { 125 u32 bch; 126 u32 strength; 127 }; 128 129 struct meson_nfc_data { 130 const struct nand_ecc_caps *ecc_caps; 131 }; 132 133 struct meson_nfc_param { 134 u32 chip_select; 135 u32 rb_select; 136 }; 137 138 struct nand_rw_cmd { 139 u32 cmd0; 140 u32 addrs[MAX_CYCLE_ADDRS]; 141 u32 cmd1; 142 }; 143 144 struct nand_timing { 145 u32 twb; 146 u32 tadl; 147 u32 tbers_max; 148 }; 149 150 struct meson_nfc { 151 struct nand_controller controller; 152 struct clk *core_clk; 153 struct clk *device_clk; 154 struct clk *phase_tx; 155 struct clk *phase_rx; 156 157 unsigned long clk_rate; 158 u32 bus_timing; 159 160 struct device *dev; 161 void __iomem *reg_base; 162 struct regmap *reg_clk; 163 struct completion completion; 164 struct list_head chips; 165 const struct meson_nfc_data *data; 166 struct meson_nfc_param param; 167 struct nand_timing timing; 168 union { 169 int cmd[32]; 170 struct nand_rw_cmd rw; 171 } cmdfifo; 172 173 dma_addr_t daddr; 174 dma_addr_t iaddr; 175 176 unsigned long assigned_cs; 177 }; 178 179 enum { 180 NFC_ECC_BCH8_1K = 2, 181 NFC_ECC_BCH24_1K, 182 NFC_ECC_BCH30_1K, 183 NFC_ECC_BCH40_1K, 184 NFC_ECC_BCH50_1K, 185 NFC_ECC_BCH60_1K, 186 }; 187 188 #define MESON_ECC_DATA(b, s) { .bch = (b), .strength = (s)} 189 190 static struct meson_nand_ecc meson_ecc[] = { 191 MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8), 192 MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24), 193 MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30), 194 MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40), 195 MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50), 196 MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60), 197 }; 198 199 static int meson_nand_calc_ecc_bytes(int step_size, int strength) 200 { 201 int ecc_bytes; 202 203 if (step_size == 512 && strength == 8) 204 return ECC_PARITY_BCH8_512B; 205 206 ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8); 207 ecc_bytes = ALIGN(ecc_bytes, 2); 208 209 return ecc_bytes; 210 } 211 212 NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps, 213 meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60); 214 NAND_ECC_CAPS_SINGLE(meson_axg_ecc_caps, 215 meson_nand_calc_ecc_bytes, 1024, 8); 216 217 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) 218 { 219 return container_of(nand, struct meson_nfc_nand_chip, nand); 220 } 221 222 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) 223 { 224 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 225 struct meson_nfc *nfc = nand_get_controller_data(nand); 226 int ret, value; 227 228 if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels)) 229 return; 230 231 nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0; 232 nfc->param.rb_select = nfc->param.chip_select; 233 nfc->timing.twb = meson_chip->twb; 234 nfc->timing.tadl = meson_chip->tadl; 235 nfc->timing.tbers_max = meson_chip->tbers_max; 236 237 if (nfc->clk_rate != meson_chip->clk_rate) { 238 ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate); 239 if (ret) { 240 dev_err(nfc->dev, "failed to set clock rate\n"); 241 return; 242 } 243 nfc->clk_rate = meson_chip->clk_rate; 244 } 245 if (nfc->bus_timing != meson_chip->bus_timing) { 246 value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5); 247 writel(value, nfc->reg_base + NFC_REG_CFG); 248 writel((1 << 31), nfc->reg_base + NFC_REG_CMD); 249 nfc->bus_timing = meson_chip->bus_timing; 250 } 251 } 252 253 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time) 254 { 255 writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff), 256 nfc->reg_base + NFC_REG_CMD); 257 } 258 259 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed) 260 { 261 writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)), 262 nfc->reg_base + NFC_REG_CMD); 263 } 264 265 static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir, 266 int scrambler) 267 { 268 struct mtd_info *mtd = nand_to_mtd(nand); 269 struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); 270 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 271 u32 bch = meson_chip->bch_mode, cmd; 272 int len = mtd->writesize, pagesize, pages; 273 274 pagesize = nand->ecc.size; 275 276 if (raw) { 277 len = mtd->writesize + mtd->oobsize; 278 cmd = (len & GENMASK(5, 0)) | scrambler | DMA_DIR(dir); 279 writel(cmd, nfc->reg_base + NFC_REG_CMD); 280 return; 281 } 282 283 pages = len / nand->ecc.size; 284 285 cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch, 286 NFC_CMD_SHORTMODE_DISABLE, pagesize, pages); 287 288 writel(cmd, nfc->reg_base + NFC_REG_CMD); 289 } 290 291 static void meson_nfc_drain_cmd(struct meson_nfc *nfc) 292 { 293 /* 294 * Insert two commands to make sure all valid commands are finished. 295 * 296 * The Nand flash controller is designed as two stages pipleline - 297 * a) fetch and b) excute. 298 * There might be cases when the driver see command queue is empty, 299 * but the Nand flash controller still has two commands buffered, 300 * one is fetched into NFC request queue (ready to run), and another 301 * is actively executing. So pushing 2 "IDLE" commands guarantees that 302 * the pipeline is emptied. 303 */ 304 meson_nfc_cmd_idle(nfc, 0); 305 meson_nfc_cmd_idle(nfc, 0); 306 } 307 308 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc, 309 unsigned int timeout_ms) 310 { 311 u32 cmd_size = 0; 312 int ret; 313 314 /* wait cmd fifo is empty */ 315 ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size, 316 !NFC_CMD_GET_SIZE(cmd_size), 317 10, timeout_ms * 1000); 318 if (ret) 319 dev_err(nfc->dev, "wait for empty CMD FIFO time out\n"); 320 321 return ret; 322 } 323 324 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc) 325 { 326 meson_nfc_drain_cmd(nfc); 327 328 return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT); 329 } 330 331 static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i) 332 { 333 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 334 int len; 335 336 len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i; 337 338 return meson_chip->data_buf + len; 339 } 340 341 static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i) 342 { 343 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 344 int len, temp; 345 346 temp = nand->ecc.size + nand->ecc.bytes; 347 len = (temp + 2) * i; 348 349 return meson_chip->data_buf + len; 350 } 351 352 static void meson_nfc_get_data_oob(struct nand_chip *nand, 353 u8 *buf, u8 *oobbuf) 354 { 355 int i, oob_len = 0; 356 u8 *dsrc, *osrc; 357 358 oob_len = nand->ecc.bytes + 2; 359 for (i = 0; i < nand->ecc.steps; i++) { 360 if (buf) { 361 dsrc = meson_nfc_data_ptr(nand, i); 362 memcpy(buf, dsrc, nand->ecc.size); 363 buf += nand->ecc.size; 364 } 365 osrc = meson_nfc_oob_ptr(nand, i); 366 memcpy(oobbuf, osrc, oob_len); 367 oobbuf += oob_len; 368 } 369 } 370 371 static void meson_nfc_set_data_oob(struct nand_chip *nand, 372 const u8 *buf, u8 *oobbuf) 373 { 374 int i, oob_len = 0; 375 u8 *dsrc, *osrc; 376 377 oob_len = nand->ecc.bytes + 2; 378 for (i = 0; i < nand->ecc.steps; i++) { 379 if (buf) { 380 dsrc = meson_nfc_data_ptr(nand, i); 381 memcpy(dsrc, buf, nand->ecc.size); 382 buf += nand->ecc.size; 383 } 384 osrc = meson_nfc_oob_ptr(nand, i); 385 memcpy(osrc, oobbuf, oob_len); 386 oobbuf += oob_len; 387 } 388 } 389 390 static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms) 391 { 392 u32 cmd, cfg; 393 int ret = 0; 394 395 meson_nfc_cmd_idle(nfc, nfc->timing.twb); 396 meson_nfc_drain_cmd(nfc); 397 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT); 398 399 cfg = readl(nfc->reg_base + NFC_REG_CFG); 400 cfg |= NFC_RB_IRQ_EN; 401 writel(cfg, nfc->reg_base + NFC_REG_CFG); 402 403 init_completion(&nfc->completion); 404 405 /* use the max erase time as the maximum clock for waiting R/B */ 406 cmd = NFC_CMD_RB | NFC_CMD_RB_INT 407 | nfc->param.chip_select | nfc->timing.tbers_max; 408 writel(cmd, nfc->reg_base + NFC_REG_CMD); 409 410 ret = wait_for_completion_timeout(&nfc->completion, 411 msecs_to_jiffies(timeout_ms)); 412 if (ret == 0) 413 ret = -1; 414 415 return ret; 416 } 417 418 static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf) 419 { 420 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 421 __le64 *info; 422 int i, count; 423 424 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) { 425 info = &meson_chip->info_buf[i]; 426 *info |= oob_buf[count]; 427 *info |= oob_buf[count + 1] << 8; 428 } 429 } 430 431 static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf) 432 { 433 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 434 __le64 *info; 435 int i, count; 436 437 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) { 438 info = &meson_chip->info_buf[i]; 439 oob_buf[count] = *info; 440 oob_buf[count + 1] = *info >> 8; 441 } 442 } 443 444 static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips, 445 u64 *correct_bitmap) 446 { 447 struct mtd_info *mtd = nand_to_mtd(nand); 448 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 449 __le64 *info; 450 int ret = 0, i; 451 452 for (i = 0; i < nand->ecc.steps; i++) { 453 info = &meson_chip->info_buf[i]; 454 if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) { 455 mtd->ecc_stats.corrected += ECC_ERR_CNT(*info); 456 *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info)); 457 *correct_bitmap |= 1 >> i; 458 continue; 459 } 460 if ((nand->options & NAND_NEED_SCRAMBLING) && 461 ECC_ZERO_CNT(*info) < nand->ecc.strength) { 462 mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info); 463 *bitflips = max_t(u32, *bitflips, 464 ECC_ZERO_CNT(*info)); 465 ret = ECC_CHECK_RETURN_FF; 466 } else { 467 ret = -EBADMSG; 468 } 469 } 470 return ret; 471 } 472 473 static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, u8 *databuf, 474 int datalen, u8 *infobuf, int infolen, 475 enum dma_data_direction dir) 476 { 477 struct meson_nfc *nfc = nand_get_controller_data(nand); 478 u32 cmd; 479 int ret = 0; 480 481 nfc->daddr = dma_map_single(nfc->dev, (void *)databuf, datalen, dir); 482 ret = dma_mapping_error(nfc->dev, nfc->daddr); 483 if (ret) { 484 dev_err(nfc->dev, "DMA mapping error\n"); 485 return ret; 486 } 487 cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr); 488 writel(cmd, nfc->reg_base + NFC_REG_CMD); 489 490 cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr); 491 writel(cmd, nfc->reg_base + NFC_REG_CMD); 492 493 if (infobuf) { 494 nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir); 495 ret = dma_mapping_error(nfc->dev, nfc->iaddr); 496 if (ret) { 497 dev_err(nfc->dev, "DMA mapping error\n"); 498 dma_unmap_single(nfc->dev, 499 nfc->daddr, datalen, dir); 500 return ret; 501 } 502 cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr); 503 writel(cmd, nfc->reg_base + NFC_REG_CMD); 504 505 cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr); 506 writel(cmd, nfc->reg_base + NFC_REG_CMD); 507 } 508 509 return ret; 510 } 511 512 static void meson_nfc_dma_buffer_release(struct nand_chip *nand, 513 int infolen, int datalen, 514 enum dma_data_direction dir) 515 { 516 struct meson_nfc *nfc = nand_get_controller_data(nand); 517 518 dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir); 519 if (infolen) 520 dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir); 521 } 522 523 static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len) 524 { 525 struct meson_nfc *nfc = nand_get_controller_data(nand); 526 int ret = 0; 527 u32 cmd; 528 u8 *info; 529 530 info = kzalloc(PER_INFO_BYTE, GFP_KERNEL); 531 ret = meson_nfc_dma_buffer_setup(nand, buf, len, info, 532 PER_INFO_BYTE, DMA_FROM_DEVICE); 533 if (ret) 534 return ret; 535 536 cmd = NFC_CMD_N2M | (len & GENMASK(5, 0)); 537 writel(cmd, nfc->reg_base + NFC_REG_CMD); 538 539 meson_nfc_drain_cmd(nfc); 540 meson_nfc_wait_cmd_finish(nfc, 1000); 541 meson_nfc_dma_buffer_release(nand, len, PER_INFO_BYTE, DMA_FROM_DEVICE); 542 kfree(info); 543 544 return ret; 545 } 546 547 static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len) 548 { 549 struct meson_nfc *nfc = nand_get_controller_data(nand); 550 int ret = 0; 551 u32 cmd; 552 553 ret = meson_nfc_dma_buffer_setup(nand, buf, len, NULL, 554 0, DMA_TO_DEVICE); 555 if (ret) 556 return ret; 557 558 cmd = NFC_CMD_M2N | (len & GENMASK(5, 0)); 559 writel(cmd, nfc->reg_base + NFC_REG_CMD); 560 561 meson_nfc_drain_cmd(nfc); 562 meson_nfc_wait_cmd_finish(nfc, 1000); 563 meson_nfc_dma_buffer_release(nand, len, 0, DMA_TO_DEVICE); 564 565 return ret; 566 } 567 568 static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand, 569 int page, bool in) 570 { 571 struct mtd_info *mtd = nand_to_mtd(nand); 572 struct meson_nfc *nfc = nand_get_controller_data(nand); 573 const struct nand_sdr_timings *sdr = 574 nand_get_sdr_timings(&nand->data_interface); 575 u32 *addrs = nfc->cmdfifo.rw.addrs; 576 u32 cs = nfc->param.chip_select; 577 u32 cmd0, cmd_num, row_start; 578 int ret = 0, i; 579 580 cmd_num = sizeof(struct nand_rw_cmd) / sizeof(int); 581 582 cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN; 583 nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0; 584 585 addrs[0] = cs | NFC_CMD_ALE | 0; 586 if (mtd->writesize <= 512) { 587 cmd_num--; 588 row_start = 1; 589 } else { 590 addrs[1] = cs | NFC_CMD_ALE | 0; 591 row_start = 2; 592 } 593 594 addrs[row_start] = cs | NFC_CMD_ALE | ROW_ADDER(page, 0); 595 addrs[row_start + 1] = cs | NFC_CMD_ALE | ROW_ADDER(page, 1); 596 597 if (nand->options & NAND_ROW_ADDR_3) 598 addrs[row_start + 2] = 599 cs | NFC_CMD_ALE | ROW_ADDER(page, 2); 600 else 601 cmd_num--; 602 603 /* subtract cmd1 */ 604 cmd_num--; 605 606 for (i = 0; i < cmd_num; i++) 607 writel_relaxed(nfc->cmdfifo.cmd[i], 608 nfc->reg_base + NFC_REG_CMD); 609 610 if (in) { 611 nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART; 612 writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD); 613 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max)); 614 } else { 615 meson_nfc_cmd_idle(nfc, nfc->timing.tadl); 616 } 617 618 return ret; 619 } 620 621 static int meson_nfc_write_page_sub(struct nand_chip *nand, 622 int page, int raw) 623 { 624 struct mtd_info *mtd = nand_to_mtd(nand); 625 const struct nand_sdr_timings *sdr = 626 nand_get_sdr_timings(&nand->data_interface); 627 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 628 struct meson_nfc *nfc = nand_get_controller_data(nand); 629 int data_len, info_len; 630 u32 cmd; 631 int ret; 632 633 meson_nfc_select_chip(nand, nand->cur_cs); 634 635 data_len = mtd->writesize + mtd->oobsize; 636 info_len = nand->ecc.steps * PER_INFO_BYTE; 637 638 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRWRITE); 639 if (ret) 640 return ret; 641 642 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf, 643 data_len, (u8 *)meson_chip->info_buf, 644 info_len, DMA_TO_DEVICE); 645 if (ret) 646 return ret; 647 648 if (nand->options & NAND_NEED_SCRAMBLING) { 649 meson_nfc_cmd_seed(nfc, page); 650 meson_nfc_cmd_access(nand, raw, DIRWRITE, 651 NFC_CMD_SCRAMBLER_ENABLE); 652 } else { 653 meson_nfc_cmd_access(nand, raw, DIRWRITE, 654 NFC_CMD_SCRAMBLER_DISABLE); 655 } 656 657 cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG; 658 writel(cmd, nfc->reg_base + NFC_REG_CMD); 659 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max)); 660 661 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE); 662 663 return ret; 664 } 665 666 static int meson_nfc_write_page_raw(struct nand_chip *nand, const u8 *buf, 667 int oob_required, int page) 668 { 669 u8 *oob_buf = nand->oob_poi; 670 671 meson_nfc_set_data_oob(nand, buf, oob_buf); 672 673 return meson_nfc_write_page_sub(nand, page, 1); 674 } 675 676 static int meson_nfc_write_page_hwecc(struct nand_chip *nand, 677 const u8 *buf, int oob_required, int page) 678 { 679 struct mtd_info *mtd = nand_to_mtd(nand); 680 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 681 u8 *oob_buf = nand->oob_poi; 682 683 memcpy(meson_chip->data_buf, buf, mtd->writesize); 684 memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE); 685 meson_nfc_set_user_byte(nand, oob_buf); 686 687 return meson_nfc_write_page_sub(nand, page, 0); 688 } 689 690 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc, 691 struct nand_chip *nand, int raw) 692 { 693 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 694 __le64 *info; 695 u32 neccpages; 696 int ret; 697 698 neccpages = raw ? 1 : nand->ecc.steps; 699 info = &meson_chip->info_buf[neccpages - 1]; 700 do { 701 usleep_range(10, 15); 702 /* info is updated by nfc dma engine*/ 703 smp_rmb(); 704 ret = *info & ECC_COMPLETE; 705 } while (!ret); 706 } 707 708 static int meson_nfc_read_page_sub(struct nand_chip *nand, 709 int page, int raw) 710 { 711 struct mtd_info *mtd = nand_to_mtd(nand); 712 struct meson_nfc *nfc = nand_get_controller_data(nand); 713 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 714 int data_len, info_len; 715 int ret; 716 717 meson_nfc_select_chip(nand, nand->cur_cs); 718 719 data_len = mtd->writesize + mtd->oobsize; 720 info_len = nand->ecc.steps * PER_INFO_BYTE; 721 722 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRREAD); 723 if (ret) 724 return ret; 725 726 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf, 727 data_len, (u8 *)meson_chip->info_buf, 728 info_len, DMA_FROM_DEVICE); 729 if (ret) 730 return ret; 731 732 if (nand->options & NAND_NEED_SCRAMBLING) { 733 meson_nfc_cmd_seed(nfc, page); 734 meson_nfc_cmd_access(nand, raw, DIRREAD, 735 NFC_CMD_SCRAMBLER_ENABLE); 736 } else { 737 meson_nfc_cmd_access(nand, raw, DIRREAD, 738 NFC_CMD_SCRAMBLER_DISABLE); 739 } 740 741 ret = meson_nfc_wait_dma_finish(nfc); 742 meson_nfc_check_ecc_pages_valid(nfc, nand, raw); 743 744 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_FROM_DEVICE); 745 746 return ret; 747 } 748 749 static int meson_nfc_read_page_raw(struct nand_chip *nand, u8 *buf, 750 int oob_required, int page) 751 { 752 u8 *oob_buf = nand->oob_poi; 753 int ret; 754 755 ret = meson_nfc_read_page_sub(nand, page, 1); 756 if (ret) 757 return ret; 758 759 meson_nfc_get_data_oob(nand, buf, oob_buf); 760 761 return 0; 762 } 763 764 static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf, 765 int oob_required, int page) 766 { 767 struct mtd_info *mtd = nand_to_mtd(nand); 768 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 769 struct nand_ecc_ctrl *ecc = &nand->ecc; 770 u64 correct_bitmap = 0; 771 u32 bitflips = 0; 772 u8 *oob_buf = nand->oob_poi; 773 int ret, i; 774 775 ret = meson_nfc_read_page_sub(nand, page, 0); 776 if (ret) 777 return ret; 778 779 meson_nfc_get_user_byte(nand, oob_buf); 780 ret = meson_nfc_ecc_correct(nand, &bitflips, &correct_bitmap); 781 if (ret == ECC_CHECK_RETURN_FF) { 782 if (buf) 783 memset(buf, 0xff, mtd->writesize); 784 memset(oob_buf, 0xff, mtd->oobsize); 785 } else if (ret < 0) { 786 if ((nand->options & NAND_NEED_SCRAMBLING) || !buf) { 787 mtd->ecc_stats.failed++; 788 return bitflips; 789 } 790 ret = meson_nfc_read_page_raw(nand, buf, 0, page); 791 if (ret) 792 return ret; 793 794 for (i = 0; i < nand->ecc.steps ; i++) { 795 u8 *data = buf + i * ecc->size; 796 u8 *oob = nand->oob_poi + i * (ecc->bytes + 2); 797 798 if (correct_bitmap & (1 << i)) 799 continue; 800 ret = nand_check_erased_ecc_chunk(data, ecc->size, 801 oob, ecc->bytes + 2, 802 NULL, 0, 803 ecc->strength); 804 if (ret < 0) { 805 mtd->ecc_stats.failed++; 806 } else { 807 mtd->ecc_stats.corrected += ret; 808 bitflips = max_t(u32, bitflips, ret); 809 } 810 } 811 } else if (buf && buf != meson_chip->data_buf) { 812 memcpy(buf, meson_chip->data_buf, mtd->writesize); 813 } 814 815 return bitflips; 816 } 817 818 static int meson_nfc_read_oob_raw(struct nand_chip *nand, int page) 819 { 820 return meson_nfc_read_page_raw(nand, NULL, 1, page); 821 } 822 823 static int meson_nfc_read_oob(struct nand_chip *nand, int page) 824 { 825 return meson_nfc_read_page_hwecc(nand, NULL, 1, page); 826 } 827 828 static bool meson_nfc_is_buffer_dma_safe(const void *buffer) 829 { 830 if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer))) 831 return true; 832 return false; 833 } 834 835 static void * 836 meson_nand_op_get_dma_safe_input_buf(const struct nand_op_instr *instr) 837 { 838 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR)) 839 return NULL; 840 841 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.in)) 842 return instr->ctx.data.buf.in; 843 844 return kzalloc(instr->ctx.data.len, GFP_KERNEL); 845 } 846 847 static void 848 meson_nand_op_put_dma_safe_input_buf(const struct nand_op_instr *instr, 849 void *buf) 850 { 851 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) || 852 WARN_ON(!buf)) 853 return; 854 855 if (buf == instr->ctx.data.buf.in) 856 return; 857 858 memcpy(instr->ctx.data.buf.in, buf, instr->ctx.data.len); 859 kfree(buf); 860 } 861 862 static void * 863 meson_nand_op_get_dma_safe_output_buf(const struct nand_op_instr *instr) 864 { 865 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR)) 866 return NULL; 867 868 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.out)) 869 return (void *)instr->ctx.data.buf.out; 870 871 return kmemdup(instr->ctx.data.buf.out, 872 instr->ctx.data.len, GFP_KERNEL); 873 } 874 875 static void 876 meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr, 877 const void *buf) 878 { 879 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) || 880 WARN_ON(!buf)) 881 return; 882 883 if (buf != instr->ctx.data.buf.out) 884 kfree(buf); 885 } 886 887 static int meson_nfc_exec_op(struct nand_chip *nand, 888 const struct nand_operation *op, bool check_only) 889 { 890 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 891 struct meson_nfc *nfc = nand_get_controller_data(nand); 892 const struct nand_op_instr *instr = NULL; 893 void *buf; 894 u32 op_id, delay_idle, cmd; 895 int i; 896 897 meson_nfc_select_chip(nand, op->cs); 898 for (op_id = 0; op_id < op->ninstrs; op_id++) { 899 instr = &op->instrs[op_id]; 900 delay_idle = DIV_ROUND_UP(PSEC_TO_NSEC(instr->delay_ns), 901 meson_chip->level1_divider * 902 NFC_CLK_CYCLE); 903 switch (instr->type) { 904 case NAND_OP_CMD_INSTR: 905 cmd = nfc->param.chip_select | NFC_CMD_CLE; 906 cmd |= instr->ctx.cmd.opcode & 0xff; 907 writel(cmd, nfc->reg_base + NFC_REG_CMD); 908 meson_nfc_cmd_idle(nfc, delay_idle); 909 break; 910 911 case NAND_OP_ADDR_INSTR: 912 for (i = 0; i < instr->ctx.addr.naddrs; i++) { 913 cmd = nfc->param.chip_select | NFC_CMD_ALE; 914 cmd |= instr->ctx.addr.addrs[i] & 0xff; 915 writel(cmd, nfc->reg_base + NFC_REG_CMD); 916 } 917 meson_nfc_cmd_idle(nfc, delay_idle); 918 break; 919 920 case NAND_OP_DATA_IN_INSTR: 921 buf = meson_nand_op_get_dma_safe_input_buf(instr); 922 if (!buf) 923 return -ENOMEM; 924 meson_nfc_read_buf(nand, buf, instr->ctx.data.len); 925 meson_nand_op_put_dma_safe_input_buf(instr, buf); 926 break; 927 928 case NAND_OP_DATA_OUT_INSTR: 929 buf = meson_nand_op_get_dma_safe_output_buf(instr); 930 if (!buf) 931 return -ENOMEM; 932 meson_nfc_write_buf(nand, buf, instr->ctx.data.len); 933 meson_nand_op_put_dma_safe_output_buf(instr, buf); 934 break; 935 936 case NAND_OP_WAITRDY_INSTR: 937 meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms); 938 if (instr->delay_ns) 939 meson_nfc_cmd_idle(nfc, delay_idle); 940 break; 941 } 942 } 943 meson_nfc_wait_cmd_finish(nfc, 1000); 944 return 0; 945 } 946 947 static int meson_ooblayout_ecc(struct mtd_info *mtd, int section, 948 struct mtd_oob_region *oobregion) 949 { 950 struct nand_chip *nand = mtd_to_nand(mtd); 951 952 if (section >= nand->ecc.steps) 953 return -ERANGE; 954 955 oobregion->offset = 2 + (section * (2 + nand->ecc.bytes)); 956 oobregion->length = nand->ecc.bytes; 957 958 return 0; 959 } 960 961 static int meson_ooblayout_free(struct mtd_info *mtd, int section, 962 struct mtd_oob_region *oobregion) 963 { 964 struct nand_chip *nand = mtd_to_nand(mtd); 965 966 if (section >= nand->ecc.steps) 967 return -ERANGE; 968 969 oobregion->offset = section * (2 + nand->ecc.bytes); 970 oobregion->length = 2; 971 972 return 0; 973 } 974 975 static const struct mtd_ooblayout_ops meson_ooblayout_ops = { 976 .ecc = meson_ooblayout_ecc, 977 .free = meson_ooblayout_free, 978 }; 979 980 static int meson_nfc_clk_init(struct meson_nfc *nfc) 981 { 982 int ret; 983 984 /* request core clock */ 985 nfc->core_clk = devm_clk_get(nfc->dev, "core"); 986 if (IS_ERR(nfc->core_clk)) { 987 dev_err(nfc->dev, "failed to get core clock\n"); 988 return PTR_ERR(nfc->core_clk); 989 } 990 991 nfc->device_clk = devm_clk_get(nfc->dev, "device"); 992 if (IS_ERR(nfc->device_clk)) { 993 dev_err(nfc->dev, "failed to get device clock\n"); 994 return PTR_ERR(nfc->device_clk); 995 } 996 997 nfc->phase_tx = devm_clk_get(nfc->dev, "tx"); 998 if (IS_ERR(nfc->phase_tx)) { 999 dev_err(nfc->dev, "failed to get TX clk\n"); 1000 return PTR_ERR(nfc->phase_tx); 1001 } 1002 1003 nfc->phase_rx = devm_clk_get(nfc->dev, "rx"); 1004 if (IS_ERR(nfc->phase_rx)) { 1005 dev_err(nfc->dev, "failed to get RX clk\n"); 1006 return PTR_ERR(nfc->phase_rx); 1007 } 1008 1009 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 1010 regmap_update_bits(nfc->reg_clk, 1011 0, CLK_SELECT_NAND, CLK_SELECT_NAND); 1012 1013 ret = clk_prepare_enable(nfc->core_clk); 1014 if (ret) { 1015 dev_err(nfc->dev, "failed to enable core clock\n"); 1016 return ret; 1017 } 1018 1019 ret = clk_prepare_enable(nfc->device_clk); 1020 if (ret) { 1021 dev_err(nfc->dev, "failed to enable device clock\n"); 1022 goto err_device_clk; 1023 } 1024 1025 ret = clk_prepare_enable(nfc->phase_tx); 1026 if (ret) { 1027 dev_err(nfc->dev, "failed to enable TX clock\n"); 1028 goto err_phase_tx; 1029 } 1030 1031 ret = clk_prepare_enable(nfc->phase_rx); 1032 if (ret) { 1033 dev_err(nfc->dev, "failed to enable RX clock\n"); 1034 goto err_phase_rx; 1035 } 1036 1037 ret = clk_set_rate(nfc->device_clk, 24000000); 1038 if (ret) 1039 goto err_phase_rx; 1040 1041 return 0; 1042 err_phase_rx: 1043 clk_disable_unprepare(nfc->phase_tx); 1044 err_phase_tx: 1045 clk_disable_unprepare(nfc->device_clk); 1046 err_device_clk: 1047 clk_disable_unprepare(nfc->core_clk); 1048 return ret; 1049 } 1050 1051 static void meson_nfc_disable_clk(struct meson_nfc *nfc) 1052 { 1053 clk_disable_unprepare(nfc->phase_rx); 1054 clk_disable_unprepare(nfc->phase_tx); 1055 clk_disable_unprepare(nfc->device_clk); 1056 clk_disable_unprepare(nfc->core_clk); 1057 } 1058 1059 static void meson_nfc_free_buffer(struct nand_chip *nand) 1060 { 1061 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1062 1063 kfree(meson_chip->info_buf); 1064 kfree(meson_chip->data_buf); 1065 } 1066 1067 static int meson_chip_buffer_init(struct nand_chip *nand) 1068 { 1069 struct mtd_info *mtd = nand_to_mtd(nand); 1070 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1071 u32 page_bytes, info_bytes, nsectors; 1072 1073 nsectors = mtd->writesize / nand->ecc.size; 1074 1075 page_bytes = mtd->writesize + mtd->oobsize; 1076 info_bytes = nsectors * PER_INFO_BYTE; 1077 1078 meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL); 1079 if (!meson_chip->data_buf) 1080 return -ENOMEM; 1081 1082 meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL); 1083 if (!meson_chip->info_buf) { 1084 kfree(meson_chip->data_buf); 1085 return -ENOMEM; 1086 } 1087 1088 return 0; 1089 } 1090 1091 static 1092 int meson_nfc_setup_data_interface(struct nand_chip *nand, int csline, 1093 const struct nand_data_interface *conf) 1094 { 1095 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1096 const struct nand_sdr_timings *timings; 1097 u32 div, bt_min, bt_max, tbers_clocks; 1098 1099 timings = nand_get_sdr_timings(conf); 1100 if (IS_ERR(timings)) 1101 return -ENOTSUPP; 1102 1103 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1104 return 0; 1105 1106 div = DIV_ROUND_UP((timings->tRC_min / 1000), NFC_CLK_CYCLE); 1107 bt_min = (timings->tREA_max + NFC_DEFAULT_DELAY) / div; 1108 bt_max = (NFC_DEFAULT_DELAY + timings->tRHOH_min + 1109 timings->tRC_min / 2) / div; 1110 1111 meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max), 1112 div * NFC_CLK_CYCLE); 1113 meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min), 1114 div * NFC_CLK_CYCLE); 1115 tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max), 1116 div * NFC_CLK_CYCLE); 1117 meson_chip->tbers_max = ilog2(tbers_clocks); 1118 if (!is_power_of_2(tbers_clocks)) 1119 meson_chip->tbers_max++; 1120 1121 bt_min = DIV_ROUND_UP(bt_min, 1000); 1122 bt_max = DIV_ROUND_UP(bt_max, 1000); 1123 1124 if (bt_max < bt_min) 1125 return -EINVAL; 1126 1127 meson_chip->level1_divider = div; 1128 meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider; 1129 meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1; 1130 1131 return 0; 1132 } 1133 1134 static int meson_nand_bch_mode(struct nand_chip *nand) 1135 { 1136 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1137 int i; 1138 1139 if (nand->ecc.strength > 60 || nand->ecc.strength < 8) 1140 return -EINVAL; 1141 1142 for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) { 1143 if (meson_ecc[i].strength == nand->ecc.strength) { 1144 meson_chip->bch_mode = meson_ecc[i].bch; 1145 return 0; 1146 } 1147 } 1148 1149 return -EINVAL; 1150 } 1151 1152 static void meson_nand_detach_chip(struct nand_chip *nand) 1153 { 1154 meson_nfc_free_buffer(nand); 1155 } 1156 1157 static int meson_nand_attach_chip(struct nand_chip *nand) 1158 { 1159 struct meson_nfc *nfc = nand_get_controller_data(nand); 1160 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1161 struct mtd_info *mtd = nand_to_mtd(nand); 1162 int nsectors = mtd->writesize / 1024; 1163 int ret; 1164 1165 if (!mtd->name) { 1166 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, 1167 "%s:nand%d", 1168 dev_name(nfc->dev), 1169 meson_chip->sels[0]); 1170 if (!mtd->name) 1171 return -ENOMEM; 1172 } 1173 1174 if (nand->bbt_options & NAND_BBT_USE_FLASH) 1175 nand->bbt_options |= NAND_BBT_NO_OOB; 1176 1177 nand->options |= NAND_NO_SUBPAGE_WRITE; 1178 1179 ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps, 1180 mtd->oobsize - 2 * nsectors); 1181 if (ret) { 1182 dev_err(nfc->dev, "failed to ECC init\n"); 1183 return -EINVAL; 1184 } 1185 1186 ret = meson_nand_bch_mode(nand); 1187 if (ret) 1188 return -EINVAL; 1189 1190 nand->ecc.mode = NAND_ECC_HW; 1191 nand->ecc.write_page_raw = meson_nfc_write_page_raw; 1192 nand->ecc.write_page = meson_nfc_write_page_hwecc; 1193 nand->ecc.write_oob_raw = nand_write_oob_std; 1194 nand->ecc.write_oob = nand_write_oob_std; 1195 1196 nand->ecc.read_page_raw = meson_nfc_read_page_raw; 1197 nand->ecc.read_page = meson_nfc_read_page_hwecc; 1198 nand->ecc.read_oob_raw = meson_nfc_read_oob_raw; 1199 nand->ecc.read_oob = meson_nfc_read_oob; 1200 1201 if (nand->options & NAND_BUSWIDTH_16) { 1202 dev_err(nfc->dev, "16bits bus width not supported"); 1203 return -EINVAL; 1204 } 1205 ret = meson_chip_buffer_init(nand); 1206 if (ret) 1207 return -ENOMEM; 1208 1209 return ret; 1210 } 1211 1212 static const struct nand_controller_ops meson_nand_controller_ops = { 1213 .attach_chip = meson_nand_attach_chip, 1214 .detach_chip = meson_nand_detach_chip, 1215 .setup_data_interface = meson_nfc_setup_data_interface, 1216 .exec_op = meson_nfc_exec_op, 1217 }; 1218 1219 static int 1220 meson_nfc_nand_chip_init(struct device *dev, 1221 struct meson_nfc *nfc, struct device_node *np) 1222 { 1223 struct meson_nfc_nand_chip *meson_chip; 1224 struct nand_chip *nand; 1225 struct mtd_info *mtd; 1226 int ret, i; 1227 u32 tmp, nsels; 1228 1229 if (!of_get_property(np, "reg", &nsels)) 1230 return -EINVAL; 1231 1232 nsels /= sizeof(u32); 1233 if (!nsels || nsels > MAX_CE_NUM) { 1234 dev_err(dev, "invalid register property size\n"); 1235 return -EINVAL; 1236 } 1237 1238 meson_chip = devm_kzalloc(dev, 1239 sizeof(*meson_chip) + (nsels * sizeof(u8)), 1240 GFP_KERNEL); 1241 if (!meson_chip) 1242 return -ENOMEM; 1243 1244 meson_chip->nsels = nsels; 1245 1246 for (i = 0; i < nsels; i++) { 1247 ret = of_property_read_u32_index(np, "reg", i, &tmp); 1248 if (ret) { 1249 dev_err(dev, "could not retrieve register property: %d\n", 1250 ret); 1251 return ret; 1252 } 1253 1254 if (test_and_set_bit(tmp, &nfc->assigned_cs)) { 1255 dev_err(dev, "CS %d already assigned\n", tmp); 1256 return -EINVAL; 1257 } 1258 } 1259 1260 nand = &meson_chip->nand; 1261 nand->controller = &nfc->controller; 1262 nand->controller->ops = &meson_nand_controller_ops; 1263 nand_set_flash_node(nand, np); 1264 nand_set_controller_data(nand, nfc); 1265 1266 nand->options |= NAND_USE_BOUNCE_BUFFER; 1267 mtd = nand_to_mtd(nand); 1268 mtd->owner = THIS_MODULE; 1269 mtd->dev.parent = dev; 1270 1271 ret = nand_scan(nand, nsels); 1272 if (ret) 1273 return ret; 1274 1275 ret = mtd_device_register(mtd, NULL, 0); 1276 if (ret) { 1277 dev_err(dev, "failed to register MTD device: %d\n", ret); 1278 nand_cleanup(nand); 1279 return ret; 1280 } 1281 1282 list_add_tail(&meson_chip->node, &nfc->chips); 1283 1284 return 0; 1285 } 1286 1287 static int meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc) 1288 { 1289 struct meson_nfc_nand_chip *meson_chip; 1290 struct mtd_info *mtd; 1291 int ret; 1292 1293 while (!list_empty(&nfc->chips)) { 1294 meson_chip = list_first_entry(&nfc->chips, 1295 struct meson_nfc_nand_chip, node); 1296 mtd = nand_to_mtd(&meson_chip->nand); 1297 ret = mtd_device_unregister(mtd); 1298 if (ret) 1299 return ret; 1300 1301 meson_nfc_free_buffer(&meson_chip->nand); 1302 nand_cleanup(&meson_chip->nand); 1303 list_del(&meson_chip->node); 1304 } 1305 1306 return 0; 1307 } 1308 1309 static int meson_nfc_nand_chips_init(struct device *dev, 1310 struct meson_nfc *nfc) 1311 { 1312 struct device_node *np = dev->of_node; 1313 struct device_node *nand_np; 1314 int ret; 1315 1316 for_each_child_of_node(np, nand_np) { 1317 ret = meson_nfc_nand_chip_init(dev, nfc, nand_np); 1318 if (ret) { 1319 meson_nfc_nand_chip_cleanup(nfc); 1320 return ret; 1321 } 1322 } 1323 1324 return 0; 1325 } 1326 1327 static irqreturn_t meson_nfc_irq(int irq, void *id) 1328 { 1329 struct meson_nfc *nfc = id; 1330 u32 cfg; 1331 1332 cfg = readl(nfc->reg_base + NFC_REG_CFG); 1333 if (!(cfg & NFC_RB_IRQ_EN)) 1334 return IRQ_NONE; 1335 1336 cfg &= ~(NFC_RB_IRQ_EN); 1337 writel(cfg, nfc->reg_base + NFC_REG_CFG); 1338 1339 complete(&nfc->completion); 1340 return IRQ_HANDLED; 1341 } 1342 1343 static const struct meson_nfc_data meson_gxl_data = { 1344 .ecc_caps = &meson_gxl_ecc_caps, 1345 }; 1346 1347 static const struct meson_nfc_data meson_axg_data = { 1348 .ecc_caps = &meson_axg_ecc_caps, 1349 }; 1350 1351 static const struct of_device_id meson_nfc_id_table[] = { 1352 { 1353 .compatible = "amlogic,meson-gxl-nfc", 1354 .data = &meson_gxl_data, 1355 }, { 1356 .compatible = "amlogic,meson-axg-nfc", 1357 .data = &meson_axg_data, 1358 }, 1359 {} 1360 }; 1361 MODULE_DEVICE_TABLE(of, meson_nfc_id_table); 1362 1363 static int meson_nfc_probe(struct platform_device *pdev) 1364 { 1365 struct device *dev = &pdev->dev; 1366 struct meson_nfc *nfc; 1367 struct resource *res; 1368 int ret, irq; 1369 1370 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1371 if (!nfc) 1372 return -ENOMEM; 1373 1374 nfc->data = of_device_get_match_data(&pdev->dev); 1375 if (!nfc->data) 1376 return -ENODEV; 1377 1378 nand_controller_init(&nfc->controller); 1379 INIT_LIST_HEAD(&nfc->chips); 1380 1381 nfc->dev = dev; 1382 1383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1384 nfc->reg_base = devm_ioremap_resource(dev, res); 1385 if (IS_ERR(nfc->reg_base)) 1386 return PTR_ERR(nfc->reg_base); 1387 1388 nfc->reg_clk = 1389 syscon_regmap_lookup_by_phandle(dev->of_node, 1390 "amlogic,mmc-syscon"); 1391 if (IS_ERR(nfc->reg_clk)) { 1392 dev_err(dev, "Failed to lookup clock base\n"); 1393 return PTR_ERR(nfc->reg_clk); 1394 } 1395 1396 irq = platform_get_irq(pdev, 0); 1397 if (irq < 0) { 1398 dev_err(dev, "no NFC IRQ resource\n"); 1399 return -EINVAL; 1400 } 1401 1402 ret = meson_nfc_clk_init(nfc); 1403 if (ret) { 1404 dev_err(dev, "failed to initialize NAND clock\n"); 1405 return ret; 1406 } 1407 1408 writel(0, nfc->reg_base + NFC_REG_CFG); 1409 ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc); 1410 if (ret) { 1411 dev_err(dev, "failed to request NFC IRQ\n"); 1412 ret = -EINVAL; 1413 goto err_clk; 1414 } 1415 1416 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 1417 if (ret) { 1418 dev_err(dev, "failed to set DMA mask\n"); 1419 goto err_clk; 1420 } 1421 1422 platform_set_drvdata(pdev, nfc); 1423 1424 ret = meson_nfc_nand_chips_init(dev, nfc); 1425 if (ret) { 1426 dev_err(dev, "failed to init NAND chips\n"); 1427 goto err_clk; 1428 } 1429 1430 return 0; 1431 err_clk: 1432 meson_nfc_disable_clk(nfc); 1433 return ret; 1434 } 1435 1436 static int meson_nfc_remove(struct platform_device *pdev) 1437 { 1438 struct meson_nfc *nfc = platform_get_drvdata(pdev); 1439 int ret; 1440 1441 ret = meson_nfc_nand_chip_cleanup(nfc); 1442 if (ret) 1443 return ret; 1444 1445 meson_nfc_disable_clk(nfc); 1446 1447 platform_set_drvdata(pdev, NULL); 1448 1449 return 0; 1450 } 1451 1452 static struct platform_driver meson_nfc_driver = { 1453 .probe = meson_nfc_probe, 1454 .remove = meson_nfc_remove, 1455 .driver = { 1456 .name = "meson-nand", 1457 .of_match_table = meson_nfc_id_table, 1458 }, 1459 }; 1460 module_platform_driver(meson_nfc_driver); 1461 1462 MODULE_LICENSE("Dual MIT/GPL"); 1463 MODULE_AUTHOR("Liang Yang <liang.yang@amlogic.com>"); 1464 MODULE_DESCRIPTION("Amlogic's Meson NAND Flash Controller driver"); 1465