1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Amlogic Meson Nand Flash Controller Driver 4 * 5 * Copyright (c) 2018 Amlogic, inc. 6 * Author: Liang Yang <liang.yang@amlogic.com> 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/mtd/rawnand.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/sched/task_stack.h> 24 25 #define NFC_REG_CMD 0x00 26 #define NFC_CMD_IDLE (0xc << 14) 27 #define NFC_CMD_CLE (0x5 << 14) 28 #define NFC_CMD_ALE (0x6 << 14) 29 #define NFC_CMD_ADL ((0 << 16) | (3 << 20)) 30 #define NFC_CMD_ADH ((1 << 16) | (3 << 20)) 31 #define NFC_CMD_AIL ((2 << 16) | (3 << 20)) 32 #define NFC_CMD_AIH ((3 << 16) | (3 << 20)) 33 #define NFC_CMD_SEED ((8 << 16) | (3 << 20)) 34 #define NFC_CMD_M2N ((0 << 17) | (2 << 20)) 35 #define NFC_CMD_N2M ((1 << 17) | (2 << 20)) 36 #define NFC_CMD_RB BIT(20) 37 #define NFC_CMD_SCRAMBLER_ENABLE BIT(19) 38 #define NFC_CMD_SCRAMBLER_DISABLE 0 39 #define NFC_CMD_SHORTMODE_DISABLE 0 40 #define NFC_CMD_RB_INT BIT(14) 41 42 #define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0)) 43 44 #define NFC_REG_CFG 0x04 45 #define NFC_REG_DADR 0x08 46 #define NFC_REG_IADR 0x0c 47 #define NFC_REG_BUF 0x10 48 #define NFC_REG_INFO 0x14 49 #define NFC_REG_DC 0x18 50 #define NFC_REG_ADR 0x1c 51 #define NFC_REG_DL 0x20 52 #define NFC_REG_DH 0x24 53 #define NFC_REG_CADR 0x28 54 #define NFC_REG_SADR 0x2c 55 #define NFC_REG_PINS 0x30 56 #define NFC_REG_VER 0x38 57 58 #define NFC_RB_IRQ_EN BIT(21) 59 60 #define CLK_DIV_SHIFT 0 61 #define CLK_DIV_WIDTH 6 62 63 #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ 64 ( \ 65 (cmd_dir) | \ 66 ((ran) << 19) | \ 67 ((bch) << 14) | \ 68 ((short_mode) << 13) | \ 69 (((page_size) & 0x7f) << 6) | \ 70 ((pages) & 0x3f) \ 71 ) 72 73 #define GENCMDDADDRL(adl, addr) ((adl) | ((addr) & 0xffff)) 74 #define GENCMDDADDRH(adh, addr) ((adh) | (((addr) >> 16) & 0xffff)) 75 #define GENCMDIADDRL(ail, addr) ((ail) | ((addr) & 0xffff)) 76 #define GENCMDIADDRH(aih, addr) ((aih) | (((addr) >> 16) & 0xffff)) 77 78 #define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) 79 80 #define ECC_CHECK_RETURN_FF (-1) 81 82 #define NAND_CE0 (0xe << 10) 83 #define NAND_CE1 (0xd << 10) 84 85 #define DMA_BUSY_TIMEOUT 0x100000 86 #define CMD_FIFO_EMPTY_TIMEOUT 1000 87 88 #define MAX_CE_NUM 2 89 90 /* eMMC clock register, misc control */ 91 #define CLK_SELECT_NAND BIT(31) 92 93 #define NFC_CLK_CYCLE 6 94 95 /* nand flash controller delay 3 ns */ 96 #define NFC_DEFAULT_DELAY 3000 97 98 #define ROW_ADDER(page, index) (((page) >> (8 * (index))) & 0xff) 99 #define MAX_CYCLE_ADDRS 5 100 #define DIRREAD 1 101 #define DIRWRITE 0 102 103 #define ECC_PARITY_BCH8_512B 14 104 #define ECC_COMPLETE BIT(31) 105 #define ECC_ERR_CNT(x) (((x) >> 24) & GENMASK(5, 0)) 106 #define ECC_ZERO_CNT(x) (((x) >> 16) & GENMASK(5, 0)) 107 #define ECC_UNCORRECTABLE 0x3f 108 109 #define PER_INFO_BYTE 8 110 111 struct meson_nfc_nand_chip { 112 struct list_head node; 113 struct nand_chip nand; 114 unsigned long clk_rate; 115 unsigned long level1_divider; 116 u32 bus_timing; 117 u32 twb; 118 u32 tadl; 119 u32 tbers_max; 120 121 u32 bch_mode; 122 u8 *data_buf; 123 __le64 *info_buf; 124 u32 nsels; 125 u8 sels[]; 126 }; 127 128 struct meson_nand_ecc { 129 u32 bch; 130 u32 strength; 131 }; 132 133 struct meson_nfc_data { 134 const struct nand_ecc_caps *ecc_caps; 135 }; 136 137 struct meson_nfc_param { 138 u32 chip_select; 139 u32 rb_select; 140 }; 141 142 struct nand_rw_cmd { 143 u32 cmd0; 144 u32 addrs[MAX_CYCLE_ADDRS]; 145 u32 cmd1; 146 }; 147 148 struct nand_timing { 149 u32 twb; 150 u32 tadl; 151 u32 tbers_max; 152 }; 153 154 struct meson_nfc { 155 struct nand_controller controller; 156 struct clk *core_clk; 157 struct clk *device_clk; 158 struct clk *nand_clk; 159 struct clk_divider nand_divider; 160 161 unsigned long clk_rate; 162 u32 bus_timing; 163 164 struct device *dev; 165 void __iomem *reg_base; 166 void __iomem *reg_clk; 167 struct completion completion; 168 struct list_head chips; 169 const struct meson_nfc_data *data; 170 struct meson_nfc_param param; 171 struct nand_timing timing; 172 union { 173 int cmd[32]; 174 struct nand_rw_cmd rw; 175 } cmdfifo; 176 177 dma_addr_t daddr; 178 dma_addr_t iaddr; 179 u32 info_bytes; 180 181 unsigned long assigned_cs; 182 }; 183 184 enum { 185 NFC_ECC_BCH8_1K = 2, 186 NFC_ECC_BCH24_1K, 187 NFC_ECC_BCH30_1K, 188 NFC_ECC_BCH40_1K, 189 NFC_ECC_BCH50_1K, 190 NFC_ECC_BCH60_1K, 191 }; 192 193 #define MESON_ECC_DATA(b, s) { .bch = (b), .strength = (s)} 194 195 static struct meson_nand_ecc meson_ecc[] = { 196 MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8), 197 MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24), 198 MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30), 199 MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40), 200 MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50), 201 MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60), 202 }; 203 204 static int meson_nand_calc_ecc_bytes(int step_size, int strength) 205 { 206 int ecc_bytes; 207 208 if (step_size == 512 && strength == 8) 209 return ECC_PARITY_BCH8_512B; 210 211 ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8); 212 ecc_bytes = ALIGN(ecc_bytes, 2); 213 214 return ecc_bytes; 215 } 216 217 NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps, 218 meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60); 219 NAND_ECC_CAPS_SINGLE(meson_axg_ecc_caps, 220 meson_nand_calc_ecc_bytes, 1024, 8); 221 222 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) 223 { 224 return container_of(nand, struct meson_nfc_nand_chip, nand); 225 } 226 227 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) 228 { 229 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 230 struct meson_nfc *nfc = nand_get_controller_data(nand); 231 int ret, value; 232 233 if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels)) 234 return; 235 236 nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0; 237 nfc->param.rb_select = nfc->param.chip_select; 238 nfc->timing.twb = meson_chip->twb; 239 nfc->timing.tadl = meson_chip->tadl; 240 nfc->timing.tbers_max = meson_chip->tbers_max; 241 242 if (nfc->clk_rate != meson_chip->clk_rate) { 243 ret = clk_set_rate(nfc->nand_clk, meson_chip->clk_rate); 244 if (ret) { 245 dev_err(nfc->dev, "failed to set clock rate\n"); 246 return; 247 } 248 nfc->clk_rate = meson_chip->clk_rate; 249 } 250 if (nfc->bus_timing != meson_chip->bus_timing) { 251 value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5); 252 writel(value, nfc->reg_base + NFC_REG_CFG); 253 writel((1 << 31), nfc->reg_base + NFC_REG_CMD); 254 nfc->bus_timing = meson_chip->bus_timing; 255 } 256 } 257 258 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time) 259 { 260 writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff), 261 nfc->reg_base + NFC_REG_CMD); 262 } 263 264 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed) 265 { 266 writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)), 267 nfc->reg_base + NFC_REG_CMD); 268 } 269 270 static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir, 271 int scrambler) 272 { 273 struct mtd_info *mtd = nand_to_mtd(nand); 274 struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); 275 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 276 u32 bch = meson_chip->bch_mode, cmd; 277 int len = mtd->writesize, pagesize, pages; 278 279 pagesize = nand->ecc.size; 280 281 if (raw) { 282 len = mtd->writesize + mtd->oobsize; 283 cmd = (len & GENMASK(13, 0)) | scrambler | DMA_DIR(dir); 284 writel(cmd, nfc->reg_base + NFC_REG_CMD); 285 return; 286 } 287 288 pages = len / nand->ecc.size; 289 290 cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch, 291 NFC_CMD_SHORTMODE_DISABLE, pagesize, pages); 292 293 writel(cmd, nfc->reg_base + NFC_REG_CMD); 294 } 295 296 static void meson_nfc_drain_cmd(struct meson_nfc *nfc) 297 { 298 /* 299 * Insert two commands to make sure all valid commands are finished. 300 * 301 * The Nand flash controller is designed as two stages pipleline - 302 * a) fetch and b) excute. 303 * There might be cases when the driver see command queue is empty, 304 * but the Nand flash controller still has two commands buffered, 305 * one is fetched into NFC request queue (ready to run), and another 306 * is actively executing. So pushing 2 "IDLE" commands guarantees that 307 * the pipeline is emptied. 308 */ 309 meson_nfc_cmd_idle(nfc, 0); 310 meson_nfc_cmd_idle(nfc, 0); 311 } 312 313 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc, 314 unsigned int timeout_ms) 315 { 316 u32 cmd_size = 0; 317 int ret; 318 319 /* wait cmd fifo is empty */ 320 ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size, 321 !NFC_CMD_GET_SIZE(cmd_size), 322 10, timeout_ms * 1000); 323 if (ret) 324 dev_err(nfc->dev, "wait for empty CMD FIFO time out\n"); 325 326 return ret; 327 } 328 329 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc) 330 { 331 meson_nfc_drain_cmd(nfc); 332 333 return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT); 334 } 335 336 static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i) 337 { 338 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 339 int len; 340 341 len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i; 342 343 return meson_chip->data_buf + len; 344 } 345 346 static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i) 347 { 348 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 349 int len, temp; 350 351 temp = nand->ecc.size + nand->ecc.bytes; 352 len = (temp + 2) * i; 353 354 return meson_chip->data_buf + len; 355 } 356 357 static void meson_nfc_get_data_oob(struct nand_chip *nand, 358 u8 *buf, u8 *oobbuf) 359 { 360 int i, oob_len = 0; 361 u8 *dsrc, *osrc; 362 363 oob_len = nand->ecc.bytes + 2; 364 for (i = 0; i < nand->ecc.steps; i++) { 365 if (buf) { 366 dsrc = meson_nfc_data_ptr(nand, i); 367 memcpy(buf, dsrc, nand->ecc.size); 368 buf += nand->ecc.size; 369 } 370 osrc = meson_nfc_oob_ptr(nand, i); 371 memcpy(oobbuf, osrc, oob_len); 372 oobbuf += oob_len; 373 } 374 } 375 376 static void meson_nfc_set_data_oob(struct nand_chip *nand, 377 const u8 *buf, u8 *oobbuf) 378 { 379 int i, oob_len = 0; 380 u8 *dsrc, *osrc; 381 382 oob_len = nand->ecc.bytes + 2; 383 for (i = 0; i < nand->ecc.steps; i++) { 384 if (buf) { 385 dsrc = meson_nfc_data_ptr(nand, i); 386 memcpy(dsrc, buf, nand->ecc.size); 387 buf += nand->ecc.size; 388 } 389 osrc = meson_nfc_oob_ptr(nand, i); 390 memcpy(osrc, oobbuf, oob_len); 391 oobbuf += oob_len; 392 } 393 } 394 395 static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms) 396 { 397 u32 cmd, cfg; 398 int ret = 0; 399 400 meson_nfc_cmd_idle(nfc, nfc->timing.twb); 401 meson_nfc_drain_cmd(nfc); 402 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT); 403 404 cfg = readl(nfc->reg_base + NFC_REG_CFG); 405 cfg |= NFC_RB_IRQ_EN; 406 writel(cfg, nfc->reg_base + NFC_REG_CFG); 407 408 reinit_completion(&nfc->completion); 409 410 /* use the max erase time as the maximum clock for waiting R/B */ 411 cmd = NFC_CMD_RB | NFC_CMD_RB_INT 412 | nfc->param.chip_select | nfc->timing.tbers_max; 413 writel(cmd, nfc->reg_base + NFC_REG_CMD); 414 415 ret = wait_for_completion_timeout(&nfc->completion, 416 msecs_to_jiffies(timeout_ms)); 417 if (ret == 0) 418 ret = -1; 419 420 return ret; 421 } 422 423 static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf) 424 { 425 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 426 __le64 *info; 427 int i, count; 428 429 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) { 430 info = &meson_chip->info_buf[i]; 431 *info |= oob_buf[count]; 432 *info |= oob_buf[count + 1] << 8; 433 } 434 } 435 436 static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf) 437 { 438 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 439 __le64 *info; 440 int i, count; 441 442 for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) { 443 info = &meson_chip->info_buf[i]; 444 oob_buf[count] = *info; 445 oob_buf[count + 1] = *info >> 8; 446 } 447 } 448 449 static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips, 450 u64 *correct_bitmap) 451 { 452 struct mtd_info *mtd = nand_to_mtd(nand); 453 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 454 __le64 *info; 455 int ret = 0, i; 456 457 for (i = 0; i < nand->ecc.steps; i++) { 458 info = &meson_chip->info_buf[i]; 459 if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) { 460 mtd->ecc_stats.corrected += ECC_ERR_CNT(*info); 461 *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info)); 462 *correct_bitmap |= BIT_ULL(i); 463 continue; 464 } 465 if ((nand->options & NAND_NEED_SCRAMBLING) && 466 ECC_ZERO_CNT(*info) < nand->ecc.strength) { 467 mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info); 468 *bitflips = max_t(u32, *bitflips, 469 ECC_ZERO_CNT(*info)); 470 ret = ECC_CHECK_RETURN_FF; 471 } else { 472 ret = -EBADMSG; 473 } 474 } 475 return ret; 476 } 477 478 static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, void *databuf, 479 int datalen, void *infobuf, int infolen, 480 enum dma_data_direction dir) 481 { 482 struct meson_nfc *nfc = nand_get_controller_data(nand); 483 u32 cmd; 484 int ret = 0; 485 486 nfc->daddr = dma_map_single(nfc->dev, databuf, datalen, dir); 487 ret = dma_mapping_error(nfc->dev, nfc->daddr); 488 if (ret) { 489 dev_err(nfc->dev, "DMA mapping error\n"); 490 return ret; 491 } 492 cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr); 493 writel(cmd, nfc->reg_base + NFC_REG_CMD); 494 495 cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr); 496 writel(cmd, nfc->reg_base + NFC_REG_CMD); 497 498 if (infobuf) { 499 nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir); 500 ret = dma_mapping_error(nfc->dev, nfc->iaddr); 501 if (ret) { 502 dev_err(nfc->dev, "DMA mapping error\n"); 503 dma_unmap_single(nfc->dev, 504 nfc->daddr, datalen, dir); 505 return ret; 506 } 507 nfc->info_bytes = infolen; 508 cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr); 509 writel(cmd, nfc->reg_base + NFC_REG_CMD); 510 511 cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr); 512 writel(cmd, nfc->reg_base + NFC_REG_CMD); 513 } 514 515 return ret; 516 } 517 518 static void meson_nfc_dma_buffer_release(struct nand_chip *nand, 519 int datalen, int infolen, 520 enum dma_data_direction dir) 521 { 522 struct meson_nfc *nfc = nand_get_controller_data(nand); 523 524 dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir); 525 if (infolen) { 526 dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir); 527 nfc->info_bytes = 0; 528 } 529 } 530 531 static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len) 532 { 533 struct meson_nfc *nfc = nand_get_controller_data(nand); 534 int ret = 0; 535 u32 cmd; 536 u8 *info; 537 538 info = kzalloc(PER_INFO_BYTE, GFP_KERNEL); 539 if (!info) 540 return -ENOMEM; 541 542 ret = meson_nfc_dma_buffer_setup(nand, buf, len, info, 543 PER_INFO_BYTE, DMA_FROM_DEVICE); 544 if (ret) 545 goto out; 546 547 cmd = NFC_CMD_N2M | (len & GENMASK(13, 0)); 548 writel(cmd, nfc->reg_base + NFC_REG_CMD); 549 550 meson_nfc_drain_cmd(nfc); 551 meson_nfc_wait_cmd_finish(nfc, 1000); 552 meson_nfc_dma_buffer_release(nand, len, PER_INFO_BYTE, DMA_FROM_DEVICE); 553 554 out: 555 kfree(info); 556 557 return ret; 558 } 559 560 static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len) 561 { 562 struct meson_nfc *nfc = nand_get_controller_data(nand); 563 int ret = 0; 564 u32 cmd; 565 566 ret = meson_nfc_dma_buffer_setup(nand, buf, len, NULL, 567 0, DMA_TO_DEVICE); 568 if (ret) 569 return ret; 570 571 cmd = NFC_CMD_M2N | (len & GENMASK(13, 0)); 572 writel(cmd, nfc->reg_base + NFC_REG_CMD); 573 574 meson_nfc_drain_cmd(nfc); 575 meson_nfc_wait_cmd_finish(nfc, 1000); 576 meson_nfc_dma_buffer_release(nand, len, 0, DMA_TO_DEVICE); 577 578 return ret; 579 } 580 581 static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand, 582 int page, bool in) 583 { 584 const struct nand_sdr_timings *sdr = 585 nand_get_sdr_timings(nand_get_interface_config(nand)); 586 struct mtd_info *mtd = nand_to_mtd(nand); 587 struct meson_nfc *nfc = nand_get_controller_data(nand); 588 u32 *addrs = nfc->cmdfifo.rw.addrs; 589 u32 cs = nfc->param.chip_select; 590 u32 cmd0, cmd_num, row_start; 591 int i; 592 593 cmd_num = sizeof(struct nand_rw_cmd) / sizeof(int); 594 595 cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN; 596 nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0; 597 598 addrs[0] = cs | NFC_CMD_ALE | 0; 599 if (mtd->writesize <= 512) { 600 cmd_num--; 601 row_start = 1; 602 } else { 603 addrs[1] = cs | NFC_CMD_ALE | 0; 604 row_start = 2; 605 } 606 607 addrs[row_start] = cs | NFC_CMD_ALE | ROW_ADDER(page, 0); 608 addrs[row_start + 1] = cs | NFC_CMD_ALE | ROW_ADDER(page, 1); 609 610 if (nand->options & NAND_ROW_ADDR_3) 611 addrs[row_start + 2] = 612 cs | NFC_CMD_ALE | ROW_ADDER(page, 2); 613 else 614 cmd_num--; 615 616 /* subtract cmd1 */ 617 cmd_num--; 618 619 for (i = 0; i < cmd_num; i++) 620 writel_relaxed(nfc->cmdfifo.cmd[i], 621 nfc->reg_base + NFC_REG_CMD); 622 623 if (in) { 624 nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART; 625 writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD); 626 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max)); 627 } else { 628 meson_nfc_cmd_idle(nfc, nfc->timing.tadl); 629 } 630 631 return 0; 632 } 633 634 static int meson_nfc_write_page_sub(struct nand_chip *nand, 635 int page, int raw) 636 { 637 const struct nand_sdr_timings *sdr = 638 nand_get_sdr_timings(nand_get_interface_config(nand)); 639 struct mtd_info *mtd = nand_to_mtd(nand); 640 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 641 struct meson_nfc *nfc = nand_get_controller_data(nand); 642 int data_len, info_len; 643 u32 cmd; 644 int ret; 645 646 meson_nfc_select_chip(nand, nand->cur_cs); 647 648 data_len = mtd->writesize + mtd->oobsize; 649 info_len = nand->ecc.steps * PER_INFO_BYTE; 650 651 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRWRITE); 652 if (ret) 653 return ret; 654 655 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf, 656 data_len, meson_chip->info_buf, 657 info_len, DMA_TO_DEVICE); 658 if (ret) 659 return ret; 660 661 if (nand->options & NAND_NEED_SCRAMBLING) { 662 meson_nfc_cmd_seed(nfc, page); 663 meson_nfc_cmd_access(nand, raw, DIRWRITE, 664 NFC_CMD_SCRAMBLER_ENABLE); 665 } else { 666 meson_nfc_cmd_access(nand, raw, DIRWRITE, 667 NFC_CMD_SCRAMBLER_DISABLE); 668 } 669 670 cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG; 671 writel(cmd, nfc->reg_base + NFC_REG_CMD); 672 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max)); 673 674 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE); 675 676 return ret; 677 } 678 679 static int meson_nfc_write_page_raw(struct nand_chip *nand, const u8 *buf, 680 int oob_required, int page) 681 { 682 u8 *oob_buf = nand->oob_poi; 683 684 meson_nfc_set_data_oob(nand, buf, oob_buf); 685 686 return meson_nfc_write_page_sub(nand, page, 1); 687 } 688 689 static int meson_nfc_write_page_hwecc(struct nand_chip *nand, 690 const u8 *buf, int oob_required, int page) 691 { 692 struct mtd_info *mtd = nand_to_mtd(nand); 693 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 694 u8 *oob_buf = nand->oob_poi; 695 696 memcpy(meson_chip->data_buf, buf, mtd->writesize); 697 memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE); 698 meson_nfc_set_user_byte(nand, oob_buf); 699 700 return meson_nfc_write_page_sub(nand, page, 0); 701 } 702 703 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc, 704 struct nand_chip *nand, int raw) 705 { 706 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 707 __le64 *info; 708 u32 neccpages; 709 int ret; 710 711 neccpages = raw ? 1 : nand->ecc.steps; 712 info = &meson_chip->info_buf[neccpages - 1]; 713 do { 714 usleep_range(10, 15); 715 /* info is updated by nfc dma engine*/ 716 smp_rmb(); 717 dma_sync_single_for_cpu(nfc->dev, nfc->iaddr, nfc->info_bytes, 718 DMA_FROM_DEVICE); 719 ret = *info & ECC_COMPLETE; 720 } while (!ret); 721 } 722 723 static int meson_nfc_read_page_sub(struct nand_chip *nand, 724 int page, int raw) 725 { 726 struct mtd_info *mtd = nand_to_mtd(nand); 727 struct meson_nfc *nfc = nand_get_controller_data(nand); 728 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 729 int data_len, info_len; 730 int ret; 731 732 meson_nfc_select_chip(nand, nand->cur_cs); 733 734 data_len = mtd->writesize + mtd->oobsize; 735 info_len = nand->ecc.steps * PER_INFO_BYTE; 736 737 ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRREAD); 738 if (ret) 739 return ret; 740 741 ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf, 742 data_len, meson_chip->info_buf, 743 info_len, DMA_FROM_DEVICE); 744 if (ret) 745 return ret; 746 747 if (nand->options & NAND_NEED_SCRAMBLING) { 748 meson_nfc_cmd_seed(nfc, page); 749 meson_nfc_cmd_access(nand, raw, DIRREAD, 750 NFC_CMD_SCRAMBLER_ENABLE); 751 } else { 752 meson_nfc_cmd_access(nand, raw, DIRREAD, 753 NFC_CMD_SCRAMBLER_DISABLE); 754 } 755 756 ret = meson_nfc_wait_dma_finish(nfc); 757 meson_nfc_check_ecc_pages_valid(nfc, nand, raw); 758 759 meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_FROM_DEVICE); 760 761 return ret; 762 } 763 764 static int meson_nfc_read_page_raw(struct nand_chip *nand, u8 *buf, 765 int oob_required, int page) 766 { 767 u8 *oob_buf = nand->oob_poi; 768 int ret; 769 770 ret = meson_nfc_read_page_sub(nand, page, 1); 771 if (ret) 772 return ret; 773 774 meson_nfc_get_data_oob(nand, buf, oob_buf); 775 776 return 0; 777 } 778 779 static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf, 780 int oob_required, int page) 781 { 782 struct mtd_info *mtd = nand_to_mtd(nand); 783 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 784 struct nand_ecc_ctrl *ecc = &nand->ecc; 785 u64 correct_bitmap = 0; 786 u32 bitflips = 0; 787 u8 *oob_buf = nand->oob_poi; 788 int ret, i; 789 790 ret = meson_nfc_read_page_sub(nand, page, 0); 791 if (ret) 792 return ret; 793 794 meson_nfc_get_user_byte(nand, oob_buf); 795 ret = meson_nfc_ecc_correct(nand, &bitflips, &correct_bitmap); 796 if (ret == ECC_CHECK_RETURN_FF) { 797 if (buf) 798 memset(buf, 0xff, mtd->writesize); 799 memset(oob_buf, 0xff, mtd->oobsize); 800 } else if (ret < 0) { 801 if ((nand->options & NAND_NEED_SCRAMBLING) || !buf) { 802 mtd->ecc_stats.failed++; 803 return bitflips; 804 } 805 ret = meson_nfc_read_page_raw(nand, buf, 0, page); 806 if (ret) 807 return ret; 808 809 for (i = 0; i < nand->ecc.steps ; i++) { 810 u8 *data = buf + i * ecc->size; 811 u8 *oob = nand->oob_poi + i * (ecc->bytes + 2); 812 813 if (correct_bitmap & BIT_ULL(i)) 814 continue; 815 ret = nand_check_erased_ecc_chunk(data, ecc->size, 816 oob, ecc->bytes + 2, 817 NULL, 0, 818 ecc->strength); 819 if (ret < 0) { 820 mtd->ecc_stats.failed++; 821 } else { 822 mtd->ecc_stats.corrected += ret; 823 bitflips = max_t(u32, bitflips, ret); 824 } 825 } 826 } else if (buf && buf != meson_chip->data_buf) { 827 memcpy(buf, meson_chip->data_buf, mtd->writesize); 828 } 829 830 return bitflips; 831 } 832 833 static int meson_nfc_read_oob_raw(struct nand_chip *nand, int page) 834 { 835 return meson_nfc_read_page_raw(nand, NULL, 1, page); 836 } 837 838 static int meson_nfc_read_oob(struct nand_chip *nand, int page) 839 { 840 return meson_nfc_read_page_hwecc(nand, NULL, 1, page); 841 } 842 843 static bool meson_nfc_is_buffer_dma_safe(const void *buffer) 844 { 845 if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer))) 846 return true; 847 return false; 848 } 849 850 static void * 851 meson_nand_op_get_dma_safe_input_buf(const struct nand_op_instr *instr) 852 { 853 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR)) 854 return NULL; 855 856 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.in)) 857 return instr->ctx.data.buf.in; 858 859 return kzalloc(instr->ctx.data.len, GFP_KERNEL); 860 } 861 862 static void 863 meson_nand_op_put_dma_safe_input_buf(const struct nand_op_instr *instr, 864 void *buf) 865 { 866 if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) || 867 WARN_ON(!buf)) 868 return; 869 870 if (buf == instr->ctx.data.buf.in) 871 return; 872 873 memcpy(instr->ctx.data.buf.in, buf, instr->ctx.data.len); 874 kfree(buf); 875 } 876 877 static void * 878 meson_nand_op_get_dma_safe_output_buf(const struct nand_op_instr *instr) 879 { 880 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR)) 881 return NULL; 882 883 if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.out)) 884 return (void *)instr->ctx.data.buf.out; 885 886 return kmemdup(instr->ctx.data.buf.out, 887 instr->ctx.data.len, GFP_KERNEL); 888 } 889 890 static void 891 meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr, 892 const void *buf) 893 { 894 if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) || 895 WARN_ON(!buf)) 896 return; 897 898 if (buf != instr->ctx.data.buf.out) 899 kfree(buf); 900 } 901 902 static int meson_nfc_exec_op(struct nand_chip *nand, 903 const struct nand_operation *op, bool check_only) 904 { 905 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 906 struct meson_nfc *nfc = nand_get_controller_data(nand); 907 const struct nand_op_instr *instr = NULL; 908 void *buf; 909 u32 op_id, delay_idle, cmd; 910 int i; 911 912 if (check_only) 913 return 0; 914 915 meson_nfc_select_chip(nand, op->cs); 916 for (op_id = 0; op_id < op->ninstrs; op_id++) { 917 instr = &op->instrs[op_id]; 918 delay_idle = DIV_ROUND_UP(PSEC_TO_NSEC(instr->delay_ns), 919 meson_chip->level1_divider * 920 NFC_CLK_CYCLE); 921 switch (instr->type) { 922 case NAND_OP_CMD_INSTR: 923 cmd = nfc->param.chip_select | NFC_CMD_CLE; 924 cmd |= instr->ctx.cmd.opcode & 0xff; 925 writel(cmd, nfc->reg_base + NFC_REG_CMD); 926 meson_nfc_cmd_idle(nfc, delay_idle); 927 break; 928 929 case NAND_OP_ADDR_INSTR: 930 for (i = 0; i < instr->ctx.addr.naddrs; i++) { 931 cmd = nfc->param.chip_select | NFC_CMD_ALE; 932 cmd |= instr->ctx.addr.addrs[i] & 0xff; 933 writel(cmd, nfc->reg_base + NFC_REG_CMD); 934 } 935 meson_nfc_cmd_idle(nfc, delay_idle); 936 break; 937 938 case NAND_OP_DATA_IN_INSTR: 939 buf = meson_nand_op_get_dma_safe_input_buf(instr); 940 if (!buf) 941 return -ENOMEM; 942 meson_nfc_read_buf(nand, buf, instr->ctx.data.len); 943 meson_nand_op_put_dma_safe_input_buf(instr, buf); 944 break; 945 946 case NAND_OP_DATA_OUT_INSTR: 947 buf = meson_nand_op_get_dma_safe_output_buf(instr); 948 if (!buf) 949 return -ENOMEM; 950 meson_nfc_write_buf(nand, buf, instr->ctx.data.len); 951 meson_nand_op_put_dma_safe_output_buf(instr, buf); 952 break; 953 954 case NAND_OP_WAITRDY_INSTR: 955 meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms); 956 if (instr->delay_ns) 957 meson_nfc_cmd_idle(nfc, delay_idle); 958 break; 959 } 960 } 961 meson_nfc_wait_cmd_finish(nfc, 1000); 962 return 0; 963 } 964 965 static int meson_ooblayout_ecc(struct mtd_info *mtd, int section, 966 struct mtd_oob_region *oobregion) 967 { 968 struct nand_chip *nand = mtd_to_nand(mtd); 969 970 if (section >= nand->ecc.steps) 971 return -ERANGE; 972 973 oobregion->offset = 2 + (section * (2 + nand->ecc.bytes)); 974 oobregion->length = nand->ecc.bytes; 975 976 return 0; 977 } 978 979 static int meson_ooblayout_free(struct mtd_info *mtd, int section, 980 struct mtd_oob_region *oobregion) 981 { 982 struct nand_chip *nand = mtd_to_nand(mtd); 983 984 if (section >= nand->ecc.steps) 985 return -ERANGE; 986 987 oobregion->offset = section * (2 + nand->ecc.bytes); 988 oobregion->length = 2; 989 990 return 0; 991 } 992 993 static const struct mtd_ooblayout_ops meson_ooblayout_ops = { 994 .ecc = meson_ooblayout_ecc, 995 .free = meson_ooblayout_free, 996 }; 997 998 static int meson_nfc_clk_init(struct meson_nfc *nfc) 999 { 1000 struct clk_parent_data nfc_divider_parent_data[1] = {0}; 1001 struct clk_init_data init = {0}; 1002 int ret; 1003 1004 /* request core clock */ 1005 nfc->core_clk = devm_clk_get(nfc->dev, "core"); 1006 if (IS_ERR(nfc->core_clk)) { 1007 dev_err(nfc->dev, "failed to get core clock\n"); 1008 return PTR_ERR(nfc->core_clk); 1009 } 1010 1011 nfc->device_clk = devm_clk_get(nfc->dev, "device"); 1012 if (IS_ERR(nfc->device_clk)) { 1013 dev_err(nfc->dev, "failed to get device clock\n"); 1014 return PTR_ERR(nfc->device_clk); 1015 } 1016 1017 init.name = devm_kasprintf(nfc->dev, 1018 GFP_KERNEL, "%s#div", 1019 dev_name(nfc->dev)); 1020 init.ops = &clk_divider_ops; 1021 nfc_divider_parent_data[0].fw_name = "device"; 1022 init.parent_data = nfc_divider_parent_data; 1023 init.num_parents = 1; 1024 nfc->nand_divider.reg = nfc->reg_clk; 1025 nfc->nand_divider.shift = CLK_DIV_SHIFT; 1026 nfc->nand_divider.width = CLK_DIV_WIDTH; 1027 nfc->nand_divider.hw.init = &init; 1028 nfc->nand_divider.flags = CLK_DIVIDER_ONE_BASED | 1029 CLK_DIVIDER_ROUND_CLOSEST | 1030 CLK_DIVIDER_ALLOW_ZERO; 1031 1032 nfc->nand_clk = devm_clk_register(nfc->dev, &nfc->nand_divider.hw); 1033 if (IS_ERR(nfc->nand_clk)) 1034 return PTR_ERR(nfc->nand_clk); 1035 1036 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 1037 writel(CLK_SELECT_NAND | readl(nfc->reg_clk), 1038 nfc->reg_clk); 1039 1040 ret = clk_prepare_enable(nfc->core_clk); 1041 if (ret) { 1042 dev_err(nfc->dev, "failed to enable core clock\n"); 1043 return ret; 1044 } 1045 1046 ret = clk_prepare_enable(nfc->device_clk); 1047 if (ret) { 1048 dev_err(nfc->dev, "failed to enable device clock\n"); 1049 goto err_device_clk; 1050 } 1051 1052 ret = clk_prepare_enable(nfc->nand_clk); 1053 if (ret) { 1054 dev_err(nfc->dev, "pre enable NFC divider fail\n"); 1055 goto err_nand_clk; 1056 } 1057 1058 ret = clk_set_rate(nfc->nand_clk, 24000000); 1059 if (ret) 1060 goto err_disable_clk; 1061 1062 return 0; 1063 1064 err_disable_clk: 1065 clk_disable_unprepare(nfc->nand_clk); 1066 err_nand_clk: 1067 clk_disable_unprepare(nfc->device_clk); 1068 err_device_clk: 1069 clk_disable_unprepare(nfc->core_clk); 1070 return ret; 1071 } 1072 1073 static void meson_nfc_disable_clk(struct meson_nfc *nfc) 1074 { 1075 clk_disable_unprepare(nfc->nand_clk); 1076 clk_disable_unprepare(nfc->device_clk); 1077 clk_disable_unprepare(nfc->core_clk); 1078 } 1079 1080 static void meson_nfc_free_buffer(struct nand_chip *nand) 1081 { 1082 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1083 1084 kfree(meson_chip->info_buf); 1085 kfree(meson_chip->data_buf); 1086 } 1087 1088 static int meson_chip_buffer_init(struct nand_chip *nand) 1089 { 1090 struct mtd_info *mtd = nand_to_mtd(nand); 1091 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1092 u32 page_bytes, info_bytes, nsectors; 1093 1094 nsectors = mtd->writesize / nand->ecc.size; 1095 1096 page_bytes = mtd->writesize + mtd->oobsize; 1097 info_bytes = nsectors * PER_INFO_BYTE; 1098 1099 meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL); 1100 if (!meson_chip->data_buf) 1101 return -ENOMEM; 1102 1103 meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL); 1104 if (!meson_chip->info_buf) { 1105 kfree(meson_chip->data_buf); 1106 return -ENOMEM; 1107 } 1108 1109 return 0; 1110 } 1111 1112 static 1113 int meson_nfc_setup_interface(struct nand_chip *nand, int csline, 1114 const struct nand_interface_config *conf) 1115 { 1116 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1117 const struct nand_sdr_timings *timings; 1118 u32 div, bt_min, bt_max, tbers_clocks; 1119 1120 timings = nand_get_sdr_timings(conf); 1121 if (IS_ERR(timings)) 1122 return -ENOTSUPP; 1123 1124 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1125 return 0; 1126 1127 div = DIV_ROUND_UP((timings->tRC_min / 1000), NFC_CLK_CYCLE); 1128 bt_min = (timings->tREA_max + NFC_DEFAULT_DELAY) / div; 1129 bt_max = (NFC_DEFAULT_DELAY + timings->tRHOH_min + 1130 timings->tRC_min / 2) / div; 1131 1132 meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max), 1133 div * NFC_CLK_CYCLE); 1134 meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min), 1135 div * NFC_CLK_CYCLE); 1136 tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max), 1137 div * NFC_CLK_CYCLE); 1138 meson_chip->tbers_max = ilog2(tbers_clocks); 1139 if (!is_power_of_2(tbers_clocks)) 1140 meson_chip->tbers_max++; 1141 1142 bt_min = DIV_ROUND_UP(bt_min, 1000); 1143 bt_max = DIV_ROUND_UP(bt_max, 1000); 1144 1145 if (bt_max < bt_min) 1146 return -EINVAL; 1147 1148 meson_chip->level1_divider = div; 1149 meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider; 1150 meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1; 1151 1152 return 0; 1153 } 1154 1155 static int meson_nand_bch_mode(struct nand_chip *nand) 1156 { 1157 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1158 int i; 1159 1160 if (nand->ecc.strength > 60 || nand->ecc.strength < 8) 1161 return -EINVAL; 1162 1163 for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) { 1164 if (meson_ecc[i].strength == nand->ecc.strength) { 1165 meson_chip->bch_mode = meson_ecc[i].bch; 1166 return 0; 1167 } 1168 } 1169 1170 return -EINVAL; 1171 } 1172 1173 static void meson_nand_detach_chip(struct nand_chip *nand) 1174 { 1175 meson_nfc_free_buffer(nand); 1176 } 1177 1178 static int meson_nand_attach_chip(struct nand_chip *nand) 1179 { 1180 struct meson_nfc *nfc = nand_get_controller_data(nand); 1181 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); 1182 struct mtd_info *mtd = nand_to_mtd(nand); 1183 int nsectors = mtd->writesize / 1024; 1184 int ret; 1185 1186 if (!mtd->name) { 1187 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, 1188 "%s:nand%d", 1189 dev_name(nfc->dev), 1190 meson_chip->sels[0]); 1191 if (!mtd->name) 1192 return -ENOMEM; 1193 } 1194 1195 if (nand->bbt_options & NAND_BBT_USE_FLASH) 1196 nand->bbt_options |= NAND_BBT_NO_OOB; 1197 1198 nand->options |= NAND_NO_SUBPAGE_WRITE; 1199 1200 ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps, 1201 mtd->oobsize - 2 * nsectors); 1202 if (ret) { 1203 dev_err(nfc->dev, "failed to ECC init\n"); 1204 return -EINVAL; 1205 } 1206 1207 mtd_set_ooblayout(mtd, &meson_ooblayout_ops); 1208 1209 ret = meson_nand_bch_mode(nand); 1210 if (ret) 1211 return -EINVAL; 1212 1213 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1214 nand->ecc.write_page_raw = meson_nfc_write_page_raw; 1215 nand->ecc.write_page = meson_nfc_write_page_hwecc; 1216 nand->ecc.write_oob_raw = nand_write_oob_std; 1217 nand->ecc.write_oob = nand_write_oob_std; 1218 1219 nand->ecc.read_page_raw = meson_nfc_read_page_raw; 1220 nand->ecc.read_page = meson_nfc_read_page_hwecc; 1221 nand->ecc.read_oob_raw = meson_nfc_read_oob_raw; 1222 nand->ecc.read_oob = meson_nfc_read_oob; 1223 1224 if (nand->options & NAND_BUSWIDTH_16) { 1225 dev_err(nfc->dev, "16bits bus width not supported"); 1226 return -EINVAL; 1227 } 1228 ret = meson_chip_buffer_init(nand); 1229 if (ret) 1230 return -ENOMEM; 1231 1232 return ret; 1233 } 1234 1235 static const struct nand_controller_ops meson_nand_controller_ops = { 1236 .attach_chip = meson_nand_attach_chip, 1237 .detach_chip = meson_nand_detach_chip, 1238 .setup_interface = meson_nfc_setup_interface, 1239 .exec_op = meson_nfc_exec_op, 1240 }; 1241 1242 static int 1243 meson_nfc_nand_chip_init(struct device *dev, 1244 struct meson_nfc *nfc, struct device_node *np) 1245 { 1246 struct meson_nfc_nand_chip *meson_chip; 1247 struct nand_chip *nand; 1248 struct mtd_info *mtd; 1249 int ret, i; 1250 u32 tmp, nsels; 1251 1252 nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32)); 1253 if (!nsels || nsels > MAX_CE_NUM) { 1254 dev_err(dev, "invalid register property size\n"); 1255 return -EINVAL; 1256 } 1257 1258 meson_chip = devm_kzalloc(dev, struct_size(meson_chip, sels, nsels), 1259 GFP_KERNEL); 1260 if (!meson_chip) 1261 return -ENOMEM; 1262 1263 meson_chip->nsels = nsels; 1264 1265 for (i = 0; i < nsels; i++) { 1266 ret = of_property_read_u32_index(np, "reg", i, &tmp); 1267 if (ret) { 1268 dev_err(dev, "could not retrieve register property: %d\n", 1269 ret); 1270 return ret; 1271 } 1272 1273 if (test_and_set_bit(tmp, &nfc->assigned_cs)) { 1274 dev_err(dev, "CS %d already assigned\n", tmp); 1275 return -EINVAL; 1276 } 1277 } 1278 1279 nand = &meson_chip->nand; 1280 nand->controller = &nfc->controller; 1281 nand->controller->ops = &meson_nand_controller_ops; 1282 nand_set_flash_node(nand, np); 1283 nand_set_controller_data(nand, nfc); 1284 1285 nand->options |= NAND_USES_DMA; 1286 mtd = nand_to_mtd(nand); 1287 mtd->owner = THIS_MODULE; 1288 mtd->dev.parent = dev; 1289 1290 ret = nand_scan(nand, nsels); 1291 if (ret) 1292 return ret; 1293 1294 ret = mtd_device_register(mtd, NULL, 0); 1295 if (ret) { 1296 dev_err(dev, "failed to register MTD device: %d\n", ret); 1297 nand_cleanup(nand); 1298 return ret; 1299 } 1300 1301 list_add_tail(&meson_chip->node, &nfc->chips); 1302 1303 return 0; 1304 } 1305 1306 static void meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc) 1307 { 1308 struct meson_nfc_nand_chip *meson_chip; 1309 struct mtd_info *mtd; 1310 1311 while (!list_empty(&nfc->chips)) { 1312 meson_chip = list_first_entry(&nfc->chips, 1313 struct meson_nfc_nand_chip, node); 1314 mtd = nand_to_mtd(&meson_chip->nand); 1315 WARN_ON(mtd_device_unregister(mtd)); 1316 1317 nand_cleanup(&meson_chip->nand); 1318 list_del(&meson_chip->node); 1319 } 1320 } 1321 1322 static int meson_nfc_nand_chips_init(struct device *dev, 1323 struct meson_nfc *nfc) 1324 { 1325 struct device_node *np = dev->of_node; 1326 struct device_node *nand_np; 1327 int ret; 1328 1329 for_each_child_of_node(np, nand_np) { 1330 ret = meson_nfc_nand_chip_init(dev, nfc, nand_np); 1331 if (ret) { 1332 meson_nfc_nand_chip_cleanup(nfc); 1333 of_node_put(nand_np); 1334 return ret; 1335 } 1336 } 1337 1338 return 0; 1339 } 1340 1341 static irqreturn_t meson_nfc_irq(int irq, void *id) 1342 { 1343 struct meson_nfc *nfc = id; 1344 u32 cfg; 1345 1346 cfg = readl(nfc->reg_base + NFC_REG_CFG); 1347 if (!(cfg & NFC_RB_IRQ_EN)) 1348 return IRQ_NONE; 1349 1350 cfg &= ~(NFC_RB_IRQ_EN); 1351 writel(cfg, nfc->reg_base + NFC_REG_CFG); 1352 1353 complete(&nfc->completion); 1354 return IRQ_HANDLED; 1355 } 1356 1357 static const struct meson_nfc_data meson_gxl_data = { 1358 .ecc_caps = &meson_gxl_ecc_caps, 1359 }; 1360 1361 static const struct meson_nfc_data meson_axg_data = { 1362 .ecc_caps = &meson_axg_ecc_caps, 1363 }; 1364 1365 static const struct of_device_id meson_nfc_id_table[] = { 1366 { 1367 .compatible = "amlogic,meson-gxl-nfc", 1368 .data = &meson_gxl_data, 1369 }, { 1370 .compatible = "amlogic,meson-axg-nfc", 1371 .data = &meson_axg_data, 1372 }, 1373 {} 1374 }; 1375 MODULE_DEVICE_TABLE(of, meson_nfc_id_table); 1376 1377 static int meson_nfc_probe(struct platform_device *pdev) 1378 { 1379 struct device *dev = &pdev->dev; 1380 struct meson_nfc *nfc; 1381 int ret, irq; 1382 1383 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1384 if (!nfc) 1385 return -ENOMEM; 1386 1387 nfc->data = of_device_get_match_data(&pdev->dev); 1388 if (!nfc->data) 1389 return -ENODEV; 1390 1391 nand_controller_init(&nfc->controller); 1392 INIT_LIST_HEAD(&nfc->chips); 1393 init_completion(&nfc->completion); 1394 1395 nfc->dev = dev; 1396 1397 nfc->reg_base = devm_platform_ioremap_resource_byname(pdev, "nfc"); 1398 if (IS_ERR(nfc->reg_base)) 1399 return PTR_ERR(nfc->reg_base); 1400 1401 nfc->reg_clk = devm_platform_ioremap_resource_byname(pdev, "emmc"); 1402 if (IS_ERR(nfc->reg_clk)) 1403 return PTR_ERR(nfc->reg_clk); 1404 1405 irq = platform_get_irq(pdev, 0); 1406 if (irq < 0) 1407 return -EINVAL; 1408 1409 ret = meson_nfc_clk_init(nfc); 1410 if (ret) { 1411 dev_err(dev, "failed to initialize NAND clock\n"); 1412 return ret; 1413 } 1414 1415 writel(0, nfc->reg_base + NFC_REG_CFG); 1416 ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc); 1417 if (ret) { 1418 dev_err(dev, "failed to request NFC IRQ\n"); 1419 ret = -EINVAL; 1420 goto err_clk; 1421 } 1422 1423 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 1424 if (ret) { 1425 dev_err(dev, "failed to set DMA mask\n"); 1426 goto err_clk; 1427 } 1428 1429 platform_set_drvdata(pdev, nfc); 1430 1431 ret = meson_nfc_nand_chips_init(dev, nfc); 1432 if (ret) { 1433 dev_err(dev, "failed to init NAND chips\n"); 1434 goto err_clk; 1435 } 1436 1437 return 0; 1438 err_clk: 1439 meson_nfc_disable_clk(nfc); 1440 return ret; 1441 } 1442 1443 static void meson_nfc_remove(struct platform_device *pdev) 1444 { 1445 struct meson_nfc *nfc = platform_get_drvdata(pdev); 1446 1447 meson_nfc_nand_chip_cleanup(nfc); 1448 1449 meson_nfc_disable_clk(nfc); 1450 } 1451 1452 static struct platform_driver meson_nfc_driver = { 1453 .probe = meson_nfc_probe, 1454 .remove_new = meson_nfc_remove, 1455 .driver = { 1456 .name = "meson-nand", 1457 .of_match_table = meson_nfc_id_table, 1458 }, 1459 }; 1460 module_platform_driver(meson_nfc_driver); 1461 1462 MODULE_LICENSE("Dual MIT/GPL"); 1463 MODULE_AUTHOR("Liang Yang <liang.yang@amlogic.com>"); 1464 MODULE_DESCRIPTION("Amlogic's Meson NAND Flash Controller driver"); 1465