1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Marvell NAND flash controller driver 4 * 5 * Copyright (C) 2017 Marvell 6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com> 7 * 8 * 9 * This NAND controller driver handles two versions of the hardware, 10 * one is called NFCv1 and is available on PXA SoCs and the other is 11 * called NFCv2 and is available on Armada SoCs. 12 * 13 * The main visible difference is that NFCv1 only has Hamming ECC 14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA 15 * is not used with NFCv2. 16 * 17 * The ECC layouts are depicted in details in Marvell AN-379, but here 18 * is a brief description. 19 * 20 * When using Hamming, the data is split in 512B chunks (either 1, 2 21 * or 4) and each chunk will have its own ECC "digest" of 6B at the 22 * beginning of the OOB area and eventually the remaining free OOB 23 * bytes (also called "spare" bytes in the driver). This engine 24 * corrects up to 1 bit per chunk and detects reliably an error if 25 * there are at most 2 bitflips. Here is the page layout used by the 26 * controller when Hamming is chosen: 27 * 28 * +-------------------------------------------------------------+ 29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes | 30 * +-------------------------------------------------------------+ 31 * 32 * When using the BCH engine, there are N identical (data + free OOB + 33 * ECC) sections and potentially an extra one to deal with 34 * configurations where the chosen (data + free OOB + ECC) sizes do 35 * not align with the page (data + OOB) size. ECC bytes are always 36 * 30B per ECC chunk. Here is the page layout used by the controller 37 * when BCH is chosen: 38 * 39 * +----------------------------------------- 40 * | Data 1 | Free OOB bytes 1 | ECC 1 | ... 41 * +----------------------------------------- 42 * 43 * ------------------------------------------- 44 * ... | Data N | Free OOB bytes N | ECC N | 45 * ------------------------------------------- 46 * 47 * --------------------------------------------+ 48 * Last Data | Last Free OOB bytes | Last ECC | 49 * --------------------------------------------+ 50 * 51 * In both cases, the layout seen by the user is always: all data 52 * first, then all free OOB bytes and finally all ECC bytes. With BCH, 53 * ECC bytes are 30B long and are padded with 0xFF to align on 32 54 * bytes. 55 * 56 * The controller has certain limitations that are handled by the 57 * driver: 58 * - It can only read 2k at a time. To overcome this limitation, the 59 * driver issues data cycles on the bus, without issuing new 60 * CMD + ADDR cycles. The Marvell term is "naked" operations. 61 * - The ECC strength in BCH mode cannot be tuned. It is fixed 16 62 * bits. What can be tuned is the ECC block size as long as it 63 * stays between 512B and 2kiB. It's usually chosen based on the 64 * chip ECC requirements. For instance, using 2kiB ECC chunks 65 * provides 4b/512B correctability. 66 * - The controller will always treat data bytes, free OOB bytes 67 * and ECC bytes in that order, no matter what the real layout is 68 * (which is usually all data then all OOB bytes). The 69 * marvell_nfc_layouts array below contains the currently 70 * supported layouts. 71 * - Because of these weird layouts, the Bad Block Markers can be 72 * located in data section. In this case, the NAND_BBT_NO_OOB_BBM 73 * option must be set to prevent scanning/writing bad block 74 * markers. 75 */ 76 77 #include <linux/module.h> 78 #include <linux/clk.h> 79 #include <linux/mtd/rawnand.h> 80 #include <linux/of.h> 81 #include <linux/iopoll.h> 82 #include <linux/interrupt.h> 83 #include <linux/platform_device.h> 84 #include <linux/slab.h> 85 #include <linux/mfd/syscon.h> 86 #include <linux/regmap.h> 87 #include <asm/unaligned.h> 88 89 #include <linux/dmaengine.h> 90 #include <linux/dma-mapping.h> 91 #include <linux/dma/pxa-dma.h> 92 #include <linux/platform_data/mtd-nand-pxa3xx.h> 93 94 /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */ 95 #define FIFO_DEPTH 8 96 #define FIFO_REP(x) (x / sizeof(u32)) 97 #define BCH_SEQ_READS (32 / FIFO_DEPTH) 98 /* NFC does not support transfers of larger chunks at a time */ 99 #define MAX_CHUNK_SIZE 2112 100 /* NFCv1 cannot read more that 7 bytes of ID */ 101 #define NFCV1_READID_LEN 7 102 /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */ 103 #define POLL_PERIOD 0 104 #define POLL_TIMEOUT 100000 105 /* Interrupt maximum wait period in ms */ 106 #define IRQ_TIMEOUT 1000 107 /* Latency in clock cycles between SoC pins and NFC logic */ 108 #define MIN_RD_DEL_CNT 3 109 /* Maximum number of contiguous address cycles */ 110 #define MAX_ADDRESS_CYC_NFCV1 5 111 #define MAX_ADDRESS_CYC_NFCV2 7 112 /* System control registers/bits to enable the NAND controller on some SoCs */ 113 #define GENCONF_SOC_DEVICE_MUX 0x208 114 #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) 115 #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20) 116 #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21) 117 #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25) 118 #define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27) 119 #define GENCONF_CLK_GATING_CTRL 0x220 120 #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2) 121 #define GENCONF_ND_CLK_CTRL 0x700 122 #define GENCONF_ND_CLK_CTRL_EN BIT(0) 123 124 /* NAND controller data flash control register */ 125 #define NDCR 0x00 126 #define NDCR_ALL_INT GENMASK(11, 0) 127 #define NDCR_CS1_CMDDM BIT(7) 128 #define NDCR_CS0_CMDDM BIT(8) 129 #define NDCR_RDYM BIT(11) 130 #define NDCR_ND_ARB_EN BIT(12) 131 #define NDCR_RA_START BIT(15) 132 #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16) 133 #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0) 134 #define NDCR_DWIDTH_M BIT(26) 135 #define NDCR_DWIDTH_C BIT(27) 136 #define NDCR_ND_RUN BIT(28) 137 #define NDCR_DMA_EN BIT(29) 138 #define NDCR_ECC_EN BIT(30) 139 #define NDCR_SPARE_EN BIT(31) 140 #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \ 141 NDCR_DWIDTH_M | NDCR_DWIDTH_C)) 142 143 /* NAND interface timing parameter 0 register */ 144 #define NDTR0 0x04 145 #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0) 146 #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3) 147 #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3) 148 #define NDTR0_SEL_NRE_EDGE BIT(7) 149 #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8) 150 #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11) 151 #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16) 152 #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19) 153 #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22) 154 #define NDTR0_SELCNTR BIT(26) 155 #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27) 156 157 /* NAND interface timing parameter 1 register */ 158 #define NDTR1 0x0C 159 #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0) 160 #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4) 161 #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8) 162 #define NDTR1_PRESCALE BIT(14) 163 #define NDTR1_WAIT_MODE BIT(15) 164 #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16) 165 166 /* NAND controller status register */ 167 #define NDSR 0x14 168 #define NDSR_WRCMDREQ BIT(0) 169 #define NDSR_RDDREQ BIT(1) 170 #define NDSR_WRDREQ BIT(2) 171 #define NDSR_CORERR BIT(3) 172 #define NDSR_UNCERR BIT(4) 173 #define NDSR_CMDD(cs) BIT(8 - cs) 174 #define NDSR_RDY(rb) BIT(11 + rb) 175 #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F) 176 177 /* NAND ECC control register */ 178 #define NDECCCTRL 0x28 179 #define NDECCCTRL_BCH_EN BIT(0) 180 181 /* NAND controller data buffer register */ 182 #define NDDB 0x40 183 184 /* NAND controller command buffer 0 register */ 185 #define NDCB0 0x48 186 #define NDCB0_CMD1(x) ((x & 0xFF) << 0) 187 #define NDCB0_CMD2(x) ((x & 0xFF) << 8) 188 #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16) 189 #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7) 190 #define NDCB0_DBC BIT(19) 191 #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21) 192 #define NDCB0_CSEL BIT(24) 193 #define NDCB0_RDY_BYP BIT(27) 194 #define NDCB0_LEN_OVRD BIT(28) 195 #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29) 196 197 /* NAND controller command buffer 1 register */ 198 #define NDCB1 0x4C 199 #define NDCB1_COLS(x) ((x & 0xFFFF) << 0) 200 #define NDCB1_ADDRS_PAGE(x) (x << 16) 201 202 /* NAND controller command buffer 2 register */ 203 #define NDCB2 0x50 204 #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0) 205 #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0) 206 207 /* NAND controller command buffer 3 register */ 208 #define NDCB3 0x54 209 #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16) 210 #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24) 211 212 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */ 213 #define TYPE_READ 0 214 #define TYPE_WRITE 1 215 #define TYPE_ERASE 2 216 #define TYPE_READ_ID 3 217 #define TYPE_STATUS 4 218 #define TYPE_RESET 5 219 #define TYPE_NAKED_CMD 6 220 #define TYPE_NAKED_ADDR 7 221 #define TYPE_MASK 7 222 #define XTYPE_MONOLITHIC_RW 0 223 #define XTYPE_LAST_NAKED_RW 1 224 #define XTYPE_FINAL_COMMAND 3 225 #define XTYPE_READ 4 226 #define XTYPE_WRITE_DISPATCH 4 227 #define XTYPE_NAKED_RW 5 228 #define XTYPE_COMMAND_DISPATCH 6 229 #define XTYPE_MASK 7 230 231 /** 232 * struct marvell_hw_ecc_layout - layout of Marvell ECC 233 * 234 * Marvell ECC engine works differently than the others, in order to limit the 235 * size of the IP, hardware engineers chose to set a fixed strength at 16 bits 236 * per subpage, and depending on a the desired strength needed by the NAND chip, 237 * a particular layout mixing data/spare/ecc is defined, with a possible last 238 * chunk smaller that the others. 239 * 240 * @writesize: Full page size on which the layout applies 241 * @chunk: Desired ECC chunk size on which the layout applies 242 * @strength: Desired ECC strength (per chunk size bytes) on which the 243 * layout applies 244 * @nchunks: Total number of chunks 245 * @full_chunk_cnt: Number of full-sized chunks, which is the number of 246 * repetitions of the pattern: 247 * (data_bytes + spare_bytes + ecc_bytes). 248 * @data_bytes: Number of data bytes per chunk 249 * @spare_bytes: Number of spare bytes per chunk 250 * @ecc_bytes: Number of ecc bytes per chunk 251 * @last_data_bytes: Number of data bytes in the last chunk 252 * @last_spare_bytes: Number of spare bytes in the last chunk 253 * @last_ecc_bytes: Number of ecc bytes in the last chunk 254 */ 255 struct marvell_hw_ecc_layout { 256 /* Constraints */ 257 int writesize; 258 int chunk; 259 int strength; 260 /* Corresponding layout */ 261 int nchunks; 262 int full_chunk_cnt; 263 int data_bytes; 264 int spare_bytes; 265 int ecc_bytes; 266 int last_data_bytes; 267 int last_spare_bytes; 268 int last_ecc_bytes; 269 }; 270 271 #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \ 272 { \ 273 .writesize = ws, \ 274 .chunk = dc, \ 275 .strength = ds, \ 276 .nchunks = nc, \ 277 .full_chunk_cnt = fcc, \ 278 .data_bytes = db, \ 279 .spare_bytes = sb, \ 280 .ecc_bytes = eb, \ 281 .last_data_bytes = ldb, \ 282 .last_spare_bytes = lsb, \ 283 .last_ecc_bytes = leb, \ 284 } 285 286 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */ 287 static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = { 288 MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0), 289 MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0), 290 MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0), 291 MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30), 292 MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,64, 30), 293 MARVELL_LAYOUT( 2048, 512, 12, 3, 2, 704, 0, 30,640, 0, 30), 294 MARVELL_LAYOUT( 2048, 512, 16, 5, 4, 512, 0, 30, 0, 32, 30), 295 MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0), 296 MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30), 297 MARVELL_LAYOUT( 4096, 512, 12, 6, 5, 704, 0, 30,576, 32, 30), 298 MARVELL_LAYOUT( 4096, 512, 16, 9, 8, 512, 0, 30, 0, 32, 30), 299 MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0), 300 MARVELL_LAYOUT( 8192, 512, 8, 9, 8, 1024, 0, 30, 0, 160, 30), 301 MARVELL_LAYOUT( 8192, 512, 12, 12, 11, 704, 0, 30,448, 64, 30), 302 MARVELL_LAYOUT( 8192, 512, 16, 17, 16, 512, 0, 30, 0, 32, 30), 303 }; 304 305 /** 306 * struct marvell_nand_chip_sel - CS line description 307 * 308 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection 309 * is made by a field in NDCB0 register, and in another field in NDCB2 register. 310 * The datasheet describes the logic with an error: ADDR5 field is once 311 * declared at the beginning of NDCB2, and another time at its end. Because the 312 * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical 313 * to use the last bit of this field instead of the first ones. 314 * 315 * @cs: Wanted CE lane. 316 * @ndcb0_csel: Value of the NDCB0 register with or without the flag 317 * selecting the wanted CE lane. This is set once when 318 * the Device Tree is probed. 319 * @rb: Ready/Busy pin for the flash chip 320 */ 321 struct marvell_nand_chip_sel { 322 unsigned int cs; 323 u32 ndcb0_csel; 324 unsigned int rb; 325 }; 326 327 /** 328 * struct marvell_nand_chip - stores NAND chip device related information 329 * 330 * @chip: Base NAND chip structure 331 * @node: Used to store NAND chips into a list 332 * @layout: NAND layout when using hardware ECC 333 * @ndcr: Controller register value for this NAND chip 334 * @ndtr0: Timing registers 0 value for this NAND chip 335 * @ndtr1: Timing registers 1 value for this NAND chip 336 * @addr_cyc: Amount of cycles needed to pass column address 337 * @selected_die: Current active CS 338 * @nsels: Number of CS lines required by the NAND chip 339 * @sels: Array of CS lines descriptions 340 */ 341 struct marvell_nand_chip { 342 struct nand_chip chip; 343 struct list_head node; 344 const struct marvell_hw_ecc_layout *layout; 345 u32 ndcr; 346 u32 ndtr0; 347 u32 ndtr1; 348 int addr_cyc; 349 int selected_die; 350 unsigned int nsels; 351 struct marvell_nand_chip_sel sels[]; 352 }; 353 354 static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip) 355 { 356 return container_of(chip, struct marvell_nand_chip, chip); 357 } 358 359 static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip 360 *nand) 361 { 362 return &nand->sels[nand->selected_die]; 363 } 364 365 /** 366 * struct marvell_nfc_caps - NAND controller capabilities for distinction 367 * between compatible strings 368 * 369 * @max_cs_nb: Number of Chip Select lines available 370 * @max_rb_nb: Number of Ready/Busy lines available 371 * @need_system_controller: Indicates if the SoC needs to have access to the 372 * system controller (ie. to enable the NAND controller) 373 * @legacy_of_bindings: Indicates if DT parsing must be done using the old 374 * fashion way 375 * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie. 376 * BCH error detection and correction algorithm, 377 * NDCB3 register has been added 378 * @use_dma: Use dma for data transfers 379 */ 380 struct marvell_nfc_caps { 381 unsigned int max_cs_nb; 382 unsigned int max_rb_nb; 383 bool need_system_controller; 384 bool legacy_of_bindings; 385 bool is_nfcv2; 386 bool use_dma; 387 }; 388 389 /** 390 * struct marvell_nfc - stores Marvell NAND controller information 391 * 392 * @controller: Base controller structure 393 * @dev: Parent device (used to print error messages) 394 * @regs: NAND controller registers 395 * @core_clk: Core clock 396 * @reg_clk: Registers clock 397 * @complete: Completion object to wait for NAND controller events 398 * @assigned_cs: Bitmask describing already assigned CS lines 399 * @chips: List containing all the NAND chips attached to 400 * this NAND controller 401 * @selected_chip: Currently selected target chip 402 * @caps: NAND controller capabilities for each compatible string 403 * @use_dma: Whetner DMA is used 404 * @dma_chan: DMA channel (NFCv1 only) 405 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only) 406 */ 407 struct marvell_nfc { 408 struct nand_controller controller; 409 struct device *dev; 410 void __iomem *regs; 411 struct clk *core_clk; 412 struct clk *reg_clk; 413 struct completion complete; 414 unsigned long assigned_cs; 415 struct list_head chips; 416 struct nand_chip *selected_chip; 417 const struct marvell_nfc_caps *caps; 418 419 /* DMA (NFCv1 only) */ 420 bool use_dma; 421 struct dma_chan *dma_chan; 422 u8 *dma_buf; 423 }; 424 425 static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl) 426 { 427 return container_of(ctrl, struct marvell_nfc, controller); 428 } 429 430 /** 431 * struct marvell_nfc_timings - NAND controller timings expressed in NAND 432 * Controller clock cycles 433 * 434 * @tRP: ND_nRE pulse width 435 * @tRH: ND_nRE high duration 436 * @tWP: ND_nWE pulse time 437 * @tWH: ND_nWE high duration 438 * @tCS: Enable signal setup time 439 * @tCH: Enable signal hold time 440 * @tADL: Address to write data delay 441 * @tAR: ND_ALE low to ND_nRE low delay 442 * @tWHR: ND_nWE high to ND_nRE low for status read 443 * @tRHW: ND_nRE high duration, read to write delay 444 * @tR: ND_nWE high to ND_nRE low for read 445 */ 446 struct marvell_nfc_timings { 447 /* NDTR0 fields */ 448 unsigned int tRP; 449 unsigned int tRH; 450 unsigned int tWP; 451 unsigned int tWH; 452 unsigned int tCS; 453 unsigned int tCH; 454 unsigned int tADL; 455 /* NDTR1 fields */ 456 unsigned int tAR; 457 unsigned int tWHR; 458 unsigned int tRHW; 459 unsigned int tR; 460 }; 461 462 /** 463 * TO_CYCLES() - Derives a duration in numbers of clock cycles. 464 * 465 * @ps: Duration in pico-seconds 466 * @period_ns: Clock period in nano-seconds 467 * 468 * Convert the duration in nano-seconds, then divide by the period and 469 * return the number of clock periods. 470 */ 471 #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns)) 472 #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \ 473 period_ns)) 474 475 /** 476 * struct marvell_nfc_op - filled during the parsing of the ->exec_op() 477 * subop subset of instructions. 478 * 479 * @ndcb: Array of values written to NDCBx registers 480 * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle 481 * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin 482 * @rdy_delay_ns: Optional delay after waiting for the RB pin 483 * @data_delay_ns: Optional delay after the data xfer 484 * @data_instr_idx: Index of the data instruction in the subop 485 * @data_instr: Pointer to the data instruction in the subop 486 */ 487 struct marvell_nfc_op { 488 u32 ndcb[4]; 489 unsigned int cle_ale_delay_ns; 490 unsigned int rdy_timeout_ms; 491 unsigned int rdy_delay_ns; 492 unsigned int data_delay_ns; 493 unsigned int data_instr_idx; 494 const struct nand_op_instr *data_instr; 495 }; 496 497 /* 498 * Internal helper to conditionnally apply a delay (from the above structure, 499 * most of the time). 500 */ 501 static void cond_delay(unsigned int ns) 502 { 503 if (!ns) 504 return; 505 506 if (ns < 10000) 507 ndelay(ns); 508 else 509 udelay(DIV_ROUND_UP(ns, 1000)); 510 } 511 512 /* 513 * The controller has many flags that could generate interrupts, most of them 514 * are disabled and polling is used. For the very slow signals, using interrupts 515 * may relax the CPU charge. 516 */ 517 static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask) 518 { 519 u32 reg; 520 521 /* Writing 1 disables the interrupt */ 522 reg = readl_relaxed(nfc->regs + NDCR); 523 writel_relaxed(reg | int_mask, nfc->regs + NDCR); 524 } 525 526 static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask) 527 { 528 u32 reg; 529 530 /* Writing 0 enables the interrupt */ 531 reg = readl_relaxed(nfc->regs + NDCR); 532 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); 533 } 534 535 static u32 marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask) 536 { 537 u32 reg; 538 539 reg = readl_relaxed(nfc->regs + NDSR); 540 writel_relaxed(int_mask, nfc->regs + NDSR); 541 542 return reg & int_mask; 543 } 544 545 static void marvell_nfc_force_byte_access(struct nand_chip *chip, 546 bool force_8bit) 547 { 548 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 549 u32 ndcr; 550 551 /* 552 * Callers of this function do not verify if the NAND is using a 16-bit 553 * an 8-bit bus for normal operations, so we need to take care of that 554 * here by leaving the configuration unchanged if the NAND does not have 555 * the NAND_BUSWIDTH_16 flag set. 556 */ 557 if (!(chip->options & NAND_BUSWIDTH_16)) 558 return; 559 560 ndcr = readl_relaxed(nfc->regs + NDCR); 561 562 if (force_8bit) 563 ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C); 564 else 565 ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 566 567 writel_relaxed(ndcr, nfc->regs + NDCR); 568 } 569 570 static int marvell_nfc_wait_ndrun(struct nand_chip *chip) 571 { 572 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 573 u32 val; 574 int ret; 575 576 /* 577 * The command is being processed, wait for the ND_RUN bit to be 578 * cleared by the NFC. If not, we must clear it by hand. 579 */ 580 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, 581 (val & NDCR_ND_RUN) == 0, 582 POLL_PERIOD, POLL_TIMEOUT); 583 if (ret) { 584 dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); 585 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 586 nfc->regs + NDCR); 587 return ret; 588 } 589 590 return 0; 591 } 592 593 /* 594 * Any time a command has to be sent to the controller, the following sequence 595 * has to be followed: 596 * - call marvell_nfc_prepare_cmd() 597 * -> activate the ND_RUN bit that will kind of 'start a job' 598 * -> wait the signal indicating the NFC is waiting for a command 599 * - send the command (cmd and address cycles) 600 * - enventually send or receive the data 601 * - call marvell_nfc_end_cmd() with the corresponding flag 602 * -> wait the flag to be triggered or cancel the job with a timeout 603 * 604 * The following helpers are here to factorize the code a bit so that 605 * specialized functions responsible for executing the actual NAND 606 * operations do not have to replicate the same code blocks. 607 */ 608 static int marvell_nfc_prepare_cmd(struct nand_chip *chip) 609 { 610 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 611 u32 ndcr, val; 612 int ret; 613 614 /* Poll ND_RUN and clear NDSR before issuing any command */ 615 ret = marvell_nfc_wait_ndrun(chip); 616 if (ret) { 617 dev_err(nfc->dev, "Last operation did not succeed\n"); 618 return ret; 619 } 620 621 ndcr = readl_relaxed(nfc->regs + NDCR); 622 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); 623 624 /* Assert ND_RUN bit and wait the NFC to be ready */ 625 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); 626 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 627 val & NDSR_WRCMDREQ, 628 POLL_PERIOD, POLL_TIMEOUT); 629 if (ret) { 630 dev_err(nfc->dev, "Timeout on WRCMDRE\n"); 631 return -ETIMEDOUT; 632 } 633 634 /* Command may be written, clear WRCMDREQ status bit */ 635 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); 636 637 return 0; 638 } 639 640 static void marvell_nfc_send_cmd(struct nand_chip *chip, 641 struct marvell_nfc_op *nfc_op) 642 { 643 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 644 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 645 646 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" 647 "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n", 648 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], 649 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); 650 651 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], 652 nfc->regs + NDCB0); 653 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); 654 writel(nfc_op->ndcb[2], nfc->regs + NDCB0); 655 656 /* 657 * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7 658 * fields are used (only available on NFCv2). 659 */ 660 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || 661 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { 662 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) 663 writel(nfc_op->ndcb[3], nfc->regs + NDCB0); 664 } 665 } 666 667 static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag, 668 const char *label) 669 { 670 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 671 u32 val; 672 int ret; 673 674 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 675 val & flag, 676 POLL_PERIOD, POLL_TIMEOUT); 677 678 if (ret) { 679 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", 680 label, val); 681 if (nfc->dma_chan) 682 dmaengine_terminate_all(nfc->dma_chan); 683 return ret; 684 } 685 686 /* 687 * DMA function uses this helper to poll on CMDD bits without wanting 688 * them to be cleared. 689 */ 690 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) 691 return 0; 692 693 writel_relaxed(flag, nfc->regs + NDSR); 694 695 return 0; 696 } 697 698 static int marvell_nfc_wait_cmdd(struct nand_chip *chip) 699 { 700 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 701 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); 702 703 return marvell_nfc_end_cmd(chip, cs_flag, "CMDD"); 704 } 705 706 static int marvell_nfc_poll_status(struct marvell_nfc *nfc, u32 mask, 707 u32 expected_val, unsigned long timeout_ms) 708 { 709 unsigned long limit; 710 u32 st; 711 712 limit = jiffies + msecs_to_jiffies(timeout_ms); 713 do { 714 st = readl_relaxed(nfc->regs + NDSR); 715 if (st & NDSR_RDY(1)) 716 st |= NDSR_RDY(0); 717 718 if ((st & mask) == expected_val) 719 return 0; 720 721 cpu_relax(); 722 } while (time_after(limit, jiffies)); 723 724 return -ETIMEDOUT; 725 } 726 727 static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms) 728 { 729 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 730 struct mtd_info *mtd = nand_to_mtd(chip); 731 u32 pending; 732 int ret; 733 734 /* Timeout is expressed in ms */ 735 if (!timeout_ms) 736 timeout_ms = IRQ_TIMEOUT; 737 738 if (mtd->oops_panic_write) { 739 ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0), 740 NDSR_RDY(0), 741 timeout_ms); 742 } else { 743 init_completion(&nfc->complete); 744 745 marvell_nfc_enable_int(nfc, NDCR_RDYM); 746 ret = wait_for_completion_timeout(&nfc->complete, 747 msecs_to_jiffies(timeout_ms)); 748 marvell_nfc_disable_int(nfc, NDCR_RDYM); 749 } 750 pending = marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1)); 751 752 /* 753 * In case the interrupt was not served in the required time frame, 754 * check if the ISR was not served or if something went actually wrong. 755 */ 756 if (!ret && !pending) { 757 dev_err(nfc->dev, "Timeout waiting for RB signal\n"); 758 return -ETIMEDOUT; 759 } 760 761 return 0; 762 } 763 764 static void marvell_nfc_select_target(struct nand_chip *chip, 765 unsigned int die_nr) 766 { 767 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 768 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 769 u32 ndcr_generic; 770 771 /* 772 * Reset the NDCR register to a clean state for this particular chip, 773 * also clear ND_RUN bit. 774 */ 775 ndcr_generic = readl_relaxed(nfc->regs + NDCR) & 776 NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN; 777 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); 778 779 /* Also reset the interrupt status register */ 780 marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 781 782 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) 783 return; 784 785 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); 786 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); 787 788 nfc->selected_chip = chip; 789 marvell_nand->selected_die = die_nr; 790 } 791 792 static irqreturn_t marvell_nfc_isr(int irq, void *dev_id) 793 { 794 struct marvell_nfc *nfc = dev_id; 795 u32 st = readl_relaxed(nfc->regs + NDSR); 796 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; 797 798 /* 799 * RDY interrupt mask is one bit in NDCR while there are two status 800 * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]). 801 */ 802 if (st & NDSR_RDY(1)) 803 st |= NDSR_RDY(0); 804 805 if (!(st & ien)) 806 return IRQ_NONE; 807 808 marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT); 809 810 if (st & (NDSR_RDY(0) | NDSR_RDY(1))) 811 complete(&nfc->complete); 812 813 return IRQ_HANDLED; 814 } 815 816 /* HW ECC related functions */ 817 static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip) 818 { 819 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 820 u32 ndcr = readl_relaxed(nfc->regs + NDCR); 821 822 if (!(ndcr & NDCR_ECC_EN)) { 823 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); 824 825 /* 826 * When enabling BCH, set threshold to 0 to always know the 827 * number of corrected bitflips. 828 */ 829 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 830 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); 831 } 832 } 833 834 static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip) 835 { 836 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 837 u32 ndcr = readl_relaxed(nfc->regs + NDCR); 838 839 if (ndcr & NDCR_ECC_EN) { 840 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); 841 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 842 writel_relaxed(0, nfc->regs + NDECCCTRL); 843 } 844 } 845 846 /* DMA related helpers */ 847 static void marvell_nfc_enable_dma(struct marvell_nfc *nfc) 848 { 849 u32 reg; 850 851 reg = readl_relaxed(nfc->regs + NDCR); 852 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); 853 } 854 855 static void marvell_nfc_disable_dma(struct marvell_nfc *nfc) 856 { 857 u32 reg; 858 859 reg = readl_relaxed(nfc->regs + NDCR); 860 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); 861 } 862 863 /* Read/write PIO/DMA accessors */ 864 static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc, 865 enum dma_data_direction direction, 866 unsigned int len) 867 { 868 unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE); 869 struct dma_async_tx_descriptor *tx; 870 struct scatterlist sg; 871 dma_cookie_t cookie; 872 int ret; 873 874 marvell_nfc_enable_dma(nfc); 875 /* Prepare the DMA transfer */ 876 sg_init_one(&sg, nfc->dma_buf, dma_len); 877 ret = dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 878 if (!ret) { 879 dev_err(nfc->dev, "Could not map DMA S/G list\n"); 880 return -ENXIO; 881 } 882 883 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, 884 direction == DMA_FROM_DEVICE ? 885 DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 886 DMA_PREP_INTERRUPT); 887 if (!tx) { 888 dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); 889 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 890 return -ENXIO; 891 } 892 893 /* Do the task and wait for it to finish */ 894 cookie = dmaengine_submit(tx); 895 ret = dma_submit_error(cookie); 896 if (ret) 897 return -EIO; 898 899 dma_async_issue_pending(nfc->dma_chan); 900 ret = marvell_nfc_wait_cmdd(nfc->selected_chip); 901 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 902 marvell_nfc_disable_dma(nfc); 903 if (ret) { 904 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", 905 dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); 906 dmaengine_terminate_all(nfc->dma_chan); 907 return -ETIMEDOUT; 908 } 909 910 return 0; 911 } 912 913 static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in, 914 unsigned int len) 915 { 916 unsigned int last_len = len % FIFO_DEPTH; 917 unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 918 int i; 919 920 for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 921 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); 922 923 if (last_len) { 924 u8 tmp_buf[FIFO_DEPTH]; 925 926 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 927 memcpy(in + last_full_offset, tmp_buf, last_len); 928 } 929 930 return 0; 931 } 932 933 static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out, 934 unsigned int len) 935 { 936 unsigned int last_len = len % FIFO_DEPTH; 937 unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 938 int i; 939 940 for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 941 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); 942 943 if (last_len) { 944 u8 tmp_buf[FIFO_DEPTH]; 945 946 memcpy(tmp_buf, out + last_full_offset, last_len); 947 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 948 } 949 950 return 0; 951 } 952 953 static void marvell_nfc_check_empty_chunk(struct nand_chip *chip, 954 u8 *data, int data_len, 955 u8 *spare, int spare_len, 956 u8 *ecc, int ecc_len, 957 unsigned int *max_bitflips) 958 { 959 struct mtd_info *mtd = nand_to_mtd(chip); 960 int bf; 961 962 /* 963 * Blank pages (all 0xFF) that have not been written may be recognized 964 * as bad if bitflips occur, so whenever an uncorrectable error occurs, 965 * check if the entire page (with ECC bytes) is actually blank or not. 966 */ 967 if (!data) 968 data_len = 0; 969 if (!spare) 970 spare_len = 0; 971 if (!ecc) 972 ecc_len = 0; 973 974 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len, 975 spare, spare_len, chip->ecc.strength); 976 if (bf < 0) { 977 mtd->ecc_stats.failed++; 978 return; 979 } 980 981 /* Update the stats and max_bitflips */ 982 mtd->ecc_stats.corrected += bf; 983 *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 984 } 985 986 /* 987 * Check if a chunk is correct or not according to the hardware ECC engine. 988 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however 989 * mtd->ecc_stats.failure is not, the function will instead return a non-zero 990 * value indicating that a check on the emptyness of the subpage must be 991 * performed before actually declaring the subpage as "corrupted". 992 */ 993 static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip, 994 unsigned int *max_bitflips) 995 { 996 struct mtd_info *mtd = nand_to_mtd(chip); 997 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 998 int bf = 0; 999 u32 ndsr; 1000 1001 ndsr = readl_relaxed(nfc->regs + NDSR); 1002 1003 /* Check uncorrectable error flag */ 1004 if (ndsr & NDSR_UNCERR) { 1005 writel_relaxed(ndsr, nfc->regs + NDSR); 1006 1007 /* 1008 * Do not increment ->ecc_stats.failed now, instead, return a 1009 * non-zero value to indicate that this chunk was apparently 1010 * bad, and it should be check to see if it empty or not. If 1011 * the chunk (with ECC bytes) is not declared empty, the calling 1012 * function must increment the failure count. 1013 */ 1014 return -EBADMSG; 1015 } 1016 1017 /* Check correctable error flag */ 1018 if (ndsr & NDSR_CORERR) { 1019 writel_relaxed(ndsr, nfc->regs + NDSR); 1020 1021 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 1022 bf = NDSR_ERRCNT(ndsr); 1023 else 1024 bf = 1; 1025 } 1026 1027 /* Update the stats and max_bitflips */ 1028 mtd->ecc_stats.corrected += bf; 1029 *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 1030 1031 return 0; 1032 } 1033 1034 /* Hamming read helpers */ 1035 static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip, 1036 u8 *data_buf, u8 *oob_buf, 1037 bool raw, int page) 1038 { 1039 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 1040 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1041 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1042 struct marvell_nfc_op nfc_op = { 1043 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 1044 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 1045 NDCB0_DBC | 1046 NDCB0_CMD1(NAND_CMD_READ0) | 1047 NDCB0_CMD2(NAND_CMD_READSTART), 1048 .ndcb[1] = NDCB1_ADDRS_PAGE(page), 1049 .ndcb[2] = NDCB2_ADDR5_PAGE(page), 1050 }; 1051 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 1052 int ret; 1053 1054 /* NFCv2 needs more information about the operation being executed */ 1055 if (nfc->caps->is_nfcv2) 1056 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 1057 1058 ret = marvell_nfc_prepare_cmd(chip); 1059 if (ret) 1060 return ret; 1061 1062 marvell_nfc_send_cmd(chip, &nfc_op); 1063 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 1064 "RDDREQ while draining FIFO (data/oob)"); 1065 if (ret) 1066 return ret; 1067 1068 /* 1069 * Read the page then the OOB area. Unlike what is shown in current 1070 * documentation, spare bytes are protected by the ECC engine, and must 1071 * be at the beginning of the OOB area or running this driver on legacy 1072 * systems will prevent the discovery of the BBM/BBT. 1073 */ 1074 if (nfc->use_dma) { 1075 marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE, 1076 lt->data_bytes + oob_bytes); 1077 memcpy(data_buf, nfc->dma_buf, lt->data_bytes); 1078 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); 1079 } else { 1080 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); 1081 marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes); 1082 } 1083 1084 ret = marvell_nfc_wait_cmdd(chip); 1085 return ret; 1086 } 1087 1088 static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf, 1089 int oob_required, int page) 1090 { 1091 marvell_nfc_select_target(chip, chip->cur_cs); 1092 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, 1093 true, page); 1094 } 1095 1096 static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf, 1097 int oob_required, int page) 1098 { 1099 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1100 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 1101 int max_bitflips = 0, ret; 1102 u8 *raw_buf; 1103 1104 marvell_nfc_select_target(chip, chip->cur_cs); 1105 marvell_nfc_enable_hw_ecc(chip); 1106 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, 1107 page); 1108 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips); 1109 marvell_nfc_disable_hw_ecc(chip); 1110 1111 if (!ret) 1112 return max_bitflips; 1113 1114 /* 1115 * When ECC failures are detected, check if the full page has been 1116 * written or not. Ignore the failure if it is actually empty. 1117 */ 1118 raw_buf = kmalloc(full_sz, GFP_KERNEL); 1119 if (!raw_buf) 1120 return -ENOMEM; 1121 1122 marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf + 1123 lt->data_bytes, true, page); 1124 marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0, 1125 &max_bitflips); 1126 kfree(raw_buf); 1127 1128 return max_bitflips; 1129 } 1130 1131 /* 1132 * Spare area in Hamming layouts is not protected by the ECC engine (even if 1133 * it appears before the ECC bytes when reading), the ->read_oob_raw() function 1134 * also stands for ->read_oob(). 1135 */ 1136 static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page) 1137 { 1138 u8 *buf = nand_get_data_buf(chip); 1139 1140 marvell_nfc_select_target(chip, chip->cur_cs); 1141 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, 1142 true, page); 1143 } 1144 1145 /* Hamming write helpers */ 1146 static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip, 1147 const u8 *data_buf, 1148 const u8 *oob_buf, bool raw, 1149 int page) 1150 { 1151 const struct nand_sdr_timings *sdr = 1152 nand_get_sdr_timings(nand_get_interface_config(chip)); 1153 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 1154 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1155 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1156 struct marvell_nfc_op nfc_op = { 1157 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | 1158 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 1159 NDCB0_CMD1(NAND_CMD_SEQIN) | 1160 NDCB0_CMD2(NAND_CMD_PAGEPROG) | 1161 NDCB0_DBC, 1162 .ndcb[1] = NDCB1_ADDRS_PAGE(page), 1163 .ndcb[2] = NDCB2_ADDR5_PAGE(page), 1164 }; 1165 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 1166 int ret; 1167 1168 /* NFCv2 needs more information about the operation being executed */ 1169 if (nfc->caps->is_nfcv2) 1170 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 1171 1172 ret = marvell_nfc_prepare_cmd(chip); 1173 if (ret) 1174 return ret; 1175 1176 marvell_nfc_send_cmd(chip, &nfc_op); 1177 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 1178 "WRDREQ while loading FIFO (data)"); 1179 if (ret) 1180 return ret; 1181 1182 /* Write the page then the OOB area */ 1183 if (nfc->use_dma) { 1184 memcpy(nfc->dma_buf, data_buf, lt->data_bytes); 1185 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); 1186 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + 1187 lt->ecc_bytes + lt->spare_bytes); 1188 } else { 1189 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); 1190 marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes); 1191 } 1192 1193 ret = marvell_nfc_wait_cmdd(chip); 1194 if (ret) 1195 return ret; 1196 1197 ret = marvell_nfc_wait_op(chip, 1198 PSEC_TO_MSEC(sdr->tPROG_max)); 1199 return ret; 1200 } 1201 1202 static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip, 1203 const u8 *buf, 1204 int oob_required, int page) 1205 { 1206 marvell_nfc_select_target(chip, chip->cur_cs); 1207 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 1208 true, page); 1209 } 1210 1211 static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip, 1212 const u8 *buf, 1213 int oob_required, int page) 1214 { 1215 int ret; 1216 1217 marvell_nfc_select_target(chip, chip->cur_cs); 1218 marvell_nfc_enable_hw_ecc(chip); 1219 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 1220 false, page); 1221 marvell_nfc_disable_hw_ecc(chip); 1222 1223 return ret; 1224 } 1225 1226 /* 1227 * Spare area in Hamming layouts is not protected by the ECC engine (even if 1228 * it appears before the ECC bytes when reading), the ->write_oob_raw() function 1229 * also stands for ->write_oob(). 1230 */ 1231 static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip, 1232 int page) 1233 { 1234 struct mtd_info *mtd = nand_to_mtd(chip); 1235 u8 *buf = nand_get_data_buf(chip); 1236 1237 memset(buf, 0xFF, mtd->writesize); 1238 1239 marvell_nfc_select_target(chip, chip->cur_cs); 1240 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 1241 true, page); 1242 } 1243 1244 /* BCH read helpers */ 1245 static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf, 1246 int oob_required, int page) 1247 { 1248 struct mtd_info *mtd = nand_to_mtd(chip); 1249 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1250 u8 *oob = chip->oob_poi; 1251 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 1252 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 1253 lt->last_spare_bytes; 1254 int data_len = lt->data_bytes; 1255 int spare_len = lt->spare_bytes; 1256 int ecc_len = lt->ecc_bytes; 1257 int chunk; 1258 1259 marvell_nfc_select_target(chip, chip->cur_cs); 1260 1261 if (oob_required) 1262 memset(chip->oob_poi, 0xFF, mtd->oobsize); 1263 1264 nand_read_page_op(chip, page, 0, NULL, 0); 1265 1266 for (chunk = 0; chunk < lt->nchunks; chunk++) { 1267 /* Update last chunk length */ 1268 if (chunk >= lt->full_chunk_cnt) { 1269 data_len = lt->last_data_bytes; 1270 spare_len = lt->last_spare_bytes; 1271 ecc_len = lt->last_ecc_bytes; 1272 } 1273 1274 /* Read data bytes*/ 1275 nand_change_read_column_op(chip, chunk * chunk_size, 1276 buf + (lt->data_bytes * chunk), 1277 data_len, false); 1278 1279 /* Read spare bytes */ 1280 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), 1281 spare_len, false, false); 1282 1283 /* Read ECC bytes */ 1284 nand_read_data_op(chip, oob + ecc_offset + 1285 (ALIGN(lt->ecc_bytes, 32) * chunk), 1286 ecc_len, false, false); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk, 1293 u8 *data, unsigned int data_len, 1294 u8 *spare, unsigned int spare_len, 1295 int page) 1296 { 1297 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 1298 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1299 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1300 int i, ret; 1301 struct marvell_nfc_op nfc_op = { 1302 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 1303 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 1304 NDCB0_LEN_OVRD, 1305 .ndcb[1] = NDCB1_ADDRS_PAGE(page), 1306 .ndcb[2] = NDCB2_ADDR5_PAGE(page), 1307 .ndcb[3] = data_len + spare_len, 1308 }; 1309 1310 ret = marvell_nfc_prepare_cmd(chip); 1311 if (ret) 1312 return; 1313 1314 if (chunk == 0) 1315 nfc_op.ndcb[0] |= NDCB0_DBC | 1316 NDCB0_CMD1(NAND_CMD_READ0) | 1317 NDCB0_CMD2(NAND_CMD_READSTART); 1318 1319 /* 1320 * Trigger the monolithic read on the first chunk, then naked read on 1321 * intermediate chunks and finally a last naked read on the last chunk. 1322 */ 1323 if (chunk == 0) 1324 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 1325 else if (chunk < lt->nchunks - 1) 1326 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 1327 else 1328 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 1329 1330 marvell_nfc_send_cmd(chip, &nfc_op); 1331 1332 /* 1333 * According to the datasheet, when reading from NDDB 1334 * with BCH enabled, after each 32 bytes reads, we 1335 * have to make sure that the NDSR.RDDREQ bit is set. 1336 * 1337 * Drain the FIFO, 8 32-bit reads at a time, and skip 1338 * the polling on the last read. 1339 * 1340 * Length is a multiple of 32 bytes, hence it is a multiple of 8 too. 1341 */ 1342 for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 1343 marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 1344 "RDDREQ while draining FIFO (data)"); 1345 marvell_nfc_xfer_data_in_pio(nfc, data, 1346 FIFO_DEPTH * BCH_SEQ_READS); 1347 data += FIFO_DEPTH * BCH_SEQ_READS; 1348 } 1349 1350 for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 1351 marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 1352 "RDDREQ while draining FIFO (OOB)"); 1353 marvell_nfc_xfer_data_in_pio(nfc, spare, 1354 FIFO_DEPTH * BCH_SEQ_READS); 1355 spare += FIFO_DEPTH * BCH_SEQ_READS; 1356 } 1357 } 1358 1359 static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip, 1360 u8 *buf, int oob_required, 1361 int page) 1362 { 1363 struct mtd_info *mtd = nand_to_mtd(chip); 1364 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1365 int data_len = lt->data_bytes, spare_len = lt->spare_bytes; 1366 u8 *data = buf, *spare = chip->oob_poi; 1367 int max_bitflips = 0; 1368 u32 failure_mask = 0; 1369 int chunk, ret; 1370 1371 marvell_nfc_select_target(chip, chip->cur_cs); 1372 1373 /* 1374 * With BCH, OOB is not fully used (and thus not read entirely), not 1375 * expected bytes could show up at the end of the OOB buffer if not 1376 * explicitly erased. 1377 */ 1378 if (oob_required) 1379 memset(chip->oob_poi, 0xFF, mtd->oobsize); 1380 1381 marvell_nfc_enable_hw_ecc(chip); 1382 1383 for (chunk = 0; chunk < lt->nchunks; chunk++) { 1384 /* Update length for the last chunk */ 1385 if (chunk >= lt->full_chunk_cnt) { 1386 data_len = lt->last_data_bytes; 1387 spare_len = lt->last_spare_bytes; 1388 } 1389 1390 /* Read the chunk and detect number of bitflips */ 1391 marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len, 1392 spare, spare_len, page); 1393 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips); 1394 if (ret) 1395 failure_mask |= BIT(chunk); 1396 1397 data += data_len; 1398 spare += spare_len; 1399 } 1400 1401 marvell_nfc_disable_hw_ecc(chip); 1402 1403 if (!failure_mask) 1404 return max_bitflips; 1405 1406 /* 1407 * Please note that dumping the ECC bytes during a normal read with OOB 1408 * area would add a significant overhead as ECC bytes are "consumed" by 1409 * the controller in normal mode and must be re-read in raw mode. To 1410 * avoid dropping the performances, we prefer not to include them. The 1411 * user should re-read the page in raw mode if ECC bytes are required. 1412 */ 1413 1414 /* 1415 * In case there is any subpage read error, we usually re-read only ECC 1416 * bytes in raw mode and check if the whole page is empty. In this case, 1417 * it is normal that the ECC check failed and we just ignore the error. 1418 * 1419 * However, it has been empirically observed that for some layouts (e.g 1420 * 2k page, 8b strength per 512B chunk), the controller tries to correct 1421 * bits and may create itself bitflips in the erased area. To overcome 1422 * this strange behavior, the whole page is re-read in raw mode, not 1423 * only the ECC bytes. 1424 */ 1425 for (chunk = 0; chunk < lt->nchunks; chunk++) { 1426 int data_off_in_page, spare_off_in_page, ecc_off_in_page; 1427 int data_off, spare_off, ecc_off; 1428 int data_len, spare_len, ecc_len; 1429 1430 /* No failure reported for this chunk, move to the next one */ 1431 if (!(failure_mask & BIT(chunk))) 1432 continue; 1433 1434 data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + 1435 lt->ecc_bytes); 1436 spare_off_in_page = data_off_in_page + 1437 (chunk < lt->full_chunk_cnt ? lt->data_bytes : 1438 lt->last_data_bytes); 1439 ecc_off_in_page = spare_off_in_page + 1440 (chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1441 lt->last_spare_bytes); 1442 1443 data_off = chunk * lt->data_bytes; 1444 spare_off = chunk * lt->spare_bytes; 1445 ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + 1446 lt->last_spare_bytes + 1447 (chunk * (lt->ecc_bytes + 2)); 1448 1449 data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : 1450 lt->last_data_bytes; 1451 spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1452 lt->last_spare_bytes; 1453 ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : 1454 lt->last_ecc_bytes; 1455 1456 /* 1457 * Only re-read the ECC bytes, unless we are using the 2k/8b 1458 * layout which is buggy in the sense that the ECC engine will 1459 * try to correct data bytes anyway, creating bitflips. In this 1460 * case, re-read the entire page. 1461 */ 1462 if (lt->writesize == 2048 && lt->strength == 8) { 1463 nand_change_read_column_op(chip, data_off_in_page, 1464 buf + data_off, data_len, 1465 false); 1466 nand_change_read_column_op(chip, spare_off_in_page, 1467 chip->oob_poi + spare_off, spare_len, 1468 false); 1469 } 1470 1471 nand_change_read_column_op(chip, ecc_off_in_page, 1472 chip->oob_poi + ecc_off, ecc_len, 1473 false); 1474 1475 /* Check the entire chunk (data + spare + ecc) for emptyness */ 1476 marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len, 1477 chip->oob_poi + spare_off, spare_len, 1478 chip->oob_poi + ecc_off, ecc_len, 1479 &max_bitflips); 1480 } 1481 1482 return max_bitflips; 1483 } 1484 1485 static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page) 1486 { 1487 u8 *buf = nand_get_data_buf(chip); 1488 1489 return chip->ecc.read_page_raw(chip, buf, true, page); 1490 } 1491 1492 static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page) 1493 { 1494 u8 *buf = nand_get_data_buf(chip); 1495 1496 return chip->ecc.read_page(chip, buf, true, page); 1497 } 1498 1499 /* BCH write helpers */ 1500 static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip, 1501 const u8 *buf, 1502 int oob_required, int page) 1503 { 1504 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1505 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 1506 int data_len = lt->data_bytes; 1507 int spare_len = lt->spare_bytes; 1508 int ecc_len = lt->ecc_bytes; 1509 int spare_offset = 0; 1510 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 1511 lt->last_spare_bytes; 1512 int chunk; 1513 1514 marvell_nfc_select_target(chip, chip->cur_cs); 1515 1516 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 1517 1518 for (chunk = 0; chunk < lt->nchunks; chunk++) { 1519 if (chunk >= lt->full_chunk_cnt) { 1520 data_len = lt->last_data_bytes; 1521 spare_len = lt->last_spare_bytes; 1522 ecc_len = lt->last_ecc_bytes; 1523 } 1524 1525 /* Point to the column of the next chunk */ 1526 nand_change_write_column_op(chip, chunk * full_chunk_size, 1527 NULL, 0, false); 1528 1529 /* Write the data */ 1530 nand_write_data_op(chip, buf + (chunk * lt->data_bytes), 1531 data_len, false); 1532 1533 if (!oob_required) 1534 continue; 1535 1536 /* Write the spare bytes */ 1537 if (spare_len) 1538 nand_write_data_op(chip, chip->oob_poi + spare_offset, 1539 spare_len, false); 1540 1541 /* Write the ECC bytes */ 1542 if (ecc_len) 1543 nand_write_data_op(chip, chip->oob_poi + ecc_offset, 1544 ecc_len, false); 1545 1546 spare_offset += spare_len; 1547 ecc_offset += ALIGN(ecc_len, 32); 1548 } 1549 1550 return nand_prog_page_end_op(chip); 1551 } 1552 1553 static int 1554 marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, 1555 const u8 *data, unsigned int data_len, 1556 const u8 *spare, unsigned int spare_len, 1557 int page) 1558 { 1559 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 1560 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1561 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1562 u32 xtype; 1563 int ret; 1564 struct marvell_nfc_op nfc_op = { 1565 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD, 1566 .ndcb[3] = data_len + spare_len, 1567 }; 1568 1569 /* 1570 * First operation dispatches the CMD_SEQIN command, issue the address 1571 * cycles and asks for the first chunk of data. 1572 * All operations in the middle (if any) will issue a naked write and 1573 * also ask for data. 1574 * Last operation (if any) asks for the last chunk of data through a 1575 * last naked write. 1576 */ 1577 if (chunk == 0) { 1578 if (lt->nchunks == 1) 1579 xtype = XTYPE_MONOLITHIC_RW; 1580 else 1581 xtype = XTYPE_WRITE_DISPATCH; 1582 1583 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | 1584 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 1585 NDCB0_CMD1(NAND_CMD_SEQIN); 1586 nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page); 1587 nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page); 1588 } else if (chunk < lt->nchunks - 1) { 1589 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 1590 } else { 1591 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 1592 } 1593 1594 /* Always dispatch the PAGEPROG command on the last chunk */ 1595 if (chunk == lt->nchunks - 1) 1596 nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC; 1597 1598 ret = marvell_nfc_prepare_cmd(chip); 1599 if (ret) 1600 return ret; 1601 1602 marvell_nfc_send_cmd(chip, &nfc_op); 1603 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 1604 "WRDREQ while loading FIFO (data)"); 1605 if (ret) 1606 return ret; 1607 1608 /* Transfer the contents */ 1609 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); 1610 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); 1611 1612 return 0; 1613 } 1614 1615 static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip, 1616 const u8 *buf, 1617 int oob_required, int page) 1618 { 1619 const struct nand_sdr_timings *sdr = 1620 nand_get_sdr_timings(nand_get_interface_config(chip)); 1621 struct mtd_info *mtd = nand_to_mtd(chip); 1622 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1623 const u8 *data = buf; 1624 const u8 *spare = chip->oob_poi; 1625 int data_len = lt->data_bytes; 1626 int spare_len = lt->spare_bytes; 1627 int chunk, ret; 1628 1629 marvell_nfc_select_target(chip, chip->cur_cs); 1630 1631 /* Spare data will be written anyway, so clear it to avoid garbage */ 1632 if (!oob_required) 1633 memset(chip->oob_poi, 0xFF, mtd->oobsize); 1634 1635 marvell_nfc_enable_hw_ecc(chip); 1636 1637 for (chunk = 0; chunk < lt->nchunks; chunk++) { 1638 if (chunk >= lt->full_chunk_cnt) { 1639 data_len = lt->last_data_bytes; 1640 spare_len = lt->last_spare_bytes; 1641 } 1642 1643 marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len, 1644 spare, spare_len, page); 1645 data += data_len; 1646 spare += spare_len; 1647 1648 /* 1649 * Waiting only for CMDD or PAGED is not enough, ECC are 1650 * partially written. No flag is set once the operation is 1651 * really finished but the ND_RUN bit is cleared, so wait for it 1652 * before stepping into the next command. 1653 */ 1654 marvell_nfc_wait_ndrun(chip); 1655 } 1656 1657 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max)); 1658 1659 marvell_nfc_disable_hw_ecc(chip); 1660 1661 if (ret) 1662 return ret; 1663 1664 return 0; 1665 } 1666 1667 static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip, 1668 int page) 1669 { 1670 struct mtd_info *mtd = nand_to_mtd(chip); 1671 u8 *buf = nand_get_data_buf(chip); 1672 1673 memset(buf, 0xFF, mtd->writesize); 1674 1675 return chip->ecc.write_page_raw(chip, buf, true, page); 1676 } 1677 1678 static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page) 1679 { 1680 struct mtd_info *mtd = nand_to_mtd(chip); 1681 u8 *buf = nand_get_data_buf(chip); 1682 1683 memset(buf, 0xFF, mtd->writesize); 1684 1685 return chip->ecc.write_page(chip, buf, true, page); 1686 } 1687 1688 /* NAND framework ->exec_op() hooks and related helpers */ 1689 static void marvell_nfc_parse_instructions(struct nand_chip *chip, 1690 const struct nand_subop *subop, 1691 struct marvell_nfc_op *nfc_op) 1692 { 1693 const struct nand_op_instr *instr = NULL; 1694 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1695 bool first_cmd = true; 1696 unsigned int op_id; 1697 int i; 1698 1699 /* Reset the input structure as most of its fields will be OR'ed */ 1700 memset(nfc_op, 0, sizeof(struct marvell_nfc_op)); 1701 1702 for (op_id = 0; op_id < subop->ninstrs; op_id++) { 1703 unsigned int offset, naddrs; 1704 const u8 *addrs; 1705 int len; 1706 1707 instr = &subop->instrs[op_id]; 1708 1709 switch (instr->type) { 1710 case NAND_OP_CMD_INSTR: 1711 if (first_cmd) 1712 nfc_op->ndcb[0] |= 1713 NDCB0_CMD1(instr->ctx.cmd.opcode); 1714 else 1715 nfc_op->ndcb[0] |= 1716 NDCB0_CMD2(instr->ctx.cmd.opcode) | 1717 NDCB0_DBC; 1718 1719 nfc_op->cle_ale_delay_ns = instr->delay_ns; 1720 first_cmd = false; 1721 break; 1722 1723 case NAND_OP_ADDR_INSTR: 1724 offset = nand_subop_get_addr_start_off(subop, op_id); 1725 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 1726 addrs = &instr->ctx.addr.addrs[offset]; 1727 1728 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); 1729 1730 for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) 1731 nfc_op->ndcb[1] |= addrs[i] << (8 * i); 1732 1733 if (naddrs >= 5) 1734 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); 1735 if (naddrs >= 6) 1736 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); 1737 if (naddrs == 7) 1738 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); 1739 1740 nfc_op->cle_ale_delay_ns = instr->delay_ns; 1741 break; 1742 1743 case NAND_OP_DATA_IN_INSTR: 1744 nfc_op->data_instr = instr; 1745 nfc_op->data_instr_idx = op_id; 1746 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); 1747 if (nfc->caps->is_nfcv2) { 1748 nfc_op->ndcb[0] |= 1749 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 1750 NDCB0_LEN_OVRD; 1751 len = nand_subop_get_data_len(subop, op_id); 1752 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 1753 } 1754 nfc_op->data_delay_ns = instr->delay_ns; 1755 break; 1756 1757 case NAND_OP_DATA_OUT_INSTR: 1758 nfc_op->data_instr = instr; 1759 nfc_op->data_instr_idx = op_id; 1760 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); 1761 if (nfc->caps->is_nfcv2) { 1762 nfc_op->ndcb[0] |= 1763 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 1764 NDCB0_LEN_OVRD; 1765 len = nand_subop_get_data_len(subop, op_id); 1766 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 1767 } 1768 nfc_op->data_delay_ns = instr->delay_ns; 1769 break; 1770 1771 case NAND_OP_WAITRDY_INSTR: 1772 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; 1773 nfc_op->rdy_delay_ns = instr->delay_ns; 1774 break; 1775 } 1776 } 1777 } 1778 1779 static int marvell_nfc_xfer_data_pio(struct nand_chip *chip, 1780 const struct nand_subop *subop, 1781 struct marvell_nfc_op *nfc_op) 1782 { 1783 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1784 const struct nand_op_instr *instr = nfc_op->data_instr; 1785 unsigned int op_id = nfc_op->data_instr_idx; 1786 unsigned int len = nand_subop_get_data_len(subop, op_id); 1787 unsigned int offset = nand_subop_get_data_start_off(subop, op_id); 1788 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); 1789 int ret; 1790 1791 if (instr->ctx.data.force_8bit) 1792 marvell_nfc_force_byte_access(chip, true); 1793 1794 if (reading) { 1795 u8 *in = instr->ctx.data.buf.in + offset; 1796 1797 ret = marvell_nfc_xfer_data_in_pio(nfc, in, len); 1798 } else { 1799 const u8 *out = instr->ctx.data.buf.out + offset; 1800 1801 ret = marvell_nfc_xfer_data_out_pio(nfc, out, len); 1802 } 1803 1804 if (instr->ctx.data.force_8bit) 1805 marvell_nfc_force_byte_access(chip, false); 1806 1807 return ret; 1808 } 1809 1810 static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip, 1811 const struct nand_subop *subop) 1812 { 1813 struct marvell_nfc_op nfc_op; 1814 bool reading; 1815 int ret; 1816 1817 marvell_nfc_parse_instructions(chip, subop, &nfc_op); 1818 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); 1819 1820 ret = marvell_nfc_prepare_cmd(chip); 1821 if (ret) 1822 return ret; 1823 1824 marvell_nfc_send_cmd(chip, &nfc_op); 1825 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 1826 "RDDREQ/WRDREQ while draining raw data"); 1827 if (ret) 1828 return ret; 1829 1830 cond_delay(nfc_op.cle_ale_delay_ns); 1831 1832 if (reading) { 1833 if (nfc_op.rdy_timeout_ms) { 1834 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 1835 if (ret) 1836 return ret; 1837 } 1838 1839 cond_delay(nfc_op.rdy_delay_ns); 1840 } 1841 1842 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 1843 ret = marvell_nfc_wait_cmdd(chip); 1844 if (ret) 1845 return ret; 1846 1847 cond_delay(nfc_op.data_delay_ns); 1848 1849 if (!reading) { 1850 if (nfc_op.rdy_timeout_ms) { 1851 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 1852 if (ret) 1853 return ret; 1854 } 1855 1856 cond_delay(nfc_op.rdy_delay_ns); 1857 } 1858 1859 /* 1860 * NDCR ND_RUN bit should be cleared automatically at the end of each 1861 * operation but experience shows that the behavior is buggy when it 1862 * comes to writes (with LEN_OVRD). Clear it by hand in this case. 1863 */ 1864 if (!reading) { 1865 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1866 1867 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 1868 nfc->regs + NDCR); 1869 } 1870 1871 return 0; 1872 } 1873 1874 static int marvell_nfc_naked_access_exec(struct nand_chip *chip, 1875 const struct nand_subop *subop) 1876 { 1877 struct marvell_nfc_op nfc_op; 1878 int ret; 1879 1880 marvell_nfc_parse_instructions(chip, subop, &nfc_op); 1881 1882 /* 1883 * Naked access are different in that they need to be flagged as naked 1884 * by the controller. Reset the controller registers fields that inform 1885 * on the type and refill them according to the ongoing operation. 1886 */ 1887 nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) | 1888 NDCB0_CMD_XTYPE(XTYPE_MASK)); 1889 switch (subop->instrs[0].type) { 1890 case NAND_OP_CMD_INSTR: 1891 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD); 1892 break; 1893 case NAND_OP_ADDR_INSTR: 1894 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR); 1895 break; 1896 case NAND_OP_DATA_IN_INSTR: 1897 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) | 1898 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 1899 break; 1900 case NAND_OP_DATA_OUT_INSTR: 1901 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) | 1902 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 1903 break; 1904 default: 1905 /* This should never happen */ 1906 break; 1907 } 1908 1909 ret = marvell_nfc_prepare_cmd(chip); 1910 if (ret) 1911 return ret; 1912 1913 marvell_nfc_send_cmd(chip, &nfc_op); 1914 1915 if (!nfc_op.data_instr) { 1916 ret = marvell_nfc_wait_cmdd(chip); 1917 cond_delay(nfc_op.cle_ale_delay_ns); 1918 return ret; 1919 } 1920 1921 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 1922 "RDDREQ/WRDREQ while draining raw data"); 1923 if (ret) 1924 return ret; 1925 1926 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 1927 ret = marvell_nfc_wait_cmdd(chip); 1928 if (ret) 1929 return ret; 1930 1931 /* 1932 * NDCR ND_RUN bit should be cleared automatically at the end of each 1933 * operation but experience shows that the behavior is buggy when it 1934 * comes to writes (with LEN_OVRD). Clear it by hand in this case. 1935 */ 1936 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { 1937 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 1938 1939 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 1940 nfc->regs + NDCR); 1941 } 1942 1943 return 0; 1944 } 1945 1946 static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip, 1947 const struct nand_subop *subop) 1948 { 1949 struct marvell_nfc_op nfc_op; 1950 int ret; 1951 1952 marvell_nfc_parse_instructions(chip, subop, &nfc_op); 1953 1954 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 1955 cond_delay(nfc_op.rdy_delay_ns); 1956 1957 return ret; 1958 } 1959 1960 static int marvell_nfc_read_id_type_exec(struct nand_chip *chip, 1961 const struct nand_subop *subop) 1962 { 1963 struct marvell_nfc_op nfc_op; 1964 int ret; 1965 1966 marvell_nfc_parse_instructions(chip, subop, &nfc_op); 1967 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 1968 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID); 1969 1970 ret = marvell_nfc_prepare_cmd(chip); 1971 if (ret) 1972 return ret; 1973 1974 marvell_nfc_send_cmd(chip, &nfc_op); 1975 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 1976 "RDDREQ while reading ID"); 1977 if (ret) 1978 return ret; 1979 1980 cond_delay(nfc_op.cle_ale_delay_ns); 1981 1982 if (nfc_op.rdy_timeout_ms) { 1983 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 1984 if (ret) 1985 return ret; 1986 } 1987 1988 cond_delay(nfc_op.rdy_delay_ns); 1989 1990 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 1991 ret = marvell_nfc_wait_cmdd(chip); 1992 if (ret) 1993 return ret; 1994 1995 cond_delay(nfc_op.data_delay_ns); 1996 1997 return 0; 1998 } 1999 2000 static int marvell_nfc_read_status_exec(struct nand_chip *chip, 2001 const struct nand_subop *subop) 2002 { 2003 struct marvell_nfc_op nfc_op; 2004 int ret; 2005 2006 marvell_nfc_parse_instructions(chip, subop, &nfc_op); 2007 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 2008 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS); 2009 2010 ret = marvell_nfc_prepare_cmd(chip); 2011 if (ret) 2012 return ret; 2013 2014 marvell_nfc_send_cmd(chip, &nfc_op); 2015 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 2016 "RDDREQ while reading status"); 2017 if (ret) 2018 return ret; 2019 2020 cond_delay(nfc_op.cle_ale_delay_ns); 2021 2022 if (nfc_op.rdy_timeout_ms) { 2023 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 2024 if (ret) 2025 return ret; 2026 } 2027 2028 cond_delay(nfc_op.rdy_delay_ns); 2029 2030 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 2031 ret = marvell_nfc_wait_cmdd(chip); 2032 if (ret) 2033 return ret; 2034 2035 cond_delay(nfc_op.data_delay_ns); 2036 2037 return 0; 2038 } 2039 2040 static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip, 2041 const struct nand_subop *subop) 2042 { 2043 struct marvell_nfc_op nfc_op; 2044 int ret; 2045 2046 marvell_nfc_parse_instructions(chip, subop, &nfc_op); 2047 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET); 2048 2049 ret = marvell_nfc_prepare_cmd(chip); 2050 if (ret) 2051 return ret; 2052 2053 marvell_nfc_send_cmd(chip, &nfc_op); 2054 ret = marvell_nfc_wait_cmdd(chip); 2055 if (ret) 2056 return ret; 2057 2058 cond_delay(nfc_op.cle_ale_delay_ns); 2059 2060 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 2061 if (ret) 2062 return ret; 2063 2064 cond_delay(nfc_op.rdy_delay_ns); 2065 2066 return 0; 2067 } 2068 2069 static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip, 2070 const struct nand_subop *subop) 2071 { 2072 struct marvell_nfc_op nfc_op; 2073 int ret; 2074 2075 marvell_nfc_parse_instructions(chip, subop, &nfc_op); 2076 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE); 2077 2078 ret = marvell_nfc_prepare_cmd(chip); 2079 if (ret) 2080 return ret; 2081 2082 marvell_nfc_send_cmd(chip, &nfc_op); 2083 ret = marvell_nfc_wait_cmdd(chip); 2084 if (ret) 2085 return ret; 2086 2087 cond_delay(nfc_op.cle_ale_delay_ns); 2088 2089 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 2090 if (ret) 2091 return ret; 2092 2093 cond_delay(nfc_op.rdy_delay_ns); 2094 2095 return 0; 2096 } 2097 2098 static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER( 2099 /* Monolithic reads/writes */ 2100 NAND_OP_PARSER_PATTERN( 2101 marvell_nfc_monolithic_access_exec, 2102 NAND_OP_PARSER_PAT_CMD_ELEM(false), 2103 NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2), 2104 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2105 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 2106 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 2107 NAND_OP_PARSER_PATTERN( 2108 marvell_nfc_monolithic_access_exec, 2109 NAND_OP_PARSER_PAT_CMD_ELEM(false), 2110 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2), 2111 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE), 2112 NAND_OP_PARSER_PAT_CMD_ELEM(true), 2113 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 2114 /* Naked commands */ 2115 NAND_OP_PARSER_PATTERN( 2116 marvell_nfc_naked_access_exec, 2117 NAND_OP_PARSER_PAT_CMD_ELEM(false)), 2118 NAND_OP_PARSER_PATTERN( 2119 marvell_nfc_naked_access_exec, 2120 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)), 2121 NAND_OP_PARSER_PATTERN( 2122 marvell_nfc_naked_access_exec, 2123 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 2124 NAND_OP_PARSER_PATTERN( 2125 marvell_nfc_naked_access_exec, 2126 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)), 2127 NAND_OP_PARSER_PATTERN( 2128 marvell_nfc_naked_waitrdy_exec, 2129 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 2130 ); 2131 2132 static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER( 2133 /* Naked commands not supported, use a function for each pattern */ 2134 NAND_OP_PARSER_PATTERN( 2135 marvell_nfc_read_id_type_exec, 2136 NAND_OP_PARSER_PAT_CMD_ELEM(false), 2137 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 2138 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), 2139 NAND_OP_PARSER_PATTERN( 2140 marvell_nfc_erase_cmd_type_exec, 2141 NAND_OP_PARSER_PAT_CMD_ELEM(false), 2142 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 2143 NAND_OP_PARSER_PAT_CMD_ELEM(false), 2144 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 2145 NAND_OP_PARSER_PATTERN( 2146 marvell_nfc_read_status_exec, 2147 NAND_OP_PARSER_PAT_CMD_ELEM(false), 2148 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), 2149 NAND_OP_PARSER_PATTERN( 2150 marvell_nfc_reset_cmd_type_exec, 2151 NAND_OP_PARSER_PAT_CMD_ELEM(false), 2152 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 2153 NAND_OP_PARSER_PATTERN( 2154 marvell_nfc_naked_waitrdy_exec, 2155 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 2156 ); 2157 2158 static int marvell_nfc_exec_op(struct nand_chip *chip, 2159 const struct nand_operation *op, 2160 bool check_only) 2161 { 2162 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2163 2164 if (!check_only) 2165 marvell_nfc_select_target(chip, op->cs); 2166 2167 if (nfc->caps->is_nfcv2) 2168 return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser, 2169 op, check_only); 2170 else 2171 return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser, 2172 op, check_only); 2173 } 2174 2175 /* 2176 * Layouts were broken in old pxa3xx_nand driver, these are supposed to be 2177 * usable. 2178 */ 2179 static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section, 2180 struct mtd_oob_region *oobregion) 2181 { 2182 struct nand_chip *chip = mtd_to_nand(mtd); 2183 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 2184 2185 if (section) 2186 return -ERANGE; 2187 2188 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + 2189 lt->last_ecc_bytes; 2190 oobregion->offset = mtd->oobsize - oobregion->length; 2191 2192 return 0; 2193 } 2194 2195 static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section, 2196 struct mtd_oob_region *oobregion) 2197 { 2198 struct nand_chip *chip = mtd_to_nand(mtd); 2199 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 2200 2201 if (section) 2202 return -ERANGE; 2203 2204 /* 2205 * Bootrom looks in bytes 0 & 5 for bad blocks for the 2206 * 4KB page / 4bit BCH combination. 2207 */ 2208 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) 2209 oobregion->offset = 6; 2210 else 2211 oobregion->offset = 2; 2212 2213 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + 2214 lt->last_spare_bytes - oobregion->offset; 2215 2216 return 0; 2217 } 2218 2219 static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = { 2220 .ecc = marvell_nand_ooblayout_ecc, 2221 .free = marvell_nand_ooblayout_free, 2222 }; 2223 2224 static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd, 2225 struct nand_ecc_ctrl *ecc) 2226 { 2227 struct nand_chip *chip = mtd_to_nand(mtd); 2228 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2229 const struct marvell_hw_ecc_layout *l; 2230 int i; 2231 2232 if (!nfc->caps->is_nfcv2 && 2233 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { 2234 dev_err(nfc->dev, 2235 "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n", 2236 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); 2237 return -ENOTSUPP; 2238 } 2239 2240 to_marvell_nand(chip)->layout = NULL; 2241 for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) { 2242 l = &marvell_nfc_layouts[i]; 2243 if (mtd->writesize == l->writesize && 2244 ecc->size == l->chunk && ecc->strength == l->strength) { 2245 to_marvell_nand(chip)->layout = l; 2246 break; 2247 } 2248 } 2249 2250 if (!to_marvell_nand(chip)->layout || 2251 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { 2252 dev_err(nfc->dev, 2253 "ECC strength %d at page size %d is not supported\n", 2254 ecc->strength, mtd->writesize); 2255 return -ENOTSUPP; 2256 } 2257 2258 /* Special care for the layout 2k/8-bit/512B */ 2259 if (l->writesize == 2048 && l->strength == 8) { 2260 if (mtd->oobsize < 128) { 2261 dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n"); 2262 return -ENOTSUPP; 2263 } else { 2264 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 2265 } 2266 } 2267 2268 mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops); 2269 ecc->steps = l->nchunks; 2270 ecc->size = l->data_bytes; 2271 2272 if (ecc->strength == 1) { 2273 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2274 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; 2275 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; 2276 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; 2277 ecc->read_oob = ecc->read_oob_raw; 2278 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; 2279 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; 2280 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; 2281 ecc->write_oob = ecc->write_oob_raw; 2282 } else { 2283 chip->ecc.algo = NAND_ECC_ALGO_BCH; 2284 ecc->strength = 16; 2285 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; 2286 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; 2287 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; 2288 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; 2289 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; 2290 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; 2291 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; 2292 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; 2293 } 2294 2295 return 0; 2296 } 2297 2298 static int marvell_nand_ecc_init(struct mtd_info *mtd, 2299 struct nand_ecc_ctrl *ecc) 2300 { 2301 struct nand_chip *chip = mtd_to_nand(mtd); 2302 const struct nand_ecc_props *requirements = 2303 nanddev_get_ecc_requirements(&chip->base); 2304 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2305 int ret; 2306 2307 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2308 (!ecc->size || !ecc->strength)) { 2309 if (requirements->step_size && requirements->strength) { 2310 ecc->size = requirements->step_size; 2311 ecc->strength = requirements->strength; 2312 } else { 2313 dev_info(nfc->dev, 2314 "No minimum ECC strength, using 1b/512B\n"); 2315 ecc->size = 512; 2316 ecc->strength = 1; 2317 } 2318 } 2319 2320 switch (ecc->engine_type) { 2321 case NAND_ECC_ENGINE_TYPE_ON_HOST: 2322 ret = marvell_nand_hw_ecc_controller_init(mtd, ecc); 2323 if (ret) 2324 return ret; 2325 break; 2326 case NAND_ECC_ENGINE_TYPE_NONE: 2327 case NAND_ECC_ENGINE_TYPE_SOFT: 2328 case NAND_ECC_ENGINE_TYPE_ON_DIE: 2329 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && 2330 mtd->writesize != SZ_2K) { 2331 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", 2332 mtd->writesize); 2333 return -EINVAL; 2334 } 2335 break; 2336 default: 2337 return -EINVAL; 2338 } 2339 2340 return 0; 2341 } 2342 2343 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; 2344 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; 2345 2346 static struct nand_bbt_descr bbt_main_descr = { 2347 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 2348 NAND_BBT_2BIT | NAND_BBT_VERSION, 2349 .offs = 8, 2350 .len = 6, 2351 .veroffs = 14, 2352 .maxblocks = 8, /* Last 8 blocks in each chip */ 2353 .pattern = bbt_pattern 2354 }; 2355 2356 static struct nand_bbt_descr bbt_mirror_descr = { 2357 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 2358 NAND_BBT_2BIT | NAND_BBT_VERSION, 2359 .offs = 8, 2360 .len = 6, 2361 .veroffs = 14, 2362 .maxblocks = 8, /* Last 8 blocks in each chip */ 2363 .pattern = bbt_mirror_pattern 2364 }; 2365 2366 static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, 2367 const struct nand_interface_config *conf) 2368 { 2369 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 2370 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2371 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; 2372 const struct nand_sdr_timings *sdr; 2373 struct marvell_nfc_timings nfc_tmg; 2374 int read_delay; 2375 2376 sdr = nand_get_sdr_timings(conf); 2377 if (IS_ERR(sdr)) 2378 return PTR_ERR(sdr); 2379 2380 /* 2381 * SDR timings are given in pico-seconds while NFC timings must be 2382 * expressed in NAND controller clock cycles, which is half of the 2383 * frequency of the accessible ECC clock retrieved by clk_get_rate(). 2384 * This is not written anywhere in the datasheet but was observed 2385 * with an oscilloscope. 2386 * 2387 * NFC datasheet gives equations from which thoses calculations 2388 * are derived, they tend to be slightly more restrictives than the 2389 * given core timings and may improve the overall speed. 2390 */ 2391 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; 2392 nfc_tmg.tRH = nfc_tmg.tRP; 2393 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; 2394 nfc_tmg.tWH = nfc_tmg.tWP; 2395 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); 2396 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; 2397 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); 2398 /* 2399 * Read delay is the time of propagation from SoC pins to NFC internal 2400 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In 2401 * EDO mode, an additional delay of tRH must be taken into account so 2402 * the data is sampled on the falling edge instead of the rising edge. 2403 */ 2404 read_delay = sdr->tRC_min >= 30000 ? 2405 MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH; 2406 2407 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); 2408 /* 2409 * tWHR and tRHW are supposed to be read to write delays (and vice 2410 * versa) but in some cases, ie. when doing a change column, they must 2411 * be greater than that to be sure tCCS delay is respected. 2412 */ 2413 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), 2414 period_ns) - 2; 2415 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), 2416 period_ns); 2417 2418 /* 2419 * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays. 2420 * NFCv1: No WAIT_MODE, tR must be maximal. 2421 */ 2422 if (nfc->caps->is_nfcv2) { 2423 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); 2424 } else { 2425 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, 2426 period_ns); 2427 if (nfc_tmg.tR + 3 > nfc_tmg.tCH) 2428 nfc_tmg.tR = nfc_tmg.tCH - 3; 2429 else 2430 nfc_tmg.tR = 0; 2431 } 2432 2433 if (chipnr < 0) 2434 return 0; 2435 2436 marvell_nand->ndtr0 = 2437 NDTR0_TRP(nfc_tmg.tRP) | 2438 NDTR0_TRH(nfc_tmg.tRH) | 2439 NDTR0_ETRP(nfc_tmg.tRP) | 2440 NDTR0_TWP(nfc_tmg.tWP) | 2441 NDTR0_TWH(nfc_tmg.tWH) | 2442 NDTR0_TCS(nfc_tmg.tCS) | 2443 NDTR0_TCH(nfc_tmg.tCH); 2444 2445 marvell_nand->ndtr1 = 2446 NDTR1_TAR(nfc_tmg.tAR) | 2447 NDTR1_TWHR(nfc_tmg.tWHR) | 2448 NDTR1_TR(nfc_tmg.tR); 2449 2450 if (nfc->caps->is_nfcv2) { 2451 marvell_nand->ndtr0 |= 2452 NDTR0_RD_CNT_DEL(read_delay) | 2453 NDTR0_SELCNTR | 2454 NDTR0_TADL(nfc_tmg.tADL); 2455 2456 marvell_nand->ndtr1 |= 2457 NDTR1_TRHW(nfc_tmg.tRHW) | 2458 NDTR1_WAIT_MODE; 2459 } 2460 2461 /* 2462 * Reset nfc->selected_chip so the next command will cause the timing 2463 * registers to be updated in marvell_nfc_select_target(). 2464 */ 2465 nfc->selected_chip = NULL; 2466 2467 return 0; 2468 } 2469 2470 static int marvell_nand_attach_chip(struct nand_chip *chip) 2471 { 2472 struct mtd_info *mtd = nand_to_mtd(chip); 2473 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 2474 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2475 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); 2476 int ret; 2477 2478 if (pdata && pdata->flash_bbt) 2479 chip->bbt_options |= NAND_BBT_USE_FLASH; 2480 2481 if (chip->bbt_options & NAND_BBT_USE_FLASH) { 2482 /* 2483 * We'll use a bad block table stored in-flash and don't 2484 * allow writing the bad block marker to the flash. 2485 */ 2486 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 2487 chip->bbt_td = &bbt_main_descr; 2488 chip->bbt_md = &bbt_mirror_descr; 2489 } 2490 2491 /* Save the chip-specific fields of NDCR */ 2492 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); 2493 if (chip->options & NAND_BUSWIDTH_16) 2494 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 2495 2496 /* 2497 * On small page NANDs, only one cycle is needed to pass the 2498 * column address. 2499 */ 2500 if (mtd->writesize <= 512) { 2501 marvell_nand->addr_cyc = 1; 2502 } else { 2503 marvell_nand->addr_cyc = 2; 2504 marvell_nand->ndcr |= NDCR_RA_START; 2505 } 2506 2507 /* 2508 * Now add the number of cycles needed to pass the row 2509 * address. 2510 * 2511 * Addressing a chip using CS 2 or 3 should also need the third row 2512 * cycle but due to inconsistance in the documentation and lack of 2513 * hardware to test this situation, this case is not supported. 2514 */ 2515 if (chip->options & NAND_ROW_ADDR_3) 2516 marvell_nand->addr_cyc += 3; 2517 else 2518 marvell_nand->addr_cyc += 2; 2519 2520 if (pdata) { 2521 chip->ecc.size = pdata->ecc_step_size; 2522 chip->ecc.strength = pdata->ecc_strength; 2523 } 2524 2525 ret = marvell_nand_ecc_init(mtd, &chip->ecc); 2526 if (ret) { 2527 dev_err(nfc->dev, "ECC init failed: %d\n", ret); 2528 return ret; 2529 } 2530 2531 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 2532 /* 2533 * Subpage write not available with hardware ECC, prohibit also 2534 * subpage read as in userspace subpage access would still be 2535 * allowed and subpage write, if used, would lead to numerous 2536 * uncorrectable ECC errors. 2537 */ 2538 chip->options |= NAND_NO_SUBPAGE_WRITE; 2539 } 2540 2541 if (pdata || nfc->caps->legacy_of_bindings) { 2542 /* 2543 * We keep the MTD name unchanged to avoid breaking platforms 2544 * where the MTD cmdline parser is used and the bootloader 2545 * has not been updated to use the new naming scheme. 2546 */ 2547 mtd->name = "pxa3xx_nand-0"; 2548 } else if (!mtd->name) { 2549 /* 2550 * If the new bindings are used and the bootloader has not been 2551 * updated to pass a new mtdparts parameter on the cmdline, you 2552 * should define the following property in your NAND node, ie: 2553 * 2554 * label = "main-storage"; 2555 * 2556 * This way, mtd->name will be set by the core when 2557 * nand_set_flash_node() is called. 2558 */ 2559 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, 2560 "%s:nand.%d", dev_name(nfc->dev), 2561 marvell_nand->sels[0].cs); 2562 if (!mtd->name) { 2563 dev_err(nfc->dev, "Failed to allocate mtd->name\n"); 2564 return -ENOMEM; 2565 } 2566 } 2567 2568 return 0; 2569 } 2570 2571 static const struct nand_controller_ops marvell_nand_controller_ops = { 2572 .attach_chip = marvell_nand_attach_chip, 2573 .exec_op = marvell_nfc_exec_op, 2574 .setup_interface = marvell_nfc_setup_interface, 2575 }; 2576 2577 static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc, 2578 struct device_node *np) 2579 { 2580 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev); 2581 struct marvell_nand_chip *marvell_nand; 2582 struct mtd_info *mtd; 2583 struct nand_chip *chip; 2584 int nsels, ret, i; 2585 u32 cs, rb; 2586 2587 /* 2588 * The legacy "num-cs" property indicates the number of CS on the only 2589 * chip connected to the controller (legacy bindings does not support 2590 * more than one chip). The CS and RB pins are always the #0. 2591 * 2592 * When not using legacy bindings, a couple of "reg" and "nand-rb" 2593 * properties must be filled. For each chip, expressed as a subnode, 2594 * "reg" points to the CS lines and "nand-rb" to the RB line. 2595 */ 2596 if (pdata || nfc->caps->legacy_of_bindings) { 2597 nsels = 1; 2598 } else { 2599 nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32)); 2600 if (nsels <= 0) { 2601 dev_err(dev, "missing/invalid reg property\n"); 2602 return -EINVAL; 2603 } 2604 } 2605 2606 /* Alloc the nand chip structure */ 2607 marvell_nand = devm_kzalloc(dev, 2608 struct_size(marvell_nand, sels, nsels), 2609 GFP_KERNEL); 2610 if (!marvell_nand) { 2611 dev_err(dev, "could not allocate chip structure\n"); 2612 return -ENOMEM; 2613 } 2614 2615 marvell_nand->nsels = nsels; 2616 marvell_nand->selected_die = -1; 2617 2618 for (i = 0; i < nsels; i++) { 2619 if (pdata || nfc->caps->legacy_of_bindings) { 2620 /* 2621 * Legacy bindings use the CS lines in natural 2622 * order (0, 1, ...) 2623 */ 2624 cs = i; 2625 } else { 2626 /* Retrieve CS id */ 2627 ret = of_property_read_u32_index(np, "reg", i, &cs); 2628 if (ret) { 2629 dev_err(dev, "could not retrieve reg property: %d\n", 2630 ret); 2631 return ret; 2632 } 2633 } 2634 2635 if (cs >= nfc->caps->max_cs_nb) { 2636 dev_err(dev, "invalid reg value: %u (max CS = %d)\n", 2637 cs, nfc->caps->max_cs_nb); 2638 return -EINVAL; 2639 } 2640 2641 if (test_and_set_bit(cs, &nfc->assigned_cs)) { 2642 dev_err(dev, "CS %d already assigned\n", cs); 2643 return -EINVAL; 2644 } 2645 2646 /* 2647 * The cs variable represents the chip select id, which must be 2648 * converted in bit fields for NDCB0 and NDCB2 to select the 2649 * right chip. Unfortunately, due to a lack of information on 2650 * the subject and incoherent documentation, the user should not 2651 * use CS1 and CS3 at all as asserting them is not supported in 2652 * a reliable way (due to multiplexing inside ADDR5 field). 2653 */ 2654 marvell_nand->sels[i].cs = cs; 2655 switch (cs) { 2656 case 0: 2657 case 2: 2658 marvell_nand->sels[i].ndcb0_csel = 0; 2659 break; 2660 case 1: 2661 case 3: 2662 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; 2663 break; 2664 default: 2665 return -EINVAL; 2666 } 2667 2668 /* Retrieve RB id */ 2669 if (pdata || nfc->caps->legacy_of_bindings) { 2670 /* Legacy bindings always use RB #0 */ 2671 rb = 0; 2672 } else { 2673 ret = of_property_read_u32_index(np, "nand-rb", i, 2674 &rb); 2675 if (ret) { 2676 dev_err(dev, 2677 "could not retrieve RB property: %d\n", 2678 ret); 2679 return ret; 2680 } 2681 } 2682 2683 if (rb >= nfc->caps->max_rb_nb) { 2684 dev_err(dev, "invalid reg value: %u (max RB = %d)\n", 2685 rb, nfc->caps->max_rb_nb); 2686 return -EINVAL; 2687 } 2688 2689 marvell_nand->sels[i].rb = rb; 2690 } 2691 2692 chip = &marvell_nand->chip; 2693 chip->controller = &nfc->controller; 2694 nand_set_flash_node(chip, np); 2695 2696 if (of_property_read_bool(np, "marvell,nand-keep-config")) 2697 chip->options |= NAND_KEEP_TIMINGS; 2698 2699 mtd = nand_to_mtd(chip); 2700 mtd->dev.parent = dev; 2701 2702 /* 2703 * Save a reference value for timing registers before 2704 * ->setup_interface() is called. 2705 */ 2706 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); 2707 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); 2708 2709 chip->options |= NAND_BUSWIDTH_AUTO; 2710 2711 ret = nand_scan(chip, marvell_nand->nsels); 2712 if (ret) { 2713 dev_err(dev, "could not scan the nand chip\n"); 2714 return ret; 2715 } 2716 2717 if (pdata) 2718 /* Legacy bindings support only one chip */ 2719 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); 2720 else 2721 ret = mtd_device_register(mtd, NULL, 0); 2722 if (ret) { 2723 dev_err(dev, "failed to register mtd device: %d\n", ret); 2724 nand_cleanup(chip); 2725 return ret; 2726 } 2727 2728 list_add_tail(&marvell_nand->node, &nfc->chips); 2729 2730 return 0; 2731 } 2732 2733 static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc) 2734 { 2735 struct marvell_nand_chip *entry, *temp; 2736 struct nand_chip *chip; 2737 int ret; 2738 2739 list_for_each_entry_safe(entry, temp, &nfc->chips, node) { 2740 chip = &entry->chip; 2741 ret = mtd_device_unregister(nand_to_mtd(chip)); 2742 WARN_ON(ret); 2743 nand_cleanup(chip); 2744 list_del(&entry->node); 2745 } 2746 } 2747 2748 static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc) 2749 { 2750 struct device_node *np = dev->of_node; 2751 struct device_node *nand_np; 2752 int max_cs = nfc->caps->max_cs_nb; 2753 int nchips; 2754 int ret; 2755 2756 if (!np) 2757 nchips = 1; 2758 else 2759 nchips = of_get_child_count(np); 2760 2761 if (nchips > max_cs) { 2762 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, 2763 max_cs); 2764 return -EINVAL; 2765 } 2766 2767 /* 2768 * Legacy bindings do not use child nodes to exhibit NAND chip 2769 * properties and layout. Instead, NAND properties are mixed with the 2770 * controller ones, and partitions are defined as direct subnodes of the 2771 * NAND controller node. 2772 */ 2773 if (nfc->caps->legacy_of_bindings) { 2774 ret = marvell_nand_chip_init(dev, nfc, np); 2775 return ret; 2776 } 2777 2778 for_each_child_of_node(np, nand_np) { 2779 ret = marvell_nand_chip_init(dev, nfc, nand_np); 2780 if (ret) { 2781 of_node_put(nand_np); 2782 goto cleanup_chips; 2783 } 2784 } 2785 2786 return 0; 2787 2788 cleanup_chips: 2789 marvell_nand_chips_cleanup(nfc); 2790 2791 return ret; 2792 } 2793 2794 static int marvell_nfc_init_dma(struct marvell_nfc *nfc) 2795 { 2796 struct platform_device *pdev = container_of(nfc->dev, 2797 struct platform_device, 2798 dev); 2799 struct dma_slave_config config = {}; 2800 struct resource *r; 2801 int ret; 2802 2803 if (!IS_ENABLED(CONFIG_PXA_DMA)) { 2804 dev_warn(nfc->dev, 2805 "DMA not enabled in configuration\n"); 2806 return -ENOTSUPP; 2807 } 2808 2809 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); 2810 if (ret) 2811 return ret; 2812 2813 nfc->dma_chan = dma_request_chan(nfc->dev, "data"); 2814 if (IS_ERR(nfc->dma_chan)) { 2815 ret = PTR_ERR(nfc->dma_chan); 2816 nfc->dma_chan = NULL; 2817 return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n"); 2818 } 2819 2820 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2821 if (!r) { 2822 ret = -ENXIO; 2823 goto release_channel; 2824 } 2825 2826 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2827 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2828 config.src_addr = r->start + NDDB; 2829 config.dst_addr = r->start + NDDB; 2830 config.src_maxburst = 32; 2831 config.dst_maxburst = 32; 2832 ret = dmaengine_slave_config(nfc->dma_chan, &config); 2833 if (ret < 0) { 2834 dev_err(nfc->dev, "Failed to configure DMA channel\n"); 2835 goto release_channel; 2836 } 2837 2838 /* 2839 * DMA must act on length multiple of 32 and this length may be 2840 * bigger than the destination buffer. Use this buffer instead 2841 * for DMA transfers and then copy the desired amount of data to 2842 * the provided buffer. 2843 */ 2844 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); 2845 if (!nfc->dma_buf) { 2846 ret = -ENOMEM; 2847 goto release_channel; 2848 } 2849 2850 nfc->use_dma = true; 2851 2852 return 0; 2853 2854 release_channel: 2855 dma_release_channel(nfc->dma_chan); 2856 nfc->dma_chan = NULL; 2857 2858 return ret; 2859 } 2860 2861 static void marvell_nfc_reset(struct marvell_nfc *nfc) 2862 { 2863 /* 2864 * ECC operations and interruptions are only enabled when specifically 2865 * needed. ECC shall not be activated in the early stages (fails probe). 2866 * Arbiter flag, even if marked as "reserved", must be set (empirical). 2867 * SPARE_EN bit must always be set or ECC bytes will not be at the same 2868 * offset in the read page and this will fail the protection. 2869 */ 2870 writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN | 2871 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); 2872 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); 2873 writel_relaxed(0, nfc->regs + NDECCCTRL); 2874 } 2875 2876 static int marvell_nfc_init(struct marvell_nfc *nfc) 2877 { 2878 struct device_node *np = nfc->dev->of_node; 2879 2880 /* 2881 * Some SoCs like A7k/A8k need to enable manually the NAND 2882 * controller, gated clocks and reset bits to avoid being bootloader 2883 * dependent. This is done through the use of the System Functions 2884 * registers. 2885 */ 2886 if (nfc->caps->need_system_controller) { 2887 struct regmap *sysctrl_base = 2888 syscon_regmap_lookup_by_phandle(np, 2889 "marvell,system-controller"); 2890 2891 if (IS_ERR(sysctrl_base)) 2892 return PTR_ERR(sysctrl_base); 2893 2894 regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, 2895 GENCONF_SOC_DEVICE_MUX_NFC_EN | 2896 GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST | 2897 GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST | 2898 GENCONF_SOC_DEVICE_MUX_NFC_INT_EN | 2899 GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN); 2900 2901 regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL, 2902 GENCONF_CLK_GATING_CTRL_ND_GATE, 2903 GENCONF_CLK_GATING_CTRL_ND_GATE); 2904 } 2905 2906 /* Configure the DMA if appropriate */ 2907 if (!nfc->caps->is_nfcv2) 2908 marvell_nfc_init_dma(nfc); 2909 2910 marvell_nfc_reset(nfc); 2911 2912 return 0; 2913 } 2914 2915 static int marvell_nfc_probe(struct platform_device *pdev) 2916 { 2917 struct device *dev = &pdev->dev; 2918 struct marvell_nfc *nfc; 2919 int ret; 2920 int irq; 2921 2922 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), 2923 GFP_KERNEL); 2924 if (!nfc) 2925 return -ENOMEM; 2926 2927 nfc->dev = dev; 2928 nand_controller_init(&nfc->controller); 2929 nfc->controller.ops = &marvell_nand_controller_ops; 2930 INIT_LIST_HEAD(&nfc->chips); 2931 2932 nfc->regs = devm_platform_ioremap_resource(pdev, 0); 2933 if (IS_ERR(nfc->regs)) 2934 return PTR_ERR(nfc->regs); 2935 2936 irq = platform_get_irq(pdev, 0); 2937 if (irq < 0) 2938 return irq; 2939 2940 nfc->core_clk = devm_clk_get(&pdev->dev, "core"); 2941 2942 /* Managed the legacy case (when the first clock was not named) */ 2943 if (nfc->core_clk == ERR_PTR(-ENOENT)) 2944 nfc->core_clk = devm_clk_get(&pdev->dev, NULL); 2945 2946 if (IS_ERR(nfc->core_clk)) 2947 return PTR_ERR(nfc->core_clk); 2948 2949 ret = clk_prepare_enable(nfc->core_clk); 2950 if (ret) 2951 return ret; 2952 2953 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); 2954 if (IS_ERR(nfc->reg_clk)) { 2955 if (PTR_ERR(nfc->reg_clk) != -ENOENT) { 2956 ret = PTR_ERR(nfc->reg_clk); 2957 goto unprepare_core_clk; 2958 } 2959 2960 nfc->reg_clk = NULL; 2961 } 2962 2963 ret = clk_prepare_enable(nfc->reg_clk); 2964 if (ret) 2965 goto unprepare_core_clk; 2966 2967 marvell_nfc_disable_int(nfc, NDCR_ALL_INT); 2968 marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 2969 ret = devm_request_irq(dev, irq, marvell_nfc_isr, 2970 0, "marvell-nfc", nfc); 2971 if (ret) 2972 goto unprepare_reg_clk; 2973 2974 /* Get NAND controller capabilities */ 2975 if (pdev->id_entry) 2976 nfc->caps = (void *)pdev->id_entry->driver_data; 2977 else 2978 nfc->caps = of_device_get_match_data(&pdev->dev); 2979 2980 if (!nfc->caps) { 2981 dev_err(dev, "Could not retrieve NFC caps\n"); 2982 ret = -EINVAL; 2983 goto unprepare_reg_clk; 2984 } 2985 2986 /* Init the controller and then probe the chips */ 2987 ret = marvell_nfc_init(nfc); 2988 if (ret) 2989 goto unprepare_reg_clk; 2990 2991 platform_set_drvdata(pdev, nfc); 2992 2993 ret = marvell_nand_chips_init(dev, nfc); 2994 if (ret) 2995 goto release_dma; 2996 2997 return 0; 2998 2999 release_dma: 3000 if (nfc->use_dma) 3001 dma_release_channel(nfc->dma_chan); 3002 unprepare_reg_clk: 3003 clk_disable_unprepare(nfc->reg_clk); 3004 unprepare_core_clk: 3005 clk_disable_unprepare(nfc->core_clk); 3006 3007 return ret; 3008 } 3009 3010 static void marvell_nfc_remove(struct platform_device *pdev) 3011 { 3012 struct marvell_nfc *nfc = platform_get_drvdata(pdev); 3013 3014 marvell_nand_chips_cleanup(nfc); 3015 3016 if (nfc->use_dma) { 3017 dmaengine_terminate_all(nfc->dma_chan); 3018 dma_release_channel(nfc->dma_chan); 3019 } 3020 3021 clk_disable_unprepare(nfc->reg_clk); 3022 clk_disable_unprepare(nfc->core_clk); 3023 } 3024 3025 static int __maybe_unused marvell_nfc_suspend(struct device *dev) 3026 { 3027 struct marvell_nfc *nfc = dev_get_drvdata(dev); 3028 struct marvell_nand_chip *chip; 3029 3030 list_for_each_entry(chip, &nfc->chips, node) 3031 marvell_nfc_wait_ndrun(&chip->chip); 3032 3033 clk_disable_unprepare(nfc->reg_clk); 3034 clk_disable_unprepare(nfc->core_clk); 3035 3036 return 0; 3037 } 3038 3039 static int __maybe_unused marvell_nfc_resume(struct device *dev) 3040 { 3041 struct marvell_nfc *nfc = dev_get_drvdata(dev); 3042 int ret; 3043 3044 ret = clk_prepare_enable(nfc->core_clk); 3045 if (ret < 0) 3046 return ret; 3047 3048 ret = clk_prepare_enable(nfc->reg_clk); 3049 if (ret < 0) { 3050 clk_disable_unprepare(nfc->core_clk); 3051 return ret; 3052 } 3053 3054 /* 3055 * Reset nfc->selected_chip so the next command will cause the timing 3056 * registers to be restored in marvell_nfc_select_target(). 3057 */ 3058 nfc->selected_chip = NULL; 3059 3060 /* Reset registers that have lost their contents */ 3061 marvell_nfc_reset(nfc); 3062 3063 return 0; 3064 } 3065 3066 static const struct dev_pm_ops marvell_nfc_pm_ops = { 3067 SET_SYSTEM_SLEEP_PM_OPS(marvell_nfc_suspend, marvell_nfc_resume) 3068 }; 3069 3070 static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { 3071 .max_cs_nb = 4, 3072 .max_rb_nb = 2, 3073 .need_system_controller = true, 3074 .is_nfcv2 = true, 3075 }; 3076 3077 static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { 3078 .max_cs_nb = 4, 3079 .max_rb_nb = 2, 3080 .is_nfcv2 = true, 3081 }; 3082 3083 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = { 3084 .max_cs_nb = 2, 3085 .max_rb_nb = 1, 3086 .use_dma = true, 3087 }; 3088 3089 static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = { 3090 .max_cs_nb = 4, 3091 .max_rb_nb = 2, 3092 .need_system_controller = true, 3093 .legacy_of_bindings = true, 3094 .is_nfcv2 = true, 3095 }; 3096 3097 static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = { 3098 .max_cs_nb = 4, 3099 .max_rb_nb = 2, 3100 .legacy_of_bindings = true, 3101 .is_nfcv2 = true, 3102 }; 3103 3104 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = { 3105 .max_cs_nb = 2, 3106 .max_rb_nb = 1, 3107 .legacy_of_bindings = true, 3108 .use_dma = true, 3109 }; 3110 3111 static const struct platform_device_id marvell_nfc_platform_ids[] = { 3112 { 3113 .name = "pxa3xx-nand", 3114 .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps, 3115 }, 3116 { /* sentinel */ }, 3117 }; 3118 MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids); 3119 3120 static const struct of_device_id marvell_nfc_of_ids[] = { 3121 { 3122 .compatible = "marvell,armada-8k-nand-controller", 3123 .data = &marvell_armada_8k_nfc_caps, 3124 }, 3125 { 3126 .compatible = "marvell,armada370-nand-controller", 3127 .data = &marvell_armada370_nfc_caps, 3128 }, 3129 { 3130 .compatible = "marvell,pxa3xx-nand-controller", 3131 .data = &marvell_pxa3xx_nfc_caps, 3132 }, 3133 /* Support for old/deprecated bindings: */ 3134 { 3135 .compatible = "marvell,armada-8k-nand", 3136 .data = &marvell_armada_8k_nfc_legacy_caps, 3137 }, 3138 { 3139 .compatible = "marvell,armada370-nand", 3140 .data = &marvell_armada370_nfc_legacy_caps, 3141 }, 3142 { 3143 .compatible = "marvell,pxa3xx-nand", 3144 .data = &marvell_pxa3xx_nfc_legacy_caps, 3145 }, 3146 { /* sentinel */ }, 3147 }; 3148 MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids); 3149 3150 static struct platform_driver marvell_nfc_driver = { 3151 .driver = { 3152 .name = "marvell-nfc", 3153 .of_match_table = marvell_nfc_of_ids, 3154 .pm = &marvell_nfc_pm_ops, 3155 }, 3156 .id_table = marvell_nfc_platform_ids, 3157 .probe = marvell_nfc_probe, 3158 .remove_new = marvell_nfc_remove, 3159 }; 3160 module_platform_driver(marvell_nfc_driver); 3161 3162 MODULE_LICENSE("GPL"); 3163 MODULE_DESCRIPTION("Marvell NAND controller driver"); 3164