193db446aSBoris Brezillon // SPDX-License-Identifier: GPL-2.0 293db446aSBoris Brezillon /* 393db446aSBoris Brezillon * Marvell NAND flash controller driver 493db446aSBoris Brezillon * 593db446aSBoris Brezillon * Copyright (C) 2017 Marvell 693db446aSBoris Brezillon * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com> 793db446aSBoris Brezillon * 833c1c5feSMiquel Raynal * 933c1c5feSMiquel Raynal * This NAND controller driver handles two versions of the hardware, 1033c1c5feSMiquel Raynal * one is called NFCv1 and is available on PXA SoCs and the other is 1133c1c5feSMiquel Raynal * called NFCv2 and is available on Armada SoCs. 1233c1c5feSMiquel Raynal * 1333c1c5feSMiquel Raynal * The main visible difference is that NFCv1 only has Hamming ECC 1433c1c5feSMiquel Raynal * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA 1533c1c5feSMiquel Raynal * is not used with NFCv2. 1633c1c5feSMiquel Raynal * 1733c1c5feSMiquel Raynal * The ECC layouts are depicted in details in Marvell AN-379, but here 1833c1c5feSMiquel Raynal * is a brief description. 1933c1c5feSMiquel Raynal * 2033c1c5feSMiquel Raynal * When using Hamming, the data is split in 512B chunks (either 1, 2 2133c1c5feSMiquel Raynal * or 4) and each chunk will have its own ECC "digest" of 6B at the 2233c1c5feSMiquel Raynal * beginning of the OOB area and eventually the remaining free OOB 2333c1c5feSMiquel Raynal * bytes (also called "spare" bytes in the driver). This engine 2433c1c5feSMiquel Raynal * corrects up to 1 bit per chunk and detects reliably an error if 2533c1c5feSMiquel Raynal * there are at most 2 bitflips. Here is the page layout used by the 2633c1c5feSMiquel Raynal * controller when Hamming is chosen: 2733c1c5feSMiquel Raynal * 2833c1c5feSMiquel Raynal * +-------------------------------------------------------------+ 2933c1c5feSMiquel Raynal * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes | 3033c1c5feSMiquel Raynal * +-------------------------------------------------------------+ 3133c1c5feSMiquel Raynal * 3233c1c5feSMiquel Raynal * When using the BCH engine, there are N identical (data + free OOB + 3333c1c5feSMiquel Raynal * ECC) sections and potentially an extra one to deal with 3433c1c5feSMiquel Raynal * configurations where the chosen (data + free OOB + ECC) sizes do 3533c1c5feSMiquel Raynal * not align with the page (data + OOB) size. ECC bytes are always 3633c1c5feSMiquel Raynal * 30B per ECC chunk. Here is the page layout used by the controller 3733c1c5feSMiquel Raynal * when BCH is chosen: 3833c1c5feSMiquel Raynal * 3933c1c5feSMiquel Raynal * +----------------------------------------- 4033c1c5feSMiquel Raynal * | Data 1 | Free OOB bytes 1 | ECC 1 | ... 4133c1c5feSMiquel Raynal * +----------------------------------------- 4233c1c5feSMiquel Raynal * 4333c1c5feSMiquel Raynal * ------------------------------------------- 4433c1c5feSMiquel Raynal * ... | Data N | Free OOB bytes N | ECC N | 4533c1c5feSMiquel Raynal * ------------------------------------------- 4633c1c5feSMiquel Raynal * 4733c1c5feSMiquel Raynal * --------------------------------------------+ 4833c1c5feSMiquel Raynal * Last Data | Last Free OOB bytes | Last ECC | 4933c1c5feSMiquel Raynal * --------------------------------------------+ 5033c1c5feSMiquel Raynal * 5133c1c5feSMiquel Raynal * In both cases, the layout seen by the user is always: all data 5233c1c5feSMiquel Raynal * first, then all free OOB bytes and finally all ECC bytes. With BCH, 5333c1c5feSMiquel Raynal * ECC bytes are 30B long and are padded with 0xFF to align on 32 5433c1c5feSMiquel Raynal * bytes. 5533c1c5feSMiquel Raynal * 5633c1c5feSMiquel Raynal * The controller has certain limitations that are handled by the 5733c1c5feSMiquel Raynal * driver: 5833c1c5feSMiquel Raynal * - It can only read 2k at a time. To overcome this limitation, the 5933c1c5feSMiquel Raynal * driver issues data cycles on the bus, without issuing new 6033c1c5feSMiquel Raynal * CMD + ADDR cycles. The Marvell term is "naked" operations. 6133c1c5feSMiquel Raynal * - The ECC strength in BCH mode cannot be tuned. It is fixed 16 6233c1c5feSMiquel Raynal * bits. What can be tuned is the ECC block size as long as it 6333c1c5feSMiquel Raynal * stays between 512B and 2kiB. It's usually chosen based on the 6433c1c5feSMiquel Raynal * chip ECC requirements. For instance, using 2kiB ECC chunks 6533c1c5feSMiquel Raynal * provides 4b/512B correctability. 6633c1c5feSMiquel Raynal * - The controller will always treat data bytes, free OOB bytes 6733c1c5feSMiquel Raynal * and ECC bytes in that order, no matter what the real layout is 6833c1c5feSMiquel Raynal * (which is usually all data then all OOB bytes). The 6933c1c5feSMiquel Raynal * marvell_nfc_layouts array below contains the currently 7033c1c5feSMiquel Raynal * supported layouts. 7133c1c5feSMiquel Raynal * - Because of these weird layouts, the Bad Block Markers can be 7233c1c5feSMiquel Raynal * located in data section. In this case, the NAND_BBT_NO_OOB_BBM 7333c1c5feSMiquel Raynal * option must be set to prevent scanning/writing bad block 7433c1c5feSMiquel Raynal * markers. 7593db446aSBoris Brezillon */ 7693db446aSBoris Brezillon 7793db446aSBoris Brezillon #include <linux/module.h> 7893db446aSBoris Brezillon #include <linux/clk.h> 7993db446aSBoris Brezillon #include <linux/mtd/rawnand.h> 8093db446aSBoris Brezillon #include <linux/of_platform.h> 8193db446aSBoris Brezillon #include <linux/iopoll.h> 8293db446aSBoris Brezillon #include <linux/interrupt.h> 8393db446aSBoris Brezillon #include <linux/slab.h> 8493db446aSBoris Brezillon #include <linux/mfd/syscon.h> 8593db446aSBoris Brezillon #include <linux/regmap.h> 8693db446aSBoris Brezillon #include <asm/unaligned.h> 8793db446aSBoris Brezillon 8893db446aSBoris Brezillon #include <linux/dmaengine.h> 8993db446aSBoris Brezillon #include <linux/dma-mapping.h> 9093db446aSBoris Brezillon #include <linux/dma/pxa-dma.h> 9193db446aSBoris Brezillon #include <linux/platform_data/mtd-nand-pxa3xx.h> 9293db446aSBoris Brezillon 9393db446aSBoris Brezillon /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */ 9493db446aSBoris Brezillon #define FIFO_DEPTH 8 9593db446aSBoris Brezillon #define FIFO_REP(x) (x / sizeof(u32)) 9693db446aSBoris Brezillon #define BCH_SEQ_READS (32 / FIFO_DEPTH) 9793db446aSBoris Brezillon /* NFC does not support transfers of larger chunks at a time */ 9893db446aSBoris Brezillon #define MAX_CHUNK_SIZE 2112 9993db446aSBoris Brezillon /* NFCv1 cannot read more that 7 bytes of ID */ 10093db446aSBoris Brezillon #define NFCV1_READID_LEN 7 10193db446aSBoris Brezillon /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */ 10293db446aSBoris Brezillon #define POLL_PERIOD 0 10393db446aSBoris Brezillon #define POLL_TIMEOUT 100000 10493db446aSBoris Brezillon /* Interrupt maximum wait period in ms */ 10593db446aSBoris Brezillon #define IRQ_TIMEOUT 1000 10693db446aSBoris Brezillon /* Latency in clock cycles between SoC pins and NFC logic */ 10793db446aSBoris Brezillon #define MIN_RD_DEL_CNT 3 10893db446aSBoris Brezillon /* Maximum number of contiguous address cycles */ 10993db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV1 5 11093db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV2 7 11193db446aSBoris Brezillon /* System control registers/bits to enable the NAND controller on some SoCs */ 11293db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX 0x208 11393db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) 11493db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20) 11593db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21) 11693db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25) 11793db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL 0x220 11893db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2) 11993db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL 0x700 12093db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL_EN BIT(0) 12193db446aSBoris Brezillon 12293db446aSBoris Brezillon /* NAND controller data flash control register */ 12393db446aSBoris Brezillon #define NDCR 0x00 12493db446aSBoris Brezillon #define NDCR_ALL_INT GENMASK(11, 0) 12593db446aSBoris Brezillon #define NDCR_CS1_CMDDM BIT(7) 12693db446aSBoris Brezillon #define NDCR_CS0_CMDDM BIT(8) 12793db446aSBoris Brezillon #define NDCR_RDYM BIT(11) 12893db446aSBoris Brezillon #define NDCR_ND_ARB_EN BIT(12) 12993db446aSBoris Brezillon #define NDCR_RA_START BIT(15) 13093db446aSBoris Brezillon #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16) 13193db446aSBoris Brezillon #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0) 13293db446aSBoris Brezillon #define NDCR_DWIDTH_M BIT(26) 13393db446aSBoris Brezillon #define NDCR_DWIDTH_C BIT(27) 13493db446aSBoris Brezillon #define NDCR_ND_RUN BIT(28) 13593db446aSBoris Brezillon #define NDCR_DMA_EN BIT(29) 13693db446aSBoris Brezillon #define NDCR_ECC_EN BIT(30) 13793db446aSBoris Brezillon #define NDCR_SPARE_EN BIT(31) 13893db446aSBoris Brezillon #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \ 13993db446aSBoris Brezillon NDCR_DWIDTH_M | NDCR_DWIDTH_C)) 14093db446aSBoris Brezillon 14193db446aSBoris Brezillon /* NAND interface timing parameter 0 register */ 14293db446aSBoris Brezillon #define NDTR0 0x04 14393db446aSBoris Brezillon #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0) 14493db446aSBoris Brezillon #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3) 14593db446aSBoris Brezillon #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3) 14693db446aSBoris Brezillon #define NDTR0_SEL_NRE_EDGE BIT(7) 14793db446aSBoris Brezillon #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8) 14893db446aSBoris Brezillon #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11) 14993db446aSBoris Brezillon #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16) 15093db446aSBoris Brezillon #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19) 15193db446aSBoris Brezillon #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22) 15293db446aSBoris Brezillon #define NDTR0_SELCNTR BIT(26) 15393db446aSBoris Brezillon #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27) 15493db446aSBoris Brezillon 15593db446aSBoris Brezillon /* NAND interface timing parameter 1 register */ 15693db446aSBoris Brezillon #define NDTR1 0x0C 15793db446aSBoris Brezillon #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0) 15893db446aSBoris Brezillon #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4) 15993db446aSBoris Brezillon #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8) 16093db446aSBoris Brezillon #define NDTR1_PRESCALE BIT(14) 16193db446aSBoris Brezillon #define NDTR1_WAIT_MODE BIT(15) 16293db446aSBoris Brezillon #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16) 16393db446aSBoris Brezillon 16493db446aSBoris Brezillon /* NAND controller status register */ 16593db446aSBoris Brezillon #define NDSR 0x14 16693db446aSBoris Brezillon #define NDSR_WRCMDREQ BIT(0) 16793db446aSBoris Brezillon #define NDSR_RDDREQ BIT(1) 16893db446aSBoris Brezillon #define NDSR_WRDREQ BIT(2) 16993db446aSBoris Brezillon #define NDSR_CORERR BIT(3) 17093db446aSBoris Brezillon #define NDSR_UNCERR BIT(4) 17193db446aSBoris Brezillon #define NDSR_CMDD(cs) BIT(8 - cs) 17293db446aSBoris Brezillon #define NDSR_RDY(rb) BIT(11 + rb) 17393db446aSBoris Brezillon #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F) 17493db446aSBoris Brezillon 17593db446aSBoris Brezillon /* NAND ECC control register */ 17693db446aSBoris Brezillon #define NDECCCTRL 0x28 17793db446aSBoris Brezillon #define NDECCCTRL_BCH_EN BIT(0) 17893db446aSBoris Brezillon 17993db446aSBoris Brezillon /* NAND controller data buffer register */ 18093db446aSBoris Brezillon #define NDDB 0x40 18193db446aSBoris Brezillon 18293db446aSBoris Brezillon /* NAND controller command buffer 0 register */ 18393db446aSBoris Brezillon #define NDCB0 0x48 18493db446aSBoris Brezillon #define NDCB0_CMD1(x) ((x & 0xFF) << 0) 18593db446aSBoris Brezillon #define NDCB0_CMD2(x) ((x & 0xFF) << 8) 18693db446aSBoris Brezillon #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16) 18793db446aSBoris Brezillon #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7) 18893db446aSBoris Brezillon #define NDCB0_DBC BIT(19) 18993db446aSBoris Brezillon #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21) 19093db446aSBoris Brezillon #define NDCB0_CSEL BIT(24) 19193db446aSBoris Brezillon #define NDCB0_RDY_BYP BIT(27) 19293db446aSBoris Brezillon #define NDCB0_LEN_OVRD BIT(28) 19393db446aSBoris Brezillon #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29) 19493db446aSBoris Brezillon 19593db446aSBoris Brezillon /* NAND controller command buffer 1 register */ 19693db446aSBoris Brezillon #define NDCB1 0x4C 19793db446aSBoris Brezillon #define NDCB1_COLS(x) ((x & 0xFFFF) << 0) 19893db446aSBoris Brezillon #define NDCB1_ADDRS_PAGE(x) (x << 16) 19993db446aSBoris Brezillon 20093db446aSBoris Brezillon /* NAND controller command buffer 2 register */ 20193db446aSBoris Brezillon #define NDCB2 0x50 20293db446aSBoris Brezillon #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0) 20393db446aSBoris Brezillon #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0) 20493db446aSBoris Brezillon 20593db446aSBoris Brezillon /* NAND controller command buffer 3 register */ 20693db446aSBoris Brezillon #define NDCB3 0x54 20793db446aSBoris Brezillon #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16) 20893db446aSBoris Brezillon #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24) 20993db446aSBoris Brezillon 21093db446aSBoris Brezillon /* NAND controller command buffer 0 register 'type' and 'xtype' fields */ 21193db446aSBoris Brezillon #define TYPE_READ 0 21293db446aSBoris Brezillon #define TYPE_WRITE 1 21393db446aSBoris Brezillon #define TYPE_ERASE 2 21493db446aSBoris Brezillon #define TYPE_READ_ID 3 21593db446aSBoris Brezillon #define TYPE_STATUS 4 21693db446aSBoris Brezillon #define TYPE_RESET 5 21793db446aSBoris Brezillon #define TYPE_NAKED_CMD 6 21893db446aSBoris Brezillon #define TYPE_NAKED_ADDR 7 21993db446aSBoris Brezillon #define TYPE_MASK 7 22093db446aSBoris Brezillon #define XTYPE_MONOLITHIC_RW 0 22193db446aSBoris Brezillon #define XTYPE_LAST_NAKED_RW 1 22293db446aSBoris Brezillon #define XTYPE_FINAL_COMMAND 3 22393db446aSBoris Brezillon #define XTYPE_READ 4 22493db446aSBoris Brezillon #define XTYPE_WRITE_DISPATCH 4 22593db446aSBoris Brezillon #define XTYPE_NAKED_RW 5 22693db446aSBoris Brezillon #define XTYPE_COMMAND_DISPATCH 6 22793db446aSBoris Brezillon #define XTYPE_MASK 7 22893db446aSBoris Brezillon 22993db446aSBoris Brezillon /** 23093db446aSBoris Brezillon * Marvell ECC engine works differently than the others, in order to limit the 23193db446aSBoris Brezillon * size of the IP, hardware engineers chose to set a fixed strength at 16 bits 23293db446aSBoris Brezillon * per subpage, and depending on a the desired strength needed by the NAND chip, 23393db446aSBoris Brezillon * a particular layout mixing data/spare/ecc is defined, with a possible last 23493db446aSBoris Brezillon * chunk smaller that the others. 23593db446aSBoris Brezillon * 23693db446aSBoris Brezillon * @writesize: Full page size on which the layout applies 23793db446aSBoris Brezillon * @chunk: Desired ECC chunk size on which the layout applies 23893db446aSBoris Brezillon * @strength: Desired ECC strength (per chunk size bytes) on which the 23993db446aSBoris Brezillon * layout applies 24093db446aSBoris Brezillon * @nchunks: Total number of chunks 24193db446aSBoris Brezillon * @full_chunk_cnt: Number of full-sized chunks, which is the number of 24293db446aSBoris Brezillon * repetitions of the pattern: 24393db446aSBoris Brezillon * (data_bytes + spare_bytes + ecc_bytes). 24493db446aSBoris Brezillon * @data_bytes: Number of data bytes per chunk 24593db446aSBoris Brezillon * @spare_bytes: Number of spare bytes per chunk 24693db446aSBoris Brezillon * @ecc_bytes: Number of ecc bytes per chunk 24793db446aSBoris Brezillon * @last_data_bytes: Number of data bytes in the last chunk 24893db446aSBoris Brezillon * @last_spare_bytes: Number of spare bytes in the last chunk 24993db446aSBoris Brezillon * @last_ecc_bytes: Number of ecc bytes in the last chunk 25093db446aSBoris Brezillon */ 25193db446aSBoris Brezillon struct marvell_hw_ecc_layout { 25293db446aSBoris Brezillon /* Constraints */ 25393db446aSBoris Brezillon int writesize; 25493db446aSBoris Brezillon int chunk; 25593db446aSBoris Brezillon int strength; 25693db446aSBoris Brezillon /* Corresponding layout */ 25793db446aSBoris Brezillon int nchunks; 25893db446aSBoris Brezillon int full_chunk_cnt; 25993db446aSBoris Brezillon int data_bytes; 26093db446aSBoris Brezillon int spare_bytes; 26193db446aSBoris Brezillon int ecc_bytes; 26293db446aSBoris Brezillon int last_data_bytes; 26393db446aSBoris Brezillon int last_spare_bytes; 26493db446aSBoris Brezillon int last_ecc_bytes; 26593db446aSBoris Brezillon }; 26693db446aSBoris Brezillon 26793db446aSBoris Brezillon #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \ 26893db446aSBoris Brezillon { \ 26993db446aSBoris Brezillon .writesize = ws, \ 27093db446aSBoris Brezillon .chunk = dc, \ 27193db446aSBoris Brezillon .strength = ds, \ 27293db446aSBoris Brezillon .nchunks = nc, \ 27393db446aSBoris Brezillon .full_chunk_cnt = fcc, \ 27493db446aSBoris Brezillon .data_bytes = db, \ 27593db446aSBoris Brezillon .spare_bytes = sb, \ 27693db446aSBoris Brezillon .ecc_bytes = eb, \ 27793db446aSBoris Brezillon .last_data_bytes = ldb, \ 27893db446aSBoris Brezillon .last_spare_bytes = lsb, \ 27993db446aSBoris Brezillon .last_ecc_bytes = leb, \ 28093db446aSBoris Brezillon } 28193db446aSBoris Brezillon 28293db446aSBoris Brezillon /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */ 28393db446aSBoris Brezillon static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = { 28493db446aSBoris Brezillon MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0), 28593db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0), 28693db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0), 2877fd130f7SMiquel Raynal MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30), 28893db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0), 28993db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30), 290e8237bfaSKonstantin Porotchkin MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0), 291e8237bfaSKonstantin Porotchkin MARVELL_LAYOUT( 8192, 512, 8, 9, 8, 1024, 0, 30, 0, 160, 30), 29293db446aSBoris Brezillon }; 29393db446aSBoris Brezillon 29493db446aSBoris Brezillon /** 29593db446aSBoris Brezillon * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection 29693db446aSBoris Brezillon * is made by a field in NDCB0 register, and in another field in NDCB2 register. 29793db446aSBoris Brezillon * The datasheet describes the logic with an error: ADDR5 field is once 29893db446aSBoris Brezillon * declared at the beginning of NDCB2, and another time at its end. Because the 29993db446aSBoris Brezillon * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical 30093db446aSBoris Brezillon * to use the last bit of this field instead of the first ones. 30193db446aSBoris Brezillon * 30293db446aSBoris Brezillon * @cs: Wanted CE lane. 30393db446aSBoris Brezillon * @ndcb0_csel: Value of the NDCB0 register with or without the flag 30493db446aSBoris Brezillon * selecting the wanted CE lane. This is set once when 30593db446aSBoris Brezillon * the Device Tree is probed. 30693db446aSBoris Brezillon * @rb: Ready/Busy pin for the flash chip 30793db446aSBoris Brezillon */ 30893db446aSBoris Brezillon struct marvell_nand_chip_sel { 30993db446aSBoris Brezillon unsigned int cs; 31093db446aSBoris Brezillon u32 ndcb0_csel; 31193db446aSBoris Brezillon unsigned int rb; 31293db446aSBoris Brezillon }; 31393db446aSBoris Brezillon 31493db446aSBoris Brezillon /** 31593db446aSBoris Brezillon * NAND chip structure: stores NAND chip device related information 31693db446aSBoris Brezillon * 31793db446aSBoris Brezillon * @chip: Base NAND chip structure 31893db446aSBoris Brezillon * @node: Used to store NAND chips into a list 31993db446aSBoris Brezillon * @layout NAND layout when using hardware ECC 32093db446aSBoris Brezillon * @ndcr: Controller register value for this NAND chip 32193db446aSBoris Brezillon * @ndtr0: Timing registers 0 value for this NAND chip 32293db446aSBoris Brezillon * @ndtr1: Timing registers 1 value for this NAND chip 32393db446aSBoris Brezillon * @selected_die: Current active CS 32493db446aSBoris Brezillon * @nsels: Number of CS lines required by the NAND chip 32593db446aSBoris Brezillon * @sels: Array of CS lines descriptions 32693db446aSBoris Brezillon */ 32793db446aSBoris Brezillon struct marvell_nand_chip { 32893db446aSBoris Brezillon struct nand_chip chip; 32993db446aSBoris Brezillon struct list_head node; 33093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *layout; 33193db446aSBoris Brezillon u32 ndcr; 33293db446aSBoris Brezillon u32 ndtr0; 33393db446aSBoris Brezillon u32 ndtr1; 33493db446aSBoris Brezillon int addr_cyc; 33593db446aSBoris Brezillon int selected_die; 33693db446aSBoris Brezillon unsigned int nsels; 33793db446aSBoris Brezillon struct marvell_nand_chip_sel sels[0]; 33893db446aSBoris Brezillon }; 33993db446aSBoris Brezillon 34093db446aSBoris Brezillon static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip) 34193db446aSBoris Brezillon { 34293db446aSBoris Brezillon return container_of(chip, struct marvell_nand_chip, chip); 34393db446aSBoris Brezillon } 34493db446aSBoris Brezillon 34593db446aSBoris Brezillon static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip 34693db446aSBoris Brezillon *nand) 34793db446aSBoris Brezillon { 34893db446aSBoris Brezillon return &nand->sels[nand->selected_die]; 34993db446aSBoris Brezillon } 35093db446aSBoris Brezillon 35193db446aSBoris Brezillon /** 35293db446aSBoris Brezillon * NAND controller capabilities for distinction between compatible strings 35393db446aSBoris Brezillon * 35493db446aSBoris Brezillon * @max_cs_nb: Number of Chip Select lines available 35593db446aSBoris Brezillon * @max_rb_nb: Number of Ready/Busy lines available 35693db446aSBoris Brezillon * @need_system_controller: Indicates if the SoC needs to have access to the 35793db446aSBoris Brezillon * system controller (ie. to enable the NAND controller) 35893db446aSBoris Brezillon * @legacy_of_bindings: Indicates if DT parsing must be done using the old 35993db446aSBoris Brezillon * fashion way 36093db446aSBoris Brezillon * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie. 36193db446aSBoris Brezillon * BCH error detection and correction algorithm, 36293db446aSBoris Brezillon * NDCB3 register has been added 36393db446aSBoris Brezillon * @use_dma: Use dma for data transfers 36493db446aSBoris Brezillon */ 36593db446aSBoris Brezillon struct marvell_nfc_caps { 36693db446aSBoris Brezillon unsigned int max_cs_nb; 36793db446aSBoris Brezillon unsigned int max_rb_nb; 36893db446aSBoris Brezillon bool need_system_controller; 36993db446aSBoris Brezillon bool legacy_of_bindings; 37093db446aSBoris Brezillon bool is_nfcv2; 37193db446aSBoris Brezillon bool use_dma; 37293db446aSBoris Brezillon }; 37393db446aSBoris Brezillon 37493db446aSBoris Brezillon /** 37593db446aSBoris Brezillon * NAND controller structure: stores Marvell NAND controller information 37693db446aSBoris Brezillon * 37793db446aSBoris Brezillon * @controller: Base controller structure 37893db446aSBoris Brezillon * @dev: Parent device (used to print error messages) 37993db446aSBoris Brezillon * @regs: NAND controller registers 3806b6de654SBoris Brezillon * @core_clk: Core clock 381961ba15cSGregory CLEMENT * @reg_clk: Regiters clock 38293db446aSBoris Brezillon * @complete: Completion object to wait for NAND controller events 38393db446aSBoris Brezillon * @assigned_cs: Bitmask describing already assigned CS lines 38493db446aSBoris Brezillon * @chips: List containing all the NAND chips attached to 38593db446aSBoris Brezillon * this NAND controller 38693db446aSBoris Brezillon * @caps: NAND controller capabilities for each compatible string 38793db446aSBoris Brezillon * @dma_chan: DMA channel (NFCv1 only) 38893db446aSBoris Brezillon * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only) 38993db446aSBoris Brezillon */ 39093db446aSBoris Brezillon struct marvell_nfc { 3917da45139SMiquel Raynal struct nand_controller controller; 39293db446aSBoris Brezillon struct device *dev; 39393db446aSBoris Brezillon void __iomem *regs; 3946b6de654SBoris Brezillon struct clk *core_clk; 395961ba15cSGregory CLEMENT struct clk *reg_clk; 39693db446aSBoris Brezillon struct completion complete; 39793db446aSBoris Brezillon unsigned long assigned_cs; 39893db446aSBoris Brezillon struct list_head chips; 39993db446aSBoris Brezillon struct nand_chip *selected_chip; 40093db446aSBoris Brezillon const struct marvell_nfc_caps *caps; 40193db446aSBoris Brezillon 40293db446aSBoris Brezillon /* DMA (NFCv1 only) */ 40393db446aSBoris Brezillon bool use_dma; 40493db446aSBoris Brezillon struct dma_chan *dma_chan; 40593db446aSBoris Brezillon u8 *dma_buf; 40693db446aSBoris Brezillon }; 40793db446aSBoris Brezillon 4087da45139SMiquel Raynal static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl) 40993db446aSBoris Brezillon { 41093db446aSBoris Brezillon return container_of(ctrl, struct marvell_nfc, controller); 41193db446aSBoris Brezillon } 41293db446aSBoris Brezillon 41393db446aSBoris Brezillon /** 41493db446aSBoris Brezillon * NAND controller timings expressed in NAND Controller clock cycles 41593db446aSBoris Brezillon * 41693db446aSBoris Brezillon * @tRP: ND_nRE pulse width 41793db446aSBoris Brezillon * @tRH: ND_nRE high duration 41893db446aSBoris Brezillon * @tWP: ND_nWE pulse time 41993db446aSBoris Brezillon * @tWH: ND_nWE high duration 42093db446aSBoris Brezillon * @tCS: Enable signal setup time 42193db446aSBoris Brezillon * @tCH: Enable signal hold time 42293db446aSBoris Brezillon * @tADL: Address to write data delay 42393db446aSBoris Brezillon * @tAR: ND_ALE low to ND_nRE low delay 42493db446aSBoris Brezillon * @tWHR: ND_nWE high to ND_nRE low for status read 42593db446aSBoris Brezillon * @tRHW: ND_nRE high duration, read to write delay 42693db446aSBoris Brezillon * @tR: ND_nWE high to ND_nRE low for read 42793db446aSBoris Brezillon */ 42893db446aSBoris Brezillon struct marvell_nfc_timings { 42993db446aSBoris Brezillon /* NDTR0 fields */ 43093db446aSBoris Brezillon unsigned int tRP; 43193db446aSBoris Brezillon unsigned int tRH; 43293db446aSBoris Brezillon unsigned int tWP; 43393db446aSBoris Brezillon unsigned int tWH; 43493db446aSBoris Brezillon unsigned int tCS; 43593db446aSBoris Brezillon unsigned int tCH; 43693db446aSBoris Brezillon unsigned int tADL; 43793db446aSBoris Brezillon /* NDTR1 fields */ 43893db446aSBoris Brezillon unsigned int tAR; 43993db446aSBoris Brezillon unsigned int tWHR; 44093db446aSBoris Brezillon unsigned int tRHW; 44193db446aSBoris Brezillon unsigned int tR; 44293db446aSBoris Brezillon }; 44393db446aSBoris Brezillon 44493db446aSBoris Brezillon /** 44593db446aSBoris Brezillon * Derives a duration in numbers of clock cycles. 44693db446aSBoris Brezillon * 44793db446aSBoris Brezillon * @ps: Duration in pico-seconds 44893db446aSBoris Brezillon * @period_ns: Clock period in nano-seconds 44993db446aSBoris Brezillon * 45093db446aSBoris Brezillon * Convert the duration in nano-seconds, then divide by the period and 45193db446aSBoris Brezillon * return the number of clock periods. 45293db446aSBoris Brezillon */ 45393db446aSBoris Brezillon #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns)) 45493db446aSBoris Brezillon #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \ 45593db446aSBoris Brezillon period_ns)) 45693db446aSBoris Brezillon 45793db446aSBoris Brezillon /** 45893db446aSBoris Brezillon * NAND driver structure filled during the parsing of the ->exec_op() subop 45993db446aSBoris Brezillon * subset of instructions. 46093db446aSBoris Brezillon * 46193db446aSBoris Brezillon * @ndcb: Array of values written to NDCBx registers 46293db446aSBoris Brezillon * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle 46393db446aSBoris Brezillon * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin 46493db446aSBoris Brezillon * @rdy_delay_ns: Optional delay after waiting for the RB pin 46593db446aSBoris Brezillon * @data_delay_ns: Optional delay after the data xfer 46693db446aSBoris Brezillon * @data_instr_idx: Index of the data instruction in the subop 46793db446aSBoris Brezillon * @data_instr: Pointer to the data instruction in the subop 46893db446aSBoris Brezillon */ 46993db446aSBoris Brezillon struct marvell_nfc_op { 47093db446aSBoris Brezillon u32 ndcb[4]; 47193db446aSBoris Brezillon unsigned int cle_ale_delay_ns; 47293db446aSBoris Brezillon unsigned int rdy_timeout_ms; 47393db446aSBoris Brezillon unsigned int rdy_delay_ns; 47493db446aSBoris Brezillon unsigned int data_delay_ns; 47593db446aSBoris Brezillon unsigned int data_instr_idx; 47693db446aSBoris Brezillon const struct nand_op_instr *data_instr; 47793db446aSBoris Brezillon }; 47893db446aSBoris Brezillon 47993db446aSBoris Brezillon /* 48093db446aSBoris Brezillon * Internal helper to conditionnally apply a delay (from the above structure, 48193db446aSBoris Brezillon * most of the time). 48293db446aSBoris Brezillon */ 48393db446aSBoris Brezillon static void cond_delay(unsigned int ns) 48493db446aSBoris Brezillon { 48593db446aSBoris Brezillon if (!ns) 48693db446aSBoris Brezillon return; 48793db446aSBoris Brezillon 48893db446aSBoris Brezillon if (ns < 10000) 48993db446aSBoris Brezillon ndelay(ns); 49093db446aSBoris Brezillon else 49193db446aSBoris Brezillon udelay(DIV_ROUND_UP(ns, 1000)); 49293db446aSBoris Brezillon } 49393db446aSBoris Brezillon 49493db446aSBoris Brezillon /* 49593db446aSBoris Brezillon * The controller has many flags that could generate interrupts, most of them 49693db446aSBoris Brezillon * are disabled and polling is used. For the very slow signals, using interrupts 49793db446aSBoris Brezillon * may relax the CPU charge. 49893db446aSBoris Brezillon */ 49993db446aSBoris Brezillon static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask) 50093db446aSBoris Brezillon { 50193db446aSBoris Brezillon u32 reg; 50293db446aSBoris Brezillon 50393db446aSBoris Brezillon /* Writing 1 disables the interrupt */ 50493db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 50593db446aSBoris Brezillon writel_relaxed(reg | int_mask, nfc->regs + NDCR); 50693db446aSBoris Brezillon } 50793db446aSBoris Brezillon 50893db446aSBoris Brezillon static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask) 50993db446aSBoris Brezillon { 51093db446aSBoris Brezillon u32 reg; 51193db446aSBoris Brezillon 51293db446aSBoris Brezillon /* Writing 0 enables the interrupt */ 51393db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 51493db446aSBoris Brezillon writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); 51593db446aSBoris Brezillon } 51693db446aSBoris Brezillon 51793db446aSBoris Brezillon static void marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask) 51893db446aSBoris Brezillon { 51993db446aSBoris Brezillon writel_relaxed(int_mask, nfc->regs + NDSR); 52093db446aSBoris Brezillon } 52193db446aSBoris Brezillon 52293db446aSBoris Brezillon static void marvell_nfc_force_byte_access(struct nand_chip *chip, 52393db446aSBoris Brezillon bool force_8bit) 52493db446aSBoris Brezillon { 52593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 52693db446aSBoris Brezillon u32 ndcr; 52793db446aSBoris Brezillon 52893db446aSBoris Brezillon /* 52993db446aSBoris Brezillon * Callers of this function do not verify if the NAND is using a 16-bit 53093db446aSBoris Brezillon * an 8-bit bus for normal operations, so we need to take care of that 53193db446aSBoris Brezillon * here by leaving the configuration unchanged if the NAND does not have 53293db446aSBoris Brezillon * the NAND_BUSWIDTH_16 flag set. 53393db446aSBoris Brezillon */ 53493db446aSBoris Brezillon if (!(chip->options & NAND_BUSWIDTH_16)) 53593db446aSBoris Brezillon return; 53693db446aSBoris Brezillon 53793db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 53893db446aSBoris Brezillon 53993db446aSBoris Brezillon if (force_8bit) 54093db446aSBoris Brezillon ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C); 54193db446aSBoris Brezillon else 54293db446aSBoris Brezillon ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 54393db446aSBoris Brezillon 54493db446aSBoris Brezillon writel_relaxed(ndcr, nfc->regs + NDCR); 54593db446aSBoris Brezillon } 54693db446aSBoris Brezillon 54793db446aSBoris Brezillon static int marvell_nfc_wait_ndrun(struct nand_chip *chip) 54893db446aSBoris Brezillon { 54993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 55093db446aSBoris Brezillon u32 val; 55193db446aSBoris Brezillon int ret; 55293db446aSBoris Brezillon 55393db446aSBoris Brezillon /* 55493db446aSBoris Brezillon * The command is being processed, wait for the ND_RUN bit to be 55593db446aSBoris Brezillon * cleared by the NFC. If not, we must clear it by hand. 55693db446aSBoris Brezillon */ 55793db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, 55893db446aSBoris Brezillon (val & NDCR_ND_RUN) == 0, 55993db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 56093db446aSBoris Brezillon if (ret) { 56193db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); 56293db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 56393db446aSBoris Brezillon nfc->regs + NDCR); 56493db446aSBoris Brezillon return ret; 56593db446aSBoris Brezillon } 56693db446aSBoris Brezillon 56793db446aSBoris Brezillon return 0; 56893db446aSBoris Brezillon } 56993db446aSBoris Brezillon 57093db446aSBoris Brezillon /* 57193db446aSBoris Brezillon * Any time a command has to be sent to the controller, the following sequence 57293db446aSBoris Brezillon * has to be followed: 57393db446aSBoris Brezillon * - call marvell_nfc_prepare_cmd() 57493db446aSBoris Brezillon * -> activate the ND_RUN bit that will kind of 'start a job' 57593db446aSBoris Brezillon * -> wait the signal indicating the NFC is waiting for a command 57693db446aSBoris Brezillon * - send the command (cmd and address cycles) 57793db446aSBoris Brezillon * - enventually send or receive the data 57893db446aSBoris Brezillon * - call marvell_nfc_end_cmd() with the corresponding flag 57993db446aSBoris Brezillon * -> wait the flag to be triggered or cancel the job with a timeout 58093db446aSBoris Brezillon * 58193db446aSBoris Brezillon * The following helpers are here to factorize the code a bit so that 58293db446aSBoris Brezillon * specialized functions responsible for executing the actual NAND 58393db446aSBoris Brezillon * operations do not have to replicate the same code blocks. 58493db446aSBoris Brezillon */ 58593db446aSBoris Brezillon static int marvell_nfc_prepare_cmd(struct nand_chip *chip) 58693db446aSBoris Brezillon { 58793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 58893db446aSBoris Brezillon u32 ndcr, val; 58993db446aSBoris Brezillon int ret; 59093db446aSBoris Brezillon 59193db446aSBoris Brezillon /* Poll ND_RUN and clear NDSR before issuing any command */ 59293db446aSBoris Brezillon ret = marvell_nfc_wait_ndrun(chip); 59393db446aSBoris Brezillon if (ret) { 59493db446aSBoris Brezillon dev_err(nfc->dev, "Last operation did not succeed\n"); 59593db446aSBoris Brezillon return ret; 59693db446aSBoris Brezillon } 59793db446aSBoris Brezillon 59893db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 59993db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); 60093db446aSBoris Brezillon 60193db446aSBoris Brezillon /* Assert ND_RUN bit and wait the NFC to be ready */ 60293db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); 60393db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 60493db446aSBoris Brezillon val & NDSR_WRCMDREQ, 60593db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 60693db446aSBoris Brezillon if (ret) { 60793db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on WRCMDRE\n"); 60893db446aSBoris Brezillon return -ETIMEDOUT; 60993db446aSBoris Brezillon } 61093db446aSBoris Brezillon 61193db446aSBoris Brezillon /* Command may be written, clear WRCMDREQ status bit */ 61293db446aSBoris Brezillon writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); 61393db446aSBoris Brezillon 61493db446aSBoris Brezillon return 0; 61593db446aSBoris Brezillon } 61693db446aSBoris Brezillon 61793db446aSBoris Brezillon static void marvell_nfc_send_cmd(struct nand_chip *chip, 61893db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 61993db446aSBoris Brezillon { 62093db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 62193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 62293db446aSBoris Brezillon 62393db446aSBoris Brezillon dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" 62493db446aSBoris Brezillon "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n", 62593db446aSBoris Brezillon (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], 62693db446aSBoris Brezillon nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); 62793db446aSBoris Brezillon 62893db446aSBoris Brezillon writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], 62993db446aSBoris Brezillon nfc->regs + NDCB0); 63093db446aSBoris Brezillon writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); 63193db446aSBoris Brezillon writel(nfc_op->ndcb[2], nfc->regs + NDCB0); 63293db446aSBoris Brezillon 63393db446aSBoris Brezillon /* 63493db446aSBoris Brezillon * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7 63593db446aSBoris Brezillon * fields are used (only available on NFCv2). 63693db446aSBoris Brezillon */ 63793db446aSBoris Brezillon if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || 63893db446aSBoris Brezillon NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { 63993db446aSBoris Brezillon if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) 64093db446aSBoris Brezillon writel(nfc_op->ndcb[3], nfc->regs + NDCB0); 64193db446aSBoris Brezillon } 64293db446aSBoris Brezillon } 64393db446aSBoris Brezillon 64493db446aSBoris Brezillon static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag, 64593db446aSBoris Brezillon const char *label) 64693db446aSBoris Brezillon { 64793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 64893db446aSBoris Brezillon u32 val; 64993db446aSBoris Brezillon int ret; 65093db446aSBoris Brezillon 65193db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 65293db446aSBoris Brezillon val & flag, 65393db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 65493db446aSBoris Brezillon 65593db446aSBoris Brezillon if (ret) { 65693db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", 65793db446aSBoris Brezillon label, val); 65893db446aSBoris Brezillon if (nfc->dma_chan) 65993db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 66093db446aSBoris Brezillon return ret; 66193db446aSBoris Brezillon } 66293db446aSBoris Brezillon 66393db446aSBoris Brezillon /* 66493db446aSBoris Brezillon * DMA function uses this helper to poll on CMDD bits without wanting 66593db446aSBoris Brezillon * them to be cleared. 66693db446aSBoris Brezillon */ 66793db446aSBoris Brezillon if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) 66893db446aSBoris Brezillon return 0; 66993db446aSBoris Brezillon 67093db446aSBoris Brezillon writel_relaxed(flag, nfc->regs + NDSR); 67193db446aSBoris Brezillon 67293db446aSBoris Brezillon return 0; 67393db446aSBoris Brezillon } 67493db446aSBoris Brezillon 67593db446aSBoris Brezillon static int marvell_nfc_wait_cmdd(struct nand_chip *chip) 67693db446aSBoris Brezillon { 67793db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 67893db446aSBoris Brezillon int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); 67993db446aSBoris Brezillon 68093db446aSBoris Brezillon return marvell_nfc_end_cmd(chip, cs_flag, "CMDD"); 68193db446aSBoris Brezillon } 68293db446aSBoris Brezillon 68393db446aSBoris Brezillon static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms) 68493db446aSBoris Brezillon { 68593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 68693db446aSBoris Brezillon int ret; 68793db446aSBoris Brezillon 68893db446aSBoris Brezillon /* Timeout is expressed in ms */ 68993db446aSBoris Brezillon if (!timeout_ms) 69093db446aSBoris Brezillon timeout_ms = IRQ_TIMEOUT; 69193db446aSBoris Brezillon 69293db446aSBoris Brezillon init_completion(&nfc->complete); 69393db446aSBoris Brezillon 69493db446aSBoris Brezillon marvell_nfc_enable_int(nfc, NDCR_RDYM); 69593db446aSBoris Brezillon ret = wait_for_completion_timeout(&nfc->complete, 69693db446aSBoris Brezillon msecs_to_jiffies(timeout_ms)); 69793db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_RDYM); 69893db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1)); 69993db446aSBoris Brezillon if (!ret) { 70093db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for RB signal\n"); 70193db446aSBoris Brezillon return -ETIMEDOUT; 70293db446aSBoris Brezillon } 70393db446aSBoris Brezillon 70493db446aSBoris Brezillon return 0; 70593db446aSBoris Brezillon } 70693db446aSBoris Brezillon 707758b56f5SBoris Brezillon static void marvell_nfc_select_chip(struct nand_chip *chip, int die_nr) 70893db446aSBoris Brezillon { 70993db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 71093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 71193db446aSBoris Brezillon u32 ndcr_generic; 71293db446aSBoris Brezillon 71393db446aSBoris Brezillon if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) 71493db446aSBoris Brezillon return; 71593db446aSBoris Brezillon 71693db446aSBoris Brezillon if (die_nr < 0 || die_nr >= marvell_nand->nsels) { 71793db446aSBoris Brezillon nfc->selected_chip = NULL; 71893db446aSBoris Brezillon marvell_nand->selected_die = -1; 71993db446aSBoris Brezillon return; 72093db446aSBoris Brezillon } 72193db446aSBoris Brezillon 72293db446aSBoris Brezillon writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); 72393db446aSBoris Brezillon writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); 72493db446aSBoris Brezillon 72593db446aSBoris Brezillon /* 72693db446aSBoris Brezillon * Reset the NDCR register to a clean state for this particular chip, 72793db446aSBoris Brezillon * also clear ND_RUN bit. 72893db446aSBoris Brezillon */ 72993db446aSBoris Brezillon ndcr_generic = readl_relaxed(nfc->regs + NDCR) & 73093db446aSBoris Brezillon NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN; 73193db446aSBoris Brezillon writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); 73293db446aSBoris Brezillon 73393db446aSBoris Brezillon /* Also reset the interrupt status register */ 73493db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 73593db446aSBoris Brezillon 73693db446aSBoris Brezillon nfc->selected_chip = chip; 73793db446aSBoris Brezillon marvell_nand->selected_die = die_nr; 73893db446aSBoris Brezillon } 73993db446aSBoris Brezillon 74093db446aSBoris Brezillon static irqreturn_t marvell_nfc_isr(int irq, void *dev_id) 74193db446aSBoris Brezillon { 74293db446aSBoris Brezillon struct marvell_nfc *nfc = dev_id; 74393db446aSBoris Brezillon u32 st = readl_relaxed(nfc->regs + NDSR); 74493db446aSBoris Brezillon u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; 74593db446aSBoris Brezillon 74693db446aSBoris Brezillon /* 74793db446aSBoris Brezillon * RDY interrupt mask is one bit in NDCR while there are two status 74893db446aSBoris Brezillon * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]). 74993db446aSBoris Brezillon */ 75093db446aSBoris Brezillon if (st & NDSR_RDY(1)) 75193db446aSBoris Brezillon st |= NDSR_RDY(0); 75293db446aSBoris Brezillon 75393db446aSBoris Brezillon if (!(st & ien)) 75493db446aSBoris Brezillon return IRQ_NONE; 75593db446aSBoris Brezillon 75693db446aSBoris Brezillon marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT); 75793db446aSBoris Brezillon 75893db446aSBoris Brezillon if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ))) 75993db446aSBoris Brezillon complete(&nfc->complete); 76093db446aSBoris Brezillon 76193db446aSBoris Brezillon return IRQ_HANDLED; 76293db446aSBoris Brezillon } 76393db446aSBoris Brezillon 76493db446aSBoris Brezillon /* HW ECC related functions */ 76593db446aSBoris Brezillon static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip) 76693db446aSBoris Brezillon { 76793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 76893db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 76993db446aSBoris Brezillon 77093db446aSBoris Brezillon if (!(ndcr & NDCR_ECC_EN)) { 77193db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); 77293db446aSBoris Brezillon 77393db446aSBoris Brezillon /* 77493db446aSBoris Brezillon * When enabling BCH, set threshold to 0 to always know the 77593db446aSBoris Brezillon * number of corrected bitflips. 77693db446aSBoris Brezillon */ 77793db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 77893db446aSBoris Brezillon writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); 77993db446aSBoris Brezillon } 78093db446aSBoris Brezillon } 78193db446aSBoris Brezillon 78293db446aSBoris Brezillon static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip) 78393db446aSBoris Brezillon { 78493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 78593db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 78693db446aSBoris Brezillon 78793db446aSBoris Brezillon if (ndcr & NDCR_ECC_EN) { 78893db446aSBoris Brezillon writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); 78993db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 79093db446aSBoris Brezillon writel_relaxed(0, nfc->regs + NDECCCTRL); 79193db446aSBoris Brezillon } 79293db446aSBoris Brezillon } 79393db446aSBoris Brezillon 79493db446aSBoris Brezillon /* DMA related helpers */ 79593db446aSBoris Brezillon static void marvell_nfc_enable_dma(struct marvell_nfc *nfc) 79693db446aSBoris Brezillon { 79793db446aSBoris Brezillon u32 reg; 79893db446aSBoris Brezillon 79993db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 80093db446aSBoris Brezillon writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); 80193db446aSBoris Brezillon } 80293db446aSBoris Brezillon 80393db446aSBoris Brezillon static void marvell_nfc_disable_dma(struct marvell_nfc *nfc) 80493db446aSBoris Brezillon { 80593db446aSBoris Brezillon u32 reg; 80693db446aSBoris Brezillon 80793db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 80893db446aSBoris Brezillon writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); 80993db446aSBoris Brezillon } 81093db446aSBoris Brezillon 81193db446aSBoris Brezillon /* Read/write PIO/DMA accessors */ 81293db446aSBoris Brezillon static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc, 81393db446aSBoris Brezillon enum dma_data_direction direction, 81493db446aSBoris Brezillon unsigned int len) 81593db446aSBoris Brezillon { 81693db446aSBoris Brezillon unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE); 81793db446aSBoris Brezillon struct dma_async_tx_descriptor *tx; 81893db446aSBoris Brezillon struct scatterlist sg; 81993db446aSBoris Brezillon dma_cookie_t cookie; 82093db446aSBoris Brezillon int ret; 82193db446aSBoris Brezillon 82293db446aSBoris Brezillon marvell_nfc_enable_dma(nfc); 82393db446aSBoris Brezillon /* Prepare the DMA transfer */ 82493db446aSBoris Brezillon sg_init_one(&sg, nfc->dma_buf, dma_len); 82593db446aSBoris Brezillon dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 82693db446aSBoris Brezillon tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, 82793db446aSBoris Brezillon direction == DMA_FROM_DEVICE ? 82893db446aSBoris Brezillon DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 82993db446aSBoris Brezillon DMA_PREP_INTERRUPT); 83093db446aSBoris Brezillon if (!tx) { 83193db446aSBoris Brezillon dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); 83293db446aSBoris Brezillon return -ENXIO; 83393db446aSBoris Brezillon } 83493db446aSBoris Brezillon 83593db446aSBoris Brezillon /* Do the task and wait for it to finish */ 83693db446aSBoris Brezillon cookie = dmaengine_submit(tx); 83793db446aSBoris Brezillon ret = dma_submit_error(cookie); 83893db446aSBoris Brezillon if (ret) 83993db446aSBoris Brezillon return -EIO; 84093db446aSBoris Brezillon 84193db446aSBoris Brezillon dma_async_issue_pending(nfc->dma_chan); 84293db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(nfc->selected_chip); 84393db446aSBoris Brezillon dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 84493db446aSBoris Brezillon marvell_nfc_disable_dma(nfc); 84593db446aSBoris Brezillon if (ret) { 84693db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", 84793db446aSBoris Brezillon dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); 84893db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 84993db446aSBoris Brezillon return -ETIMEDOUT; 85093db446aSBoris Brezillon } 85193db446aSBoris Brezillon 85293db446aSBoris Brezillon return 0; 85393db446aSBoris Brezillon } 85493db446aSBoris Brezillon 85593db446aSBoris Brezillon static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in, 85693db446aSBoris Brezillon unsigned int len) 85793db446aSBoris Brezillon { 85893db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 85993db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 86093db446aSBoris Brezillon int i; 86193db446aSBoris Brezillon 86293db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 86393db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); 86493db446aSBoris Brezillon 86593db446aSBoris Brezillon if (last_len) { 86693db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 86793db446aSBoris Brezillon 86893db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 86993db446aSBoris Brezillon memcpy(in + last_full_offset, tmp_buf, last_len); 87093db446aSBoris Brezillon } 87193db446aSBoris Brezillon 87293db446aSBoris Brezillon return 0; 87393db446aSBoris Brezillon } 87493db446aSBoris Brezillon 87593db446aSBoris Brezillon static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out, 87693db446aSBoris Brezillon unsigned int len) 87793db446aSBoris Brezillon { 87893db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 87993db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 88093db446aSBoris Brezillon int i; 88193db446aSBoris Brezillon 88293db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 88393db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); 88493db446aSBoris Brezillon 88593db446aSBoris Brezillon if (last_len) { 88693db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 88793db446aSBoris Brezillon 88893db446aSBoris Brezillon memcpy(tmp_buf, out + last_full_offset, last_len); 88993db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 89093db446aSBoris Brezillon } 89193db446aSBoris Brezillon 89293db446aSBoris Brezillon return 0; 89393db446aSBoris Brezillon } 89493db446aSBoris Brezillon 89593db446aSBoris Brezillon static void marvell_nfc_check_empty_chunk(struct nand_chip *chip, 89693db446aSBoris Brezillon u8 *data, int data_len, 89793db446aSBoris Brezillon u8 *spare, int spare_len, 89893db446aSBoris Brezillon u8 *ecc, int ecc_len, 89993db446aSBoris Brezillon unsigned int *max_bitflips) 90093db446aSBoris Brezillon { 90193db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 90293db446aSBoris Brezillon int bf; 90393db446aSBoris Brezillon 90493db446aSBoris Brezillon /* 90593db446aSBoris Brezillon * Blank pages (all 0xFF) that have not been written may be recognized 90693db446aSBoris Brezillon * as bad if bitflips occur, so whenever an uncorrectable error occurs, 90793db446aSBoris Brezillon * check if the entire page (with ECC bytes) is actually blank or not. 90893db446aSBoris Brezillon */ 90993db446aSBoris Brezillon if (!data) 91093db446aSBoris Brezillon data_len = 0; 91193db446aSBoris Brezillon if (!spare) 91293db446aSBoris Brezillon spare_len = 0; 91393db446aSBoris Brezillon if (!ecc) 91493db446aSBoris Brezillon ecc_len = 0; 91593db446aSBoris Brezillon 91693db446aSBoris Brezillon bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len, 91793db446aSBoris Brezillon spare, spare_len, chip->ecc.strength); 91893db446aSBoris Brezillon if (bf < 0) { 91993db446aSBoris Brezillon mtd->ecc_stats.failed++; 92093db446aSBoris Brezillon return; 92193db446aSBoris Brezillon } 92293db446aSBoris Brezillon 92393db446aSBoris Brezillon /* Update the stats and max_bitflips */ 92493db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 92593db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 92693db446aSBoris Brezillon } 92793db446aSBoris Brezillon 92893db446aSBoris Brezillon /* 92993db446aSBoris Brezillon * Check a chunk is correct or not according to hardware ECC engine. 93093db446aSBoris Brezillon * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however 93193db446aSBoris Brezillon * mtd->ecc_stats.failure is not, the function will instead return a non-zero 93293db446aSBoris Brezillon * value indicating that a check on the emptyness of the subpage must be 93393db446aSBoris Brezillon * performed before declaring the subpage corrupted. 93493db446aSBoris Brezillon */ 93593db446aSBoris Brezillon static int marvell_nfc_hw_ecc_correct(struct nand_chip *chip, 93693db446aSBoris Brezillon unsigned int *max_bitflips) 93793db446aSBoris Brezillon { 93893db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 93993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 94093db446aSBoris Brezillon int bf = 0; 94193db446aSBoris Brezillon u32 ndsr; 94293db446aSBoris Brezillon 94393db446aSBoris Brezillon ndsr = readl_relaxed(nfc->regs + NDSR); 94493db446aSBoris Brezillon 94593db446aSBoris Brezillon /* Check uncorrectable error flag */ 94693db446aSBoris Brezillon if (ndsr & NDSR_UNCERR) { 94793db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 94893db446aSBoris Brezillon 94993db446aSBoris Brezillon /* 95093db446aSBoris Brezillon * Do not increment ->ecc_stats.failed now, instead, return a 95193db446aSBoris Brezillon * non-zero value to indicate that this chunk was apparently 95293db446aSBoris Brezillon * bad, and it should be check to see if it empty or not. If 95393db446aSBoris Brezillon * the chunk (with ECC bytes) is not declared empty, the calling 95493db446aSBoris Brezillon * function must increment the failure count. 95593db446aSBoris Brezillon */ 95693db446aSBoris Brezillon return -EBADMSG; 95793db446aSBoris Brezillon } 95893db446aSBoris Brezillon 95993db446aSBoris Brezillon /* Check correctable error flag */ 96093db446aSBoris Brezillon if (ndsr & NDSR_CORERR) { 96193db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 96293db446aSBoris Brezillon 96393db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 96493db446aSBoris Brezillon bf = NDSR_ERRCNT(ndsr); 96593db446aSBoris Brezillon else 96693db446aSBoris Brezillon bf = 1; 96793db446aSBoris Brezillon } 96893db446aSBoris Brezillon 96993db446aSBoris Brezillon /* Update the stats and max_bitflips */ 97093db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 97193db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 97293db446aSBoris Brezillon 97393db446aSBoris Brezillon return 0; 97493db446aSBoris Brezillon } 97593db446aSBoris Brezillon 97693db446aSBoris Brezillon /* Hamming read helpers */ 97793db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip, 97893db446aSBoris Brezillon u8 *data_buf, u8 *oob_buf, 97993db446aSBoris Brezillon bool raw, int page) 98093db446aSBoris Brezillon { 98193db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 98293db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 98393db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 98493db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 98593db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 98693db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 98793db446aSBoris Brezillon NDCB0_DBC | 98893db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 98993db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART), 99093db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 99193db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 99293db446aSBoris Brezillon }; 99393db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 99493db446aSBoris Brezillon int ret; 99593db446aSBoris Brezillon 99693db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 99793db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 99893db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 99993db446aSBoris Brezillon 100093db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 100193db446aSBoris Brezillon if (ret) 100293db446aSBoris Brezillon return ret; 100393db446aSBoris Brezillon 100493db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 100593db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 100693db446aSBoris Brezillon "RDDREQ while draining FIFO (data/oob)"); 100793db446aSBoris Brezillon if (ret) 100893db446aSBoris Brezillon return ret; 100993db446aSBoris Brezillon 101093db446aSBoris Brezillon /* 101193db446aSBoris Brezillon * Read the page then the OOB area. Unlike what is shown in current 101293db446aSBoris Brezillon * documentation, spare bytes are protected by the ECC engine, and must 101393db446aSBoris Brezillon * be at the beginning of the OOB area or running this driver on legacy 101493db446aSBoris Brezillon * systems will prevent the discovery of the BBM/BBT. 101593db446aSBoris Brezillon */ 101693db446aSBoris Brezillon if (nfc->use_dma) { 101793db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE, 101893db446aSBoris Brezillon lt->data_bytes + oob_bytes); 101993db446aSBoris Brezillon memcpy(data_buf, nfc->dma_buf, lt->data_bytes); 102093db446aSBoris Brezillon memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); 102193db446aSBoris Brezillon } else { 102293db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); 102393db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes); 102493db446aSBoris Brezillon } 102593db446aSBoris Brezillon 102693db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 102793db446aSBoris Brezillon 102893db446aSBoris Brezillon return ret; 102993db446aSBoris Brezillon } 103093db446aSBoris Brezillon 1031b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf, 103293db446aSBoris Brezillon int oob_required, int page) 103393db446aSBoris Brezillon { 103493db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, 103593db446aSBoris Brezillon true, page); 103693db446aSBoris Brezillon } 103793db446aSBoris Brezillon 1038b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf, 1039b9761687SBoris Brezillon int oob_required, int page) 104093db446aSBoris Brezillon { 104193db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 104293db446aSBoris Brezillon unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 104393db446aSBoris Brezillon int max_bitflips = 0, ret; 104493db446aSBoris Brezillon u8 *raw_buf; 104593db446aSBoris Brezillon 104693db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 104793db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, 104893db446aSBoris Brezillon page); 104993db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips); 105093db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 105193db446aSBoris Brezillon 105293db446aSBoris Brezillon if (!ret) 105393db446aSBoris Brezillon return max_bitflips; 105493db446aSBoris Brezillon 105593db446aSBoris Brezillon /* 105693db446aSBoris Brezillon * When ECC failures are detected, check if the full page has been 105793db446aSBoris Brezillon * written or not. Ignore the failure if it is actually empty. 105893db446aSBoris Brezillon */ 105993db446aSBoris Brezillon raw_buf = kmalloc(full_sz, GFP_KERNEL); 106093db446aSBoris Brezillon if (!raw_buf) 106193db446aSBoris Brezillon return -ENOMEM; 106293db446aSBoris Brezillon 106393db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf + 106493db446aSBoris Brezillon lt->data_bytes, true, page); 106593db446aSBoris Brezillon marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0, 106693db446aSBoris Brezillon &max_bitflips); 106793db446aSBoris Brezillon kfree(raw_buf); 106893db446aSBoris Brezillon 106993db446aSBoris Brezillon return max_bitflips; 107093db446aSBoris Brezillon } 107193db446aSBoris Brezillon 107293db446aSBoris Brezillon /* 107393db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 107493db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->read_oob_raw() function 107593db446aSBoris Brezillon * also stands for ->read_oob(). 107693db446aSBoris Brezillon */ 1077b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page) 107893db446aSBoris Brezillon { 107993db446aSBoris Brezillon /* Invalidate page cache */ 108093db446aSBoris Brezillon chip->pagebuf = -1; 108193db446aSBoris Brezillon 108293db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, chip->data_buf, 108393db446aSBoris Brezillon chip->oob_poi, true, page); 108493db446aSBoris Brezillon } 108593db446aSBoris Brezillon 108693db446aSBoris Brezillon /* Hamming write helpers */ 108793db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip, 108893db446aSBoris Brezillon const u8 *data_buf, 108993db446aSBoris Brezillon const u8 *oob_buf, bool raw, 109093db446aSBoris Brezillon int page) 109193db446aSBoris Brezillon { 109293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 109393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 109493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 109593db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 109693db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | 109793db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 109893db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN) | 109993db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_PAGEPROG) | 110093db446aSBoris Brezillon NDCB0_DBC, 110193db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 110293db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 110393db446aSBoris Brezillon }; 110493db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 110593db446aSBoris Brezillon int ret; 110693db446aSBoris Brezillon 110793db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 110893db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 110993db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 111093db446aSBoris Brezillon 111193db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 111293db446aSBoris Brezillon if (ret) 111393db446aSBoris Brezillon return ret; 111493db446aSBoris Brezillon 111593db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 111693db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 111793db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 111893db446aSBoris Brezillon if (ret) 111993db446aSBoris Brezillon return ret; 112093db446aSBoris Brezillon 112193db446aSBoris Brezillon /* Write the page then the OOB area */ 112293db446aSBoris Brezillon if (nfc->use_dma) { 112393db446aSBoris Brezillon memcpy(nfc->dma_buf, data_buf, lt->data_bytes); 112493db446aSBoris Brezillon memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); 112593db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + 112693db446aSBoris Brezillon lt->ecc_bytes + lt->spare_bytes); 112793db446aSBoris Brezillon } else { 112893db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); 112993db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes); 113093db446aSBoris Brezillon } 113193db446aSBoris Brezillon 113293db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 113393db446aSBoris Brezillon if (ret) 113493db446aSBoris Brezillon return ret; 113593db446aSBoris Brezillon 113693db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, 1137b76401fcSChris Packham PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); 113893db446aSBoris Brezillon return ret; 113993db446aSBoris Brezillon } 114093db446aSBoris Brezillon 1141767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip, 114293db446aSBoris Brezillon const u8 *buf, 114393db446aSBoris Brezillon int oob_required, int page) 114493db446aSBoris Brezillon { 114593db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 114693db446aSBoris Brezillon true, page); 114793db446aSBoris Brezillon } 114893db446aSBoris Brezillon 1149767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip, 115093db446aSBoris Brezillon const u8 *buf, 115193db446aSBoris Brezillon int oob_required, int page) 115293db446aSBoris Brezillon { 115393db446aSBoris Brezillon int ret; 115493db446aSBoris Brezillon 115593db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 115693db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 115793db446aSBoris Brezillon false, page); 115893db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 115993db446aSBoris Brezillon 116093db446aSBoris Brezillon return ret; 116193db446aSBoris Brezillon } 116293db446aSBoris Brezillon 116393db446aSBoris Brezillon /* 116493db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 116593db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->write_oob_raw() function 116693db446aSBoris Brezillon * also stands for ->write_oob(). 116793db446aSBoris Brezillon */ 1168767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip, 116993db446aSBoris Brezillon int page) 117093db446aSBoris Brezillon { 1171767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1172767eb6fbSBoris Brezillon 117393db446aSBoris Brezillon /* Invalidate page cache */ 117493db446aSBoris Brezillon chip->pagebuf = -1; 117593db446aSBoris Brezillon 117693db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 117793db446aSBoris Brezillon 117893db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, chip->data_buf, 117993db446aSBoris Brezillon chip->oob_poi, true, page); 118093db446aSBoris Brezillon } 118193db446aSBoris Brezillon 118293db446aSBoris Brezillon /* BCH read helpers */ 1183b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf, 118493db446aSBoris Brezillon int oob_required, int page) 118593db446aSBoris Brezillon { 1186b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 118793db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 118893db446aSBoris Brezillon u8 *oob = chip->oob_poi; 118993db446aSBoris Brezillon int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 119093db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 119193db446aSBoris Brezillon lt->last_spare_bytes; 119293db446aSBoris Brezillon int data_len = lt->data_bytes; 119393db446aSBoris Brezillon int spare_len = lt->spare_bytes; 119493db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 119593db446aSBoris Brezillon int chunk; 119693db446aSBoris Brezillon 119793db446aSBoris Brezillon if (oob_required) 119893db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 119993db446aSBoris Brezillon 120093db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0); 120193db446aSBoris Brezillon 120293db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 120393db446aSBoris Brezillon /* Update last chunk length */ 120493db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 120593db446aSBoris Brezillon data_len = lt->last_data_bytes; 120693db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 120793db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 120893db446aSBoris Brezillon } 120993db446aSBoris Brezillon 121093db446aSBoris Brezillon /* Read data bytes*/ 121193db446aSBoris Brezillon nand_change_read_column_op(chip, chunk * chunk_size, 121293db446aSBoris Brezillon buf + (lt->data_bytes * chunk), 121393db446aSBoris Brezillon data_len, false); 121493db446aSBoris Brezillon 121593db446aSBoris Brezillon /* Read spare bytes */ 121693db446aSBoris Brezillon nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), 121793db446aSBoris Brezillon spare_len, false); 121893db446aSBoris Brezillon 121993db446aSBoris Brezillon /* Read ECC bytes */ 122093db446aSBoris Brezillon nand_read_data_op(chip, oob + ecc_offset + 122193db446aSBoris Brezillon (ALIGN(lt->ecc_bytes, 32) * chunk), 122293db446aSBoris Brezillon ecc_len, false); 122393db446aSBoris Brezillon } 122493db446aSBoris Brezillon 122593db446aSBoris Brezillon return 0; 122693db446aSBoris Brezillon } 122793db446aSBoris Brezillon 122893db446aSBoris Brezillon static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk, 122993db446aSBoris Brezillon u8 *data, unsigned int data_len, 123093db446aSBoris Brezillon u8 *spare, unsigned int spare_len, 123193db446aSBoris Brezillon int page) 123293db446aSBoris Brezillon { 123393db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 123493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 123593db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 123693db446aSBoris Brezillon int i, ret; 123793db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 123893db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 123993db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 124093db446aSBoris Brezillon NDCB0_LEN_OVRD, 124193db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 124293db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 124393db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 124493db446aSBoris Brezillon }; 124593db446aSBoris Brezillon 124693db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 124793db446aSBoris Brezillon if (ret) 124893db446aSBoris Brezillon return; 124993db446aSBoris Brezillon 125093db446aSBoris Brezillon if (chunk == 0) 125193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_DBC | 125293db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 125393db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART); 125493db446aSBoris Brezillon 125593db446aSBoris Brezillon /* 125690d61763SBoris Brezillon * Trigger the monolithic read on the first chunk, then naked read on 125790d61763SBoris Brezillon * intermediate chunks and finally a last naked read on the last chunk. 125893db446aSBoris Brezillon */ 125990d61763SBoris Brezillon if (chunk == 0) 126093db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 126190d61763SBoris Brezillon else if (chunk < lt->nchunks - 1) 126290d61763SBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 126393db446aSBoris Brezillon else 126493db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 126593db446aSBoris Brezillon 126693db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 126793db446aSBoris Brezillon 126893db446aSBoris Brezillon /* 126993db446aSBoris Brezillon * According to the datasheet, when reading from NDDB 127093db446aSBoris Brezillon * with BCH enabled, after each 32 bytes reads, we 127193db446aSBoris Brezillon * have to make sure that the NDSR.RDDREQ bit is set. 127293db446aSBoris Brezillon * 127393db446aSBoris Brezillon * Drain the FIFO, 8 32-bit reads at a time, and skip 127493db446aSBoris Brezillon * the polling on the last read. 127593db446aSBoris Brezillon * 127693db446aSBoris Brezillon * Length is a multiple of 32 bytes, hence it is a multiple of 8 too. 127793db446aSBoris Brezillon */ 127893db446aSBoris Brezillon for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 127993db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 128093db446aSBoris Brezillon "RDDREQ while draining FIFO (data)"); 128193db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data, 128293db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 128393db446aSBoris Brezillon data += FIFO_DEPTH * BCH_SEQ_READS; 128493db446aSBoris Brezillon } 128593db446aSBoris Brezillon 128693db446aSBoris Brezillon for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 128793db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 128893db446aSBoris Brezillon "RDDREQ while draining FIFO (OOB)"); 128993db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, spare, 129093db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 129193db446aSBoris Brezillon spare += FIFO_DEPTH * BCH_SEQ_READS; 129293db446aSBoris Brezillon } 129393db446aSBoris Brezillon } 129493db446aSBoris Brezillon 1295b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip, 129693db446aSBoris Brezillon u8 *buf, int oob_required, 129793db446aSBoris Brezillon int page) 129893db446aSBoris Brezillon { 1299b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 130093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1301dbfc6718SMiquel Raynal int data_len = lt->data_bytes, spare_len = lt->spare_bytes; 1302dbfc6718SMiquel Raynal u8 *data = buf, *spare = chip->oob_poi; 130393db446aSBoris Brezillon int max_bitflips = 0; 130493db446aSBoris Brezillon u32 failure_mask = 0; 1305dbfc6718SMiquel Raynal int chunk, ret; 130693db446aSBoris Brezillon 130793db446aSBoris Brezillon /* 130893db446aSBoris Brezillon * With BCH, OOB is not fully used (and thus not read entirely), not 130993db446aSBoris Brezillon * expected bytes could show up at the end of the OOB buffer if not 131093db446aSBoris Brezillon * explicitly erased. 131193db446aSBoris Brezillon */ 131293db446aSBoris Brezillon if (oob_required) 131393db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 131493db446aSBoris Brezillon 131593db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 131693db446aSBoris Brezillon 131793db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 131893db446aSBoris Brezillon /* Update length for the last chunk */ 131993db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 132093db446aSBoris Brezillon data_len = lt->last_data_bytes; 132193db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 132293db446aSBoris Brezillon } 132393db446aSBoris Brezillon 132493db446aSBoris Brezillon /* Read the chunk and detect number of bitflips */ 132593db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len, 132693db446aSBoris Brezillon spare, spare_len, page); 132793db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips); 132893db446aSBoris Brezillon if (ret) 132993db446aSBoris Brezillon failure_mask |= BIT(chunk); 133093db446aSBoris Brezillon 133193db446aSBoris Brezillon data += data_len; 133293db446aSBoris Brezillon spare += spare_len; 133393db446aSBoris Brezillon } 133493db446aSBoris Brezillon 133593db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 133693db446aSBoris Brezillon 133793db446aSBoris Brezillon if (!failure_mask) 133893db446aSBoris Brezillon return max_bitflips; 133993db446aSBoris Brezillon 134093db446aSBoris Brezillon /* 134193db446aSBoris Brezillon * Please note that dumping the ECC bytes during a normal read with OOB 134293db446aSBoris Brezillon * area would add a significant overhead as ECC bytes are "consumed" by 134393db446aSBoris Brezillon * the controller in normal mode and must be re-read in raw mode. To 134493db446aSBoris Brezillon * avoid dropping the performances, we prefer not to include them. The 134593db446aSBoris Brezillon * user should re-read the page in raw mode if ECC bytes are required. 1346dbfc6718SMiquel Raynal */ 1347dbfc6718SMiquel Raynal 1348dbfc6718SMiquel Raynal /* 1349dbfc6718SMiquel Raynal * In case there is any subpage read error reported by ->correct(), we 1350dbfc6718SMiquel Raynal * usually re-read only ECC bytes in raw mode and check if the whole 1351dbfc6718SMiquel Raynal * page is empty. In this case, it is normal that the ECC check failed 1352dbfc6718SMiquel Raynal * and we just ignore the error. 135393db446aSBoris Brezillon * 13547fd130f7SMiquel Raynal * However, it has been empirically observed that for some layouts (e.g 13557fd130f7SMiquel Raynal * 2k page, 8b strength per 512B chunk), the controller tries to correct 13567fd130f7SMiquel Raynal * bits and may create itself bitflips in the erased area. To overcome 13577fd130f7SMiquel Raynal * this strange behavior, the whole page is re-read in raw mode, not 13587fd130f7SMiquel Raynal * only the ECC bytes. 135993db446aSBoris Brezillon */ 136093db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 1361dbfc6718SMiquel Raynal int data_off_in_page, spare_off_in_page, ecc_off_in_page; 1362dbfc6718SMiquel Raynal int data_off, spare_off, ecc_off; 1363dbfc6718SMiquel Raynal int data_len, spare_len, ecc_len; 1364dbfc6718SMiquel Raynal 136593db446aSBoris Brezillon /* No failure reported for this chunk, move to the next one */ 136693db446aSBoris Brezillon if (!(failure_mask & BIT(chunk))) 136793db446aSBoris Brezillon continue; 136893db446aSBoris Brezillon 1369dbfc6718SMiquel Raynal data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + 1370dbfc6718SMiquel Raynal lt->ecc_bytes); 1371dbfc6718SMiquel Raynal spare_off_in_page = data_off_in_page + 1372dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->data_bytes : 1373dbfc6718SMiquel Raynal lt->last_data_bytes); 1374dbfc6718SMiquel Raynal ecc_off_in_page = spare_off_in_page + 1375dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1376dbfc6718SMiquel Raynal lt->last_spare_bytes); 1377dbfc6718SMiquel Raynal 1378dbfc6718SMiquel Raynal data_off = chunk * lt->data_bytes; 1379dbfc6718SMiquel Raynal spare_off = chunk * lt->spare_bytes; 1380dbfc6718SMiquel Raynal ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + 138193db446aSBoris Brezillon lt->last_spare_bytes + 1382dbfc6718SMiquel Raynal (chunk * (lt->ecc_bytes + 2)); 138393db446aSBoris Brezillon 1384dbfc6718SMiquel Raynal data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : 1385dbfc6718SMiquel Raynal lt->last_data_bytes; 1386dbfc6718SMiquel Raynal spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1387dbfc6718SMiquel Raynal lt->last_spare_bytes; 1388dbfc6718SMiquel Raynal ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : 1389dbfc6718SMiquel Raynal lt->last_ecc_bytes; 139093db446aSBoris Brezillon 13917fd130f7SMiquel Raynal /* 13927fd130f7SMiquel Raynal * Only re-read the ECC bytes, unless we are using the 2k/8b 13937fd130f7SMiquel Raynal * layout which is buggy in the sense that the ECC engine will 13947fd130f7SMiquel Raynal * try to correct data bytes anyway, creating bitflips. In this 13957fd130f7SMiquel Raynal * case, re-read the entire page. 13967fd130f7SMiquel Raynal */ 13977fd130f7SMiquel Raynal if (lt->writesize == 2048 && lt->strength == 8) { 13987fd130f7SMiquel Raynal nand_change_read_column_op(chip, data_off_in_page, 13997fd130f7SMiquel Raynal buf + data_off, data_len, 14007fd130f7SMiquel Raynal false); 14017fd130f7SMiquel Raynal nand_change_read_column_op(chip, spare_off_in_page, 14027fd130f7SMiquel Raynal chip->oob_poi + spare_off, spare_len, 14037fd130f7SMiquel Raynal false); 14047fd130f7SMiquel Raynal } 14057fd130f7SMiquel Raynal 1406dbfc6718SMiquel Raynal nand_change_read_column_op(chip, ecc_off_in_page, 1407dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len, 1408dbfc6718SMiquel Raynal false); 140993db446aSBoris Brezillon 141093db446aSBoris Brezillon /* Check the entire chunk (data + spare + ecc) for emptyness */ 1411dbfc6718SMiquel Raynal marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len, 1412dbfc6718SMiquel Raynal chip->oob_poi + spare_off, spare_len, 1413dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len, 141493db446aSBoris Brezillon &max_bitflips); 141593db446aSBoris Brezillon } 141693db446aSBoris Brezillon 141793db446aSBoris Brezillon return max_bitflips; 141893db446aSBoris Brezillon } 141993db446aSBoris Brezillon 1420b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page) 142193db446aSBoris Brezillon { 142293db446aSBoris Brezillon /* Invalidate page cache */ 142393db446aSBoris Brezillon chip->pagebuf = -1; 142493db446aSBoris Brezillon 1425b9761687SBoris Brezillon return chip->ecc.read_page_raw(chip, chip->data_buf, true, page); 142693db446aSBoris Brezillon } 142793db446aSBoris Brezillon 1428b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page) 142993db446aSBoris Brezillon { 143093db446aSBoris Brezillon /* Invalidate page cache */ 143193db446aSBoris Brezillon chip->pagebuf = -1; 143293db446aSBoris Brezillon 1433b9761687SBoris Brezillon return chip->ecc.read_page(chip, chip->data_buf, true, page); 143493db446aSBoris Brezillon } 143593db446aSBoris Brezillon 143693db446aSBoris Brezillon /* BCH write helpers */ 1437767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip, 143893db446aSBoris Brezillon const u8 *buf, 143993db446aSBoris Brezillon int oob_required, int page) 144093db446aSBoris Brezillon { 144193db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 144293db446aSBoris Brezillon int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 144393db446aSBoris Brezillon int data_len = lt->data_bytes; 144493db446aSBoris Brezillon int spare_len = lt->spare_bytes; 144593db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 144693db446aSBoris Brezillon int spare_offset = 0; 144793db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 144893db446aSBoris Brezillon lt->last_spare_bytes; 144993db446aSBoris Brezillon int chunk; 145093db446aSBoris Brezillon 145193db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0); 145293db446aSBoris Brezillon 145393db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 145493db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 145593db446aSBoris Brezillon data_len = lt->last_data_bytes; 145693db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 145793db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 145893db446aSBoris Brezillon } 145993db446aSBoris Brezillon 146093db446aSBoris Brezillon /* Point to the column of the next chunk */ 146193db446aSBoris Brezillon nand_change_write_column_op(chip, chunk * full_chunk_size, 146293db446aSBoris Brezillon NULL, 0, false); 146393db446aSBoris Brezillon 146493db446aSBoris Brezillon /* Write the data */ 146593db446aSBoris Brezillon nand_write_data_op(chip, buf + (chunk * lt->data_bytes), 146693db446aSBoris Brezillon data_len, false); 146793db446aSBoris Brezillon 146893db446aSBoris Brezillon if (!oob_required) 146993db446aSBoris Brezillon continue; 147093db446aSBoris Brezillon 147193db446aSBoris Brezillon /* Write the spare bytes */ 147293db446aSBoris Brezillon if (spare_len) 147393db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + spare_offset, 147493db446aSBoris Brezillon spare_len, false); 147593db446aSBoris Brezillon 147693db446aSBoris Brezillon /* Write the ECC bytes */ 147793db446aSBoris Brezillon if (ecc_len) 147893db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + ecc_offset, 147993db446aSBoris Brezillon ecc_len, false); 148093db446aSBoris Brezillon 148193db446aSBoris Brezillon spare_offset += spare_len; 148293db446aSBoris Brezillon ecc_offset += ALIGN(ecc_len, 32); 148393db446aSBoris Brezillon } 148493db446aSBoris Brezillon 148593db446aSBoris Brezillon return nand_prog_page_end_op(chip); 148693db446aSBoris Brezillon } 148793db446aSBoris Brezillon 148893db446aSBoris Brezillon static int 148993db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, 149093db446aSBoris Brezillon const u8 *data, unsigned int data_len, 149193db446aSBoris Brezillon const u8 *spare, unsigned int spare_len, 149293db446aSBoris Brezillon int page) 149393db446aSBoris Brezillon { 149493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 149593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 149693db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1497a2ee41fdSMiquel Raynal u32 xtype; 149893db446aSBoris Brezillon int ret; 149993db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 150093db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD, 150193db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 150293db446aSBoris Brezillon }; 150393db446aSBoris Brezillon 150493db446aSBoris Brezillon /* 150593db446aSBoris Brezillon * First operation dispatches the CMD_SEQIN command, issue the address 150693db446aSBoris Brezillon * cycles and asks for the first chunk of data. 150793db446aSBoris Brezillon * All operations in the middle (if any) will issue a naked write and 150893db446aSBoris Brezillon * also ask for data. 150993db446aSBoris Brezillon * Last operation (if any) asks for the last chunk of data through a 151093db446aSBoris Brezillon * last naked write. 151193db446aSBoris Brezillon */ 151293db446aSBoris Brezillon if (chunk == 0) { 1513a2ee41fdSMiquel Raynal if (lt->nchunks == 1) 1514a2ee41fdSMiquel Raynal xtype = XTYPE_MONOLITHIC_RW; 1515a2ee41fdSMiquel Raynal else 1516a2ee41fdSMiquel Raynal xtype = XTYPE_WRITE_DISPATCH; 1517a2ee41fdSMiquel Raynal 1518a2ee41fdSMiquel Raynal nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | 151993db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 152093db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN); 152193db446aSBoris Brezillon nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page); 152293db446aSBoris Brezillon nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page); 152393db446aSBoris Brezillon } else if (chunk < lt->nchunks - 1) { 152493db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 152593db446aSBoris Brezillon } else { 152693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 152793db446aSBoris Brezillon } 152893db446aSBoris Brezillon 152993db446aSBoris Brezillon /* Always dispatch the PAGEPROG command on the last chunk */ 153093db446aSBoris Brezillon if (chunk == lt->nchunks - 1) 153193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC; 153293db446aSBoris Brezillon 153393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 153493db446aSBoris Brezillon if (ret) 153593db446aSBoris Brezillon return ret; 153693db446aSBoris Brezillon 153793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 153893db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 153993db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 154093db446aSBoris Brezillon if (ret) 154193db446aSBoris Brezillon return ret; 154293db446aSBoris Brezillon 154393db446aSBoris Brezillon /* Transfer the contents */ 154493db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); 154593db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); 154693db446aSBoris Brezillon 154793db446aSBoris Brezillon return 0; 154893db446aSBoris Brezillon } 154993db446aSBoris Brezillon 1550767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip, 155193db446aSBoris Brezillon const u8 *buf, 155293db446aSBoris Brezillon int oob_required, int page) 155393db446aSBoris Brezillon { 1554767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 155593db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 155693db446aSBoris Brezillon const u8 *data = buf; 155793db446aSBoris Brezillon const u8 *spare = chip->oob_poi; 155893db446aSBoris Brezillon int data_len = lt->data_bytes; 155993db446aSBoris Brezillon int spare_len = lt->spare_bytes; 156093db446aSBoris Brezillon int chunk, ret; 156193db446aSBoris Brezillon 156293db446aSBoris Brezillon /* Spare data will be written anyway, so clear it to avoid garbage */ 156393db446aSBoris Brezillon if (!oob_required) 156493db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 156593db446aSBoris Brezillon 156693db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 156793db446aSBoris Brezillon 156893db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 156993db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 157093db446aSBoris Brezillon data_len = lt->last_data_bytes; 157193db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 157293db446aSBoris Brezillon } 157393db446aSBoris Brezillon 157493db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len, 157593db446aSBoris Brezillon spare, spare_len, page); 157693db446aSBoris Brezillon data += data_len; 157793db446aSBoris Brezillon spare += spare_len; 157893db446aSBoris Brezillon 157993db446aSBoris Brezillon /* 158093db446aSBoris Brezillon * Waiting only for CMDD or PAGED is not enough, ECC are 158193db446aSBoris Brezillon * partially written. No flag is set once the operation is 158293db446aSBoris Brezillon * really finished but the ND_RUN bit is cleared, so wait for it 158393db446aSBoris Brezillon * before stepping into the next command. 158493db446aSBoris Brezillon */ 158593db446aSBoris Brezillon marvell_nfc_wait_ndrun(chip); 158693db446aSBoris Brezillon } 158793db446aSBoris Brezillon 158893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, 1589b76401fcSChris Packham PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); 159093db446aSBoris Brezillon 159193db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 159293db446aSBoris Brezillon 159393db446aSBoris Brezillon if (ret) 159493db446aSBoris Brezillon return ret; 159593db446aSBoris Brezillon 159693db446aSBoris Brezillon return 0; 159793db446aSBoris Brezillon } 159893db446aSBoris Brezillon 1599767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip, 160093db446aSBoris Brezillon int page) 160193db446aSBoris Brezillon { 1602767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1603767eb6fbSBoris Brezillon 160493db446aSBoris Brezillon /* Invalidate page cache */ 160593db446aSBoris Brezillon chip->pagebuf = -1; 160693db446aSBoris Brezillon 160793db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 160893db446aSBoris Brezillon 1609767eb6fbSBoris Brezillon return chip->ecc.write_page_raw(chip, chip->data_buf, true, page); 161093db446aSBoris Brezillon } 161193db446aSBoris Brezillon 1612767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page) 161393db446aSBoris Brezillon { 1614767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1615767eb6fbSBoris Brezillon 161693db446aSBoris Brezillon /* Invalidate page cache */ 161793db446aSBoris Brezillon chip->pagebuf = -1; 161893db446aSBoris Brezillon 161993db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 162093db446aSBoris Brezillon 1621767eb6fbSBoris Brezillon return chip->ecc.write_page(chip, chip->data_buf, true, page); 162293db446aSBoris Brezillon } 162393db446aSBoris Brezillon 162493db446aSBoris Brezillon /* NAND framework ->exec_op() hooks and related helpers */ 162593db446aSBoris Brezillon static void marvell_nfc_parse_instructions(struct nand_chip *chip, 162693db446aSBoris Brezillon const struct nand_subop *subop, 162793db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 162893db446aSBoris Brezillon { 162993db446aSBoris Brezillon const struct nand_op_instr *instr = NULL; 163093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 163193db446aSBoris Brezillon bool first_cmd = true; 163293db446aSBoris Brezillon unsigned int op_id; 163393db446aSBoris Brezillon int i; 163493db446aSBoris Brezillon 163593db446aSBoris Brezillon /* Reset the input structure as most of its fields will be OR'ed */ 163693db446aSBoris Brezillon memset(nfc_op, 0, sizeof(struct marvell_nfc_op)); 163793db446aSBoris Brezillon 163893db446aSBoris Brezillon for (op_id = 0; op_id < subop->ninstrs; op_id++) { 163993db446aSBoris Brezillon unsigned int offset, naddrs; 164093db446aSBoris Brezillon const u8 *addrs; 164193db446aSBoris Brezillon int len = nand_subop_get_data_len(subop, op_id); 164293db446aSBoris Brezillon 164393db446aSBoris Brezillon instr = &subop->instrs[op_id]; 164493db446aSBoris Brezillon 164593db446aSBoris Brezillon switch (instr->type) { 164693db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 164793db446aSBoris Brezillon if (first_cmd) 164893db446aSBoris Brezillon nfc_op->ndcb[0] |= 164993db446aSBoris Brezillon NDCB0_CMD1(instr->ctx.cmd.opcode); 165093db446aSBoris Brezillon else 165193db446aSBoris Brezillon nfc_op->ndcb[0] |= 165293db446aSBoris Brezillon NDCB0_CMD2(instr->ctx.cmd.opcode) | 165393db446aSBoris Brezillon NDCB0_DBC; 165493db446aSBoris Brezillon 165593db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 165693db446aSBoris Brezillon first_cmd = false; 165793db446aSBoris Brezillon break; 165893db446aSBoris Brezillon 165993db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 166093db446aSBoris Brezillon offset = nand_subop_get_addr_start_off(subop, op_id); 166193db446aSBoris Brezillon naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 166293db446aSBoris Brezillon addrs = &instr->ctx.addr.addrs[offset]; 166393db446aSBoris Brezillon 166493db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); 166593db446aSBoris Brezillon 166693db446aSBoris Brezillon for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) 166793db446aSBoris Brezillon nfc_op->ndcb[1] |= addrs[i] << (8 * i); 166893db446aSBoris Brezillon 166993db446aSBoris Brezillon if (naddrs >= 5) 167093db446aSBoris Brezillon nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); 167193db446aSBoris Brezillon if (naddrs >= 6) 167293db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); 167393db446aSBoris Brezillon if (naddrs == 7) 167493db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); 167593db446aSBoris Brezillon 167693db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 167793db446aSBoris Brezillon break; 167893db446aSBoris Brezillon 167993db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 168093db446aSBoris Brezillon nfc_op->data_instr = instr; 168193db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 168293db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); 168393db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 168493db446aSBoris Brezillon nfc_op->ndcb[0] |= 168593db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 168693db446aSBoris Brezillon NDCB0_LEN_OVRD; 168793db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 168893db446aSBoris Brezillon } 168993db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 169093db446aSBoris Brezillon break; 169193db446aSBoris Brezillon 169293db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 169393db446aSBoris Brezillon nfc_op->data_instr = instr; 169493db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 169593db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); 169693db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 169793db446aSBoris Brezillon nfc_op->ndcb[0] |= 169893db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 169993db446aSBoris Brezillon NDCB0_LEN_OVRD; 170093db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 170193db446aSBoris Brezillon } 170293db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 170393db446aSBoris Brezillon break; 170493db446aSBoris Brezillon 170593db446aSBoris Brezillon case NAND_OP_WAITRDY_INSTR: 170693db446aSBoris Brezillon nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; 170793db446aSBoris Brezillon nfc_op->rdy_delay_ns = instr->delay_ns; 170893db446aSBoris Brezillon break; 170993db446aSBoris Brezillon } 171093db446aSBoris Brezillon } 171193db446aSBoris Brezillon } 171293db446aSBoris Brezillon 171393db446aSBoris Brezillon static int marvell_nfc_xfer_data_pio(struct nand_chip *chip, 171493db446aSBoris Brezillon const struct nand_subop *subop, 171593db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 171693db446aSBoris Brezillon { 171793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 171893db446aSBoris Brezillon const struct nand_op_instr *instr = nfc_op->data_instr; 171993db446aSBoris Brezillon unsigned int op_id = nfc_op->data_instr_idx; 172093db446aSBoris Brezillon unsigned int len = nand_subop_get_data_len(subop, op_id); 172193db446aSBoris Brezillon unsigned int offset = nand_subop_get_data_start_off(subop, op_id); 172293db446aSBoris Brezillon bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); 172393db446aSBoris Brezillon int ret; 172493db446aSBoris Brezillon 172593db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 172693db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, true); 172793db446aSBoris Brezillon 172893db446aSBoris Brezillon if (reading) { 172993db446aSBoris Brezillon u8 *in = instr->ctx.data.buf.in + offset; 173093db446aSBoris Brezillon 173193db446aSBoris Brezillon ret = marvell_nfc_xfer_data_in_pio(nfc, in, len); 173293db446aSBoris Brezillon } else { 173393db446aSBoris Brezillon const u8 *out = instr->ctx.data.buf.out + offset; 173493db446aSBoris Brezillon 173593db446aSBoris Brezillon ret = marvell_nfc_xfer_data_out_pio(nfc, out, len); 173693db446aSBoris Brezillon } 173793db446aSBoris Brezillon 173893db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 173993db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, false); 174093db446aSBoris Brezillon 174193db446aSBoris Brezillon return ret; 174293db446aSBoris Brezillon } 174393db446aSBoris Brezillon 174493db446aSBoris Brezillon static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip, 174593db446aSBoris Brezillon const struct nand_subop *subop) 174693db446aSBoris Brezillon { 174793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 174893db446aSBoris Brezillon bool reading; 174993db446aSBoris Brezillon int ret; 175093db446aSBoris Brezillon 175193db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 175293db446aSBoris Brezillon reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); 175393db446aSBoris Brezillon 175493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 175593db446aSBoris Brezillon if (ret) 175693db446aSBoris Brezillon return ret; 175793db446aSBoris Brezillon 175893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 175993db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 176093db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 176193db446aSBoris Brezillon if (ret) 176293db446aSBoris Brezillon return ret; 176393db446aSBoris Brezillon 176493db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 176593db446aSBoris Brezillon 176693db446aSBoris Brezillon if (reading) { 176793db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 176893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 176993db446aSBoris Brezillon if (ret) 177093db446aSBoris Brezillon return ret; 177193db446aSBoris Brezillon } 177293db446aSBoris Brezillon 177393db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 177493db446aSBoris Brezillon } 177593db446aSBoris Brezillon 177693db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 177793db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 177893db446aSBoris Brezillon if (ret) 177993db446aSBoris Brezillon return ret; 178093db446aSBoris Brezillon 178193db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 178293db446aSBoris Brezillon 178393db446aSBoris Brezillon if (!reading) { 178493db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 178593db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 178693db446aSBoris Brezillon if (ret) 178793db446aSBoris Brezillon return ret; 178893db446aSBoris Brezillon } 178993db446aSBoris Brezillon 179093db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 179193db446aSBoris Brezillon } 179293db446aSBoris Brezillon 179393db446aSBoris Brezillon /* 179493db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 179593db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 179693db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 179793db446aSBoris Brezillon */ 179893db446aSBoris Brezillon if (!reading) { 179993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 180093db446aSBoris Brezillon 180193db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 180293db446aSBoris Brezillon nfc->regs + NDCR); 180393db446aSBoris Brezillon } 180493db446aSBoris Brezillon 180593db446aSBoris Brezillon return 0; 180693db446aSBoris Brezillon } 180793db446aSBoris Brezillon 180893db446aSBoris Brezillon static int marvell_nfc_naked_access_exec(struct nand_chip *chip, 180993db446aSBoris Brezillon const struct nand_subop *subop) 181093db446aSBoris Brezillon { 181193db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 181293db446aSBoris Brezillon int ret; 181393db446aSBoris Brezillon 181493db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 181593db446aSBoris Brezillon 181693db446aSBoris Brezillon /* 181793db446aSBoris Brezillon * Naked access are different in that they need to be flagged as naked 181893db446aSBoris Brezillon * by the controller. Reset the controller registers fields that inform 181993db446aSBoris Brezillon * on the type and refill them according to the ongoing operation. 182093db446aSBoris Brezillon */ 182193db446aSBoris Brezillon nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) | 182293db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MASK)); 182393db446aSBoris Brezillon switch (subop->instrs[0].type) { 182493db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 182593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD); 182693db446aSBoris Brezillon break; 182793db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 182893db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR); 182993db446aSBoris Brezillon break; 183093db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 183193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) | 183293db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 183393db446aSBoris Brezillon break; 183493db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 183593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) | 183693db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 183793db446aSBoris Brezillon break; 183893db446aSBoris Brezillon default: 183993db446aSBoris Brezillon /* This should never happen */ 184093db446aSBoris Brezillon break; 184193db446aSBoris Brezillon } 184293db446aSBoris Brezillon 184393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 184493db446aSBoris Brezillon if (ret) 184593db446aSBoris Brezillon return ret; 184693db446aSBoris Brezillon 184793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 184893db446aSBoris Brezillon 184993db446aSBoris Brezillon if (!nfc_op.data_instr) { 185093db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 185193db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 185293db446aSBoris Brezillon return ret; 185393db446aSBoris Brezillon } 185493db446aSBoris Brezillon 185593db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 185693db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 185793db446aSBoris Brezillon if (ret) 185893db446aSBoris Brezillon return ret; 185993db446aSBoris Brezillon 186093db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 186193db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 186293db446aSBoris Brezillon if (ret) 186393db446aSBoris Brezillon return ret; 186493db446aSBoris Brezillon 186593db446aSBoris Brezillon /* 186693db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 186793db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 186893db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 186993db446aSBoris Brezillon */ 187093db446aSBoris Brezillon if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { 187193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 187293db446aSBoris Brezillon 187393db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 187493db446aSBoris Brezillon nfc->regs + NDCR); 187593db446aSBoris Brezillon } 187693db446aSBoris Brezillon 187793db446aSBoris Brezillon return 0; 187893db446aSBoris Brezillon } 187993db446aSBoris Brezillon 188093db446aSBoris Brezillon static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip, 188193db446aSBoris Brezillon const struct nand_subop *subop) 188293db446aSBoris Brezillon { 188393db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 188493db446aSBoris Brezillon int ret; 188593db446aSBoris Brezillon 188693db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 188793db446aSBoris Brezillon 188893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 188993db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 189093db446aSBoris Brezillon 189193db446aSBoris Brezillon return ret; 189293db446aSBoris Brezillon } 189393db446aSBoris Brezillon 189493db446aSBoris Brezillon static int marvell_nfc_read_id_type_exec(struct nand_chip *chip, 189593db446aSBoris Brezillon const struct nand_subop *subop) 189693db446aSBoris Brezillon { 189793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 189893db446aSBoris Brezillon int ret; 189993db446aSBoris Brezillon 190093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 190193db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 190293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID); 190393db446aSBoris Brezillon 190493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 190593db446aSBoris Brezillon if (ret) 190693db446aSBoris Brezillon return ret; 190793db446aSBoris Brezillon 190893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 190993db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 191093db446aSBoris Brezillon "RDDREQ while reading ID"); 191193db446aSBoris Brezillon if (ret) 191293db446aSBoris Brezillon return ret; 191393db446aSBoris Brezillon 191493db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 191593db446aSBoris Brezillon 191693db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 191793db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 191893db446aSBoris Brezillon if (ret) 191993db446aSBoris Brezillon return ret; 192093db446aSBoris Brezillon } 192193db446aSBoris Brezillon 192293db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 192393db446aSBoris Brezillon 192493db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 192593db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 192693db446aSBoris Brezillon if (ret) 192793db446aSBoris Brezillon return ret; 192893db446aSBoris Brezillon 192993db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 193093db446aSBoris Brezillon 193193db446aSBoris Brezillon return 0; 193293db446aSBoris Brezillon } 193393db446aSBoris Brezillon 193493db446aSBoris Brezillon static int marvell_nfc_read_status_exec(struct nand_chip *chip, 193593db446aSBoris Brezillon const struct nand_subop *subop) 193693db446aSBoris Brezillon { 193793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 193893db446aSBoris Brezillon int ret; 193993db446aSBoris Brezillon 194093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 194193db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 194293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS); 194393db446aSBoris Brezillon 194493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 194593db446aSBoris Brezillon if (ret) 194693db446aSBoris Brezillon return ret; 194793db446aSBoris Brezillon 194893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 194993db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 195093db446aSBoris Brezillon "RDDREQ while reading status"); 195193db446aSBoris Brezillon if (ret) 195293db446aSBoris Brezillon return ret; 195393db446aSBoris Brezillon 195493db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 195593db446aSBoris Brezillon 195693db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 195793db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 195893db446aSBoris Brezillon if (ret) 195993db446aSBoris Brezillon return ret; 196093db446aSBoris Brezillon } 196193db446aSBoris Brezillon 196293db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 196393db446aSBoris Brezillon 196493db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 196593db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 196693db446aSBoris Brezillon if (ret) 196793db446aSBoris Brezillon return ret; 196893db446aSBoris Brezillon 196993db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 197093db446aSBoris Brezillon 197193db446aSBoris Brezillon return 0; 197293db446aSBoris Brezillon } 197393db446aSBoris Brezillon 197493db446aSBoris Brezillon static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip, 197593db446aSBoris Brezillon const struct nand_subop *subop) 197693db446aSBoris Brezillon { 197793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 197893db446aSBoris Brezillon int ret; 197993db446aSBoris Brezillon 198093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 198193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET); 198293db446aSBoris Brezillon 198393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 198493db446aSBoris Brezillon if (ret) 198593db446aSBoris Brezillon return ret; 198693db446aSBoris Brezillon 198793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 198893db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 198993db446aSBoris Brezillon if (ret) 199093db446aSBoris Brezillon return ret; 199193db446aSBoris Brezillon 199293db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 199393db446aSBoris Brezillon 199493db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 199593db446aSBoris Brezillon if (ret) 199693db446aSBoris Brezillon return ret; 199793db446aSBoris Brezillon 199893db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 199993db446aSBoris Brezillon 200093db446aSBoris Brezillon return 0; 200193db446aSBoris Brezillon } 200293db446aSBoris Brezillon 200393db446aSBoris Brezillon static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip, 200493db446aSBoris Brezillon const struct nand_subop *subop) 200593db446aSBoris Brezillon { 200693db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 200793db446aSBoris Brezillon int ret; 200893db446aSBoris Brezillon 200993db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 201093db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE); 201193db446aSBoris Brezillon 201293db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 201393db446aSBoris Brezillon if (ret) 201493db446aSBoris Brezillon return ret; 201593db446aSBoris Brezillon 201693db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 201793db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 201893db446aSBoris Brezillon if (ret) 201993db446aSBoris Brezillon return ret; 202093db446aSBoris Brezillon 202193db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 202293db446aSBoris Brezillon 202393db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 202493db446aSBoris Brezillon if (ret) 202593db446aSBoris Brezillon return ret; 202693db446aSBoris Brezillon 202793db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 202893db446aSBoris Brezillon 202993db446aSBoris Brezillon return 0; 203093db446aSBoris Brezillon } 203193db446aSBoris Brezillon 203293db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER( 203393db446aSBoris Brezillon /* Monolithic reads/writes */ 203493db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 203593db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 203693db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 203793db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2), 203893db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 203993db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 204093db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 204193db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 204293db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 204393db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 204493db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2), 204593db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE), 204693db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 204793db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 204893db446aSBoris Brezillon /* Naked commands */ 204993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 205093db446aSBoris Brezillon marvell_nfc_naked_access_exec, 205193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false)), 205293db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 205393db446aSBoris Brezillon marvell_nfc_naked_access_exec, 205493db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)), 205593db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 205693db446aSBoris Brezillon marvell_nfc_naked_access_exec, 205793db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 205893db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 205993db446aSBoris Brezillon marvell_nfc_naked_access_exec, 206093db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)), 206193db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 206293db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 206393db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 206493db446aSBoris Brezillon ); 206593db446aSBoris Brezillon 206693db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER( 206793db446aSBoris Brezillon /* Naked commands not supported, use a function for each pattern */ 206893db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 206993db446aSBoris Brezillon marvell_nfc_read_id_type_exec, 207093db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 207193db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 207293db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), 207393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 207493db446aSBoris Brezillon marvell_nfc_erase_cmd_type_exec, 207593db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 207693db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 207793db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 207893db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 207993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 208093db446aSBoris Brezillon marvell_nfc_read_status_exec, 208193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 208293db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), 208393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 208493db446aSBoris Brezillon marvell_nfc_reset_cmd_type_exec, 208593db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 208693db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 208793db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 208893db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 208993db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 209093db446aSBoris Brezillon ); 209193db446aSBoris Brezillon 209293db446aSBoris Brezillon static int marvell_nfc_exec_op(struct nand_chip *chip, 209393db446aSBoris Brezillon const struct nand_operation *op, 209493db446aSBoris Brezillon bool check_only) 209593db446aSBoris Brezillon { 209693db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 209793db446aSBoris Brezillon 209893db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 209993db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser, 210093db446aSBoris Brezillon op, check_only); 210193db446aSBoris Brezillon else 210293db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser, 210393db446aSBoris Brezillon op, check_only); 210493db446aSBoris Brezillon } 210593db446aSBoris Brezillon 210693db446aSBoris Brezillon /* 210793db446aSBoris Brezillon * Layouts were broken in old pxa3xx_nand driver, these are supposed to be 210893db446aSBoris Brezillon * usable. 210993db446aSBoris Brezillon */ 211093db446aSBoris Brezillon static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section, 211193db446aSBoris Brezillon struct mtd_oob_region *oobregion) 211293db446aSBoris Brezillon { 211393db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 211493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 211593db446aSBoris Brezillon 211693db446aSBoris Brezillon if (section) 211793db446aSBoris Brezillon return -ERANGE; 211893db446aSBoris Brezillon 211993db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + 212093db446aSBoris Brezillon lt->last_ecc_bytes; 212193db446aSBoris Brezillon oobregion->offset = mtd->oobsize - oobregion->length; 212293db446aSBoris Brezillon 212393db446aSBoris Brezillon return 0; 212493db446aSBoris Brezillon } 212593db446aSBoris Brezillon 212693db446aSBoris Brezillon static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section, 212793db446aSBoris Brezillon struct mtd_oob_region *oobregion) 212893db446aSBoris Brezillon { 212993db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 213093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 213193db446aSBoris Brezillon 213293db446aSBoris Brezillon if (section) 213393db446aSBoris Brezillon return -ERANGE; 213493db446aSBoris Brezillon 213593db446aSBoris Brezillon /* 213693db446aSBoris Brezillon * Bootrom looks in bytes 0 & 5 for bad blocks for the 213793db446aSBoris Brezillon * 4KB page / 4bit BCH combination. 213893db446aSBoris Brezillon */ 213993db446aSBoris Brezillon if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) 214093db446aSBoris Brezillon oobregion->offset = 6; 214193db446aSBoris Brezillon else 214293db446aSBoris Brezillon oobregion->offset = 2; 214393db446aSBoris Brezillon 214493db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + 214593db446aSBoris Brezillon lt->last_spare_bytes - oobregion->offset; 214693db446aSBoris Brezillon 214793db446aSBoris Brezillon return 0; 214893db446aSBoris Brezillon } 214993db446aSBoris Brezillon 215093db446aSBoris Brezillon static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = { 215193db446aSBoris Brezillon .ecc = marvell_nand_ooblayout_ecc, 215293db446aSBoris Brezillon .free = marvell_nand_ooblayout_free, 215393db446aSBoris Brezillon }; 215493db446aSBoris Brezillon 215593db446aSBoris Brezillon static int marvell_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, 215693db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 215793db446aSBoris Brezillon { 215893db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 215993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 216093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *l; 216193db446aSBoris Brezillon int i; 216293db446aSBoris Brezillon 216393db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && 216493db446aSBoris Brezillon (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { 216593db446aSBoris Brezillon dev_err(nfc->dev, 216693db446aSBoris Brezillon "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n", 216793db446aSBoris Brezillon mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); 216893db446aSBoris Brezillon return -ENOTSUPP; 216993db446aSBoris Brezillon } 217093db446aSBoris Brezillon 217193db446aSBoris Brezillon to_marvell_nand(chip)->layout = NULL; 217293db446aSBoris Brezillon for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) { 217393db446aSBoris Brezillon l = &marvell_nfc_layouts[i]; 217493db446aSBoris Brezillon if (mtd->writesize == l->writesize && 217593db446aSBoris Brezillon ecc->size == l->chunk && ecc->strength == l->strength) { 217693db446aSBoris Brezillon to_marvell_nand(chip)->layout = l; 217793db446aSBoris Brezillon break; 217893db446aSBoris Brezillon } 217993db446aSBoris Brezillon } 218093db446aSBoris Brezillon 218193db446aSBoris Brezillon if (!to_marvell_nand(chip)->layout || 218293db446aSBoris Brezillon (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { 218393db446aSBoris Brezillon dev_err(nfc->dev, 218493db446aSBoris Brezillon "ECC strength %d at page size %d is not supported\n", 218593db446aSBoris Brezillon ecc->strength, mtd->writesize); 218693db446aSBoris Brezillon return -ENOTSUPP; 218793db446aSBoris Brezillon } 218893db446aSBoris Brezillon 21897fd130f7SMiquel Raynal /* Special care for the layout 2k/8-bit/512B */ 21907fd130f7SMiquel Raynal if (l->writesize == 2048 && l->strength == 8) { 21917fd130f7SMiquel Raynal if (mtd->oobsize < 128) { 21927fd130f7SMiquel Raynal dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n"); 21937fd130f7SMiquel Raynal return -ENOTSUPP; 21947fd130f7SMiquel Raynal } else { 21957fd130f7SMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 21967fd130f7SMiquel Raynal } 21977fd130f7SMiquel Raynal } 21987fd130f7SMiquel Raynal 219993db446aSBoris Brezillon mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops); 220093db446aSBoris Brezillon ecc->steps = l->nchunks; 220193db446aSBoris Brezillon ecc->size = l->data_bytes; 220293db446aSBoris Brezillon 220393db446aSBoris Brezillon if (ecc->strength == 1) { 220493db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_HAMMING; 220593db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; 220693db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; 220793db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; 220893db446aSBoris Brezillon ecc->read_oob = ecc->read_oob_raw; 220993db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; 221093db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; 221193db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; 221293db446aSBoris Brezillon ecc->write_oob = ecc->write_oob_raw; 221393db446aSBoris Brezillon } else { 221493db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_BCH; 221593db446aSBoris Brezillon ecc->strength = 16; 221693db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; 221793db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; 221893db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; 221993db446aSBoris Brezillon ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; 222093db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; 222193db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; 222293db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; 222393db446aSBoris Brezillon ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; 222493db446aSBoris Brezillon } 222593db446aSBoris Brezillon 222693db446aSBoris Brezillon return 0; 222793db446aSBoris Brezillon } 222893db446aSBoris Brezillon 222993db446aSBoris Brezillon static int marvell_nand_ecc_init(struct mtd_info *mtd, 223093db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 223193db446aSBoris Brezillon { 223293db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 223393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 223493db446aSBoris Brezillon int ret; 223593db446aSBoris Brezillon 223693db446aSBoris Brezillon if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) { 223793db446aSBoris Brezillon if (chip->ecc_step_ds && chip->ecc_strength_ds) { 223893db446aSBoris Brezillon ecc->size = chip->ecc_step_ds; 223993db446aSBoris Brezillon ecc->strength = chip->ecc_strength_ds; 224093db446aSBoris Brezillon } else { 224193db446aSBoris Brezillon dev_info(nfc->dev, 224293db446aSBoris Brezillon "No minimum ECC strength, using 1b/512B\n"); 224393db446aSBoris Brezillon ecc->size = 512; 224493db446aSBoris Brezillon ecc->strength = 1; 224593db446aSBoris Brezillon } 224693db446aSBoris Brezillon } 224793db446aSBoris Brezillon 224893db446aSBoris Brezillon switch (ecc->mode) { 224993db446aSBoris Brezillon case NAND_ECC_HW: 225093db446aSBoris Brezillon ret = marvell_nand_hw_ecc_ctrl_init(mtd, ecc); 225193db446aSBoris Brezillon if (ret) 225293db446aSBoris Brezillon return ret; 225393db446aSBoris Brezillon break; 225493db446aSBoris Brezillon case NAND_ECC_NONE: 225593db446aSBoris Brezillon case NAND_ECC_SOFT: 2256ed6d0285SChris Packham case NAND_ECC_ON_DIE: 225793db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && 225893db446aSBoris Brezillon mtd->writesize != SZ_2K) { 225993db446aSBoris Brezillon dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", 226093db446aSBoris Brezillon mtd->writesize); 226193db446aSBoris Brezillon return -EINVAL; 226293db446aSBoris Brezillon } 226393db446aSBoris Brezillon break; 226493db446aSBoris Brezillon default: 226593db446aSBoris Brezillon return -EINVAL; 226693db446aSBoris Brezillon } 226793db446aSBoris Brezillon 226893db446aSBoris Brezillon return 0; 226993db446aSBoris Brezillon } 227093db446aSBoris Brezillon 227193db446aSBoris Brezillon static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; 227293db446aSBoris Brezillon static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; 227393db446aSBoris Brezillon 227493db446aSBoris Brezillon static struct nand_bbt_descr bbt_main_descr = { 227593db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 227693db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 227793db446aSBoris Brezillon .offs = 8, 227893db446aSBoris Brezillon .len = 6, 227993db446aSBoris Brezillon .veroffs = 14, 228093db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 228193db446aSBoris Brezillon .pattern = bbt_pattern 228293db446aSBoris Brezillon }; 228393db446aSBoris Brezillon 228493db446aSBoris Brezillon static struct nand_bbt_descr bbt_mirror_descr = { 228593db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 228693db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 228793db446aSBoris Brezillon .offs = 8, 228893db446aSBoris Brezillon .len = 6, 228993db446aSBoris Brezillon .veroffs = 14, 229093db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 229193db446aSBoris Brezillon .pattern = bbt_mirror_pattern 229293db446aSBoris Brezillon }; 229393db446aSBoris Brezillon 2294858838b8SBoris Brezillon static int marvell_nfc_setup_data_interface(struct nand_chip *chip, int chipnr, 229593db446aSBoris Brezillon const struct nand_data_interface 229693db446aSBoris Brezillon *conf) 229793db446aSBoris Brezillon { 229893db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 229993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 23006b6de654SBoris Brezillon unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; 230193db446aSBoris Brezillon const struct nand_sdr_timings *sdr; 230293db446aSBoris Brezillon struct marvell_nfc_timings nfc_tmg; 230393db446aSBoris Brezillon int read_delay; 230493db446aSBoris Brezillon 230593db446aSBoris Brezillon sdr = nand_get_sdr_timings(conf); 230693db446aSBoris Brezillon if (IS_ERR(sdr)) 230793db446aSBoris Brezillon return PTR_ERR(sdr); 230893db446aSBoris Brezillon 230993db446aSBoris Brezillon /* 231093db446aSBoris Brezillon * SDR timings are given in pico-seconds while NFC timings must be 231193db446aSBoris Brezillon * expressed in NAND controller clock cycles, which is half of the 231293db446aSBoris Brezillon * frequency of the accessible ECC clock retrieved by clk_get_rate(). 231393db446aSBoris Brezillon * This is not written anywhere in the datasheet but was observed 231493db446aSBoris Brezillon * with an oscilloscope. 231593db446aSBoris Brezillon * 231693db446aSBoris Brezillon * NFC datasheet gives equations from which thoses calculations 231793db446aSBoris Brezillon * are derived, they tend to be slightly more restrictives than the 231893db446aSBoris Brezillon * given core timings and may improve the overall speed. 231993db446aSBoris Brezillon */ 232093db446aSBoris Brezillon nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; 232193db446aSBoris Brezillon nfc_tmg.tRH = nfc_tmg.tRP; 232293db446aSBoris Brezillon nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; 232393db446aSBoris Brezillon nfc_tmg.tWH = nfc_tmg.tWP; 232493db446aSBoris Brezillon nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); 232593db446aSBoris Brezillon nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; 232693db446aSBoris Brezillon nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); 232793db446aSBoris Brezillon /* 232893db446aSBoris Brezillon * Read delay is the time of propagation from SoC pins to NFC internal 232993db446aSBoris Brezillon * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In 233093db446aSBoris Brezillon * EDO mode, an additional delay of tRH must be taken into account so 233193db446aSBoris Brezillon * the data is sampled on the falling edge instead of the rising edge. 233293db446aSBoris Brezillon */ 233393db446aSBoris Brezillon read_delay = sdr->tRC_min >= 30000 ? 233493db446aSBoris Brezillon MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH; 233593db446aSBoris Brezillon 233693db446aSBoris Brezillon nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); 233793db446aSBoris Brezillon /* 233893db446aSBoris Brezillon * tWHR and tRHW are supposed to be read to write delays (and vice 233993db446aSBoris Brezillon * versa) but in some cases, ie. when doing a change column, they must 234093db446aSBoris Brezillon * be greater than that to be sure tCCS delay is respected. 234193db446aSBoris Brezillon */ 234293db446aSBoris Brezillon nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), 234393db446aSBoris Brezillon period_ns) - 2, 234493db446aSBoris Brezillon nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), 234593db446aSBoris Brezillon period_ns); 234693db446aSBoris Brezillon 234793db446aSBoris Brezillon /* 234893db446aSBoris Brezillon * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays. 234993db446aSBoris Brezillon * NFCv1: No WAIT_MODE, tR must be maximal. 235093db446aSBoris Brezillon */ 235193db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 235293db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); 235393db446aSBoris Brezillon } else { 235493db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, 235593db446aSBoris Brezillon period_ns); 235693db446aSBoris Brezillon if (nfc_tmg.tR + 3 > nfc_tmg.tCH) 235793db446aSBoris Brezillon nfc_tmg.tR = nfc_tmg.tCH - 3; 235893db446aSBoris Brezillon else 235993db446aSBoris Brezillon nfc_tmg.tR = 0; 236093db446aSBoris Brezillon } 236193db446aSBoris Brezillon 236293db446aSBoris Brezillon if (chipnr < 0) 236393db446aSBoris Brezillon return 0; 236493db446aSBoris Brezillon 236593db446aSBoris Brezillon marvell_nand->ndtr0 = 236693db446aSBoris Brezillon NDTR0_TRP(nfc_tmg.tRP) | 236793db446aSBoris Brezillon NDTR0_TRH(nfc_tmg.tRH) | 236893db446aSBoris Brezillon NDTR0_ETRP(nfc_tmg.tRP) | 236993db446aSBoris Brezillon NDTR0_TWP(nfc_tmg.tWP) | 237093db446aSBoris Brezillon NDTR0_TWH(nfc_tmg.tWH) | 237193db446aSBoris Brezillon NDTR0_TCS(nfc_tmg.tCS) | 237293db446aSBoris Brezillon NDTR0_TCH(nfc_tmg.tCH); 237393db446aSBoris Brezillon 237493db446aSBoris Brezillon marvell_nand->ndtr1 = 237593db446aSBoris Brezillon NDTR1_TAR(nfc_tmg.tAR) | 237693db446aSBoris Brezillon NDTR1_TWHR(nfc_tmg.tWHR) | 237793db446aSBoris Brezillon NDTR1_TR(nfc_tmg.tR); 237893db446aSBoris Brezillon 237993db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 238093db446aSBoris Brezillon marvell_nand->ndtr0 |= 238193db446aSBoris Brezillon NDTR0_RD_CNT_DEL(read_delay) | 238293db446aSBoris Brezillon NDTR0_SELCNTR | 238393db446aSBoris Brezillon NDTR0_TADL(nfc_tmg.tADL); 238493db446aSBoris Brezillon 238593db446aSBoris Brezillon marvell_nand->ndtr1 |= 238693db446aSBoris Brezillon NDTR1_TRHW(nfc_tmg.tRHW) | 238793db446aSBoris Brezillon NDTR1_WAIT_MODE; 238893db446aSBoris Brezillon } 238993db446aSBoris Brezillon 239093db446aSBoris Brezillon return 0; 239193db446aSBoris Brezillon } 239293db446aSBoris Brezillon 23938831e48bSMiquel Raynal static int marvell_nand_attach_chip(struct nand_chip *chip) 23948831e48bSMiquel Raynal { 23958831e48bSMiquel Raynal struct mtd_info *mtd = nand_to_mtd(chip); 23968831e48bSMiquel Raynal struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 23978831e48bSMiquel Raynal struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 23988831e48bSMiquel Raynal struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); 23998831e48bSMiquel Raynal int ret; 24008831e48bSMiquel Raynal 24018831e48bSMiquel Raynal if (pdata && pdata->flash_bbt) 24028831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_USE_FLASH; 24038831e48bSMiquel Raynal 24048831e48bSMiquel Raynal if (chip->bbt_options & NAND_BBT_USE_FLASH) { 24058831e48bSMiquel Raynal /* 24068831e48bSMiquel Raynal * We'll use a bad block table stored in-flash and don't 24078831e48bSMiquel Raynal * allow writing the bad block marker to the flash. 24088831e48bSMiquel Raynal */ 24098831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 24108831e48bSMiquel Raynal chip->bbt_td = &bbt_main_descr; 24118831e48bSMiquel Raynal chip->bbt_md = &bbt_mirror_descr; 24128831e48bSMiquel Raynal } 24138831e48bSMiquel Raynal 24148831e48bSMiquel Raynal /* Save the chip-specific fields of NDCR */ 24158831e48bSMiquel Raynal marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); 24168831e48bSMiquel Raynal if (chip->options & NAND_BUSWIDTH_16) 24178831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 24188831e48bSMiquel Raynal 24198831e48bSMiquel Raynal /* 24208831e48bSMiquel Raynal * On small page NANDs, only one cycle is needed to pass the 24218831e48bSMiquel Raynal * column address. 24228831e48bSMiquel Raynal */ 24238831e48bSMiquel Raynal if (mtd->writesize <= 512) { 24248831e48bSMiquel Raynal marvell_nand->addr_cyc = 1; 24258831e48bSMiquel Raynal } else { 24268831e48bSMiquel Raynal marvell_nand->addr_cyc = 2; 24278831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_RA_START; 24288831e48bSMiquel Raynal } 24298831e48bSMiquel Raynal 24308831e48bSMiquel Raynal /* 24318831e48bSMiquel Raynal * Now add the number of cycles needed to pass the row 24328831e48bSMiquel Raynal * address. 24338831e48bSMiquel Raynal * 24348831e48bSMiquel Raynal * Addressing a chip using CS 2 or 3 should also need the third row 24358831e48bSMiquel Raynal * cycle but due to inconsistance in the documentation and lack of 24368831e48bSMiquel Raynal * hardware to test this situation, this case is not supported. 24378831e48bSMiquel Raynal */ 24388831e48bSMiquel Raynal if (chip->options & NAND_ROW_ADDR_3) 24398831e48bSMiquel Raynal marvell_nand->addr_cyc += 3; 24408831e48bSMiquel Raynal else 24418831e48bSMiquel Raynal marvell_nand->addr_cyc += 2; 24428831e48bSMiquel Raynal 24438831e48bSMiquel Raynal if (pdata) { 24448831e48bSMiquel Raynal chip->ecc.size = pdata->ecc_step_size; 24458831e48bSMiquel Raynal chip->ecc.strength = pdata->ecc_strength; 24468831e48bSMiquel Raynal } 24478831e48bSMiquel Raynal 24488831e48bSMiquel Raynal ret = marvell_nand_ecc_init(mtd, &chip->ecc); 24498831e48bSMiquel Raynal if (ret) { 24508831e48bSMiquel Raynal dev_err(nfc->dev, "ECC init failed: %d\n", ret); 24518831e48bSMiquel Raynal return ret; 24528831e48bSMiquel Raynal } 24538831e48bSMiquel Raynal 24548831e48bSMiquel Raynal if (chip->ecc.mode == NAND_ECC_HW) { 24558831e48bSMiquel Raynal /* 24568831e48bSMiquel Raynal * Subpage write not available with hardware ECC, prohibit also 24578831e48bSMiquel Raynal * subpage read as in userspace subpage access would still be 24588831e48bSMiquel Raynal * allowed and subpage write, if used, would lead to numerous 24598831e48bSMiquel Raynal * uncorrectable ECC errors. 24608831e48bSMiquel Raynal */ 24618831e48bSMiquel Raynal chip->options |= NAND_NO_SUBPAGE_WRITE; 24628831e48bSMiquel Raynal } 24638831e48bSMiquel Raynal 24648831e48bSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) { 24658831e48bSMiquel Raynal /* 24668831e48bSMiquel Raynal * We keep the MTD name unchanged to avoid breaking platforms 24678831e48bSMiquel Raynal * where the MTD cmdline parser is used and the bootloader 24688831e48bSMiquel Raynal * has not been updated to use the new naming scheme. 24698831e48bSMiquel Raynal */ 24708831e48bSMiquel Raynal mtd->name = "pxa3xx_nand-0"; 24718831e48bSMiquel Raynal } else if (!mtd->name) { 24728831e48bSMiquel Raynal /* 24738831e48bSMiquel Raynal * If the new bindings are used and the bootloader has not been 24748831e48bSMiquel Raynal * updated to pass a new mtdparts parameter on the cmdline, you 24758831e48bSMiquel Raynal * should define the following property in your NAND node, ie: 24768831e48bSMiquel Raynal * 24778831e48bSMiquel Raynal * label = "main-storage"; 24788831e48bSMiquel Raynal * 24798831e48bSMiquel Raynal * This way, mtd->name will be set by the core when 24808831e48bSMiquel Raynal * nand_set_flash_node() is called. 24818831e48bSMiquel Raynal */ 24828831e48bSMiquel Raynal mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, 24838831e48bSMiquel Raynal "%s:nand.%d", dev_name(nfc->dev), 24848831e48bSMiquel Raynal marvell_nand->sels[0].cs); 24858831e48bSMiquel Raynal if (!mtd->name) { 24868831e48bSMiquel Raynal dev_err(nfc->dev, "Failed to allocate mtd->name\n"); 24878831e48bSMiquel Raynal return -ENOMEM; 24888831e48bSMiquel Raynal } 24898831e48bSMiquel Raynal } 24908831e48bSMiquel Raynal 24918831e48bSMiquel Raynal return 0; 24928831e48bSMiquel Raynal } 24938831e48bSMiquel Raynal 24948831e48bSMiquel Raynal static const struct nand_controller_ops marvell_nand_controller_ops = { 24958831e48bSMiquel Raynal .attach_chip = marvell_nand_attach_chip, 24968831e48bSMiquel Raynal }; 24978831e48bSMiquel Raynal 249893db446aSBoris Brezillon static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc, 249993db446aSBoris Brezillon struct device_node *np) 250093db446aSBoris Brezillon { 250193db446aSBoris Brezillon struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev); 250293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand; 250393db446aSBoris Brezillon struct mtd_info *mtd; 250493db446aSBoris Brezillon struct nand_chip *chip; 250593db446aSBoris Brezillon int nsels, ret, i; 250693db446aSBoris Brezillon u32 cs, rb; 250793db446aSBoris Brezillon 250893db446aSBoris Brezillon /* 250993db446aSBoris Brezillon * The legacy "num-cs" property indicates the number of CS on the only 251093db446aSBoris Brezillon * chip connected to the controller (legacy bindings does not support 2511f6997becSMiquel Raynal * more than one chip). The CS and RB pins are always the #0. 251293db446aSBoris Brezillon * 251393db446aSBoris Brezillon * When not using legacy bindings, a couple of "reg" and "nand-rb" 251493db446aSBoris Brezillon * properties must be filled. For each chip, expressed as a subnode, 251593db446aSBoris Brezillon * "reg" points to the CS lines and "nand-rb" to the RB line. 251693db446aSBoris Brezillon */ 2517f6997becSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) { 251893db446aSBoris Brezillon nsels = 1; 2519f6997becSMiquel Raynal } else { 2520f6997becSMiquel Raynal nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32)); 2521f6997becSMiquel Raynal if (nsels <= 0) { 2522f6997becSMiquel Raynal dev_err(dev, "missing/invalid reg property\n"); 252393db446aSBoris Brezillon return -EINVAL; 252493db446aSBoris Brezillon } 252593db446aSBoris Brezillon } 252693db446aSBoris Brezillon 252793db446aSBoris Brezillon /* Alloc the nand chip structure */ 252893db446aSBoris Brezillon marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) + 252993db446aSBoris Brezillon (nsels * 253093db446aSBoris Brezillon sizeof(struct marvell_nand_chip_sel)), 253193db446aSBoris Brezillon GFP_KERNEL); 253293db446aSBoris Brezillon if (!marvell_nand) { 253393db446aSBoris Brezillon dev_err(dev, "could not allocate chip structure\n"); 253493db446aSBoris Brezillon return -ENOMEM; 253593db446aSBoris Brezillon } 253693db446aSBoris Brezillon 253793db446aSBoris Brezillon marvell_nand->nsels = nsels; 253893db446aSBoris Brezillon marvell_nand->selected_die = -1; 253993db446aSBoris Brezillon 254093db446aSBoris Brezillon for (i = 0; i < nsels; i++) { 254193db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 254293db446aSBoris Brezillon /* 254393db446aSBoris Brezillon * Legacy bindings use the CS lines in natural 254493db446aSBoris Brezillon * order (0, 1, ...) 254593db446aSBoris Brezillon */ 254693db446aSBoris Brezillon cs = i; 254793db446aSBoris Brezillon } else { 254893db446aSBoris Brezillon /* Retrieve CS id */ 254993db446aSBoris Brezillon ret = of_property_read_u32_index(np, "reg", i, &cs); 255093db446aSBoris Brezillon if (ret) { 255193db446aSBoris Brezillon dev_err(dev, "could not retrieve reg property: %d\n", 255293db446aSBoris Brezillon ret); 255393db446aSBoris Brezillon return ret; 255493db446aSBoris Brezillon } 255593db446aSBoris Brezillon } 255693db446aSBoris Brezillon 255793db446aSBoris Brezillon if (cs >= nfc->caps->max_cs_nb) { 255893db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max CS = %d)\n", 255993db446aSBoris Brezillon cs, nfc->caps->max_cs_nb); 256093db446aSBoris Brezillon return -EINVAL; 256193db446aSBoris Brezillon } 256293db446aSBoris Brezillon 256393db446aSBoris Brezillon if (test_and_set_bit(cs, &nfc->assigned_cs)) { 256493db446aSBoris Brezillon dev_err(dev, "CS %d already assigned\n", cs); 256593db446aSBoris Brezillon return -EINVAL; 256693db446aSBoris Brezillon } 256793db446aSBoris Brezillon 256893db446aSBoris Brezillon /* 256993db446aSBoris Brezillon * The cs variable represents the chip select id, which must be 257093db446aSBoris Brezillon * converted in bit fields for NDCB0 and NDCB2 to select the 257193db446aSBoris Brezillon * right chip. Unfortunately, due to a lack of information on 257293db446aSBoris Brezillon * the subject and incoherent documentation, the user should not 257393db446aSBoris Brezillon * use CS1 and CS3 at all as asserting them is not supported in 257493db446aSBoris Brezillon * a reliable way (due to multiplexing inside ADDR5 field). 257593db446aSBoris Brezillon */ 257693db446aSBoris Brezillon marvell_nand->sels[i].cs = cs; 257793db446aSBoris Brezillon switch (cs) { 257893db446aSBoris Brezillon case 0: 257993db446aSBoris Brezillon case 2: 258093db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = 0; 258193db446aSBoris Brezillon break; 258293db446aSBoris Brezillon case 1: 258393db446aSBoris Brezillon case 3: 258493db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; 258593db446aSBoris Brezillon break; 258693db446aSBoris Brezillon default: 258793db446aSBoris Brezillon return -EINVAL; 258893db446aSBoris Brezillon } 258993db446aSBoris Brezillon 259093db446aSBoris Brezillon /* Retrieve RB id */ 259193db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 259293db446aSBoris Brezillon /* Legacy bindings always use RB #0 */ 259393db446aSBoris Brezillon rb = 0; 259493db446aSBoris Brezillon } else { 259593db446aSBoris Brezillon ret = of_property_read_u32_index(np, "nand-rb", i, 259693db446aSBoris Brezillon &rb); 259793db446aSBoris Brezillon if (ret) { 259893db446aSBoris Brezillon dev_err(dev, 259993db446aSBoris Brezillon "could not retrieve RB property: %d\n", 260093db446aSBoris Brezillon ret); 260193db446aSBoris Brezillon return ret; 260293db446aSBoris Brezillon } 260393db446aSBoris Brezillon } 260493db446aSBoris Brezillon 260593db446aSBoris Brezillon if (rb >= nfc->caps->max_rb_nb) { 260693db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max RB = %d)\n", 260793db446aSBoris Brezillon rb, nfc->caps->max_rb_nb); 260893db446aSBoris Brezillon return -EINVAL; 260993db446aSBoris Brezillon } 261093db446aSBoris Brezillon 261193db446aSBoris Brezillon marvell_nand->sels[i].rb = rb; 261293db446aSBoris Brezillon } 261393db446aSBoris Brezillon 261493db446aSBoris Brezillon chip = &marvell_nand->chip; 261593db446aSBoris Brezillon chip->controller = &nfc->controller; 261693db446aSBoris Brezillon nand_set_flash_node(chip, np); 261793db446aSBoris Brezillon 261893db446aSBoris Brezillon chip->exec_op = marvell_nfc_exec_op; 261993db446aSBoris Brezillon chip->select_chip = marvell_nfc_select_chip; 262093db446aSBoris Brezillon if (!of_property_read_bool(np, "marvell,nand-keep-config")) 262193db446aSBoris Brezillon chip->setup_data_interface = marvell_nfc_setup_data_interface; 262293db446aSBoris Brezillon 262393db446aSBoris Brezillon mtd = nand_to_mtd(chip); 262493db446aSBoris Brezillon mtd->dev.parent = dev; 262593db446aSBoris Brezillon 262693db446aSBoris Brezillon /* 262793db446aSBoris Brezillon * Default to HW ECC engine mode. If the nand-ecc-mode property is given 262893db446aSBoris Brezillon * in the DT node, this entry will be overwritten in nand_scan_ident(). 262993db446aSBoris Brezillon */ 263093db446aSBoris Brezillon chip->ecc.mode = NAND_ECC_HW; 263193db446aSBoris Brezillon 263293db446aSBoris Brezillon /* 263393db446aSBoris Brezillon * Save a reference value for timing registers before 263493db446aSBoris Brezillon * ->setup_data_interface() is called. 263593db446aSBoris Brezillon */ 263693db446aSBoris Brezillon marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); 263793db446aSBoris Brezillon marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); 263893db446aSBoris Brezillon 263993db446aSBoris Brezillon chip->options |= NAND_BUSWIDTH_AUTO; 26408831e48bSMiquel Raynal 264100ad378fSBoris Brezillon ret = nand_scan(chip, marvell_nand->nsels); 264293db446aSBoris Brezillon if (ret) { 26438831e48bSMiquel Raynal dev_err(dev, "could not scan the nand chip\n"); 264493db446aSBoris Brezillon return ret; 264593db446aSBoris Brezillon } 264693db446aSBoris Brezillon 264793db446aSBoris Brezillon if (pdata) 264893db446aSBoris Brezillon /* Legacy bindings support only one chip */ 26493383fb35SBoris Brezillon ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); 265093db446aSBoris Brezillon else 265193db446aSBoris Brezillon ret = mtd_device_register(mtd, NULL, 0); 265293db446aSBoris Brezillon if (ret) { 265393db446aSBoris Brezillon dev_err(dev, "failed to register mtd device: %d\n", ret); 265459ac276fSBoris Brezillon nand_release(chip); 265593db446aSBoris Brezillon return ret; 265693db446aSBoris Brezillon } 265793db446aSBoris Brezillon 265893db446aSBoris Brezillon list_add_tail(&marvell_nand->node, &nfc->chips); 265993db446aSBoris Brezillon 266093db446aSBoris Brezillon return 0; 266193db446aSBoris Brezillon } 266293db446aSBoris Brezillon 266393db446aSBoris Brezillon static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc) 266493db446aSBoris Brezillon { 266593db446aSBoris Brezillon struct device_node *np = dev->of_node; 266693db446aSBoris Brezillon struct device_node *nand_np; 266793db446aSBoris Brezillon int max_cs = nfc->caps->max_cs_nb; 266893db446aSBoris Brezillon int nchips; 266993db446aSBoris Brezillon int ret; 267093db446aSBoris Brezillon 267193db446aSBoris Brezillon if (!np) 267293db446aSBoris Brezillon nchips = 1; 267393db446aSBoris Brezillon else 267493db446aSBoris Brezillon nchips = of_get_child_count(np); 267593db446aSBoris Brezillon 267693db446aSBoris Brezillon if (nchips > max_cs) { 267793db446aSBoris Brezillon dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, 267893db446aSBoris Brezillon max_cs); 267993db446aSBoris Brezillon return -EINVAL; 268093db446aSBoris Brezillon } 268193db446aSBoris Brezillon 268293db446aSBoris Brezillon /* 268393db446aSBoris Brezillon * Legacy bindings do not use child nodes to exhibit NAND chip 268493db446aSBoris Brezillon * properties and layout. Instead, NAND properties are mixed with the 268593db446aSBoris Brezillon * controller ones, and partitions are defined as direct subnodes of the 268693db446aSBoris Brezillon * NAND controller node. 268793db446aSBoris Brezillon */ 268893db446aSBoris Brezillon if (nfc->caps->legacy_of_bindings) { 268993db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, np); 269093db446aSBoris Brezillon return ret; 269193db446aSBoris Brezillon } 269293db446aSBoris Brezillon 269393db446aSBoris Brezillon for_each_child_of_node(np, nand_np) { 269493db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, nand_np); 269593db446aSBoris Brezillon if (ret) { 269693db446aSBoris Brezillon of_node_put(nand_np); 269793db446aSBoris Brezillon return ret; 269893db446aSBoris Brezillon } 269993db446aSBoris Brezillon } 270093db446aSBoris Brezillon 270193db446aSBoris Brezillon return 0; 270293db446aSBoris Brezillon } 270393db446aSBoris Brezillon 270493db446aSBoris Brezillon static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc) 270593db446aSBoris Brezillon { 270693db446aSBoris Brezillon struct marvell_nand_chip *entry, *temp; 270793db446aSBoris Brezillon 270893db446aSBoris Brezillon list_for_each_entry_safe(entry, temp, &nfc->chips, node) { 270959ac276fSBoris Brezillon nand_release(&entry->chip); 271093db446aSBoris Brezillon list_del(&entry->node); 271193db446aSBoris Brezillon } 271293db446aSBoris Brezillon } 271393db446aSBoris Brezillon 271493db446aSBoris Brezillon static int marvell_nfc_init_dma(struct marvell_nfc *nfc) 271593db446aSBoris Brezillon { 271693db446aSBoris Brezillon struct platform_device *pdev = container_of(nfc->dev, 271793db446aSBoris Brezillon struct platform_device, 271893db446aSBoris Brezillon dev); 271993db446aSBoris Brezillon struct dma_slave_config config = {}; 272093db446aSBoris Brezillon struct resource *r; 272193db446aSBoris Brezillon int ret; 272293db446aSBoris Brezillon 272393db446aSBoris Brezillon if (!IS_ENABLED(CONFIG_PXA_DMA)) { 272493db446aSBoris Brezillon dev_warn(nfc->dev, 272593db446aSBoris Brezillon "DMA not enabled in configuration\n"); 272693db446aSBoris Brezillon return -ENOTSUPP; 272793db446aSBoris Brezillon } 272893db446aSBoris Brezillon 272993db446aSBoris Brezillon ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); 273093db446aSBoris Brezillon if (ret) 273193db446aSBoris Brezillon return ret; 273293db446aSBoris Brezillon 2733ac75a50bSRobert Jarzmik nfc->dma_chan = dma_request_slave_channel(nfc->dev, "data"); 273493db446aSBoris Brezillon if (!nfc->dma_chan) { 273593db446aSBoris Brezillon dev_err(nfc->dev, 273693db446aSBoris Brezillon "Unable to request data DMA channel\n"); 273793db446aSBoris Brezillon return -ENODEV; 273893db446aSBoris Brezillon } 273993db446aSBoris Brezillon 274093db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 274193db446aSBoris Brezillon if (!r) 274293db446aSBoris Brezillon return -ENXIO; 274393db446aSBoris Brezillon 274493db446aSBoris Brezillon config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 274593db446aSBoris Brezillon config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 274693db446aSBoris Brezillon config.src_addr = r->start + NDDB; 274793db446aSBoris Brezillon config.dst_addr = r->start + NDDB; 274893db446aSBoris Brezillon config.src_maxburst = 32; 274993db446aSBoris Brezillon config.dst_maxburst = 32; 275093db446aSBoris Brezillon ret = dmaengine_slave_config(nfc->dma_chan, &config); 275193db446aSBoris Brezillon if (ret < 0) { 275293db446aSBoris Brezillon dev_err(nfc->dev, "Failed to configure DMA channel\n"); 275393db446aSBoris Brezillon return ret; 275493db446aSBoris Brezillon } 275593db446aSBoris Brezillon 275693db446aSBoris Brezillon /* 275793db446aSBoris Brezillon * DMA must act on length multiple of 32 and this length may be 275893db446aSBoris Brezillon * bigger than the destination buffer. Use this buffer instead 275993db446aSBoris Brezillon * for DMA transfers and then copy the desired amount of data to 276093db446aSBoris Brezillon * the provided buffer. 276193db446aSBoris Brezillon */ 276293db446aSBoris Brezillon nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); 276393db446aSBoris Brezillon if (!nfc->dma_buf) 276493db446aSBoris Brezillon return -ENOMEM; 276593db446aSBoris Brezillon 276693db446aSBoris Brezillon nfc->use_dma = true; 276793db446aSBoris Brezillon 276893db446aSBoris Brezillon return 0; 276993db446aSBoris Brezillon } 277093db446aSBoris Brezillon 2771bd9c3f9bSDaniel Mack static void marvell_nfc_reset(struct marvell_nfc *nfc) 2772bd9c3f9bSDaniel Mack { 2773bd9c3f9bSDaniel Mack /* 2774bd9c3f9bSDaniel Mack * ECC operations and interruptions are only enabled when specifically 2775bd9c3f9bSDaniel Mack * needed. ECC shall not be activated in the early stages (fails probe). 2776bd9c3f9bSDaniel Mack * Arbiter flag, even if marked as "reserved", must be set (empirical). 2777bd9c3f9bSDaniel Mack * SPARE_EN bit must always be set or ECC bytes will not be at the same 2778bd9c3f9bSDaniel Mack * offset in the read page and this will fail the protection. 2779bd9c3f9bSDaniel Mack */ 2780bd9c3f9bSDaniel Mack writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN | 2781bd9c3f9bSDaniel Mack NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); 2782bd9c3f9bSDaniel Mack writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); 2783bd9c3f9bSDaniel Mack writel_relaxed(0, nfc->regs + NDECCCTRL); 2784bd9c3f9bSDaniel Mack } 2785bd9c3f9bSDaniel Mack 278693db446aSBoris Brezillon static int marvell_nfc_init(struct marvell_nfc *nfc) 278793db446aSBoris Brezillon { 278893db446aSBoris Brezillon struct device_node *np = nfc->dev->of_node; 278993db446aSBoris Brezillon 279093db446aSBoris Brezillon /* 279193db446aSBoris Brezillon * Some SoCs like A7k/A8k need to enable manually the NAND 279293db446aSBoris Brezillon * controller, gated clocks and reset bits to avoid being bootloader 279393db446aSBoris Brezillon * dependent. This is done through the use of the System Functions 279493db446aSBoris Brezillon * registers. 279593db446aSBoris Brezillon */ 279693db446aSBoris Brezillon if (nfc->caps->need_system_controller) { 279793db446aSBoris Brezillon struct regmap *sysctrl_base = 279893db446aSBoris Brezillon syscon_regmap_lookup_by_phandle(np, 279993db446aSBoris Brezillon "marvell,system-controller"); 280093db446aSBoris Brezillon 280193db446aSBoris Brezillon if (IS_ERR(sysctrl_base)) 280293db446aSBoris Brezillon return PTR_ERR(sysctrl_base); 280393db446aSBoris Brezillon 280488aa3bbfSThomas Petazzoni regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, 280588aa3bbfSThomas Petazzoni GENCONF_SOC_DEVICE_MUX_NFC_EN | 280693db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST | 280793db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST | 280888aa3bbfSThomas Petazzoni GENCONF_SOC_DEVICE_MUX_NFC_INT_EN); 280993db446aSBoris Brezillon 281088aa3bbfSThomas Petazzoni regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL, 281188aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE, 281288aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE); 281393db446aSBoris Brezillon 281488aa3bbfSThomas Petazzoni regmap_update_bits(sysctrl_base, GENCONF_ND_CLK_CTRL, 281588aa3bbfSThomas Petazzoni GENCONF_ND_CLK_CTRL_EN, 281688aa3bbfSThomas Petazzoni GENCONF_ND_CLK_CTRL_EN); 281793db446aSBoris Brezillon } 281893db446aSBoris Brezillon 281993db446aSBoris Brezillon /* Configure the DMA if appropriate */ 282093db446aSBoris Brezillon if (!nfc->caps->is_nfcv2) 282193db446aSBoris Brezillon marvell_nfc_init_dma(nfc); 282293db446aSBoris Brezillon 2823bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc); 282493db446aSBoris Brezillon 282593db446aSBoris Brezillon return 0; 282693db446aSBoris Brezillon } 282793db446aSBoris Brezillon 282893db446aSBoris Brezillon static int marvell_nfc_probe(struct platform_device *pdev) 282993db446aSBoris Brezillon { 283093db446aSBoris Brezillon struct device *dev = &pdev->dev; 283193db446aSBoris Brezillon struct resource *r; 283293db446aSBoris Brezillon struct marvell_nfc *nfc; 283393db446aSBoris Brezillon int ret; 283493db446aSBoris Brezillon int irq; 283593db446aSBoris Brezillon 283693db446aSBoris Brezillon nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), 283793db446aSBoris Brezillon GFP_KERNEL); 283893db446aSBoris Brezillon if (!nfc) 283993db446aSBoris Brezillon return -ENOMEM; 284093db446aSBoris Brezillon 284193db446aSBoris Brezillon nfc->dev = dev; 28427da45139SMiquel Raynal nand_controller_init(&nfc->controller); 28438831e48bSMiquel Raynal nfc->controller.ops = &marvell_nand_controller_ops; 284493db446aSBoris Brezillon INIT_LIST_HEAD(&nfc->chips); 284593db446aSBoris Brezillon 284693db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 284793db446aSBoris Brezillon nfc->regs = devm_ioremap_resource(dev, r); 284893db446aSBoris Brezillon if (IS_ERR(nfc->regs)) 284993db446aSBoris Brezillon return PTR_ERR(nfc->regs); 285093db446aSBoris Brezillon 285193db446aSBoris Brezillon irq = platform_get_irq(pdev, 0); 285293db446aSBoris Brezillon if (irq < 0) { 285393db446aSBoris Brezillon dev_err(dev, "failed to retrieve irq\n"); 285493db446aSBoris Brezillon return irq; 285593db446aSBoris Brezillon } 285693db446aSBoris Brezillon 28576b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, "core"); 2858961ba15cSGregory CLEMENT 2859961ba15cSGregory CLEMENT /* Managed the legacy case (when the first clock was not named) */ 28606b6de654SBoris Brezillon if (nfc->core_clk == ERR_PTR(-ENOENT)) 28616b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, NULL); 2862961ba15cSGregory CLEMENT 28636b6de654SBoris Brezillon if (IS_ERR(nfc->core_clk)) 28646b6de654SBoris Brezillon return PTR_ERR(nfc->core_clk); 286593db446aSBoris Brezillon 28666b6de654SBoris Brezillon ret = clk_prepare_enable(nfc->core_clk); 286793db446aSBoris Brezillon if (ret) 286893db446aSBoris Brezillon return ret; 286993db446aSBoris Brezillon 2870961ba15cSGregory CLEMENT nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); 2871f9e64d61SDaniel Mack if (IS_ERR(nfc->reg_clk)) { 2872961ba15cSGregory CLEMENT if (PTR_ERR(nfc->reg_clk) != -ENOENT) { 2873961ba15cSGregory CLEMENT ret = PTR_ERR(nfc->reg_clk); 28746b6de654SBoris Brezillon goto unprepare_core_clk; 2875961ba15cSGregory CLEMENT } 2876f9e64d61SDaniel Mack 2877f9e64d61SDaniel Mack nfc->reg_clk = NULL; 2878961ba15cSGregory CLEMENT } 2879961ba15cSGregory CLEMENT 2880f9e64d61SDaniel Mack ret = clk_prepare_enable(nfc->reg_clk); 2881f9e64d61SDaniel Mack if (ret) 2882f9e64d61SDaniel Mack goto unprepare_core_clk; 2883f9e64d61SDaniel Mack 288493db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_ALL_INT); 288593db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 288693db446aSBoris Brezillon ret = devm_request_irq(dev, irq, marvell_nfc_isr, 288793db446aSBoris Brezillon 0, "marvell-nfc", nfc); 288893db446aSBoris Brezillon if (ret) 2889961ba15cSGregory CLEMENT goto unprepare_reg_clk; 289093db446aSBoris Brezillon 289193db446aSBoris Brezillon /* Get NAND controller capabilities */ 289293db446aSBoris Brezillon if (pdev->id_entry) 289393db446aSBoris Brezillon nfc->caps = (void *)pdev->id_entry->driver_data; 289493db446aSBoris Brezillon else 289593db446aSBoris Brezillon nfc->caps = of_device_get_match_data(&pdev->dev); 289693db446aSBoris Brezillon 289793db446aSBoris Brezillon if (!nfc->caps) { 289893db446aSBoris Brezillon dev_err(dev, "Could not retrieve NFC caps\n"); 289993db446aSBoris Brezillon ret = -EINVAL; 2900961ba15cSGregory CLEMENT goto unprepare_reg_clk; 290193db446aSBoris Brezillon } 290293db446aSBoris Brezillon 290393db446aSBoris Brezillon /* Init the controller and then probe the chips */ 290493db446aSBoris Brezillon ret = marvell_nfc_init(nfc); 290593db446aSBoris Brezillon if (ret) 2906961ba15cSGregory CLEMENT goto unprepare_reg_clk; 290793db446aSBoris Brezillon 290893db446aSBoris Brezillon platform_set_drvdata(pdev, nfc); 290993db446aSBoris Brezillon 291093db446aSBoris Brezillon ret = marvell_nand_chips_init(dev, nfc); 291193db446aSBoris Brezillon if (ret) 2912961ba15cSGregory CLEMENT goto unprepare_reg_clk; 291393db446aSBoris Brezillon 291493db446aSBoris Brezillon return 0; 291593db446aSBoris Brezillon 2916961ba15cSGregory CLEMENT unprepare_reg_clk: 2917961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 29186b6de654SBoris Brezillon unprepare_core_clk: 29196b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 292093db446aSBoris Brezillon 292193db446aSBoris Brezillon return ret; 292293db446aSBoris Brezillon } 292393db446aSBoris Brezillon 292493db446aSBoris Brezillon static int marvell_nfc_remove(struct platform_device *pdev) 292593db446aSBoris Brezillon { 292693db446aSBoris Brezillon struct marvell_nfc *nfc = platform_get_drvdata(pdev); 292793db446aSBoris Brezillon 292893db446aSBoris Brezillon marvell_nand_chips_cleanup(nfc); 292993db446aSBoris Brezillon 293093db446aSBoris Brezillon if (nfc->use_dma) { 293193db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 293293db446aSBoris Brezillon dma_release_channel(nfc->dma_chan); 293393db446aSBoris Brezillon } 293493db446aSBoris Brezillon 2935961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 29366b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 293793db446aSBoris Brezillon 293893db446aSBoris Brezillon return 0; 293993db446aSBoris Brezillon } 294093db446aSBoris Brezillon 2941bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_suspend(struct device *dev) 2942bd9c3f9bSDaniel Mack { 2943bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev); 2944bd9c3f9bSDaniel Mack struct marvell_nand_chip *chip; 2945bd9c3f9bSDaniel Mack 2946bd9c3f9bSDaniel Mack list_for_each_entry(chip, &nfc->chips, node) 2947bd9c3f9bSDaniel Mack marvell_nfc_wait_ndrun(&chip->chip); 2948bd9c3f9bSDaniel Mack 2949bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->reg_clk); 2950bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->core_clk); 2951bd9c3f9bSDaniel Mack 2952bd9c3f9bSDaniel Mack return 0; 2953bd9c3f9bSDaniel Mack } 2954bd9c3f9bSDaniel Mack 2955bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_resume(struct device *dev) 2956bd9c3f9bSDaniel Mack { 2957bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev); 2958bd9c3f9bSDaniel Mack int ret; 2959bd9c3f9bSDaniel Mack 2960bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->core_clk); 2961bd9c3f9bSDaniel Mack if (ret < 0) 2962bd9c3f9bSDaniel Mack return ret; 2963bd9c3f9bSDaniel Mack 2964bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->reg_clk); 2965bd9c3f9bSDaniel Mack if (ret < 0) 2966bd9c3f9bSDaniel Mack return ret; 2967bd9c3f9bSDaniel Mack 2968bd9c3f9bSDaniel Mack /* 2969bd9c3f9bSDaniel Mack * Reset nfc->selected_chip so the next command will cause the timing 2970bd9c3f9bSDaniel Mack * registers to be restored in marvell_nfc_select_chip(). 2971bd9c3f9bSDaniel Mack */ 2972bd9c3f9bSDaniel Mack nfc->selected_chip = NULL; 2973bd9c3f9bSDaniel Mack 2974bd9c3f9bSDaniel Mack /* Reset registers that have lost their contents */ 2975bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc); 2976bd9c3f9bSDaniel Mack 2977bd9c3f9bSDaniel Mack return 0; 2978bd9c3f9bSDaniel Mack } 2979bd9c3f9bSDaniel Mack 2980bd9c3f9bSDaniel Mack static const struct dev_pm_ops marvell_nfc_pm_ops = { 2981bd9c3f9bSDaniel Mack SET_SYSTEM_SLEEP_PM_OPS(marvell_nfc_suspend, marvell_nfc_resume) 2982bd9c3f9bSDaniel Mack }; 2983bd9c3f9bSDaniel Mack 298493db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { 298593db446aSBoris Brezillon .max_cs_nb = 4, 298693db446aSBoris Brezillon .max_rb_nb = 2, 298793db446aSBoris Brezillon .need_system_controller = true, 298893db446aSBoris Brezillon .is_nfcv2 = true, 298993db446aSBoris Brezillon }; 299093db446aSBoris Brezillon 299193db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { 299293db446aSBoris Brezillon .max_cs_nb = 4, 299393db446aSBoris Brezillon .max_rb_nb = 2, 299493db446aSBoris Brezillon .is_nfcv2 = true, 299593db446aSBoris Brezillon }; 299693db446aSBoris Brezillon 299793db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = { 299893db446aSBoris Brezillon .max_cs_nb = 2, 299993db446aSBoris Brezillon .max_rb_nb = 1, 300093db446aSBoris Brezillon .use_dma = true, 300193db446aSBoris Brezillon }; 300293db446aSBoris Brezillon 300393db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = { 300493db446aSBoris Brezillon .max_cs_nb = 4, 300593db446aSBoris Brezillon .max_rb_nb = 2, 300693db446aSBoris Brezillon .need_system_controller = true, 300793db446aSBoris Brezillon .legacy_of_bindings = true, 300893db446aSBoris Brezillon .is_nfcv2 = true, 300993db446aSBoris Brezillon }; 301093db446aSBoris Brezillon 301193db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = { 301293db446aSBoris Brezillon .max_cs_nb = 4, 301393db446aSBoris Brezillon .max_rb_nb = 2, 301493db446aSBoris Brezillon .legacy_of_bindings = true, 301593db446aSBoris Brezillon .is_nfcv2 = true, 301693db446aSBoris Brezillon }; 301793db446aSBoris Brezillon 301893db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = { 301993db446aSBoris Brezillon .max_cs_nb = 2, 302093db446aSBoris Brezillon .max_rb_nb = 1, 302193db446aSBoris Brezillon .legacy_of_bindings = true, 302293db446aSBoris Brezillon .use_dma = true, 302393db446aSBoris Brezillon }; 302493db446aSBoris Brezillon 302593db446aSBoris Brezillon static const struct platform_device_id marvell_nfc_platform_ids[] = { 302693db446aSBoris Brezillon { 302793db446aSBoris Brezillon .name = "pxa3xx-nand", 302893db446aSBoris Brezillon .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps, 302993db446aSBoris Brezillon }, 303093db446aSBoris Brezillon { /* sentinel */ }, 303193db446aSBoris Brezillon }; 303293db446aSBoris Brezillon MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids); 303393db446aSBoris Brezillon 303493db446aSBoris Brezillon static const struct of_device_id marvell_nfc_of_ids[] = { 303593db446aSBoris Brezillon { 303693db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand-controller", 303793db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_caps, 303893db446aSBoris Brezillon }, 303993db446aSBoris Brezillon { 304093db446aSBoris Brezillon .compatible = "marvell,armada370-nand-controller", 304193db446aSBoris Brezillon .data = &marvell_armada370_nfc_caps, 304293db446aSBoris Brezillon }, 304393db446aSBoris Brezillon { 304493db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand-controller", 304593db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_caps, 304693db446aSBoris Brezillon }, 304793db446aSBoris Brezillon /* Support for old/deprecated bindings: */ 304893db446aSBoris Brezillon { 304993db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand", 305093db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_legacy_caps, 305193db446aSBoris Brezillon }, 305293db446aSBoris Brezillon { 305393db446aSBoris Brezillon .compatible = "marvell,armada370-nand", 305493db446aSBoris Brezillon .data = &marvell_armada370_nfc_legacy_caps, 305593db446aSBoris Brezillon }, 305693db446aSBoris Brezillon { 305793db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand", 305893db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_legacy_caps, 305993db446aSBoris Brezillon }, 306093db446aSBoris Brezillon { /* sentinel */ }, 306193db446aSBoris Brezillon }; 306293db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids); 306393db446aSBoris Brezillon 306493db446aSBoris Brezillon static struct platform_driver marvell_nfc_driver = { 306593db446aSBoris Brezillon .driver = { 306693db446aSBoris Brezillon .name = "marvell-nfc", 306793db446aSBoris Brezillon .of_match_table = marvell_nfc_of_ids, 3068bd9c3f9bSDaniel Mack .pm = &marvell_nfc_pm_ops, 306993db446aSBoris Brezillon }, 307093db446aSBoris Brezillon .id_table = marvell_nfc_platform_ids, 307193db446aSBoris Brezillon .probe = marvell_nfc_probe, 307293db446aSBoris Brezillon .remove = marvell_nfc_remove, 307393db446aSBoris Brezillon }; 307493db446aSBoris Brezillon module_platform_driver(marvell_nfc_driver); 307593db446aSBoris Brezillon 307693db446aSBoris Brezillon MODULE_LICENSE("GPL"); 307793db446aSBoris Brezillon MODULE_DESCRIPTION("Marvell NAND controller driver"); 3078