193db446aSBoris Brezillon // SPDX-License-Identifier: GPL-2.0 293db446aSBoris Brezillon /* 393db446aSBoris Brezillon * Marvell NAND flash controller driver 493db446aSBoris Brezillon * 593db446aSBoris Brezillon * Copyright (C) 2017 Marvell 693db446aSBoris Brezillon * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com> 793db446aSBoris Brezillon * 833c1c5feSMiquel Raynal * 933c1c5feSMiquel Raynal * This NAND controller driver handles two versions of the hardware, 1033c1c5feSMiquel Raynal * one is called NFCv1 and is available on PXA SoCs and the other is 1133c1c5feSMiquel Raynal * called NFCv2 and is available on Armada SoCs. 1233c1c5feSMiquel Raynal * 1333c1c5feSMiquel Raynal * The main visible difference is that NFCv1 only has Hamming ECC 1433c1c5feSMiquel Raynal * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA 1533c1c5feSMiquel Raynal * is not used with NFCv2. 1633c1c5feSMiquel Raynal * 1733c1c5feSMiquel Raynal * The ECC layouts are depicted in details in Marvell AN-379, but here 1833c1c5feSMiquel Raynal * is a brief description. 1933c1c5feSMiquel Raynal * 2033c1c5feSMiquel Raynal * When using Hamming, the data is split in 512B chunks (either 1, 2 2133c1c5feSMiquel Raynal * or 4) and each chunk will have its own ECC "digest" of 6B at the 2233c1c5feSMiquel Raynal * beginning of the OOB area and eventually the remaining free OOB 2333c1c5feSMiquel Raynal * bytes (also called "spare" bytes in the driver). This engine 2433c1c5feSMiquel Raynal * corrects up to 1 bit per chunk and detects reliably an error if 2533c1c5feSMiquel Raynal * there are at most 2 bitflips. Here is the page layout used by the 2633c1c5feSMiquel Raynal * controller when Hamming is chosen: 2733c1c5feSMiquel Raynal * 2833c1c5feSMiquel Raynal * +-------------------------------------------------------------+ 2933c1c5feSMiquel Raynal * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes | 3033c1c5feSMiquel Raynal * +-------------------------------------------------------------+ 3133c1c5feSMiquel Raynal * 3233c1c5feSMiquel Raynal * When using the BCH engine, there are N identical (data + free OOB + 3333c1c5feSMiquel Raynal * ECC) sections and potentially an extra one to deal with 3433c1c5feSMiquel Raynal * configurations where the chosen (data + free OOB + ECC) sizes do 3533c1c5feSMiquel Raynal * not align with the page (data + OOB) size. ECC bytes are always 3633c1c5feSMiquel Raynal * 30B per ECC chunk. Here is the page layout used by the controller 3733c1c5feSMiquel Raynal * when BCH is chosen: 3833c1c5feSMiquel Raynal * 3933c1c5feSMiquel Raynal * +----------------------------------------- 4033c1c5feSMiquel Raynal * | Data 1 | Free OOB bytes 1 | ECC 1 | ... 4133c1c5feSMiquel Raynal * +----------------------------------------- 4233c1c5feSMiquel Raynal * 4333c1c5feSMiquel Raynal * ------------------------------------------- 4433c1c5feSMiquel Raynal * ... | Data N | Free OOB bytes N | ECC N | 4533c1c5feSMiquel Raynal * ------------------------------------------- 4633c1c5feSMiquel Raynal * 4733c1c5feSMiquel Raynal * --------------------------------------------+ 4833c1c5feSMiquel Raynal * Last Data | Last Free OOB bytes | Last ECC | 4933c1c5feSMiquel Raynal * --------------------------------------------+ 5033c1c5feSMiquel Raynal * 5133c1c5feSMiquel Raynal * In both cases, the layout seen by the user is always: all data 5233c1c5feSMiquel Raynal * first, then all free OOB bytes and finally all ECC bytes. With BCH, 5333c1c5feSMiquel Raynal * ECC bytes are 30B long and are padded with 0xFF to align on 32 5433c1c5feSMiquel Raynal * bytes. 5533c1c5feSMiquel Raynal * 5633c1c5feSMiquel Raynal * The controller has certain limitations that are handled by the 5733c1c5feSMiquel Raynal * driver: 5833c1c5feSMiquel Raynal * - It can only read 2k at a time. To overcome this limitation, the 5933c1c5feSMiquel Raynal * driver issues data cycles on the bus, without issuing new 6033c1c5feSMiquel Raynal * CMD + ADDR cycles. The Marvell term is "naked" operations. 6133c1c5feSMiquel Raynal * - The ECC strength in BCH mode cannot be tuned. It is fixed 16 6233c1c5feSMiquel Raynal * bits. What can be tuned is the ECC block size as long as it 6333c1c5feSMiquel Raynal * stays between 512B and 2kiB. It's usually chosen based on the 6433c1c5feSMiquel Raynal * chip ECC requirements. For instance, using 2kiB ECC chunks 6533c1c5feSMiquel Raynal * provides 4b/512B correctability. 6633c1c5feSMiquel Raynal * - The controller will always treat data bytes, free OOB bytes 6733c1c5feSMiquel Raynal * and ECC bytes in that order, no matter what the real layout is 6833c1c5feSMiquel Raynal * (which is usually all data then all OOB bytes). The 6933c1c5feSMiquel Raynal * marvell_nfc_layouts array below contains the currently 7033c1c5feSMiquel Raynal * supported layouts. 7133c1c5feSMiquel Raynal * - Because of these weird layouts, the Bad Block Markers can be 7233c1c5feSMiquel Raynal * located in data section. In this case, the NAND_BBT_NO_OOB_BBM 7333c1c5feSMiquel Raynal * option must be set to prevent scanning/writing bad block 7433c1c5feSMiquel Raynal * markers. 7593db446aSBoris Brezillon */ 7693db446aSBoris Brezillon 7793db446aSBoris Brezillon #include <linux/module.h> 7893db446aSBoris Brezillon #include <linux/clk.h> 7993db446aSBoris Brezillon #include <linux/mtd/rawnand.h> 8093db446aSBoris Brezillon #include <linux/of_platform.h> 8193db446aSBoris Brezillon #include <linux/iopoll.h> 8293db446aSBoris Brezillon #include <linux/interrupt.h> 8393db446aSBoris Brezillon #include <linux/slab.h> 8493db446aSBoris Brezillon #include <linux/mfd/syscon.h> 8593db446aSBoris Brezillon #include <linux/regmap.h> 8693db446aSBoris Brezillon #include <asm/unaligned.h> 8793db446aSBoris Brezillon 8893db446aSBoris Brezillon #include <linux/dmaengine.h> 8993db446aSBoris Brezillon #include <linux/dma-mapping.h> 9093db446aSBoris Brezillon #include <linux/dma/pxa-dma.h> 9193db446aSBoris Brezillon #include <linux/platform_data/mtd-nand-pxa3xx.h> 9293db446aSBoris Brezillon 9393db446aSBoris Brezillon /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */ 9493db446aSBoris Brezillon #define FIFO_DEPTH 8 9593db446aSBoris Brezillon #define FIFO_REP(x) (x / sizeof(u32)) 9693db446aSBoris Brezillon #define BCH_SEQ_READS (32 / FIFO_DEPTH) 9793db446aSBoris Brezillon /* NFC does not support transfers of larger chunks at a time */ 9893db446aSBoris Brezillon #define MAX_CHUNK_SIZE 2112 9993db446aSBoris Brezillon /* NFCv1 cannot read more that 7 bytes of ID */ 10093db446aSBoris Brezillon #define NFCV1_READID_LEN 7 10193db446aSBoris Brezillon /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */ 10293db446aSBoris Brezillon #define POLL_PERIOD 0 10393db446aSBoris Brezillon #define POLL_TIMEOUT 100000 10493db446aSBoris Brezillon /* Interrupt maximum wait period in ms */ 10593db446aSBoris Brezillon #define IRQ_TIMEOUT 1000 10693db446aSBoris Brezillon /* Latency in clock cycles between SoC pins and NFC logic */ 10793db446aSBoris Brezillon #define MIN_RD_DEL_CNT 3 10893db446aSBoris Brezillon /* Maximum number of contiguous address cycles */ 10993db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV1 5 11093db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV2 7 11193db446aSBoris Brezillon /* System control registers/bits to enable the NAND controller on some SoCs */ 11293db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX 0x208 11393db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) 11493db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20) 11593db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21) 11693db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25) 11793db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL 0x220 11893db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2) 11993db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL 0x700 12093db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL_EN BIT(0) 12193db446aSBoris Brezillon 12293db446aSBoris Brezillon /* NAND controller data flash control register */ 12393db446aSBoris Brezillon #define NDCR 0x00 12493db446aSBoris Brezillon #define NDCR_ALL_INT GENMASK(11, 0) 12593db446aSBoris Brezillon #define NDCR_CS1_CMDDM BIT(7) 12693db446aSBoris Brezillon #define NDCR_CS0_CMDDM BIT(8) 12793db446aSBoris Brezillon #define NDCR_RDYM BIT(11) 12893db446aSBoris Brezillon #define NDCR_ND_ARB_EN BIT(12) 12993db446aSBoris Brezillon #define NDCR_RA_START BIT(15) 13093db446aSBoris Brezillon #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16) 13193db446aSBoris Brezillon #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0) 13293db446aSBoris Brezillon #define NDCR_DWIDTH_M BIT(26) 13393db446aSBoris Brezillon #define NDCR_DWIDTH_C BIT(27) 13493db446aSBoris Brezillon #define NDCR_ND_RUN BIT(28) 13593db446aSBoris Brezillon #define NDCR_DMA_EN BIT(29) 13693db446aSBoris Brezillon #define NDCR_ECC_EN BIT(30) 13793db446aSBoris Brezillon #define NDCR_SPARE_EN BIT(31) 13893db446aSBoris Brezillon #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \ 13993db446aSBoris Brezillon NDCR_DWIDTH_M | NDCR_DWIDTH_C)) 14093db446aSBoris Brezillon 14193db446aSBoris Brezillon /* NAND interface timing parameter 0 register */ 14293db446aSBoris Brezillon #define NDTR0 0x04 14393db446aSBoris Brezillon #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0) 14493db446aSBoris Brezillon #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3) 14593db446aSBoris Brezillon #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3) 14693db446aSBoris Brezillon #define NDTR0_SEL_NRE_EDGE BIT(7) 14793db446aSBoris Brezillon #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8) 14893db446aSBoris Brezillon #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11) 14993db446aSBoris Brezillon #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16) 15093db446aSBoris Brezillon #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19) 15193db446aSBoris Brezillon #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22) 15293db446aSBoris Brezillon #define NDTR0_SELCNTR BIT(26) 15393db446aSBoris Brezillon #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27) 15493db446aSBoris Brezillon 15593db446aSBoris Brezillon /* NAND interface timing parameter 1 register */ 15693db446aSBoris Brezillon #define NDTR1 0x0C 15793db446aSBoris Brezillon #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0) 15893db446aSBoris Brezillon #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4) 15993db446aSBoris Brezillon #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8) 16093db446aSBoris Brezillon #define NDTR1_PRESCALE BIT(14) 16193db446aSBoris Brezillon #define NDTR1_WAIT_MODE BIT(15) 16293db446aSBoris Brezillon #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16) 16393db446aSBoris Brezillon 16493db446aSBoris Brezillon /* NAND controller status register */ 16593db446aSBoris Brezillon #define NDSR 0x14 16693db446aSBoris Brezillon #define NDSR_WRCMDREQ BIT(0) 16793db446aSBoris Brezillon #define NDSR_RDDREQ BIT(1) 16893db446aSBoris Brezillon #define NDSR_WRDREQ BIT(2) 16993db446aSBoris Brezillon #define NDSR_CORERR BIT(3) 17093db446aSBoris Brezillon #define NDSR_UNCERR BIT(4) 17193db446aSBoris Brezillon #define NDSR_CMDD(cs) BIT(8 - cs) 17293db446aSBoris Brezillon #define NDSR_RDY(rb) BIT(11 + rb) 17393db446aSBoris Brezillon #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F) 17493db446aSBoris Brezillon 17593db446aSBoris Brezillon /* NAND ECC control register */ 17693db446aSBoris Brezillon #define NDECCCTRL 0x28 17793db446aSBoris Brezillon #define NDECCCTRL_BCH_EN BIT(0) 17893db446aSBoris Brezillon 17993db446aSBoris Brezillon /* NAND controller data buffer register */ 18093db446aSBoris Brezillon #define NDDB 0x40 18193db446aSBoris Brezillon 18293db446aSBoris Brezillon /* NAND controller command buffer 0 register */ 18393db446aSBoris Brezillon #define NDCB0 0x48 18493db446aSBoris Brezillon #define NDCB0_CMD1(x) ((x & 0xFF) << 0) 18593db446aSBoris Brezillon #define NDCB0_CMD2(x) ((x & 0xFF) << 8) 18693db446aSBoris Brezillon #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16) 18793db446aSBoris Brezillon #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7) 18893db446aSBoris Brezillon #define NDCB0_DBC BIT(19) 18993db446aSBoris Brezillon #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21) 19093db446aSBoris Brezillon #define NDCB0_CSEL BIT(24) 19193db446aSBoris Brezillon #define NDCB0_RDY_BYP BIT(27) 19293db446aSBoris Brezillon #define NDCB0_LEN_OVRD BIT(28) 19393db446aSBoris Brezillon #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29) 19493db446aSBoris Brezillon 19593db446aSBoris Brezillon /* NAND controller command buffer 1 register */ 19693db446aSBoris Brezillon #define NDCB1 0x4C 19793db446aSBoris Brezillon #define NDCB1_COLS(x) ((x & 0xFFFF) << 0) 19893db446aSBoris Brezillon #define NDCB1_ADDRS_PAGE(x) (x << 16) 19993db446aSBoris Brezillon 20093db446aSBoris Brezillon /* NAND controller command buffer 2 register */ 20193db446aSBoris Brezillon #define NDCB2 0x50 20293db446aSBoris Brezillon #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0) 20393db446aSBoris Brezillon #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0) 20493db446aSBoris Brezillon 20593db446aSBoris Brezillon /* NAND controller command buffer 3 register */ 20693db446aSBoris Brezillon #define NDCB3 0x54 20793db446aSBoris Brezillon #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16) 20893db446aSBoris Brezillon #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24) 20993db446aSBoris Brezillon 21093db446aSBoris Brezillon /* NAND controller command buffer 0 register 'type' and 'xtype' fields */ 21193db446aSBoris Brezillon #define TYPE_READ 0 21293db446aSBoris Brezillon #define TYPE_WRITE 1 21393db446aSBoris Brezillon #define TYPE_ERASE 2 21493db446aSBoris Brezillon #define TYPE_READ_ID 3 21593db446aSBoris Brezillon #define TYPE_STATUS 4 21693db446aSBoris Brezillon #define TYPE_RESET 5 21793db446aSBoris Brezillon #define TYPE_NAKED_CMD 6 21893db446aSBoris Brezillon #define TYPE_NAKED_ADDR 7 21993db446aSBoris Brezillon #define TYPE_MASK 7 22093db446aSBoris Brezillon #define XTYPE_MONOLITHIC_RW 0 22193db446aSBoris Brezillon #define XTYPE_LAST_NAKED_RW 1 22293db446aSBoris Brezillon #define XTYPE_FINAL_COMMAND 3 22393db446aSBoris Brezillon #define XTYPE_READ 4 22493db446aSBoris Brezillon #define XTYPE_WRITE_DISPATCH 4 22593db446aSBoris Brezillon #define XTYPE_NAKED_RW 5 22693db446aSBoris Brezillon #define XTYPE_COMMAND_DISPATCH 6 22793db446aSBoris Brezillon #define XTYPE_MASK 7 22893db446aSBoris Brezillon 22993db446aSBoris Brezillon /** 230c4bc1ec9SKrzysztof Kozlowski * struct marvell_hw_ecc_layout - layout of Marvell ECC 231c4bc1ec9SKrzysztof Kozlowski * 23293db446aSBoris Brezillon * Marvell ECC engine works differently than the others, in order to limit the 23393db446aSBoris Brezillon * size of the IP, hardware engineers chose to set a fixed strength at 16 bits 23493db446aSBoris Brezillon * per subpage, and depending on a the desired strength needed by the NAND chip, 23593db446aSBoris Brezillon * a particular layout mixing data/spare/ecc is defined, with a possible last 23693db446aSBoris Brezillon * chunk smaller that the others. 23793db446aSBoris Brezillon * 23893db446aSBoris Brezillon * @writesize: Full page size on which the layout applies 23993db446aSBoris Brezillon * @chunk: Desired ECC chunk size on which the layout applies 24093db446aSBoris Brezillon * @strength: Desired ECC strength (per chunk size bytes) on which the 24193db446aSBoris Brezillon * layout applies 24293db446aSBoris Brezillon * @nchunks: Total number of chunks 24393db446aSBoris Brezillon * @full_chunk_cnt: Number of full-sized chunks, which is the number of 24493db446aSBoris Brezillon * repetitions of the pattern: 24593db446aSBoris Brezillon * (data_bytes + spare_bytes + ecc_bytes). 24693db446aSBoris Brezillon * @data_bytes: Number of data bytes per chunk 24793db446aSBoris Brezillon * @spare_bytes: Number of spare bytes per chunk 24893db446aSBoris Brezillon * @ecc_bytes: Number of ecc bytes per chunk 24993db446aSBoris Brezillon * @last_data_bytes: Number of data bytes in the last chunk 25093db446aSBoris Brezillon * @last_spare_bytes: Number of spare bytes in the last chunk 25193db446aSBoris Brezillon * @last_ecc_bytes: Number of ecc bytes in the last chunk 25293db446aSBoris Brezillon */ 25393db446aSBoris Brezillon struct marvell_hw_ecc_layout { 25493db446aSBoris Brezillon /* Constraints */ 25593db446aSBoris Brezillon int writesize; 25693db446aSBoris Brezillon int chunk; 25793db446aSBoris Brezillon int strength; 25893db446aSBoris Brezillon /* Corresponding layout */ 25993db446aSBoris Brezillon int nchunks; 26093db446aSBoris Brezillon int full_chunk_cnt; 26193db446aSBoris Brezillon int data_bytes; 26293db446aSBoris Brezillon int spare_bytes; 26393db446aSBoris Brezillon int ecc_bytes; 26493db446aSBoris Brezillon int last_data_bytes; 26593db446aSBoris Brezillon int last_spare_bytes; 26693db446aSBoris Brezillon int last_ecc_bytes; 26793db446aSBoris Brezillon }; 26893db446aSBoris Brezillon 26993db446aSBoris Brezillon #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \ 27093db446aSBoris Brezillon { \ 27193db446aSBoris Brezillon .writesize = ws, \ 27293db446aSBoris Brezillon .chunk = dc, \ 27393db446aSBoris Brezillon .strength = ds, \ 27493db446aSBoris Brezillon .nchunks = nc, \ 27593db446aSBoris Brezillon .full_chunk_cnt = fcc, \ 27693db446aSBoris Brezillon .data_bytes = db, \ 27793db446aSBoris Brezillon .spare_bytes = sb, \ 27893db446aSBoris Brezillon .ecc_bytes = eb, \ 27993db446aSBoris Brezillon .last_data_bytes = ldb, \ 28093db446aSBoris Brezillon .last_spare_bytes = lsb, \ 28193db446aSBoris Brezillon .last_ecc_bytes = leb, \ 28293db446aSBoris Brezillon } 28393db446aSBoris Brezillon 28493db446aSBoris Brezillon /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */ 28593db446aSBoris Brezillon static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = { 28693db446aSBoris Brezillon MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0), 28793db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0), 28893db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0), 2897fd130f7SMiquel Raynal MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30), 29093db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0), 29193db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30), 292e8237bfaSKonstantin Porotchkin MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0), 293e8237bfaSKonstantin Porotchkin MARVELL_LAYOUT( 8192, 512, 8, 9, 8, 1024, 0, 30, 0, 160, 30), 29493db446aSBoris Brezillon }; 29593db446aSBoris Brezillon 29693db446aSBoris Brezillon /** 297c4bc1ec9SKrzysztof Kozlowski * struct marvell_nand_chip_sel - CS line description 298c4bc1ec9SKrzysztof Kozlowski * 29993db446aSBoris Brezillon * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection 30093db446aSBoris Brezillon * is made by a field in NDCB0 register, and in another field in NDCB2 register. 30193db446aSBoris Brezillon * The datasheet describes the logic with an error: ADDR5 field is once 30293db446aSBoris Brezillon * declared at the beginning of NDCB2, and another time at its end. Because the 30393db446aSBoris Brezillon * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical 30493db446aSBoris Brezillon * to use the last bit of this field instead of the first ones. 30593db446aSBoris Brezillon * 30693db446aSBoris Brezillon * @cs: Wanted CE lane. 30793db446aSBoris Brezillon * @ndcb0_csel: Value of the NDCB0 register with or without the flag 30893db446aSBoris Brezillon * selecting the wanted CE lane. This is set once when 30993db446aSBoris Brezillon * the Device Tree is probed. 31093db446aSBoris Brezillon * @rb: Ready/Busy pin for the flash chip 31193db446aSBoris Brezillon */ 31293db446aSBoris Brezillon struct marvell_nand_chip_sel { 31393db446aSBoris Brezillon unsigned int cs; 31493db446aSBoris Brezillon u32 ndcb0_csel; 31593db446aSBoris Brezillon unsigned int rb; 31693db446aSBoris Brezillon }; 31793db446aSBoris Brezillon 31893db446aSBoris Brezillon /** 319c4bc1ec9SKrzysztof Kozlowski * struct marvell_nand_chip - stores NAND chip device related information 32093db446aSBoris Brezillon * 32193db446aSBoris Brezillon * @chip: Base NAND chip structure 32293db446aSBoris Brezillon * @node: Used to store NAND chips into a list 323c4bc1ec9SKrzysztof Kozlowski * @layout: NAND layout when using hardware ECC 32493db446aSBoris Brezillon * @ndcr: Controller register value for this NAND chip 32593db446aSBoris Brezillon * @ndtr0: Timing registers 0 value for this NAND chip 32693db446aSBoris Brezillon * @ndtr1: Timing registers 1 value for this NAND chip 327c4bc1ec9SKrzysztof Kozlowski * @addr_cyc: Amount of cycles needed to pass column address 32893db446aSBoris Brezillon * @selected_die: Current active CS 32993db446aSBoris Brezillon * @nsels: Number of CS lines required by the NAND chip 33093db446aSBoris Brezillon * @sels: Array of CS lines descriptions 33193db446aSBoris Brezillon */ 33293db446aSBoris Brezillon struct marvell_nand_chip { 33393db446aSBoris Brezillon struct nand_chip chip; 33493db446aSBoris Brezillon struct list_head node; 33593db446aSBoris Brezillon const struct marvell_hw_ecc_layout *layout; 33693db446aSBoris Brezillon u32 ndcr; 33793db446aSBoris Brezillon u32 ndtr0; 33893db446aSBoris Brezillon u32 ndtr1; 33993db446aSBoris Brezillon int addr_cyc; 34093db446aSBoris Brezillon int selected_die; 34193db446aSBoris Brezillon unsigned int nsels; 34249f1c330SGustavo A. R. Silva struct marvell_nand_chip_sel sels[]; 34393db446aSBoris Brezillon }; 34493db446aSBoris Brezillon 34593db446aSBoris Brezillon static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip) 34693db446aSBoris Brezillon { 34793db446aSBoris Brezillon return container_of(chip, struct marvell_nand_chip, chip); 34893db446aSBoris Brezillon } 34993db446aSBoris Brezillon 35093db446aSBoris Brezillon static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip 35193db446aSBoris Brezillon *nand) 35293db446aSBoris Brezillon { 35393db446aSBoris Brezillon return &nand->sels[nand->selected_die]; 35493db446aSBoris Brezillon } 35593db446aSBoris Brezillon 35693db446aSBoris Brezillon /** 357c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc_caps - NAND controller capabilities for distinction 358c4bc1ec9SKrzysztof Kozlowski * between compatible strings 35993db446aSBoris Brezillon * 36093db446aSBoris Brezillon * @max_cs_nb: Number of Chip Select lines available 36193db446aSBoris Brezillon * @max_rb_nb: Number of Ready/Busy lines available 36293db446aSBoris Brezillon * @need_system_controller: Indicates if the SoC needs to have access to the 36393db446aSBoris Brezillon * system controller (ie. to enable the NAND controller) 36493db446aSBoris Brezillon * @legacy_of_bindings: Indicates if DT parsing must be done using the old 36593db446aSBoris Brezillon * fashion way 36693db446aSBoris Brezillon * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie. 36793db446aSBoris Brezillon * BCH error detection and correction algorithm, 36893db446aSBoris Brezillon * NDCB3 register has been added 36993db446aSBoris Brezillon * @use_dma: Use dma for data transfers 37093db446aSBoris Brezillon */ 37193db446aSBoris Brezillon struct marvell_nfc_caps { 37293db446aSBoris Brezillon unsigned int max_cs_nb; 37393db446aSBoris Brezillon unsigned int max_rb_nb; 37493db446aSBoris Brezillon bool need_system_controller; 37593db446aSBoris Brezillon bool legacy_of_bindings; 37693db446aSBoris Brezillon bool is_nfcv2; 37793db446aSBoris Brezillon bool use_dma; 37893db446aSBoris Brezillon }; 37993db446aSBoris Brezillon 38093db446aSBoris Brezillon /** 381c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc - stores Marvell NAND controller information 38293db446aSBoris Brezillon * 38393db446aSBoris Brezillon * @controller: Base controller structure 38493db446aSBoris Brezillon * @dev: Parent device (used to print error messages) 38593db446aSBoris Brezillon * @regs: NAND controller registers 3866b6de654SBoris Brezillon * @core_clk: Core clock 3871b489effSMiquel Raynal * @reg_clk: Registers clock 38893db446aSBoris Brezillon * @complete: Completion object to wait for NAND controller events 38993db446aSBoris Brezillon * @assigned_cs: Bitmask describing already assigned CS lines 39093db446aSBoris Brezillon * @chips: List containing all the NAND chips attached to 39193db446aSBoris Brezillon * this NAND controller 392c4bc1ec9SKrzysztof Kozlowski * @selected_chip: Currently selected target chip 39393db446aSBoris Brezillon * @caps: NAND controller capabilities for each compatible string 394c4bc1ec9SKrzysztof Kozlowski * @use_dma: Whetner DMA is used 39593db446aSBoris Brezillon * @dma_chan: DMA channel (NFCv1 only) 39693db446aSBoris Brezillon * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only) 39793db446aSBoris Brezillon */ 39893db446aSBoris Brezillon struct marvell_nfc { 3997da45139SMiquel Raynal struct nand_controller controller; 40093db446aSBoris Brezillon struct device *dev; 40193db446aSBoris Brezillon void __iomem *regs; 4026b6de654SBoris Brezillon struct clk *core_clk; 403961ba15cSGregory CLEMENT struct clk *reg_clk; 40493db446aSBoris Brezillon struct completion complete; 40593db446aSBoris Brezillon unsigned long assigned_cs; 40693db446aSBoris Brezillon struct list_head chips; 40793db446aSBoris Brezillon struct nand_chip *selected_chip; 40893db446aSBoris Brezillon const struct marvell_nfc_caps *caps; 40993db446aSBoris Brezillon 41093db446aSBoris Brezillon /* DMA (NFCv1 only) */ 41193db446aSBoris Brezillon bool use_dma; 41293db446aSBoris Brezillon struct dma_chan *dma_chan; 41393db446aSBoris Brezillon u8 *dma_buf; 41493db446aSBoris Brezillon }; 41593db446aSBoris Brezillon 4167da45139SMiquel Raynal static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl) 41793db446aSBoris Brezillon { 41893db446aSBoris Brezillon return container_of(ctrl, struct marvell_nfc, controller); 41993db446aSBoris Brezillon } 42093db446aSBoris Brezillon 42193db446aSBoris Brezillon /** 422c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc_timings - NAND controller timings expressed in NAND 423c4bc1ec9SKrzysztof Kozlowski * Controller clock cycles 42493db446aSBoris Brezillon * 42593db446aSBoris Brezillon * @tRP: ND_nRE pulse width 42693db446aSBoris Brezillon * @tRH: ND_nRE high duration 42793db446aSBoris Brezillon * @tWP: ND_nWE pulse time 42893db446aSBoris Brezillon * @tWH: ND_nWE high duration 42993db446aSBoris Brezillon * @tCS: Enable signal setup time 43093db446aSBoris Brezillon * @tCH: Enable signal hold time 43193db446aSBoris Brezillon * @tADL: Address to write data delay 43293db446aSBoris Brezillon * @tAR: ND_ALE low to ND_nRE low delay 43393db446aSBoris Brezillon * @tWHR: ND_nWE high to ND_nRE low for status read 43493db446aSBoris Brezillon * @tRHW: ND_nRE high duration, read to write delay 43593db446aSBoris Brezillon * @tR: ND_nWE high to ND_nRE low for read 43693db446aSBoris Brezillon */ 43793db446aSBoris Brezillon struct marvell_nfc_timings { 43893db446aSBoris Brezillon /* NDTR0 fields */ 43993db446aSBoris Brezillon unsigned int tRP; 44093db446aSBoris Brezillon unsigned int tRH; 44193db446aSBoris Brezillon unsigned int tWP; 44293db446aSBoris Brezillon unsigned int tWH; 44393db446aSBoris Brezillon unsigned int tCS; 44493db446aSBoris Brezillon unsigned int tCH; 44593db446aSBoris Brezillon unsigned int tADL; 44693db446aSBoris Brezillon /* NDTR1 fields */ 44793db446aSBoris Brezillon unsigned int tAR; 44893db446aSBoris Brezillon unsigned int tWHR; 44993db446aSBoris Brezillon unsigned int tRHW; 45093db446aSBoris Brezillon unsigned int tR; 45193db446aSBoris Brezillon }; 45293db446aSBoris Brezillon 45393db446aSBoris Brezillon /** 45493db446aSBoris Brezillon * Derives a duration in numbers of clock cycles. 45593db446aSBoris Brezillon * 45693db446aSBoris Brezillon * @ps: Duration in pico-seconds 45793db446aSBoris Brezillon * @period_ns: Clock period in nano-seconds 45893db446aSBoris Brezillon * 45993db446aSBoris Brezillon * Convert the duration in nano-seconds, then divide by the period and 46093db446aSBoris Brezillon * return the number of clock periods. 46193db446aSBoris Brezillon */ 46293db446aSBoris Brezillon #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns)) 46393db446aSBoris Brezillon #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \ 46493db446aSBoris Brezillon period_ns)) 46593db446aSBoris Brezillon 46693db446aSBoris Brezillon /** 467c4bc1ec9SKrzysztof Kozlowski * struct marvell_nfc_op - filled during the parsing of the ->exec_op() 468c4bc1ec9SKrzysztof Kozlowski * subop subset of instructions. 46993db446aSBoris Brezillon * 47093db446aSBoris Brezillon * @ndcb: Array of values written to NDCBx registers 47193db446aSBoris Brezillon * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle 47293db446aSBoris Brezillon * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin 47393db446aSBoris Brezillon * @rdy_delay_ns: Optional delay after waiting for the RB pin 47493db446aSBoris Brezillon * @data_delay_ns: Optional delay after the data xfer 47593db446aSBoris Brezillon * @data_instr_idx: Index of the data instruction in the subop 47693db446aSBoris Brezillon * @data_instr: Pointer to the data instruction in the subop 47793db446aSBoris Brezillon */ 47893db446aSBoris Brezillon struct marvell_nfc_op { 47993db446aSBoris Brezillon u32 ndcb[4]; 48093db446aSBoris Brezillon unsigned int cle_ale_delay_ns; 48193db446aSBoris Brezillon unsigned int rdy_timeout_ms; 48293db446aSBoris Brezillon unsigned int rdy_delay_ns; 48393db446aSBoris Brezillon unsigned int data_delay_ns; 48493db446aSBoris Brezillon unsigned int data_instr_idx; 48593db446aSBoris Brezillon const struct nand_op_instr *data_instr; 48693db446aSBoris Brezillon }; 48793db446aSBoris Brezillon 48893db446aSBoris Brezillon /* 48993db446aSBoris Brezillon * Internal helper to conditionnally apply a delay (from the above structure, 49093db446aSBoris Brezillon * most of the time). 49193db446aSBoris Brezillon */ 49293db446aSBoris Brezillon static void cond_delay(unsigned int ns) 49393db446aSBoris Brezillon { 49493db446aSBoris Brezillon if (!ns) 49593db446aSBoris Brezillon return; 49693db446aSBoris Brezillon 49793db446aSBoris Brezillon if (ns < 10000) 49893db446aSBoris Brezillon ndelay(ns); 49993db446aSBoris Brezillon else 50093db446aSBoris Brezillon udelay(DIV_ROUND_UP(ns, 1000)); 50193db446aSBoris Brezillon } 50293db446aSBoris Brezillon 50393db446aSBoris Brezillon /* 50493db446aSBoris Brezillon * The controller has many flags that could generate interrupts, most of them 50593db446aSBoris Brezillon * are disabled and polling is used. For the very slow signals, using interrupts 50693db446aSBoris Brezillon * may relax the CPU charge. 50793db446aSBoris Brezillon */ 50893db446aSBoris Brezillon static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask) 50993db446aSBoris Brezillon { 51093db446aSBoris Brezillon u32 reg; 51193db446aSBoris Brezillon 51293db446aSBoris Brezillon /* Writing 1 disables the interrupt */ 51393db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 51493db446aSBoris Brezillon writel_relaxed(reg | int_mask, nfc->regs + NDCR); 51593db446aSBoris Brezillon } 51693db446aSBoris Brezillon 51793db446aSBoris Brezillon static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask) 51893db446aSBoris Brezillon { 51993db446aSBoris Brezillon u32 reg; 52093db446aSBoris Brezillon 52193db446aSBoris Brezillon /* Writing 0 enables the interrupt */ 52293db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 52393db446aSBoris Brezillon writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); 52493db446aSBoris Brezillon } 52593db446aSBoris Brezillon 526cafb56ddSMiquel Raynal static u32 marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask) 52793db446aSBoris Brezillon { 528cafb56ddSMiquel Raynal u32 reg; 529cafb56ddSMiquel Raynal 530cafb56ddSMiquel Raynal reg = readl_relaxed(nfc->regs + NDSR); 53193db446aSBoris Brezillon writel_relaxed(int_mask, nfc->regs + NDSR); 532cafb56ddSMiquel Raynal 533cafb56ddSMiquel Raynal return reg & int_mask; 53493db446aSBoris Brezillon } 53593db446aSBoris Brezillon 53693db446aSBoris Brezillon static void marvell_nfc_force_byte_access(struct nand_chip *chip, 53793db446aSBoris Brezillon bool force_8bit) 53893db446aSBoris Brezillon { 53993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 54093db446aSBoris Brezillon u32 ndcr; 54193db446aSBoris Brezillon 54293db446aSBoris Brezillon /* 54393db446aSBoris Brezillon * Callers of this function do not verify if the NAND is using a 16-bit 54493db446aSBoris Brezillon * an 8-bit bus for normal operations, so we need to take care of that 54593db446aSBoris Brezillon * here by leaving the configuration unchanged if the NAND does not have 54693db446aSBoris Brezillon * the NAND_BUSWIDTH_16 flag set. 54793db446aSBoris Brezillon */ 54893db446aSBoris Brezillon if (!(chip->options & NAND_BUSWIDTH_16)) 54993db446aSBoris Brezillon return; 55093db446aSBoris Brezillon 55193db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 55293db446aSBoris Brezillon 55393db446aSBoris Brezillon if (force_8bit) 55493db446aSBoris Brezillon ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C); 55593db446aSBoris Brezillon else 55693db446aSBoris Brezillon ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 55793db446aSBoris Brezillon 55893db446aSBoris Brezillon writel_relaxed(ndcr, nfc->regs + NDCR); 55993db446aSBoris Brezillon } 56093db446aSBoris Brezillon 56193db446aSBoris Brezillon static int marvell_nfc_wait_ndrun(struct nand_chip *chip) 56293db446aSBoris Brezillon { 56393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 56493db446aSBoris Brezillon u32 val; 56593db446aSBoris Brezillon int ret; 56693db446aSBoris Brezillon 56793db446aSBoris Brezillon /* 56893db446aSBoris Brezillon * The command is being processed, wait for the ND_RUN bit to be 56993db446aSBoris Brezillon * cleared by the NFC. If not, we must clear it by hand. 57093db446aSBoris Brezillon */ 57193db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, 57293db446aSBoris Brezillon (val & NDCR_ND_RUN) == 0, 57393db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 57493db446aSBoris Brezillon if (ret) { 57593db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); 57693db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 57793db446aSBoris Brezillon nfc->regs + NDCR); 57893db446aSBoris Brezillon return ret; 57993db446aSBoris Brezillon } 58093db446aSBoris Brezillon 58193db446aSBoris Brezillon return 0; 58293db446aSBoris Brezillon } 58393db446aSBoris Brezillon 58493db446aSBoris Brezillon /* 58593db446aSBoris Brezillon * Any time a command has to be sent to the controller, the following sequence 58693db446aSBoris Brezillon * has to be followed: 58793db446aSBoris Brezillon * - call marvell_nfc_prepare_cmd() 58893db446aSBoris Brezillon * -> activate the ND_RUN bit that will kind of 'start a job' 58993db446aSBoris Brezillon * -> wait the signal indicating the NFC is waiting for a command 59093db446aSBoris Brezillon * - send the command (cmd and address cycles) 59193db446aSBoris Brezillon * - enventually send or receive the data 59293db446aSBoris Brezillon * - call marvell_nfc_end_cmd() with the corresponding flag 59393db446aSBoris Brezillon * -> wait the flag to be triggered or cancel the job with a timeout 59493db446aSBoris Brezillon * 59593db446aSBoris Brezillon * The following helpers are here to factorize the code a bit so that 59693db446aSBoris Brezillon * specialized functions responsible for executing the actual NAND 59793db446aSBoris Brezillon * operations do not have to replicate the same code blocks. 59893db446aSBoris Brezillon */ 59993db446aSBoris Brezillon static int marvell_nfc_prepare_cmd(struct nand_chip *chip) 60093db446aSBoris Brezillon { 60193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 60293db446aSBoris Brezillon u32 ndcr, val; 60393db446aSBoris Brezillon int ret; 60493db446aSBoris Brezillon 60593db446aSBoris Brezillon /* Poll ND_RUN and clear NDSR before issuing any command */ 60693db446aSBoris Brezillon ret = marvell_nfc_wait_ndrun(chip); 60793db446aSBoris Brezillon if (ret) { 60893db446aSBoris Brezillon dev_err(nfc->dev, "Last operation did not succeed\n"); 60993db446aSBoris Brezillon return ret; 61093db446aSBoris Brezillon } 61193db446aSBoris Brezillon 61293db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 61393db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); 61493db446aSBoris Brezillon 61593db446aSBoris Brezillon /* Assert ND_RUN bit and wait the NFC to be ready */ 61693db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); 61793db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 61893db446aSBoris Brezillon val & NDSR_WRCMDREQ, 61993db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 62093db446aSBoris Brezillon if (ret) { 62193db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on WRCMDRE\n"); 62293db446aSBoris Brezillon return -ETIMEDOUT; 62393db446aSBoris Brezillon } 62493db446aSBoris Brezillon 62593db446aSBoris Brezillon /* Command may be written, clear WRCMDREQ status bit */ 62693db446aSBoris Brezillon writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); 62793db446aSBoris Brezillon 62893db446aSBoris Brezillon return 0; 62993db446aSBoris Brezillon } 63093db446aSBoris Brezillon 63193db446aSBoris Brezillon static void marvell_nfc_send_cmd(struct nand_chip *chip, 63293db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 63393db446aSBoris Brezillon { 63493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 63593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 63693db446aSBoris Brezillon 63793db446aSBoris Brezillon dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" 63893db446aSBoris Brezillon "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n", 63993db446aSBoris Brezillon (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], 64093db446aSBoris Brezillon nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); 64193db446aSBoris Brezillon 64293db446aSBoris Brezillon writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], 64393db446aSBoris Brezillon nfc->regs + NDCB0); 64493db446aSBoris Brezillon writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); 64593db446aSBoris Brezillon writel(nfc_op->ndcb[2], nfc->regs + NDCB0); 64693db446aSBoris Brezillon 64793db446aSBoris Brezillon /* 64893db446aSBoris Brezillon * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7 64993db446aSBoris Brezillon * fields are used (only available on NFCv2). 65093db446aSBoris Brezillon */ 65193db446aSBoris Brezillon if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || 65293db446aSBoris Brezillon NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { 65393db446aSBoris Brezillon if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) 65493db446aSBoris Brezillon writel(nfc_op->ndcb[3], nfc->regs + NDCB0); 65593db446aSBoris Brezillon } 65693db446aSBoris Brezillon } 65793db446aSBoris Brezillon 65893db446aSBoris Brezillon static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag, 65993db446aSBoris Brezillon const char *label) 66093db446aSBoris Brezillon { 66193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 66293db446aSBoris Brezillon u32 val; 66393db446aSBoris Brezillon int ret; 66493db446aSBoris Brezillon 66593db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 66693db446aSBoris Brezillon val & flag, 66793db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 66893db446aSBoris Brezillon 66993db446aSBoris Brezillon if (ret) { 67093db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", 67193db446aSBoris Brezillon label, val); 67293db446aSBoris Brezillon if (nfc->dma_chan) 67393db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 67493db446aSBoris Brezillon return ret; 67593db446aSBoris Brezillon } 67693db446aSBoris Brezillon 67793db446aSBoris Brezillon /* 67893db446aSBoris Brezillon * DMA function uses this helper to poll on CMDD bits without wanting 67993db446aSBoris Brezillon * them to be cleared. 68093db446aSBoris Brezillon */ 68193db446aSBoris Brezillon if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) 68293db446aSBoris Brezillon return 0; 68393db446aSBoris Brezillon 68493db446aSBoris Brezillon writel_relaxed(flag, nfc->regs + NDSR); 68593db446aSBoris Brezillon 68693db446aSBoris Brezillon return 0; 68793db446aSBoris Brezillon } 68893db446aSBoris Brezillon 68993db446aSBoris Brezillon static int marvell_nfc_wait_cmdd(struct nand_chip *chip) 69093db446aSBoris Brezillon { 69193db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 69293db446aSBoris Brezillon int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); 69393db446aSBoris Brezillon 69493db446aSBoris Brezillon return marvell_nfc_end_cmd(chip, cs_flag, "CMDD"); 69593db446aSBoris Brezillon } 69693db446aSBoris Brezillon 69785a3ebbbSChris Packham static int marvell_nfc_poll_status(struct marvell_nfc *nfc, u32 mask, 69885a3ebbbSChris Packham u32 expected_val, unsigned long timeout_ms) 69985a3ebbbSChris Packham { 70085a3ebbbSChris Packham unsigned long limit; 70185a3ebbbSChris Packham u32 st; 70285a3ebbbSChris Packham 70385a3ebbbSChris Packham limit = jiffies + msecs_to_jiffies(timeout_ms); 70485a3ebbbSChris Packham do { 70585a3ebbbSChris Packham st = readl_relaxed(nfc->regs + NDSR); 70685a3ebbbSChris Packham if (st & NDSR_RDY(1)) 70785a3ebbbSChris Packham st |= NDSR_RDY(0); 70885a3ebbbSChris Packham 70985a3ebbbSChris Packham if ((st & mask) == expected_val) 71085a3ebbbSChris Packham return 0; 71185a3ebbbSChris Packham 71285a3ebbbSChris Packham cpu_relax(); 71385a3ebbbSChris Packham } while (time_after(limit, jiffies)); 71485a3ebbbSChris Packham 71585a3ebbbSChris Packham return -ETIMEDOUT; 71685a3ebbbSChris Packham } 71785a3ebbbSChris Packham 71893db446aSBoris Brezillon static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms) 71993db446aSBoris Brezillon { 72093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 72185a3ebbbSChris Packham struct mtd_info *mtd = nand_to_mtd(chip); 722cafb56ddSMiquel Raynal u32 pending; 72393db446aSBoris Brezillon int ret; 72493db446aSBoris Brezillon 72593db446aSBoris Brezillon /* Timeout is expressed in ms */ 72693db446aSBoris Brezillon if (!timeout_ms) 72793db446aSBoris Brezillon timeout_ms = IRQ_TIMEOUT; 72893db446aSBoris Brezillon 72985a3ebbbSChris Packham if (mtd->oops_panic_write) { 73085a3ebbbSChris Packham ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0), 73185a3ebbbSChris Packham NDSR_RDY(0), 73285a3ebbbSChris Packham timeout_ms); 73385a3ebbbSChris Packham } else { 73493db446aSBoris Brezillon init_completion(&nfc->complete); 73593db446aSBoris Brezillon 73693db446aSBoris Brezillon marvell_nfc_enable_int(nfc, NDCR_RDYM); 73793db446aSBoris Brezillon ret = wait_for_completion_timeout(&nfc->complete, 73893db446aSBoris Brezillon msecs_to_jiffies(timeout_ms)); 73993db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_RDYM); 74085a3ebbbSChris Packham } 741cafb56ddSMiquel Raynal pending = marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1)); 742cafb56ddSMiquel Raynal 743cafb56ddSMiquel Raynal /* 744cafb56ddSMiquel Raynal * In case the interrupt was not served in the required time frame, 745cafb56ddSMiquel Raynal * check if the ISR was not served or if something went actually wrong. 746cafb56ddSMiquel Raynal */ 747c2707577SMiquel Raynal if (!ret && !pending) { 74893db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for RB signal\n"); 74993db446aSBoris Brezillon return -ETIMEDOUT; 75093db446aSBoris Brezillon } 75193db446aSBoris Brezillon 75293db446aSBoris Brezillon return 0; 75393db446aSBoris Brezillon } 75493db446aSBoris Brezillon 755b2525141SBoris Brezillon static void marvell_nfc_select_target(struct nand_chip *chip, 756b2525141SBoris Brezillon unsigned int die_nr) 75793db446aSBoris Brezillon { 75893db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 75993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 76093db446aSBoris Brezillon u32 ndcr_generic; 76193db446aSBoris Brezillon 76293db446aSBoris Brezillon /* 76393db446aSBoris Brezillon * Reset the NDCR register to a clean state for this particular chip, 76493db446aSBoris Brezillon * also clear ND_RUN bit. 76593db446aSBoris Brezillon */ 76693db446aSBoris Brezillon ndcr_generic = readl_relaxed(nfc->regs + NDCR) & 76793db446aSBoris Brezillon NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN; 76893db446aSBoris Brezillon writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); 76993db446aSBoris Brezillon 77093db446aSBoris Brezillon /* Also reset the interrupt status register */ 77193db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 77293db446aSBoris Brezillon 7739a8f612cSMiquel Raynal if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) 7749a8f612cSMiquel Raynal return; 7759a8f612cSMiquel Raynal 7769a8f612cSMiquel Raynal writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); 7779a8f612cSMiquel Raynal writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); 7789a8f612cSMiquel Raynal 77993db446aSBoris Brezillon nfc->selected_chip = chip; 78093db446aSBoris Brezillon marvell_nand->selected_die = die_nr; 78193db446aSBoris Brezillon } 78293db446aSBoris Brezillon 78393db446aSBoris Brezillon static irqreturn_t marvell_nfc_isr(int irq, void *dev_id) 78493db446aSBoris Brezillon { 78593db446aSBoris Brezillon struct marvell_nfc *nfc = dev_id; 78693db446aSBoris Brezillon u32 st = readl_relaxed(nfc->regs + NDSR); 78793db446aSBoris Brezillon u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; 78893db446aSBoris Brezillon 78993db446aSBoris Brezillon /* 79093db446aSBoris Brezillon * RDY interrupt mask is one bit in NDCR while there are two status 79193db446aSBoris Brezillon * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]). 79293db446aSBoris Brezillon */ 79393db446aSBoris Brezillon if (st & NDSR_RDY(1)) 79493db446aSBoris Brezillon st |= NDSR_RDY(0); 79593db446aSBoris Brezillon 79693db446aSBoris Brezillon if (!(st & ien)) 79793db446aSBoris Brezillon return IRQ_NONE; 79893db446aSBoris Brezillon 79993db446aSBoris Brezillon marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT); 80093db446aSBoris Brezillon 80153c83b59SMiquel Raynal if (st & (NDSR_RDY(0) | NDSR_RDY(1))) 80293db446aSBoris Brezillon complete(&nfc->complete); 80393db446aSBoris Brezillon 80493db446aSBoris Brezillon return IRQ_HANDLED; 80593db446aSBoris Brezillon } 80693db446aSBoris Brezillon 80793db446aSBoris Brezillon /* HW ECC related functions */ 80893db446aSBoris Brezillon static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip) 80993db446aSBoris Brezillon { 81093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 81193db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 81293db446aSBoris Brezillon 81393db446aSBoris Brezillon if (!(ndcr & NDCR_ECC_EN)) { 81493db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); 81593db446aSBoris Brezillon 81693db446aSBoris Brezillon /* 81793db446aSBoris Brezillon * When enabling BCH, set threshold to 0 to always know the 81893db446aSBoris Brezillon * number of corrected bitflips. 81993db446aSBoris Brezillon */ 820e0a564aeSMiquel Raynal if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 82193db446aSBoris Brezillon writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); 82293db446aSBoris Brezillon } 82393db446aSBoris Brezillon } 82493db446aSBoris Brezillon 82593db446aSBoris Brezillon static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip) 82693db446aSBoris Brezillon { 82793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 82893db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 82993db446aSBoris Brezillon 83093db446aSBoris Brezillon if (ndcr & NDCR_ECC_EN) { 83193db446aSBoris Brezillon writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); 832e0a564aeSMiquel Raynal if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 83393db446aSBoris Brezillon writel_relaxed(0, nfc->regs + NDECCCTRL); 83493db446aSBoris Brezillon } 83593db446aSBoris Brezillon } 83693db446aSBoris Brezillon 83793db446aSBoris Brezillon /* DMA related helpers */ 83893db446aSBoris Brezillon static void marvell_nfc_enable_dma(struct marvell_nfc *nfc) 83993db446aSBoris Brezillon { 84093db446aSBoris Brezillon u32 reg; 84193db446aSBoris Brezillon 84293db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 84393db446aSBoris Brezillon writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); 84493db446aSBoris Brezillon } 84593db446aSBoris Brezillon 84693db446aSBoris Brezillon static void marvell_nfc_disable_dma(struct marvell_nfc *nfc) 84793db446aSBoris Brezillon { 84893db446aSBoris Brezillon u32 reg; 84993db446aSBoris Brezillon 85093db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 85193db446aSBoris Brezillon writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); 85293db446aSBoris Brezillon } 85393db446aSBoris Brezillon 85493db446aSBoris Brezillon /* Read/write PIO/DMA accessors */ 85593db446aSBoris Brezillon static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc, 85693db446aSBoris Brezillon enum dma_data_direction direction, 85793db446aSBoris Brezillon unsigned int len) 85893db446aSBoris Brezillon { 85993db446aSBoris Brezillon unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE); 86093db446aSBoris Brezillon struct dma_async_tx_descriptor *tx; 86193db446aSBoris Brezillon struct scatterlist sg; 86293db446aSBoris Brezillon dma_cookie_t cookie; 86393db446aSBoris Brezillon int ret; 86493db446aSBoris Brezillon 86593db446aSBoris Brezillon marvell_nfc_enable_dma(nfc); 86693db446aSBoris Brezillon /* Prepare the DMA transfer */ 86793db446aSBoris Brezillon sg_init_one(&sg, nfc->dma_buf, dma_len); 86893db446aSBoris Brezillon dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 86993db446aSBoris Brezillon tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, 87093db446aSBoris Brezillon direction == DMA_FROM_DEVICE ? 87193db446aSBoris Brezillon DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 87293db446aSBoris Brezillon DMA_PREP_INTERRUPT); 87393db446aSBoris Brezillon if (!tx) { 87493db446aSBoris Brezillon dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); 87593db446aSBoris Brezillon return -ENXIO; 87693db446aSBoris Brezillon } 87793db446aSBoris Brezillon 87893db446aSBoris Brezillon /* Do the task and wait for it to finish */ 87993db446aSBoris Brezillon cookie = dmaengine_submit(tx); 88093db446aSBoris Brezillon ret = dma_submit_error(cookie); 88193db446aSBoris Brezillon if (ret) 88293db446aSBoris Brezillon return -EIO; 88393db446aSBoris Brezillon 88493db446aSBoris Brezillon dma_async_issue_pending(nfc->dma_chan); 88593db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(nfc->selected_chip); 88693db446aSBoris Brezillon dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 88793db446aSBoris Brezillon marvell_nfc_disable_dma(nfc); 88893db446aSBoris Brezillon if (ret) { 88993db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", 89093db446aSBoris Brezillon dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); 89193db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 89293db446aSBoris Brezillon return -ETIMEDOUT; 89393db446aSBoris Brezillon } 89493db446aSBoris Brezillon 89593db446aSBoris Brezillon return 0; 89693db446aSBoris Brezillon } 89793db446aSBoris Brezillon 89893db446aSBoris Brezillon static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in, 89993db446aSBoris Brezillon unsigned int len) 90093db446aSBoris Brezillon { 90193db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 90293db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 90393db446aSBoris Brezillon int i; 90493db446aSBoris Brezillon 90593db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 90693db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); 90793db446aSBoris Brezillon 90893db446aSBoris Brezillon if (last_len) { 90993db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 91093db446aSBoris Brezillon 91193db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 91293db446aSBoris Brezillon memcpy(in + last_full_offset, tmp_buf, last_len); 91393db446aSBoris Brezillon } 91493db446aSBoris Brezillon 91593db446aSBoris Brezillon return 0; 91693db446aSBoris Brezillon } 91793db446aSBoris Brezillon 91893db446aSBoris Brezillon static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out, 91993db446aSBoris Brezillon unsigned int len) 92093db446aSBoris Brezillon { 92193db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 92293db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 92393db446aSBoris Brezillon int i; 92493db446aSBoris Brezillon 92593db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 92693db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); 92793db446aSBoris Brezillon 92893db446aSBoris Brezillon if (last_len) { 92993db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 93093db446aSBoris Brezillon 93193db446aSBoris Brezillon memcpy(tmp_buf, out + last_full_offset, last_len); 93293db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 93393db446aSBoris Brezillon } 93493db446aSBoris Brezillon 93593db446aSBoris Brezillon return 0; 93693db446aSBoris Brezillon } 93793db446aSBoris Brezillon 93893db446aSBoris Brezillon static void marvell_nfc_check_empty_chunk(struct nand_chip *chip, 93993db446aSBoris Brezillon u8 *data, int data_len, 94093db446aSBoris Brezillon u8 *spare, int spare_len, 94193db446aSBoris Brezillon u8 *ecc, int ecc_len, 94293db446aSBoris Brezillon unsigned int *max_bitflips) 94393db446aSBoris Brezillon { 94493db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 94593db446aSBoris Brezillon int bf; 94693db446aSBoris Brezillon 94793db446aSBoris Brezillon /* 94893db446aSBoris Brezillon * Blank pages (all 0xFF) that have not been written may be recognized 94993db446aSBoris Brezillon * as bad if bitflips occur, so whenever an uncorrectable error occurs, 95093db446aSBoris Brezillon * check if the entire page (with ECC bytes) is actually blank or not. 95193db446aSBoris Brezillon */ 95293db446aSBoris Brezillon if (!data) 95393db446aSBoris Brezillon data_len = 0; 95493db446aSBoris Brezillon if (!spare) 95593db446aSBoris Brezillon spare_len = 0; 95693db446aSBoris Brezillon if (!ecc) 95793db446aSBoris Brezillon ecc_len = 0; 95893db446aSBoris Brezillon 95993db446aSBoris Brezillon bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len, 96093db446aSBoris Brezillon spare, spare_len, chip->ecc.strength); 96193db446aSBoris Brezillon if (bf < 0) { 96293db446aSBoris Brezillon mtd->ecc_stats.failed++; 96393db446aSBoris Brezillon return; 96493db446aSBoris Brezillon } 96593db446aSBoris Brezillon 96693db446aSBoris Brezillon /* Update the stats and max_bitflips */ 96793db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 96893db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 96993db446aSBoris Brezillon } 97093db446aSBoris Brezillon 97193db446aSBoris Brezillon /* 9721617942aSMiquel Raynal * Check if a chunk is correct or not according to the hardware ECC engine. 97393db446aSBoris Brezillon * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however 97493db446aSBoris Brezillon * mtd->ecc_stats.failure is not, the function will instead return a non-zero 97593db446aSBoris Brezillon * value indicating that a check on the emptyness of the subpage must be 9761617942aSMiquel Raynal * performed before actually declaring the subpage as "corrupted". 97793db446aSBoris Brezillon */ 9781617942aSMiquel Raynal static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip, 97993db446aSBoris Brezillon unsigned int *max_bitflips) 98093db446aSBoris Brezillon { 98193db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 98293db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 98393db446aSBoris Brezillon int bf = 0; 98493db446aSBoris Brezillon u32 ndsr; 98593db446aSBoris Brezillon 98693db446aSBoris Brezillon ndsr = readl_relaxed(nfc->regs + NDSR); 98793db446aSBoris Brezillon 98893db446aSBoris Brezillon /* Check uncorrectable error flag */ 98993db446aSBoris Brezillon if (ndsr & NDSR_UNCERR) { 99093db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 99193db446aSBoris Brezillon 99293db446aSBoris Brezillon /* 99393db446aSBoris Brezillon * Do not increment ->ecc_stats.failed now, instead, return a 99493db446aSBoris Brezillon * non-zero value to indicate that this chunk was apparently 99593db446aSBoris Brezillon * bad, and it should be check to see if it empty or not. If 99693db446aSBoris Brezillon * the chunk (with ECC bytes) is not declared empty, the calling 99793db446aSBoris Brezillon * function must increment the failure count. 99893db446aSBoris Brezillon */ 99993db446aSBoris Brezillon return -EBADMSG; 100093db446aSBoris Brezillon } 100193db446aSBoris Brezillon 100293db446aSBoris Brezillon /* Check correctable error flag */ 100393db446aSBoris Brezillon if (ndsr & NDSR_CORERR) { 100493db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 100593db446aSBoris Brezillon 1006e0a564aeSMiquel Raynal if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 100793db446aSBoris Brezillon bf = NDSR_ERRCNT(ndsr); 100893db446aSBoris Brezillon else 100993db446aSBoris Brezillon bf = 1; 101093db446aSBoris Brezillon } 101193db446aSBoris Brezillon 101293db446aSBoris Brezillon /* Update the stats and max_bitflips */ 101393db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 101493db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 101593db446aSBoris Brezillon 101693db446aSBoris Brezillon return 0; 101793db446aSBoris Brezillon } 101893db446aSBoris Brezillon 101993db446aSBoris Brezillon /* Hamming read helpers */ 102093db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip, 102193db446aSBoris Brezillon u8 *data_buf, u8 *oob_buf, 102293db446aSBoris Brezillon bool raw, int page) 102393db446aSBoris Brezillon { 102493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 102593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 102693db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 102793db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 102893db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 102993db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 103093db446aSBoris Brezillon NDCB0_DBC | 103193db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 103293db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART), 103393db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 103493db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 103593db446aSBoris Brezillon }; 103693db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 103793db446aSBoris Brezillon int ret; 103893db446aSBoris Brezillon 103993db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 104093db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 104193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 104293db446aSBoris Brezillon 104393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 104493db446aSBoris Brezillon if (ret) 104593db446aSBoris Brezillon return ret; 104693db446aSBoris Brezillon 104793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 104893db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 104993db446aSBoris Brezillon "RDDREQ while draining FIFO (data/oob)"); 105093db446aSBoris Brezillon if (ret) 105193db446aSBoris Brezillon return ret; 105293db446aSBoris Brezillon 105393db446aSBoris Brezillon /* 105493db446aSBoris Brezillon * Read the page then the OOB area. Unlike what is shown in current 105593db446aSBoris Brezillon * documentation, spare bytes are protected by the ECC engine, and must 105693db446aSBoris Brezillon * be at the beginning of the OOB area or running this driver on legacy 105793db446aSBoris Brezillon * systems will prevent the discovery of the BBM/BBT. 105893db446aSBoris Brezillon */ 105993db446aSBoris Brezillon if (nfc->use_dma) { 106093db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE, 106193db446aSBoris Brezillon lt->data_bytes + oob_bytes); 106293db446aSBoris Brezillon memcpy(data_buf, nfc->dma_buf, lt->data_bytes); 106393db446aSBoris Brezillon memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); 106493db446aSBoris Brezillon } else { 106593db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); 106693db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes); 106793db446aSBoris Brezillon } 106893db446aSBoris Brezillon 106993db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 107093db446aSBoris Brezillon return ret; 107193db446aSBoris Brezillon } 107293db446aSBoris Brezillon 1073b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf, 107493db446aSBoris Brezillon int oob_required, int page) 107593db446aSBoris Brezillon { 1076b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 107793db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, 107893db446aSBoris Brezillon true, page); 107993db446aSBoris Brezillon } 108093db446aSBoris Brezillon 1081b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf, 1082b9761687SBoris Brezillon int oob_required, int page) 108393db446aSBoris Brezillon { 108493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 108593db446aSBoris Brezillon unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 108693db446aSBoris Brezillon int max_bitflips = 0, ret; 108793db446aSBoris Brezillon u8 *raw_buf; 108893db446aSBoris Brezillon 1089b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 109093db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 109193db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, 109293db446aSBoris Brezillon page); 10931617942aSMiquel Raynal ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips); 109493db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 109593db446aSBoris Brezillon 109693db446aSBoris Brezillon if (!ret) 109793db446aSBoris Brezillon return max_bitflips; 109893db446aSBoris Brezillon 109993db446aSBoris Brezillon /* 110093db446aSBoris Brezillon * When ECC failures are detected, check if the full page has been 110193db446aSBoris Brezillon * written or not. Ignore the failure if it is actually empty. 110293db446aSBoris Brezillon */ 110393db446aSBoris Brezillon raw_buf = kmalloc(full_sz, GFP_KERNEL); 110493db446aSBoris Brezillon if (!raw_buf) 110593db446aSBoris Brezillon return -ENOMEM; 110693db446aSBoris Brezillon 110793db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf + 110893db446aSBoris Brezillon lt->data_bytes, true, page); 110993db446aSBoris Brezillon marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0, 111093db446aSBoris Brezillon &max_bitflips); 111193db446aSBoris Brezillon kfree(raw_buf); 111293db446aSBoris Brezillon 111393db446aSBoris Brezillon return max_bitflips; 111493db446aSBoris Brezillon } 111593db446aSBoris Brezillon 111693db446aSBoris Brezillon /* 111793db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 111893db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->read_oob_raw() function 111993db446aSBoris Brezillon * also stands for ->read_oob(). 112093db446aSBoris Brezillon */ 1121b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page) 112293db446aSBoris Brezillon { 1123eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip); 112493db446aSBoris Brezillon 1125b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 1126eeab7174SBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, 1127eeab7174SBoris Brezillon true, page); 112893db446aSBoris Brezillon } 112993db446aSBoris Brezillon 113093db446aSBoris Brezillon /* Hamming write helpers */ 113193db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip, 113293db446aSBoris Brezillon const u8 *data_buf, 113393db446aSBoris Brezillon const u8 *oob_buf, bool raw, 113493db446aSBoris Brezillon int page) 113593db446aSBoris Brezillon { 1136e0160cd4SMiquel Raynal const struct nand_sdr_timings *sdr = 1137e0160cd4SMiquel Raynal nand_get_sdr_timings(nand_get_interface_config(chip)); 113893db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 113993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 114093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 114193db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 114293db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | 114393db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 114493db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN) | 114593db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_PAGEPROG) | 114693db446aSBoris Brezillon NDCB0_DBC, 114793db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 114893db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 114993db446aSBoris Brezillon }; 115093db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 115193db446aSBoris Brezillon int ret; 115293db446aSBoris Brezillon 115393db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 115493db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 115593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 115693db446aSBoris Brezillon 115793db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 115893db446aSBoris Brezillon if (ret) 115993db446aSBoris Brezillon return ret; 116093db446aSBoris Brezillon 116193db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 116293db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 116393db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 116493db446aSBoris Brezillon if (ret) 116593db446aSBoris Brezillon return ret; 116693db446aSBoris Brezillon 116793db446aSBoris Brezillon /* Write the page then the OOB area */ 116893db446aSBoris Brezillon if (nfc->use_dma) { 116993db446aSBoris Brezillon memcpy(nfc->dma_buf, data_buf, lt->data_bytes); 117093db446aSBoris Brezillon memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); 117193db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + 117293db446aSBoris Brezillon lt->ecc_bytes + lt->spare_bytes); 117393db446aSBoris Brezillon } else { 117493db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); 117593db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes); 117693db446aSBoris Brezillon } 117793db446aSBoris Brezillon 117893db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 117993db446aSBoris Brezillon if (ret) 118093db446aSBoris Brezillon return ret; 118193db446aSBoris Brezillon 118293db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, 1183e0160cd4SMiquel Raynal PSEC_TO_MSEC(sdr->tPROG_max)); 118493db446aSBoris Brezillon return ret; 118593db446aSBoris Brezillon } 118693db446aSBoris Brezillon 1187767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip, 118893db446aSBoris Brezillon const u8 *buf, 118993db446aSBoris Brezillon int oob_required, int page) 119093db446aSBoris Brezillon { 1191b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 119293db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 119393db446aSBoris Brezillon true, page); 119493db446aSBoris Brezillon } 119593db446aSBoris Brezillon 1196767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip, 119793db446aSBoris Brezillon const u8 *buf, 119893db446aSBoris Brezillon int oob_required, int page) 119993db446aSBoris Brezillon { 120093db446aSBoris Brezillon int ret; 120193db446aSBoris Brezillon 1202b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 120393db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 120493db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 120593db446aSBoris Brezillon false, page); 120693db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 120793db446aSBoris Brezillon 120893db446aSBoris Brezillon return ret; 120993db446aSBoris Brezillon } 121093db446aSBoris Brezillon 121193db446aSBoris Brezillon /* 121293db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 121393db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->write_oob_raw() function 121493db446aSBoris Brezillon * also stands for ->write_oob(). 121593db446aSBoris Brezillon */ 1216767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip, 121793db446aSBoris Brezillon int page) 121893db446aSBoris Brezillon { 1219767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1220eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip); 1221767eb6fbSBoris Brezillon 1222eeab7174SBoris Brezillon memset(buf, 0xFF, mtd->writesize); 122393db446aSBoris Brezillon 1224b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 1225eeab7174SBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 1226eeab7174SBoris Brezillon true, page); 122793db446aSBoris Brezillon } 122893db446aSBoris Brezillon 122993db446aSBoris Brezillon /* BCH read helpers */ 1230b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf, 123193db446aSBoris Brezillon int oob_required, int page) 123293db446aSBoris Brezillon { 1233b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 123493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 123593db446aSBoris Brezillon u8 *oob = chip->oob_poi; 123693db446aSBoris Brezillon int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 123793db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 123893db446aSBoris Brezillon lt->last_spare_bytes; 123993db446aSBoris Brezillon int data_len = lt->data_bytes; 124093db446aSBoris Brezillon int spare_len = lt->spare_bytes; 124193db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 124293db446aSBoris Brezillon int chunk; 124393db446aSBoris Brezillon 1244b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 1245b2525141SBoris Brezillon 124693db446aSBoris Brezillon if (oob_required) 124793db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 124893db446aSBoris Brezillon 124993db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0); 125093db446aSBoris Brezillon 125193db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 125293db446aSBoris Brezillon /* Update last chunk length */ 125393db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 125493db446aSBoris Brezillon data_len = lt->last_data_bytes; 125593db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 125693db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 125793db446aSBoris Brezillon } 125893db446aSBoris Brezillon 125993db446aSBoris Brezillon /* Read data bytes*/ 126093db446aSBoris Brezillon nand_change_read_column_op(chip, chunk * chunk_size, 126193db446aSBoris Brezillon buf + (lt->data_bytes * chunk), 126293db446aSBoris Brezillon data_len, false); 126393db446aSBoris Brezillon 126493db446aSBoris Brezillon /* Read spare bytes */ 126593db446aSBoris Brezillon nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), 1266b451f5beSMiquel Raynal spare_len, false, false); 126793db446aSBoris Brezillon 126893db446aSBoris Brezillon /* Read ECC bytes */ 126993db446aSBoris Brezillon nand_read_data_op(chip, oob + ecc_offset + 127093db446aSBoris Brezillon (ALIGN(lt->ecc_bytes, 32) * chunk), 1271b451f5beSMiquel Raynal ecc_len, false, false); 127293db446aSBoris Brezillon } 127393db446aSBoris Brezillon 127493db446aSBoris Brezillon return 0; 127593db446aSBoris Brezillon } 127693db446aSBoris Brezillon 127793db446aSBoris Brezillon static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk, 127893db446aSBoris Brezillon u8 *data, unsigned int data_len, 127993db446aSBoris Brezillon u8 *spare, unsigned int spare_len, 128093db446aSBoris Brezillon int page) 128193db446aSBoris Brezillon { 128293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 128393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 128493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 128593db446aSBoris Brezillon int i, ret; 128693db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 128793db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 128893db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 128993db446aSBoris Brezillon NDCB0_LEN_OVRD, 129093db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 129193db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 129293db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 129393db446aSBoris Brezillon }; 129493db446aSBoris Brezillon 129593db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 129693db446aSBoris Brezillon if (ret) 129793db446aSBoris Brezillon return; 129893db446aSBoris Brezillon 129993db446aSBoris Brezillon if (chunk == 0) 130093db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_DBC | 130193db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 130293db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART); 130393db446aSBoris Brezillon 130493db446aSBoris Brezillon /* 130590d61763SBoris Brezillon * Trigger the monolithic read on the first chunk, then naked read on 130690d61763SBoris Brezillon * intermediate chunks and finally a last naked read on the last chunk. 130793db446aSBoris Brezillon */ 130890d61763SBoris Brezillon if (chunk == 0) 130993db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 131090d61763SBoris Brezillon else if (chunk < lt->nchunks - 1) 131190d61763SBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 131293db446aSBoris Brezillon else 131393db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 131493db446aSBoris Brezillon 131593db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 131693db446aSBoris Brezillon 131793db446aSBoris Brezillon /* 131893db446aSBoris Brezillon * According to the datasheet, when reading from NDDB 131993db446aSBoris Brezillon * with BCH enabled, after each 32 bytes reads, we 132093db446aSBoris Brezillon * have to make sure that the NDSR.RDDREQ bit is set. 132193db446aSBoris Brezillon * 132293db446aSBoris Brezillon * Drain the FIFO, 8 32-bit reads at a time, and skip 132393db446aSBoris Brezillon * the polling on the last read. 132493db446aSBoris Brezillon * 132593db446aSBoris Brezillon * Length is a multiple of 32 bytes, hence it is a multiple of 8 too. 132693db446aSBoris Brezillon */ 132793db446aSBoris Brezillon for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 132893db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 132993db446aSBoris Brezillon "RDDREQ while draining FIFO (data)"); 133093db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data, 133193db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 133293db446aSBoris Brezillon data += FIFO_DEPTH * BCH_SEQ_READS; 133393db446aSBoris Brezillon } 133493db446aSBoris Brezillon 133593db446aSBoris Brezillon for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 133693db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 133793db446aSBoris Brezillon "RDDREQ while draining FIFO (OOB)"); 133893db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, spare, 133993db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 134093db446aSBoris Brezillon spare += FIFO_DEPTH * BCH_SEQ_READS; 134193db446aSBoris Brezillon } 134293db446aSBoris Brezillon } 134393db446aSBoris Brezillon 1344b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip, 134593db446aSBoris Brezillon u8 *buf, int oob_required, 134693db446aSBoris Brezillon int page) 134793db446aSBoris Brezillon { 1348b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 134993db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1350dbfc6718SMiquel Raynal int data_len = lt->data_bytes, spare_len = lt->spare_bytes; 1351dbfc6718SMiquel Raynal u8 *data = buf, *spare = chip->oob_poi; 135293db446aSBoris Brezillon int max_bitflips = 0; 135393db446aSBoris Brezillon u32 failure_mask = 0; 1354dbfc6718SMiquel Raynal int chunk, ret; 135593db446aSBoris Brezillon 1356b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 1357b2525141SBoris Brezillon 135893db446aSBoris Brezillon /* 135993db446aSBoris Brezillon * With BCH, OOB is not fully used (and thus not read entirely), not 136093db446aSBoris Brezillon * expected bytes could show up at the end of the OOB buffer if not 136193db446aSBoris Brezillon * explicitly erased. 136293db446aSBoris Brezillon */ 136393db446aSBoris Brezillon if (oob_required) 136493db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 136593db446aSBoris Brezillon 136693db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 136793db446aSBoris Brezillon 136893db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 136993db446aSBoris Brezillon /* Update length for the last chunk */ 137093db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 137193db446aSBoris Brezillon data_len = lt->last_data_bytes; 137293db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 137393db446aSBoris Brezillon } 137493db446aSBoris Brezillon 137593db446aSBoris Brezillon /* Read the chunk and detect number of bitflips */ 137693db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len, 137793db446aSBoris Brezillon spare, spare_len, page); 13781617942aSMiquel Raynal ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips); 137993db446aSBoris Brezillon if (ret) 138093db446aSBoris Brezillon failure_mask |= BIT(chunk); 138193db446aSBoris Brezillon 138293db446aSBoris Brezillon data += data_len; 138393db446aSBoris Brezillon spare += spare_len; 138493db446aSBoris Brezillon } 138593db446aSBoris Brezillon 138693db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 138793db446aSBoris Brezillon 138893db446aSBoris Brezillon if (!failure_mask) 138993db446aSBoris Brezillon return max_bitflips; 139093db446aSBoris Brezillon 139193db446aSBoris Brezillon /* 139293db446aSBoris Brezillon * Please note that dumping the ECC bytes during a normal read with OOB 139393db446aSBoris Brezillon * area would add a significant overhead as ECC bytes are "consumed" by 139493db446aSBoris Brezillon * the controller in normal mode and must be re-read in raw mode. To 139593db446aSBoris Brezillon * avoid dropping the performances, we prefer not to include them. The 139693db446aSBoris Brezillon * user should re-read the page in raw mode if ECC bytes are required. 1397dbfc6718SMiquel Raynal */ 1398dbfc6718SMiquel Raynal 1399dbfc6718SMiquel Raynal /* 14001617942aSMiquel Raynal * In case there is any subpage read error, we usually re-read only ECC 14011617942aSMiquel Raynal * bytes in raw mode and check if the whole page is empty. In this case, 14021617942aSMiquel Raynal * it is normal that the ECC check failed and we just ignore the error. 140393db446aSBoris Brezillon * 14047fd130f7SMiquel Raynal * However, it has been empirically observed that for some layouts (e.g 14057fd130f7SMiquel Raynal * 2k page, 8b strength per 512B chunk), the controller tries to correct 14067fd130f7SMiquel Raynal * bits and may create itself bitflips in the erased area. To overcome 14077fd130f7SMiquel Raynal * this strange behavior, the whole page is re-read in raw mode, not 14087fd130f7SMiquel Raynal * only the ECC bytes. 140993db446aSBoris Brezillon */ 141093db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 1411dbfc6718SMiquel Raynal int data_off_in_page, spare_off_in_page, ecc_off_in_page; 1412dbfc6718SMiquel Raynal int data_off, spare_off, ecc_off; 1413dbfc6718SMiquel Raynal int data_len, spare_len, ecc_len; 1414dbfc6718SMiquel Raynal 141593db446aSBoris Brezillon /* No failure reported for this chunk, move to the next one */ 141693db446aSBoris Brezillon if (!(failure_mask & BIT(chunk))) 141793db446aSBoris Brezillon continue; 141893db446aSBoris Brezillon 1419dbfc6718SMiquel Raynal data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + 1420dbfc6718SMiquel Raynal lt->ecc_bytes); 1421dbfc6718SMiquel Raynal spare_off_in_page = data_off_in_page + 1422dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->data_bytes : 1423dbfc6718SMiquel Raynal lt->last_data_bytes); 1424dbfc6718SMiquel Raynal ecc_off_in_page = spare_off_in_page + 1425dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1426dbfc6718SMiquel Raynal lt->last_spare_bytes); 1427dbfc6718SMiquel Raynal 1428dbfc6718SMiquel Raynal data_off = chunk * lt->data_bytes; 1429dbfc6718SMiquel Raynal spare_off = chunk * lt->spare_bytes; 1430dbfc6718SMiquel Raynal ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + 143193db446aSBoris Brezillon lt->last_spare_bytes + 1432dbfc6718SMiquel Raynal (chunk * (lt->ecc_bytes + 2)); 143393db446aSBoris Brezillon 1434dbfc6718SMiquel Raynal data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : 1435dbfc6718SMiquel Raynal lt->last_data_bytes; 1436dbfc6718SMiquel Raynal spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1437dbfc6718SMiquel Raynal lt->last_spare_bytes; 1438dbfc6718SMiquel Raynal ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : 1439dbfc6718SMiquel Raynal lt->last_ecc_bytes; 144093db446aSBoris Brezillon 14417fd130f7SMiquel Raynal /* 14427fd130f7SMiquel Raynal * Only re-read the ECC bytes, unless we are using the 2k/8b 14437fd130f7SMiquel Raynal * layout which is buggy in the sense that the ECC engine will 14447fd130f7SMiquel Raynal * try to correct data bytes anyway, creating bitflips. In this 14457fd130f7SMiquel Raynal * case, re-read the entire page. 14467fd130f7SMiquel Raynal */ 14477fd130f7SMiquel Raynal if (lt->writesize == 2048 && lt->strength == 8) { 14487fd130f7SMiquel Raynal nand_change_read_column_op(chip, data_off_in_page, 14497fd130f7SMiquel Raynal buf + data_off, data_len, 14507fd130f7SMiquel Raynal false); 14517fd130f7SMiquel Raynal nand_change_read_column_op(chip, spare_off_in_page, 14527fd130f7SMiquel Raynal chip->oob_poi + spare_off, spare_len, 14537fd130f7SMiquel Raynal false); 14547fd130f7SMiquel Raynal } 14557fd130f7SMiquel Raynal 1456dbfc6718SMiquel Raynal nand_change_read_column_op(chip, ecc_off_in_page, 1457dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len, 1458dbfc6718SMiquel Raynal false); 145993db446aSBoris Brezillon 146093db446aSBoris Brezillon /* Check the entire chunk (data + spare + ecc) for emptyness */ 1461dbfc6718SMiquel Raynal marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len, 1462dbfc6718SMiquel Raynal chip->oob_poi + spare_off, spare_len, 1463dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len, 146493db446aSBoris Brezillon &max_bitflips); 146593db446aSBoris Brezillon } 146693db446aSBoris Brezillon 146793db446aSBoris Brezillon return max_bitflips; 146893db446aSBoris Brezillon } 146993db446aSBoris Brezillon 1470b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page) 147193db446aSBoris Brezillon { 1472eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip); 147393db446aSBoris Brezillon 1474eeab7174SBoris Brezillon return chip->ecc.read_page_raw(chip, buf, true, page); 147593db446aSBoris Brezillon } 147693db446aSBoris Brezillon 1477b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page) 147893db446aSBoris Brezillon { 1479eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip); 148093db446aSBoris Brezillon 1481eeab7174SBoris Brezillon return chip->ecc.read_page(chip, buf, true, page); 148293db446aSBoris Brezillon } 148393db446aSBoris Brezillon 148493db446aSBoris Brezillon /* BCH write helpers */ 1485767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip, 148693db446aSBoris Brezillon const u8 *buf, 148793db446aSBoris Brezillon int oob_required, int page) 148893db446aSBoris Brezillon { 148993db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 149093db446aSBoris Brezillon int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 149193db446aSBoris Brezillon int data_len = lt->data_bytes; 149293db446aSBoris Brezillon int spare_len = lt->spare_bytes; 149393db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 149493db446aSBoris Brezillon int spare_offset = 0; 149593db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 149693db446aSBoris Brezillon lt->last_spare_bytes; 149793db446aSBoris Brezillon int chunk; 149893db446aSBoris Brezillon 1499b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 1500b2525141SBoris Brezillon 150193db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0); 150293db446aSBoris Brezillon 150393db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 150493db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 150593db446aSBoris Brezillon data_len = lt->last_data_bytes; 150693db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 150793db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 150893db446aSBoris Brezillon } 150993db446aSBoris Brezillon 151093db446aSBoris Brezillon /* Point to the column of the next chunk */ 151193db446aSBoris Brezillon nand_change_write_column_op(chip, chunk * full_chunk_size, 151293db446aSBoris Brezillon NULL, 0, false); 151393db446aSBoris Brezillon 151493db446aSBoris Brezillon /* Write the data */ 151593db446aSBoris Brezillon nand_write_data_op(chip, buf + (chunk * lt->data_bytes), 151693db446aSBoris Brezillon data_len, false); 151793db446aSBoris Brezillon 151893db446aSBoris Brezillon if (!oob_required) 151993db446aSBoris Brezillon continue; 152093db446aSBoris Brezillon 152193db446aSBoris Brezillon /* Write the spare bytes */ 152293db446aSBoris Brezillon if (spare_len) 152393db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + spare_offset, 152493db446aSBoris Brezillon spare_len, false); 152593db446aSBoris Brezillon 152693db446aSBoris Brezillon /* Write the ECC bytes */ 152793db446aSBoris Brezillon if (ecc_len) 152893db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + ecc_offset, 152993db446aSBoris Brezillon ecc_len, false); 153093db446aSBoris Brezillon 153193db446aSBoris Brezillon spare_offset += spare_len; 153293db446aSBoris Brezillon ecc_offset += ALIGN(ecc_len, 32); 153393db446aSBoris Brezillon } 153493db446aSBoris Brezillon 153593db446aSBoris Brezillon return nand_prog_page_end_op(chip); 153693db446aSBoris Brezillon } 153793db446aSBoris Brezillon 153893db446aSBoris Brezillon static int 153993db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, 154093db446aSBoris Brezillon const u8 *data, unsigned int data_len, 154193db446aSBoris Brezillon const u8 *spare, unsigned int spare_len, 154293db446aSBoris Brezillon int page) 154393db446aSBoris Brezillon { 154493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 154593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 154693db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1547a2ee41fdSMiquel Raynal u32 xtype; 154893db446aSBoris Brezillon int ret; 154993db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 155093db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD, 155193db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 155293db446aSBoris Brezillon }; 155393db446aSBoris Brezillon 155493db446aSBoris Brezillon /* 155593db446aSBoris Brezillon * First operation dispatches the CMD_SEQIN command, issue the address 155693db446aSBoris Brezillon * cycles and asks for the first chunk of data. 155793db446aSBoris Brezillon * All operations in the middle (if any) will issue a naked write and 155893db446aSBoris Brezillon * also ask for data. 155993db446aSBoris Brezillon * Last operation (if any) asks for the last chunk of data through a 156093db446aSBoris Brezillon * last naked write. 156193db446aSBoris Brezillon */ 156293db446aSBoris Brezillon if (chunk == 0) { 1563a2ee41fdSMiquel Raynal if (lt->nchunks == 1) 1564a2ee41fdSMiquel Raynal xtype = XTYPE_MONOLITHIC_RW; 1565a2ee41fdSMiquel Raynal else 1566a2ee41fdSMiquel Raynal xtype = XTYPE_WRITE_DISPATCH; 1567a2ee41fdSMiquel Raynal 1568a2ee41fdSMiquel Raynal nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | 156993db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 157093db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN); 157193db446aSBoris Brezillon nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page); 157293db446aSBoris Brezillon nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page); 157393db446aSBoris Brezillon } else if (chunk < lt->nchunks - 1) { 157493db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 157593db446aSBoris Brezillon } else { 157693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 157793db446aSBoris Brezillon } 157893db446aSBoris Brezillon 157993db446aSBoris Brezillon /* Always dispatch the PAGEPROG command on the last chunk */ 158093db446aSBoris Brezillon if (chunk == lt->nchunks - 1) 158193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC; 158293db446aSBoris Brezillon 158393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 158493db446aSBoris Brezillon if (ret) 158593db446aSBoris Brezillon return ret; 158693db446aSBoris Brezillon 158793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 158893db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 158993db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 159093db446aSBoris Brezillon if (ret) 159193db446aSBoris Brezillon return ret; 159293db446aSBoris Brezillon 159393db446aSBoris Brezillon /* Transfer the contents */ 159493db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); 159593db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); 159693db446aSBoris Brezillon 159793db446aSBoris Brezillon return 0; 159893db446aSBoris Brezillon } 159993db446aSBoris Brezillon 1600767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip, 160193db446aSBoris Brezillon const u8 *buf, 160293db446aSBoris Brezillon int oob_required, int page) 160393db446aSBoris Brezillon { 1604e0160cd4SMiquel Raynal const struct nand_sdr_timings *sdr = 1605e0160cd4SMiquel Raynal nand_get_sdr_timings(nand_get_interface_config(chip)); 1606767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 160793db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 160893db446aSBoris Brezillon const u8 *data = buf; 160993db446aSBoris Brezillon const u8 *spare = chip->oob_poi; 161093db446aSBoris Brezillon int data_len = lt->data_bytes; 161193db446aSBoris Brezillon int spare_len = lt->spare_bytes; 161293db446aSBoris Brezillon int chunk, ret; 161393db446aSBoris Brezillon 1614b2525141SBoris Brezillon marvell_nfc_select_target(chip, chip->cur_cs); 1615b2525141SBoris Brezillon 161693db446aSBoris Brezillon /* Spare data will be written anyway, so clear it to avoid garbage */ 161793db446aSBoris Brezillon if (!oob_required) 161893db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 161993db446aSBoris Brezillon 162093db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 162193db446aSBoris Brezillon 162293db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 162393db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 162493db446aSBoris Brezillon data_len = lt->last_data_bytes; 162593db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 162693db446aSBoris Brezillon } 162793db446aSBoris Brezillon 162893db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len, 162993db446aSBoris Brezillon spare, spare_len, page); 163093db446aSBoris Brezillon data += data_len; 163193db446aSBoris Brezillon spare += spare_len; 163293db446aSBoris Brezillon 163393db446aSBoris Brezillon /* 163493db446aSBoris Brezillon * Waiting only for CMDD or PAGED is not enough, ECC are 163593db446aSBoris Brezillon * partially written. No flag is set once the operation is 163693db446aSBoris Brezillon * really finished but the ND_RUN bit is cleared, so wait for it 163793db446aSBoris Brezillon * before stepping into the next command. 163893db446aSBoris Brezillon */ 163993db446aSBoris Brezillon marvell_nfc_wait_ndrun(chip); 164093db446aSBoris Brezillon } 164193db446aSBoris Brezillon 1642e0160cd4SMiquel Raynal ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max)); 164393db446aSBoris Brezillon 164493db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 164593db446aSBoris Brezillon 164693db446aSBoris Brezillon if (ret) 164793db446aSBoris Brezillon return ret; 164893db446aSBoris Brezillon 164993db446aSBoris Brezillon return 0; 165093db446aSBoris Brezillon } 165193db446aSBoris Brezillon 1652767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip, 165393db446aSBoris Brezillon int page) 165493db446aSBoris Brezillon { 1655767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1656eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip); 1657767eb6fbSBoris Brezillon 1658eeab7174SBoris Brezillon memset(buf, 0xFF, mtd->writesize); 165993db446aSBoris Brezillon 1660eeab7174SBoris Brezillon return chip->ecc.write_page_raw(chip, buf, true, page); 166193db446aSBoris Brezillon } 166293db446aSBoris Brezillon 1663767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page) 166493db446aSBoris Brezillon { 1665767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1666eeab7174SBoris Brezillon u8 *buf = nand_get_data_buf(chip); 1667767eb6fbSBoris Brezillon 1668eeab7174SBoris Brezillon memset(buf, 0xFF, mtd->writesize); 166993db446aSBoris Brezillon 1670eeab7174SBoris Brezillon return chip->ecc.write_page(chip, buf, true, page); 167193db446aSBoris Brezillon } 167293db446aSBoris Brezillon 167393db446aSBoris Brezillon /* NAND framework ->exec_op() hooks and related helpers */ 167493db446aSBoris Brezillon static void marvell_nfc_parse_instructions(struct nand_chip *chip, 167593db446aSBoris Brezillon const struct nand_subop *subop, 167693db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 167793db446aSBoris Brezillon { 167893db446aSBoris Brezillon const struct nand_op_instr *instr = NULL; 167993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 168093db446aSBoris Brezillon bool first_cmd = true; 168193db446aSBoris Brezillon unsigned int op_id; 168293db446aSBoris Brezillon int i; 168393db446aSBoris Brezillon 168493db446aSBoris Brezillon /* Reset the input structure as most of its fields will be OR'ed */ 168593db446aSBoris Brezillon memset(nfc_op, 0, sizeof(struct marvell_nfc_op)); 168693db446aSBoris Brezillon 168793db446aSBoris Brezillon for (op_id = 0; op_id < subop->ninstrs; op_id++) { 168893db446aSBoris Brezillon unsigned int offset, naddrs; 168993db446aSBoris Brezillon const u8 *addrs; 169021a26806SMiquel Raynal int len; 169193db446aSBoris Brezillon 169293db446aSBoris Brezillon instr = &subop->instrs[op_id]; 169393db446aSBoris Brezillon 169493db446aSBoris Brezillon switch (instr->type) { 169593db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 169693db446aSBoris Brezillon if (first_cmd) 169793db446aSBoris Brezillon nfc_op->ndcb[0] |= 169893db446aSBoris Brezillon NDCB0_CMD1(instr->ctx.cmd.opcode); 169993db446aSBoris Brezillon else 170093db446aSBoris Brezillon nfc_op->ndcb[0] |= 170193db446aSBoris Brezillon NDCB0_CMD2(instr->ctx.cmd.opcode) | 170293db446aSBoris Brezillon NDCB0_DBC; 170393db446aSBoris Brezillon 170493db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 170593db446aSBoris Brezillon first_cmd = false; 170693db446aSBoris Brezillon break; 170793db446aSBoris Brezillon 170893db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 170993db446aSBoris Brezillon offset = nand_subop_get_addr_start_off(subop, op_id); 171093db446aSBoris Brezillon naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 171193db446aSBoris Brezillon addrs = &instr->ctx.addr.addrs[offset]; 171293db446aSBoris Brezillon 171393db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); 171493db446aSBoris Brezillon 171593db446aSBoris Brezillon for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) 171693db446aSBoris Brezillon nfc_op->ndcb[1] |= addrs[i] << (8 * i); 171793db446aSBoris Brezillon 171893db446aSBoris Brezillon if (naddrs >= 5) 171993db446aSBoris Brezillon nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); 172093db446aSBoris Brezillon if (naddrs >= 6) 172193db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); 172293db446aSBoris Brezillon if (naddrs == 7) 172393db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); 172493db446aSBoris Brezillon 172593db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 172693db446aSBoris Brezillon break; 172793db446aSBoris Brezillon 172893db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 172993db446aSBoris Brezillon nfc_op->data_instr = instr; 173093db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 173193db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); 173293db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 173393db446aSBoris Brezillon nfc_op->ndcb[0] |= 173493db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 173593db446aSBoris Brezillon NDCB0_LEN_OVRD; 173621a26806SMiquel Raynal len = nand_subop_get_data_len(subop, op_id); 173793db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 173893db446aSBoris Brezillon } 173993db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 174093db446aSBoris Brezillon break; 174193db446aSBoris Brezillon 174293db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 174393db446aSBoris Brezillon nfc_op->data_instr = instr; 174493db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 174593db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); 174693db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 174793db446aSBoris Brezillon nfc_op->ndcb[0] |= 174893db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 174993db446aSBoris Brezillon NDCB0_LEN_OVRD; 175021a26806SMiquel Raynal len = nand_subop_get_data_len(subop, op_id); 175193db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 175293db446aSBoris Brezillon } 175393db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 175493db446aSBoris Brezillon break; 175593db446aSBoris Brezillon 175693db446aSBoris Brezillon case NAND_OP_WAITRDY_INSTR: 175793db446aSBoris Brezillon nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; 175893db446aSBoris Brezillon nfc_op->rdy_delay_ns = instr->delay_ns; 175993db446aSBoris Brezillon break; 176093db446aSBoris Brezillon } 176193db446aSBoris Brezillon } 176293db446aSBoris Brezillon } 176393db446aSBoris Brezillon 176493db446aSBoris Brezillon static int marvell_nfc_xfer_data_pio(struct nand_chip *chip, 176593db446aSBoris Brezillon const struct nand_subop *subop, 176693db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 176793db446aSBoris Brezillon { 176893db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 176993db446aSBoris Brezillon const struct nand_op_instr *instr = nfc_op->data_instr; 177093db446aSBoris Brezillon unsigned int op_id = nfc_op->data_instr_idx; 177193db446aSBoris Brezillon unsigned int len = nand_subop_get_data_len(subop, op_id); 177293db446aSBoris Brezillon unsigned int offset = nand_subop_get_data_start_off(subop, op_id); 177393db446aSBoris Brezillon bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); 177493db446aSBoris Brezillon int ret; 177593db446aSBoris Brezillon 177693db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 177793db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, true); 177893db446aSBoris Brezillon 177993db446aSBoris Brezillon if (reading) { 178093db446aSBoris Brezillon u8 *in = instr->ctx.data.buf.in + offset; 178193db446aSBoris Brezillon 178293db446aSBoris Brezillon ret = marvell_nfc_xfer_data_in_pio(nfc, in, len); 178393db446aSBoris Brezillon } else { 178493db446aSBoris Brezillon const u8 *out = instr->ctx.data.buf.out + offset; 178593db446aSBoris Brezillon 178693db446aSBoris Brezillon ret = marvell_nfc_xfer_data_out_pio(nfc, out, len); 178793db446aSBoris Brezillon } 178893db446aSBoris Brezillon 178993db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 179093db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, false); 179193db446aSBoris Brezillon 179293db446aSBoris Brezillon return ret; 179393db446aSBoris Brezillon } 179493db446aSBoris Brezillon 179593db446aSBoris Brezillon static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip, 179693db446aSBoris Brezillon const struct nand_subop *subop) 179793db446aSBoris Brezillon { 179893db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 179993db446aSBoris Brezillon bool reading; 180093db446aSBoris Brezillon int ret; 180193db446aSBoris Brezillon 180293db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 180393db446aSBoris Brezillon reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); 180493db446aSBoris Brezillon 180593db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 180693db446aSBoris Brezillon if (ret) 180793db446aSBoris Brezillon return ret; 180893db446aSBoris Brezillon 180993db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 181093db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 181193db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 181293db446aSBoris Brezillon if (ret) 181393db446aSBoris Brezillon return ret; 181493db446aSBoris Brezillon 181593db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 181693db446aSBoris Brezillon 181793db446aSBoris Brezillon if (reading) { 181893db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 181993db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 182093db446aSBoris Brezillon if (ret) 182193db446aSBoris Brezillon return ret; 182293db446aSBoris Brezillon } 182393db446aSBoris Brezillon 182493db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 182593db446aSBoris Brezillon } 182693db446aSBoris Brezillon 182793db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 182893db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 182993db446aSBoris Brezillon if (ret) 183093db446aSBoris Brezillon return ret; 183193db446aSBoris Brezillon 183293db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 183393db446aSBoris Brezillon 183493db446aSBoris Brezillon if (!reading) { 183593db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 183693db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 183793db446aSBoris Brezillon if (ret) 183893db446aSBoris Brezillon return ret; 183993db446aSBoris Brezillon } 184093db446aSBoris Brezillon 184193db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 184293db446aSBoris Brezillon } 184393db446aSBoris Brezillon 184493db446aSBoris Brezillon /* 184593db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 184693db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 184793db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 184893db446aSBoris Brezillon */ 184993db446aSBoris Brezillon if (!reading) { 185093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 185193db446aSBoris Brezillon 185293db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 185393db446aSBoris Brezillon nfc->regs + NDCR); 185493db446aSBoris Brezillon } 185593db446aSBoris Brezillon 185693db446aSBoris Brezillon return 0; 185793db446aSBoris Brezillon } 185893db446aSBoris Brezillon 185993db446aSBoris Brezillon static int marvell_nfc_naked_access_exec(struct nand_chip *chip, 186093db446aSBoris Brezillon const struct nand_subop *subop) 186193db446aSBoris Brezillon { 186293db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 186393db446aSBoris Brezillon int ret; 186493db446aSBoris Brezillon 186593db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 186693db446aSBoris Brezillon 186793db446aSBoris Brezillon /* 186893db446aSBoris Brezillon * Naked access are different in that they need to be flagged as naked 186993db446aSBoris Brezillon * by the controller. Reset the controller registers fields that inform 187093db446aSBoris Brezillon * on the type and refill them according to the ongoing operation. 187193db446aSBoris Brezillon */ 187293db446aSBoris Brezillon nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) | 187393db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MASK)); 187493db446aSBoris Brezillon switch (subop->instrs[0].type) { 187593db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 187693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD); 187793db446aSBoris Brezillon break; 187893db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 187993db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR); 188093db446aSBoris Brezillon break; 188193db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 188293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) | 188393db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 188493db446aSBoris Brezillon break; 188593db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 188693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) | 188793db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 188893db446aSBoris Brezillon break; 188993db446aSBoris Brezillon default: 189093db446aSBoris Brezillon /* This should never happen */ 189193db446aSBoris Brezillon break; 189293db446aSBoris Brezillon } 189393db446aSBoris Brezillon 189493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 189593db446aSBoris Brezillon if (ret) 189693db446aSBoris Brezillon return ret; 189793db446aSBoris Brezillon 189893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 189993db446aSBoris Brezillon 190093db446aSBoris Brezillon if (!nfc_op.data_instr) { 190193db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 190293db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 190393db446aSBoris Brezillon return ret; 190493db446aSBoris Brezillon } 190593db446aSBoris Brezillon 190693db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 190793db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 190893db446aSBoris Brezillon if (ret) 190993db446aSBoris Brezillon return ret; 191093db446aSBoris Brezillon 191193db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 191293db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 191393db446aSBoris Brezillon if (ret) 191493db446aSBoris Brezillon return ret; 191593db446aSBoris Brezillon 191693db446aSBoris Brezillon /* 191793db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 191893db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 191993db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 192093db446aSBoris Brezillon */ 192193db446aSBoris Brezillon if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { 192293db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 192393db446aSBoris Brezillon 192493db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 192593db446aSBoris Brezillon nfc->regs + NDCR); 192693db446aSBoris Brezillon } 192793db446aSBoris Brezillon 192893db446aSBoris Brezillon return 0; 192993db446aSBoris Brezillon } 193093db446aSBoris Brezillon 193193db446aSBoris Brezillon static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip, 193293db446aSBoris Brezillon const struct nand_subop *subop) 193393db446aSBoris Brezillon { 193493db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 193593db446aSBoris Brezillon int ret; 193693db446aSBoris Brezillon 193793db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 193893db446aSBoris Brezillon 193993db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 194093db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 194193db446aSBoris Brezillon 194293db446aSBoris Brezillon return ret; 194393db446aSBoris Brezillon } 194493db446aSBoris Brezillon 194593db446aSBoris Brezillon static int marvell_nfc_read_id_type_exec(struct nand_chip *chip, 194693db446aSBoris Brezillon const struct nand_subop *subop) 194793db446aSBoris Brezillon { 194893db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 194993db446aSBoris Brezillon int ret; 195093db446aSBoris Brezillon 195193db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 195293db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 195393db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID); 195493db446aSBoris Brezillon 195593db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 195693db446aSBoris Brezillon if (ret) 195793db446aSBoris Brezillon return ret; 195893db446aSBoris Brezillon 195993db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 196093db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 196193db446aSBoris Brezillon "RDDREQ while reading ID"); 196293db446aSBoris Brezillon if (ret) 196393db446aSBoris Brezillon return ret; 196493db446aSBoris Brezillon 196593db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 196693db446aSBoris Brezillon 196793db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 196893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 196993db446aSBoris Brezillon if (ret) 197093db446aSBoris Brezillon return ret; 197193db446aSBoris Brezillon } 197293db446aSBoris Brezillon 197393db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 197493db446aSBoris Brezillon 197593db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 197693db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 197793db446aSBoris Brezillon if (ret) 197893db446aSBoris Brezillon return ret; 197993db446aSBoris Brezillon 198093db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 198193db446aSBoris Brezillon 198293db446aSBoris Brezillon return 0; 198393db446aSBoris Brezillon } 198493db446aSBoris Brezillon 198593db446aSBoris Brezillon static int marvell_nfc_read_status_exec(struct nand_chip *chip, 198693db446aSBoris Brezillon const struct nand_subop *subop) 198793db446aSBoris Brezillon { 198893db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 198993db446aSBoris Brezillon int ret; 199093db446aSBoris Brezillon 199193db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 199293db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 199393db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS); 199493db446aSBoris Brezillon 199593db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 199693db446aSBoris Brezillon if (ret) 199793db446aSBoris Brezillon return ret; 199893db446aSBoris Brezillon 199993db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 200093db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 200193db446aSBoris Brezillon "RDDREQ while reading status"); 200293db446aSBoris Brezillon if (ret) 200393db446aSBoris Brezillon return ret; 200493db446aSBoris Brezillon 200593db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 200693db446aSBoris Brezillon 200793db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 200893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 200993db446aSBoris Brezillon if (ret) 201093db446aSBoris Brezillon return ret; 201193db446aSBoris Brezillon } 201293db446aSBoris Brezillon 201393db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 201493db446aSBoris Brezillon 201593db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 201693db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 201793db446aSBoris Brezillon if (ret) 201893db446aSBoris Brezillon return ret; 201993db446aSBoris Brezillon 202093db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 202193db446aSBoris Brezillon 202293db446aSBoris Brezillon return 0; 202393db446aSBoris Brezillon } 202493db446aSBoris Brezillon 202593db446aSBoris Brezillon static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip, 202693db446aSBoris Brezillon const struct nand_subop *subop) 202793db446aSBoris Brezillon { 202893db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 202993db446aSBoris Brezillon int ret; 203093db446aSBoris Brezillon 203193db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 203293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET); 203393db446aSBoris Brezillon 203493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 203593db446aSBoris Brezillon if (ret) 203693db446aSBoris Brezillon return ret; 203793db446aSBoris Brezillon 203893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 203993db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 204093db446aSBoris Brezillon if (ret) 204193db446aSBoris Brezillon return ret; 204293db446aSBoris Brezillon 204393db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 204493db446aSBoris Brezillon 204593db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 204693db446aSBoris Brezillon if (ret) 204793db446aSBoris Brezillon return ret; 204893db446aSBoris Brezillon 204993db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 205093db446aSBoris Brezillon 205193db446aSBoris Brezillon return 0; 205293db446aSBoris Brezillon } 205393db446aSBoris Brezillon 205493db446aSBoris Brezillon static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip, 205593db446aSBoris Brezillon const struct nand_subop *subop) 205693db446aSBoris Brezillon { 205793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 205893db446aSBoris Brezillon int ret; 205993db446aSBoris Brezillon 206093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 206193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE); 206293db446aSBoris Brezillon 206393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 206493db446aSBoris Brezillon if (ret) 206593db446aSBoris Brezillon return ret; 206693db446aSBoris Brezillon 206793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 206893db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 206993db446aSBoris Brezillon if (ret) 207093db446aSBoris Brezillon return ret; 207193db446aSBoris Brezillon 207293db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 207393db446aSBoris Brezillon 207493db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 207593db446aSBoris Brezillon if (ret) 207693db446aSBoris Brezillon return ret; 207793db446aSBoris Brezillon 207893db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 207993db446aSBoris Brezillon 208093db446aSBoris Brezillon return 0; 208193db446aSBoris Brezillon } 208293db446aSBoris Brezillon 208393db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER( 208493db446aSBoris Brezillon /* Monolithic reads/writes */ 208593db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 208693db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 208793db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 208893db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2), 208993db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 209093db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 209193db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 209293db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 209393db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 209493db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 209593db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2), 209693db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE), 209793db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 209893db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 209993db446aSBoris Brezillon /* Naked commands */ 210093db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 210193db446aSBoris Brezillon marvell_nfc_naked_access_exec, 210293db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false)), 210393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 210493db446aSBoris Brezillon marvell_nfc_naked_access_exec, 210593db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)), 210693db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 210793db446aSBoris Brezillon marvell_nfc_naked_access_exec, 210893db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 210993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 211093db446aSBoris Brezillon marvell_nfc_naked_access_exec, 211193db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)), 211293db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 211393db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 211493db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 211593db446aSBoris Brezillon ); 211693db446aSBoris Brezillon 211793db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER( 211893db446aSBoris Brezillon /* Naked commands not supported, use a function for each pattern */ 211993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 212093db446aSBoris Brezillon marvell_nfc_read_id_type_exec, 212193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 212293db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 212393db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), 212493db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 212593db446aSBoris Brezillon marvell_nfc_erase_cmd_type_exec, 212693db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 212793db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 212893db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 212993db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 213093db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 213193db446aSBoris Brezillon marvell_nfc_read_status_exec, 213293db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 213393db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), 213493db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 213593db446aSBoris Brezillon marvell_nfc_reset_cmd_type_exec, 213693db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 213793db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 213893db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 213993db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 214093db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 214193db446aSBoris Brezillon ); 214293db446aSBoris Brezillon 214393db446aSBoris Brezillon static int marvell_nfc_exec_op(struct nand_chip *chip, 214493db446aSBoris Brezillon const struct nand_operation *op, 214593db446aSBoris Brezillon bool check_only) 214693db446aSBoris Brezillon { 214793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 214893db446aSBoris Brezillon 2149ce446b4bSBoris Brezillon if (!check_only) 2150b2525141SBoris Brezillon marvell_nfc_select_target(chip, op->cs); 2151b2525141SBoris Brezillon 215293db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 215393db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser, 215493db446aSBoris Brezillon op, check_only); 215593db446aSBoris Brezillon else 215693db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser, 215793db446aSBoris Brezillon op, check_only); 215893db446aSBoris Brezillon } 215993db446aSBoris Brezillon 216093db446aSBoris Brezillon /* 216193db446aSBoris Brezillon * Layouts were broken in old pxa3xx_nand driver, these are supposed to be 216293db446aSBoris Brezillon * usable. 216393db446aSBoris Brezillon */ 216493db446aSBoris Brezillon static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section, 216593db446aSBoris Brezillon struct mtd_oob_region *oobregion) 216693db446aSBoris Brezillon { 216793db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 216893db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 216993db446aSBoris Brezillon 217093db446aSBoris Brezillon if (section) 217193db446aSBoris Brezillon return -ERANGE; 217293db446aSBoris Brezillon 217393db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + 217493db446aSBoris Brezillon lt->last_ecc_bytes; 217593db446aSBoris Brezillon oobregion->offset = mtd->oobsize - oobregion->length; 217693db446aSBoris Brezillon 217793db446aSBoris Brezillon return 0; 217893db446aSBoris Brezillon } 217993db446aSBoris Brezillon 218093db446aSBoris Brezillon static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section, 218193db446aSBoris Brezillon struct mtd_oob_region *oobregion) 218293db446aSBoris Brezillon { 218393db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 218493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 218593db446aSBoris Brezillon 218693db446aSBoris Brezillon if (section) 218793db446aSBoris Brezillon return -ERANGE; 218893db446aSBoris Brezillon 218993db446aSBoris Brezillon /* 219093db446aSBoris Brezillon * Bootrom looks in bytes 0 & 5 for bad blocks for the 219193db446aSBoris Brezillon * 4KB page / 4bit BCH combination. 219293db446aSBoris Brezillon */ 219393db446aSBoris Brezillon if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) 219493db446aSBoris Brezillon oobregion->offset = 6; 219593db446aSBoris Brezillon else 219693db446aSBoris Brezillon oobregion->offset = 2; 219793db446aSBoris Brezillon 219893db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + 219993db446aSBoris Brezillon lt->last_spare_bytes - oobregion->offset; 220093db446aSBoris Brezillon 220193db446aSBoris Brezillon return 0; 220293db446aSBoris Brezillon } 220393db446aSBoris Brezillon 220493db446aSBoris Brezillon static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = { 220593db446aSBoris Brezillon .ecc = marvell_nand_ooblayout_ecc, 220693db446aSBoris Brezillon .free = marvell_nand_ooblayout_free, 220793db446aSBoris Brezillon }; 220893db446aSBoris Brezillon 220982c6c04eSMiquel Raynal static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd, 221093db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 221193db446aSBoris Brezillon { 221293db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 221393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 221493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *l; 221593db446aSBoris Brezillon int i; 221693db446aSBoris Brezillon 221793db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && 221893db446aSBoris Brezillon (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { 221993db446aSBoris Brezillon dev_err(nfc->dev, 222093db446aSBoris Brezillon "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n", 222193db446aSBoris Brezillon mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); 222293db446aSBoris Brezillon return -ENOTSUPP; 222393db446aSBoris Brezillon } 222493db446aSBoris Brezillon 222593db446aSBoris Brezillon to_marvell_nand(chip)->layout = NULL; 222693db446aSBoris Brezillon for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) { 222793db446aSBoris Brezillon l = &marvell_nfc_layouts[i]; 222893db446aSBoris Brezillon if (mtd->writesize == l->writesize && 222993db446aSBoris Brezillon ecc->size == l->chunk && ecc->strength == l->strength) { 223093db446aSBoris Brezillon to_marvell_nand(chip)->layout = l; 223193db446aSBoris Brezillon break; 223293db446aSBoris Brezillon } 223393db446aSBoris Brezillon } 223493db446aSBoris Brezillon 223593db446aSBoris Brezillon if (!to_marvell_nand(chip)->layout || 223693db446aSBoris Brezillon (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { 223793db446aSBoris Brezillon dev_err(nfc->dev, 223893db446aSBoris Brezillon "ECC strength %d at page size %d is not supported\n", 223993db446aSBoris Brezillon ecc->strength, mtd->writesize); 224093db446aSBoris Brezillon return -ENOTSUPP; 224193db446aSBoris Brezillon } 224293db446aSBoris Brezillon 22437fd130f7SMiquel Raynal /* Special care for the layout 2k/8-bit/512B */ 22447fd130f7SMiquel Raynal if (l->writesize == 2048 && l->strength == 8) { 22457fd130f7SMiquel Raynal if (mtd->oobsize < 128) { 22467fd130f7SMiquel Raynal dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n"); 22477fd130f7SMiquel Raynal return -ENOTSUPP; 22487fd130f7SMiquel Raynal } else { 22497fd130f7SMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 22507fd130f7SMiquel Raynal } 22517fd130f7SMiquel Raynal } 22527fd130f7SMiquel Raynal 225393db446aSBoris Brezillon mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops); 225493db446aSBoris Brezillon ecc->steps = l->nchunks; 225593db446aSBoris Brezillon ecc->size = l->data_bytes; 225693db446aSBoris Brezillon 225793db446aSBoris Brezillon if (ecc->strength == 1) { 2258e0a564aeSMiquel Raynal chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 225993db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; 226093db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; 226193db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; 226293db446aSBoris Brezillon ecc->read_oob = ecc->read_oob_raw; 226393db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; 226493db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; 226593db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; 226693db446aSBoris Brezillon ecc->write_oob = ecc->write_oob_raw; 226793db446aSBoris Brezillon } else { 2268e0a564aeSMiquel Raynal chip->ecc.algo = NAND_ECC_ALGO_BCH; 226993db446aSBoris Brezillon ecc->strength = 16; 227093db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; 227193db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; 227293db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; 227393db446aSBoris Brezillon ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; 227493db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; 227593db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; 227693db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; 227793db446aSBoris Brezillon ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; 227893db446aSBoris Brezillon } 227993db446aSBoris Brezillon 228093db446aSBoris Brezillon return 0; 228193db446aSBoris Brezillon } 228293db446aSBoris Brezillon 228393db446aSBoris Brezillon static int marvell_nand_ecc_init(struct mtd_info *mtd, 228493db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 228593db446aSBoris Brezillon { 228693db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 228753576c7bSMiquel Raynal const struct nand_ecc_props *requirements = 228853576c7bSMiquel Raynal nanddev_get_ecc_requirements(&chip->base); 228993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 229093db446aSBoris Brezillon int ret; 229193db446aSBoris Brezillon 2292bace41f8SMiquel Raynal if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2293bace41f8SMiquel Raynal (!ecc->size || !ecc->strength)) { 229453576c7bSMiquel Raynal if (requirements->step_size && requirements->strength) { 229553576c7bSMiquel Raynal ecc->size = requirements->step_size; 229653576c7bSMiquel Raynal ecc->strength = requirements->strength; 229793db446aSBoris Brezillon } else { 229893db446aSBoris Brezillon dev_info(nfc->dev, 229993db446aSBoris Brezillon "No minimum ECC strength, using 1b/512B\n"); 230093db446aSBoris Brezillon ecc->size = 512; 230193db446aSBoris Brezillon ecc->strength = 1; 230293db446aSBoris Brezillon } 230393db446aSBoris Brezillon } 230493db446aSBoris Brezillon 2305bace41f8SMiquel Raynal switch (ecc->engine_type) { 2306bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_ON_HOST: 230782c6c04eSMiquel Raynal ret = marvell_nand_hw_ecc_controller_init(mtd, ecc); 230893db446aSBoris Brezillon if (ret) 230993db446aSBoris Brezillon return ret; 231093db446aSBoris Brezillon break; 2311bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_NONE: 2312bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_SOFT: 2313bace41f8SMiquel Raynal case NAND_ECC_ENGINE_TYPE_ON_DIE: 231493db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && 231593db446aSBoris Brezillon mtd->writesize != SZ_2K) { 231693db446aSBoris Brezillon dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", 231793db446aSBoris Brezillon mtd->writesize); 231893db446aSBoris Brezillon return -EINVAL; 231993db446aSBoris Brezillon } 232093db446aSBoris Brezillon break; 232193db446aSBoris Brezillon default: 232293db446aSBoris Brezillon return -EINVAL; 232393db446aSBoris Brezillon } 232493db446aSBoris Brezillon 232593db446aSBoris Brezillon return 0; 232693db446aSBoris Brezillon } 232793db446aSBoris Brezillon 232893db446aSBoris Brezillon static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; 232993db446aSBoris Brezillon static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; 233093db446aSBoris Brezillon 233193db446aSBoris Brezillon static struct nand_bbt_descr bbt_main_descr = { 233293db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 233393db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 233493db446aSBoris Brezillon .offs = 8, 233593db446aSBoris Brezillon .len = 6, 233693db446aSBoris Brezillon .veroffs = 14, 233793db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 233893db446aSBoris Brezillon .pattern = bbt_pattern 233993db446aSBoris Brezillon }; 234093db446aSBoris Brezillon 234193db446aSBoris Brezillon static struct nand_bbt_descr bbt_mirror_descr = { 234293db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 234393db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 234493db446aSBoris Brezillon .offs = 8, 234593db446aSBoris Brezillon .len = 6, 234693db446aSBoris Brezillon .veroffs = 14, 234793db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 234893db446aSBoris Brezillon .pattern = bbt_mirror_pattern 234993db446aSBoris Brezillon }; 235093db446aSBoris Brezillon 23514c46667bSMiquel Raynal static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, 23524c46667bSMiquel Raynal const struct nand_interface_config *conf) 235393db446aSBoris Brezillon { 235493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 235593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 23566b6de654SBoris Brezillon unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; 235793db446aSBoris Brezillon const struct nand_sdr_timings *sdr; 235893db446aSBoris Brezillon struct marvell_nfc_timings nfc_tmg; 235993db446aSBoris Brezillon int read_delay; 236093db446aSBoris Brezillon 236193db446aSBoris Brezillon sdr = nand_get_sdr_timings(conf); 236293db446aSBoris Brezillon if (IS_ERR(sdr)) 236393db446aSBoris Brezillon return PTR_ERR(sdr); 236493db446aSBoris Brezillon 236593db446aSBoris Brezillon /* 236693db446aSBoris Brezillon * SDR timings are given in pico-seconds while NFC timings must be 236793db446aSBoris Brezillon * expressed in NAND controller clock cycles, which is half of the 236893db446aSBoris Brezillon * frequency of the accessible ECC clock retrieved by clk_get_rate(). 236993db446aSBoris Brezillon * This is not written anywhere in the datasheet but was observed 237093db446aSBoris Brezillon * with an oscilloscope. 237193db446aSBoris Brezillon * 237293db446aSBoris Brezillon * NFC datasheet gives equations from which thoses calculations 237393db446aSBoris Brezillon * are derived, they tend to be slightly more restrictives than the 237493db446aSBoris Brezillon * given core timings and may improve the overall speed. 237593db446aSBoris Brezillon */ 237693db446aSBoris Brezillon nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; 237793db446aSBoris Brezillon nfc_tmg.tRH = nfc_tmg.tRP; 237893db446aSBoris Brezillon nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; 237993db446aSBoris Brezillon nfc_tmg.tWH = nfc_tmg.tWP; 238093db446aSBoris Brezillon nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); 238193db446aSBoris Brezillon nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; 238293db446aSBoris Brezillon nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); 238393db446aSBoris Brezillon /* 238493db446aSBoris Brezillon * Read delay is the time of propagation from SoC pins to NFC internal 238593db446aSBoris Brezillon * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In 238693db446aSBoris Brezillon * EDO mode, an additional delay of tRH must be taken into account so 238793db446aSBoris Brezillon * the data is sampled on the falling edge instead of the rising edge. 238893db446aSBoris Brezillon */ 238993db446aSBoris Brezillon read_delay = sdr->tRC_min >= 30000 ? 239093db446aSBoris Brezillon MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH; 239193db446aSBoris Brezillon 239293db446aSBoris Brezillon nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); 239393db446aSBoris Brezillon /* 239493db446aSBoris Brezillon * tWHR and tRHW are supposed to be read to write delays (and vice 239593db446aSBoris Brezillon * versa) but in some cases, ie. when doing a change column, they must 239693db446aSBoris Brezillon * be greater than that to be sure tCCS delay is respected. 239793db446aSBoris Brezillon */ 239893db446aSBoris Brezillon nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), 2399*e64ab8e8SZheng Yongjun period_ns) - 2; 240093db446aSBoris Brezillon nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), 240193db446aSBoris Brezillon period_ns); 240293db446aSBoris Brezillon 240393db446aSBoris Brezillon /* 240493db446aSBoris Brezillon * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays. 240593db446aSBoris Brezillon * NFCv1: No WAIT_MODE, tR must be maximal. 240693db446aSBoris Brezillon */ 240793db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 240893db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); 240993db446aSBoris Brezillon } else { 241093db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, 241193db446aSBoris Brezillon period_ns); 241293db446aSBoris Brezillon if (nfc_tmg.tR + 3 > nfc_tmg.tCH) 241393db446aSBoris Brezillon nfc_tmg.tR = nfc_tmg.tCH - 3; 241493db446aSBoris Brezillon else 241593db446aSBoris Brezillon nfc_tmg.tR = 0; 241693db446aSBoris Brezillon } 241793db446aSBoris Brezillon 241893db446aSBoris Brezillon if (chipnr < 0) 241993db446aSBoris Brezillon return 0; 242093db446aSBoris Brezillon 242193db446aSBoris Brezillon marvell_nand->ndtr0 = 242293db446aSBoris Brezillon NDTR0_TRP(nfc_tmg.tRP) | 242393db446aSBoris Brezillon NDTR0_TRH(nfc_tmg.tRH) | 242493db446aSBoris Brezillon NDTR0_ETRP(nfc_tmg.tRP) | 242593db446aSBoris Brezillon NDTR0_TWP(nfc_tmg.tWP) | 242693db446aSBoris Brezillon NDTR0_TWH(nfc_tmg.tWH) | 242793db446aSBoris Brezillon NDTR0_TCS(nfc_tmg.tCS) | 242893db446aSBoris Brezillon NDTR0_TCH(nfc_tmg.tCH); 242993db446aSBoris Brezillon 243093db446aSBoris Brezillon marvell_nand->ndtr1 = 243193db446aSBoris Brezillon NDTR1_TAR(nfc_tmg.tAR) | 243293db446aSBoris Brezillon NDTR1_TWHR(nfc_tmg.tWHR) | 243393db446aSBoris Brezillon NDTR1_TR(nfc_tmg.tR); 243493db446aSBoris Brezillon 243593db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 243693db446aSBoris Brezillon marvell_nand->ndtr0 |= 243793db446aSBoris Brezillon NDTR0_RD_CNT_DEL(read_delay) | 243893db446aSBoris Brezillon NDTR0_SELCNTR | 243993db446aSBoris Brezillon NDTR0_TADL(nfc_tmg.tADL); 244093db446aSBoris Brezillon 244193db446aSBoris Brezillon marvell_nand->ndtr1 |= 244293db446aSBoris Brezillon NDTR1_TRHW(nfc_tmg.tRHW) | 244393db446aSBoris Brezillon NDTR1_WAIT_MODE; 244493db446aSBoris Brezillon } 244593db446aSBoris Brezillon 244693db446aSBoris Brezillon return 0; 244793db446aSBoris Brezillon } 244893db446aSBoris Brezillon 24498831e48bSMiquel Raynal static int marvell_nand_attach_chip(struct nand_chip *chip) 24508831e48bSMiquel Raynal { 24518831e48bSMiquel Raynal struct mtd_info *mtd = nand_to_mtd(chip); 24528831e48bSMiquel Raynal struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 24538831e48bSMiquel Raynal struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 24548831e48bSMiquel Raynal struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); 24558831e48bSMiquel Raynal int ret; 24568831e48bSMiquel Raynal 24578831e48bSMiquel Raynal if (pdata && pdata->flash_bbt) 24588831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_USE_FLASH; 24598831e48bSMiquel Raynal 24608831e48bSMiquel Raynal if (chip->bbt_options & NAND_BBT_USE_FLASH) { 24618831e48bSMiquel Raynal /* 24628831e48bSMiquel Raynal * We'll use a bad block table stored in-flash and don't 24638831e48bSMiquel Raynal * allow writing the bad block marker to the flash. 24648831e48bSMiquel Raynal */ 24658831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 24668831e48bSMiquel Raynal chip->bbt_td = &bbt_main_descr; 24678831e48bSMiquel Raynal chip->bbt_md = &bbt_mirror_descr; 24688831e48bSMiquel Raynal } 24698831e48bSMiquel Raynal 24708831e48bSMiquel Raynal /* Save the chip-specific fields of NDCR */ 24718831e48bSMiquel Raynal marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); 24728831e48bSMiquel Raynal if (chip->options & NAND_BUSWIDTH_16) 24738831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 24748831e48bSMiquel Raynal 24758831e48bSMiquel Raynal /* 24768831e48bSMiquel Raynal * On small page NANDs, only one cycle is needed to pass the 24778831e48bSMiquel Raynal * column address. 24788831e48bSMiquel Raynal */ 24798831e48bSMiquel Raynal if (mtd->writesize <= 512) { 24808831e48bSMiquel Raynal marvell_nand->addr_cyc = 1; 24818831e48bSMiquel Raynal } else { 24828831e48bSMiquel Raynal marvell_nand->addr_cyc = 2; 24838831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_RA_START; 24848831e48bSMiquel Raynal } 24858831e48bSMiquel Raynal 24868831e48bSMiquel Raynal /* 24878831e48bSMiquel Raynal * Now add the number of cycles needed to pass the row 24888831e48bSMiquel Raynal * address. 24898831e48bSMiquel Raynal * 24908831e48bSMiquel Raynal * Addressing a chip using CS 2 or 3 should also need the third row 24918831e48bSMiquel Raynal * cycle but due to inconsistance in the documentation and lack of 24928831e48bSMiquel Raynal * hardware to test this situation, this case is not supported. 24938831e48bSMiquel Raynal */ 24948831e48bSMiquel Raynal if (chip->options & NAND_ROW_ADDR_3) 24958831e48bSMiquel Raynal marvell_nand->addr_cyc += 3; 24968831e48bSMiquel Raynal else 24978831e48bSMiquel Raynal marvell_nand->addr_cyc += 2; 24988831e48bSMiquel Raynal 24998831e48bSMiquel Raynal if (pdata) { 25008831e48bSMiquel Raynal chip->ecc.size = pdata->ecc_step_size; 25018831e48bSMiquel Raynal chip->ecc.strength = pdata->ecc_strength; 25028831e48bSMiquel Raynal } 25038831e48bSMiquel Raynal 25048831e48bSMiquel Raynal ret = marvell_nand_ecc_init(mtd, &chip->ecc); 25058831e48bSMiquel Raynal if (ret) { 25068831e48bSMiquel Raynal dev_err(nfc->dev, "ECC init failed: %d\n", ret); 25078831e48bSMiquel Raynal return ret; 25088831e48bSMiquel Raynal } 25098831e48bSMiquel Raynal 2510bace41f8SMiquel Raynal if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 25118831e48bSMiquel Raynal /* 25128831e48bSMiquel Raynal * Subpage write not available with hardware ECC, prohibit also 25138831e48bSMiquel Raynal * subpage read as in userspace subpage access would still be 25148831e48bSMiquel Raynal * allowed and subpage write, if used, would lead to numerous 25158831e48bSMiquel Raynal * uncorrectable ECC errors. 25168831e48bSMiquel Raynal */ 25178831e48bSMiquel Raynal chip->options |= NAND_NO_SUBPAGE_WRITE; 25188831e48bSMiquel Raynal } 25198831e48bSMiquel Raynal 25208831e48bSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) { 25218831e48bSMiquel Raynal /* 25228831e48bSMiquel Raynal * We keep the MTD name unchanged to avoid breaking platforms 25238831e48bSMiquel Raynal * where the MTD cmdline parser is used and the bootloader 25248831e48bSMiquel Raynal * has not been updated to use the new naming scheme. 25258831e48bSMiquel Raynal */ 25268831e48bSMiquel Raynal mtd->name = "pxa3xx_nand-0"; 25278831e48bSMiquel Raynal } else if (!mtd->name) { 25288831e48bSMiquel Raynal /* 25298831e48bSMiquel Raynal * If the new bindings are used and the bootloader has not been 25308831e48bSMiquel Raynal * updated to pass a new mtdparts parameter on the cmdline, you 25318831e48bSMiquel Raynal * should define the following property in your NAND node, ie: 25328831e48bSMiquel Raynal * 25338831e48bSMiquel Raynal * label = "main-storage"; 25348831e48bSMiquel Raynal * 25358831e48bSMiquel Raynal * This way, mtd->name will be set by the core when 25368831e48bSMiquel Raynal * nand_set_flash_node() is called. 25378831e48bSMiquel Raynal */ 25388831e48bSMiquel Raynal mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, 25398831e48bSMiquel Raynal "%s:nand.%d", dev_name(nfc->dev), 25408831e48bSMiquel Raynal marvell_nand->sels[0].cs); 25418831e48bSMiquel Raynal if (!mtd->name) { 25428831e48bSMiquel Raynal dev_err(nfc->dev, "Failed to allocate mtd->name\n"); 25438831e48bSMiquel Raynal return -ENOMEM; 25448831e48bSMiquel Raynal } 25458831e48bSMiquel Raynal } 25468831e48bSMiquel Raynal 25478831e48bSMiquel Raynal return 0; 25488831e48bSMiquel Raynal } 25498831e48bSMiquel Raynal 25508831e48bSMiquel Raynal static const struct nand_controller_ops marvell_nand_controller_ops = { 25518831e48bSMiquel Raynal .attach_chip = marvell_nand_attach_chip, 2552f2abfeb2SBoris Brezillon .exec_op = marvell_nfc_exec_op, 25534c46667bSMiquel Raynal .setup_interface = marvell_nfc_setup_interface, 25548831e48bSMiquel Raynal }; 25558831e48bSMiquel Raynal 255693db446aSBoris Brezillon static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc, 255793db446aSBoris Brezillon struct device_node *np) 255893db446aSBoris Brezillon { 255993db446aSBoris Brezillon struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev); 256093db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand; 256193db446aSBoris Brezillon struct mtd_info *mtd; 256293db446aSBoris Brezillon struct nand_chip *chip; 256393db446aSBoris Brezillon int nsels, ret, i; 256493db446aSBoris Brezillon u32 cs, rb; 256593db446aSBoris Brezillon 256693db446aSBoris Brezillon /* 256793db446aSBoris Brezillon * The legacy "num-cs" property indicates the number of CS on the only 256893db446aSBoris Brezillon * chip connected to the controller (legacy bindings does not support 2569f6997becSMiquel Raynal * more than one chip). The CS and RB pins are always the #0. 257093db446aSBoris Brezillon * 257193db446aSBoris Brezillon * When not using legacy bindings, a couple of "reg" and "nand-rb" 257293db446aSBoris Brezillon * properties must be filled. For each chip, expressed as a subnode, 257393db446aSBoris Brezillon * "reg" points to the CS lines and "nand-rb" to the RB line. 257493db446aSBoris Brezillon */ 2575f6997becSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) { 257693db446aSBoris Brezillon nsels = 1; 2577f6997becSMiquel Raynal } else { 2578f6997becSMiquel Raynal nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32)); 2579f6997becSMiquel Raynal if (nsels <= 0) { 2580f6997becSMiquel Raynal dev_err(dev, "missing/invalid reg property\n"); 258193db446aSBoris Brezillon return -EINVAL; 258293db446aSBoris Brezillon } 258393db446aSBoris Brezillon } 258493db446aSBoris Brezillon 258593db446aSBoris Brezillon /* Alloc the nand chip structure */ 25867b301965SGustavo A. R. Silva marvell_nand = devm_kzalloc(dev, 25877b301965SGustavo A. R. Silva struct_size(marvell_nand, sels, nsels), 258893db446aSBoris Brezillon GFP_KERNEL); 258993db446aSBoris Brezillon if (!marvell_nand) { 259093db446aSBoris Brezillon dev_err(dev, "could not allocate chip structure\n"); 259193db446aSBoris Brezillon return -ENOMEM; 259293db446aSBoris Brezillon } 259393db446aSBoris Brezillon 259493db446aSBoris Brezillon marvell_nand->nsels = nsels; 259593db446aSBoris Brezillon marvell_nand->selected_die = -1; 259693db446aSBoris Brezillon 259793db446aSBoris Brezillon for (i = 0; i < nsels; i++) { 259893db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 259993db446aSBoris Brezillon /* 260093db446aSBoris Brezillon * Legacy bindings use the CS lines in natural 260193db446aSBoris Brezillon * order (0, 1, ...) 260293db446aSBoris Brezillon */ 260393db446aSBoris Brezillon cs = i; 260493db446aSBoris Brezillon } else { 260593db446aSBoris Brezillon /* Retrieve CS id */ 260693db446aSBoris Brezillon ret = of_property_read_u32_index(np, "reg", i, &cs); 260793db446aSBoris Brezillon if (ret) { 260893db446aSBoris Brezillon dev_err(dev, "could not retrieve reg property: %d\n", 260993db446aSBoris Brezillon ret); 261093db446aSBoris Brezillon return ret; 261193db446aSBoris Brezillon } 261293db446aSBoris Brezillon } 261393db446aSBoris Brezillon 261493db446aSBoris Brezillon if (cs >= nfc->caps->max_cs_nb) { 261593db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max CS = %d)\n", 261693db446aSBoris Brezillon cs, nfc->caps->max_cs_nb); 261793db446aSBoris Brezillon return -EINVAL; 261893db446aSBoris Brezillon } 261993db446aSBoris Brezillon 262093db446aSBoris Brezillon if (test_and_set_bit(cs, &nfc->assigned_cs)) { 262193db446aSBoris Brezillon dev_err(dev, "CS %d already assigned\n", cs); 262293db446aSBoris Brezillon return -EINVAL; 262393db446aSBoris Brezillon } 262493db446aSBoris Brezillon 262593db446aSBoris Brezillon /* 262693db446aSBoris Brezillon * The cs variable represents the chip select id, which must be 262793db446aSBoris Brezillon * converted in bit fields for NDCB0 and NDCB2 to select the 262893db446aSBoris Brezillon * right chip. Unfortunately, due to a lack of information on 262993db446aSBoris Brezillon * the subject and incoherent documentation, the user should not 263093db446aSBoris Brezillon * use CS1 and CS3 at all as asserting them is not supported in 263193db446aSBoris Brezillon * a reliable way (due to multiplexing inside ADDR5 field). 263293db446aSBoris Brezillon */ 263393db446aSBoris Brezillon marvell_nand->sels[i].cs = cs; 263493db446aSBoris Brezillon switch (cs) { 263593db446aSBoris Brezillon case 0: 263693db446aSBoris Brezillon case 2: 263793db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = 0; 263893db446aSBoris Brezillon break; 263993db446aSBoris Brezillon case 1: 264093db446aSBoris Brezillon case 3: 264193db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; 264293db446aSBoris Brezillon break; 264393db446aSBoris Brezillon default: 264493db446aSBoris Brezillon return -EINVAL; 264593db446aSBoris Brezillon } 264693db446aSBoris Brezillon 264793db446aSBoris Brezillon /* Retrieve RB id */ 264893db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 264993db446aSBoris Brezillon /* Legacy bindings always use RB #0 */ 265093db446aSBoris Brezillon rb = 0; 265193db446aSBoris Brezillon } else { 265293db446aSBoris Brezillon ret = of_property_read_u32_index(np, "nand-rb", i, 265393db446aSBoris Brezillon &rb); 265493db446aSBoris Brezillon if (ret) { 265593db446aSBoris Brezillon dev_err(dev, 265693db446aSBoris Brezillon "could not retrieve RB property: %d\n", 265793db446aSBoris Brezillon ret); 265893db446aSBoris Brezillon return ret; 265993db446aSBoris Brezillon } 266093db446aSBoris Brezillon } 266193db446aSBoris Brezillon 266293db446aSBoris Brezillon if (rb >= nfc->caps->max_rb_nb) { 266393db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max RB = %d)\n", 266493db446aSBoris Brezillon rb, nfc->caps->max_rb_nb); 266593db446aSBoris Brezillon return -EINVAL; 266693db446aSBoris Brezillon } 266793db446aSBoris Brezillon 266893db446aSBoris Brezillon marvell_nand->sels[i].rb = rb; 266993db446aSBoris Brezillon } 267093db446aSBoris Brezillon 267193db446aSBoris Brezillon chip = &marvell_nand->chip; 267293db446aSBoris Brezillon chip->controller = &nfc->controller; 267393db446aSBoris Brezillon nand_set_flash_node(chip, np); 267493db446aSBoris Brezillon 267593db446aSBoris Brezillon if (!of_property_read_bool(np, "marvell,nand-keep-config")) 26767a08dbaeSBoris Brezillon chip->options |= NAND_KEEP_TIMINGS; 267793db446aSBoris Brezillon 267893db446aSBoris Brezillon mtd = nand_to_mtd(chip); 267993db446aSBoris Brezillon mtd->dev.parent = dev; 268093db446aSBoris Brezillon 268193db446aSBoris Brezillon /* 268293db446aSBoris Brezillon * Save a reference value for timing registers before 26834c46667bSMiquel Raynal * ->setup_interface() is called. 268493db446aSBoris Brezillon */ 268593db446aSBoris Brezillon marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); 268693db446aSBoris Brezillon marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); 268793db446aSBoris Brezillon 268893db446aSBoris Brezillon chip->options |= NAND_BUSWIDTH_AUTO; 26898831e48bSMiquel Raynal 269000ad378fSBoris Brezillon ret = nand_scan(chip, marvell_nand->nsels); 269193db446aSBoris Brezillon if (ret) { 26928831e48bSMiquel Raynal dev_err(dev, "could not scan the nand chip\n"); 269393db446aSBoris Brezillon return ret; 269493db446aSBoris Brezillon } 269593db446aSBoris Brezillon 269693db446aSBoris Brezillon if (pdata) 269793db446aSBoris Brezillon /* Legacy bindings support only one chip */ 26983383fb35SBoris Brezillon ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); 269993db446aSBoris Brezillon else 270093db446aSBoris Brezillon ret = mtd_device_register(mtd, NULL, 0); 270193db446aSBoris Brezillon if (ret) { 270293db446aSBoris Brezillon dev_err(dev, "failed to register mtd device: %d\n", ret); 27037a0c18fbSMiquel Raynal nand_cleanup(chip); 270493db446aSBoris Brezillon return ret; 270593db446aSBoris Brezillon } 270693db446aSBoris Brezillon 270793db446aSBoris Brezillon list_add_tail(&marvell_nand->node, &nfc->chips); 270893db446aSBoris Brezillon 270993db446aSBoris Brezillon return 0; 271093db446aSBoris Brezillon } 271193db446aSBoris Brezillon 2712c525b7afSMiquel Raynal static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc) 2713c525b7afSMiquel Raynal { 2714c525b7afSMiquel Raynal struct marvell_nand_chip *entry, *temp; 27155ecbba61SMiquel Raynal struct nand_chip *chip; 27165ecbba61SMiquel Raynal int ret; 2717c525b7afSMiquel Raynal 2718c525b7afSMiquel Raynal list_for_each_entry_safe(entry, temp, &nfc->chips, node) { 27195ecbba61SMiquel Raynal chip = &entry->chip; 27205ecbba61SMiquel Raynal ret = mtd_device_unregister(nand_to_mtd(chip)); 27215ecbba61SMiquel Raynal WARN_ON(ret); 27225ecbba61SMiquel Raynal nand_cleanup(chip); 2723c525b7afSMiquel Raynal list_del(&entry->node); 2724c525b7afSMiquel Raynal } 2725c525b7afSMiquel Raynal } 2726c525b7afSMiquel Raynal 272793db446aSBoris Brezillon static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc) 272893db446aSBoris Brezillon { 272993db446aSBoris Brezillon struct device_node *np = dev->of_node; 273093db446aSBoris Brezillon struct device_node *nand_np; 273193db446aSBoris Brezillon int max_cs = nfc->caps->max_cs_nb; 273293db446aSBoris Brezillon int nchips; 273393db446aSBoris Brezillon int ret; 273493db446aSBoris Brezillon 273593db446aSBoris Brezillon if (!np) 273693db446aSBoris Brezillon nchips = 1; 273793db446aSBoris Brezillon else 273893db446aSBoris Brezillon nchips = of_get_child_count(np); 273993db446aSBoris Brezillon 274093db446aSBoris Brezillon if (nchips > max_cs) { 274193db446aSBoris Brezillon dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, 274293db446aSBoris Brezillon max_cs); 274393db446aSBoris Brezillon return -EINVAL; 274493db446aSBoris Brezillon } 274593db446aSBoris Brezillon 274693db446aSBoris Brezillon /* 274793db446aSBoris Brezillon * Legacy bindings do not use child nodes to exhibit NAND chip 274893db446aSBoris Brezillon * properties and layout. Instead, NAND properties are mixed with the 274993db446aSBoris Brezillon * controller ones, and partitions are defined as direct subnodes of the 275093db446aSBoris Brezillon * NAND controller node. 275193db446aSBoris Brezillon */ 275293db446aSBoris Brezillon if (nfc->caps->legacy_of_bindings) { 275393db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, np); 275493db446aSBoris Brezillon return ret; 275593db446aSBoris Brezillon } 275693db446aSBoris Brezillon 275793db446aSBoris Brezillon for_each_child_of_node(np, nand_np) { 275893db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, nand_np); 275993db446aSBoris Brezillon if (ret) { 276093db446aSBoris Brezillon of_node_put(nand_np); 2761c525b7afSMiquel Raynal goto cleanup_chips; 276293db446aSBoris Brezillon } 276393db446aSBoris Brezillon } 276493db446aSBoris Brezillon 276593db446aSBoris Brezillon return 0; 276693db446aSBoris Brezillon 2767c525b7afSMiquel Raynal cleanup_chips: 2768c525b7afSMiquel Raynal marvell_nand_chips_cleanup(nfc); 276993db446aSBoris Brezillon 2770c525b7afSMiquel Raynal return ret; 277193db446aSBoris Brezillon } 277293db446aSBoris Brezillon 277393db446aSBoris Brezillon static int marvell_nfc_init_dma(struct marvell_nfc *nfc) 277493db446aSBoris Brezillon { 277593db446aSBoris Brezillon struct platform_device *pdev = container_of(nfc->dev, 277693db446aSBoris Brezillon struct platform_device, 277793db446aSBoris Brezillon dev); 277893db446aSBoris Brezillon struct dma_slave_config config = {}; 277993db446aSBoris Brezillon struct resource *r; 278093db446aSBoris Brezillon int ret; 278193db446aSBoris Brezillon 278293db446aSBoris Brezillon if (!IS_ENABLED(CONFIG_PXA_DMA)) { 278393db446aSBoris Brezillon dev_warn(nfc->dev, 278493db446aSBoris Brezillon "DMA not enabled in configuration\n"); 278593db446aSBoris Brezillon return -ENOTSUPP; 278693db446aSBoris Brezillon } 278793db446aSBoris Brezillon 278893db446aSBoris Brezillon ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); 278993db446aSBoris Brezillon if (ret) 279093db446aSBoris Brezillon return ret; 279193db446aSBoris Brezillon 2792cf9e2389SPeter Ujfalusi nfc->dma_chan = dma_request_chan(nfc->dev, "data"); 2793cf9e2389SPeter Ujfalusi if (IS_ERR(nfc->dma_chan)) { 2794cf9e2389SPeter Ujfalusi ret = PTR_ERR(nfc->dma_chan); 2795cf9e2389SPeter Ujfalusi nfc->dma_chan = NULL; 27966ce92faeSKrzysztof Kozlowski return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n"); 279793db446aSBoris Brezillon } 279893db446aSBoris Brezillon 279993db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2800aafe30baSPeter Ujfalusi if (!r) { 2801aafe30baSPeter Ujfalusi ret = -ENXIO; 2802aafe30baSPeter Ujfalusi goto release_channel; 2803aafe30baSPeter Ujfalusi } 280493db446aSBoris Brezillon 280593db446aSBoris Brezillon config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 280693db446aSBoris Brezillon config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 280793db446aSBoris Brezillon config.src_addr = r->start + NDDB; 280893db446aSBoris Brezillon config.dst_addr = r->start + NDDB; 280993db446aSBoris Brezillon config.src_maxburst = 32; 281093db446aSBoris Brezillon config.dst_maxburst = 32; 281193db446aSBoris Brezillon ret = dmaengine_slave_config(nfc->dma_chan, &config); 281293db446aSBoris Brezillon if (ret < 0) { 281393db446aSBoris Brezillon dev_err(nfc->dev, "Failed to configure DMA channel\n"); 2814aafe30baSPeter Ujfalusi goto release_channel; 281593db446aSBoris Brezillon } 281693db446aSBoris Brezillon 281793db446aSBoris Brezillon /* 281893db446aSBoris Brezillon * DMA must act on length multiple of 32 and this length may be 281993db446aSBoris Brezillon * bigger than the destination buffer. Use this buffer instead 282093db446aSBoris Brezillon * for DMA transfers and then copy the desired amount of data to 282193db446aSBoris Brezillon * the provided buffer. 282293db446aSBoris Brezillon */ 282393db446aSBoris Brezillon nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); 2824aafe30baSPeter Ujfalusi if (!nfc->dma_buf) { 2825aafe30baSPeter Ujfalusi ret = -ENOMEM; 2826aafe30baSPeter Ujfalusi goto release_channel; 2827aafe30baSPeter Ujfalusi } 282893db446aSBoris Brezillon 282993db446aSBoris Brezillon nfc->use_dma = true; 283093db446aSBoris Brezillon 283193db446aSBoris Brezillon return 0; 2832aafe30baSPeter Ujfalusi 2833aafe30baSPeter Ujfalusi release_channel: 2834aafe30baSPeter Ujfalusi dma_release_channel(nfc->dma_chan); 2835aafe30baSPeter Ujfalusi nfc->dma_chan = NULL; 2836aafe30baSPeter Ujfalusi 2837aafe30baSPeter Ujfalusi return ret; 283893db446aSBoris Brezillon } 283993db446aSBoris Brezillon 2840bd9c3f9bSDaniel Mack static void marvell_nfc_reset(struct marvell_nfc *nfc) 2841bd9c3f9bSDaniel Mack { 2842bd9c3f9bSDaniel Mack /* 2843bd9c3f9bSDaniel Mack * ECC operations and interruptions are only enabled when specifically 2844bd9c3f9bSDaniel Mack * needed. ECC shall not be activated in the early stages (fails probe). 2845bd9c3f9bSDaniel Mack * Arbiter flag, even if marked as "reserved", must be set (empirical). 2846bd9c3f9bSDaniel Mack * SPARE_EN bit must always be set or ECC bytes will not be at the same 2847bd9c3f9bSDaniel Mack * offset in the read page and this will fail the protection. 2848bd9c3f9bSDaniel Mack */ 2849bd9c3f9bSDaniel Mack writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN | 2850bd9c3f9bSDaniel Mack NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); 2851bd9c3f9bSDaniel Mack writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); 2852bd9c3f9bSDaniel Mack writel_relaxed(0, nfc->regs + NDECCCTRL); 2853bd9c3f9bSDaniel Mack } 2854bd9c3f9bSDaniel Mack 285593db446aSBoris Brezillon static int marvell_nfc_init(struct marvell_nfc *nfc) 285693db446aSBoris Brezillon { 285793db446aSBoris Brezillon struct device_node *np = nfc->dev->of_node; 285893db446aSBoris Brezillon 285993db446aSBoris Brezillon /* 286093db446aSBoris Brezillon * Some SoCs like A7k/A8k need to enable manually the NAND 286193db446aSBoris Brezillon * controller, gated clocks and reset bits to avoid being bootloader 286293db446aSBoris Brezillon * dependent. This is done through the use of the System Functions 286393db446aSBoris Brezillon * registers. 286493db446aSBoris Brezillon */ 286593db446aSBoris Brezillon if (nfc->caps->need_system_controller) { 286693db446aSBoris Brezillon struct regmap *sysctrl_base = 286793db446aSBoris Brezillon syscon_regmap_lookup_by_phandle(np, 286893db446aSBoris Brezillon "marvell,system-controller"); 286993db446aSBoris Brezillon 287093db446aSBoris Brezillon if (IS_ERR(sysctrl_base)) 287193db446aSBoris Brezillon return PTR_ERR(sysctrl_base); 287293db446aSBoris Brezillon 287388aa3bbfSThomas Petazzoni regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, 287488aa3bbfSThomas Petazzoni GENCONF_SOC_DEVICE_MUX_NFC_EN | 287593db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST | 287693db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST | 287788aa3bbfSThomas Petazzoni GENCONF_SOC_DEVICE_MUX_NFC_INT_EN); 287893db446aSBoris Brezillon 287988aa3bbfSThomas Petazzoni regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL, 288088aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE, 288188aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE); 288293db446aSBoris Brezillon 288388aa3bbfSThomas Petazzoni regmap_update_bits(sysctrl_base, GENCONF_ND_CLK_CTRL, 288488aa3bbfSThomas Petazzoni GENCONF_ND_CLK_CTRL_EN, 288588aa3bbfSThomas Petazzoni GENCONF_ND_CLK_CTRL_EN); 288693db446aSBoris Brezillon } 288793db446aSBoris Brezillon 288893db446aSBoris Brezillon /* Configure the DMA if appropriate */ 288993db446aSBoris Brezillon if (!nfc->caps->is_nfcv2) 289093db446aSBoris Brezillon marvell_nfc_init_dma(nfc); 289193db446aSBoris Brezillon 2892bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc); 289393db446aSBoris Brezillon 289493db446aSBoris Brezillon return 0; 289593db446aSBoris Brezillon } 289693db446aSBoris Brezillon 289793db446aSBoris Brezillon static int marvell_nfc_probe(struct platform_device *pdev) 289893db446aSBoris Brezillon { 289993db446aSBoris Brezillon struct device *dev = &pdev->dev; 290093db446aSBoris Brezillon struct marvell_nfc *nfc; 290193db446aSBoris Brezillon int ret; 290293db446aSBoris Brezillon int irq; 290393db446aSBoris Brezillon 290493db446aSBoris Brezillon nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), 290593db446aSBoris Brezillon GFP_KERNEL); 290693db446aSBoris Brezillon if (!nfc) 290793db446aSBoris Brezillon return -ENOMEM; 290893db446aSBoris Brezillon 290993db446aSBoris Brezillon nfc->dev = dev; 29107da45139SMiquel Raynal nand_controller_init(&nfc->controller); 29118831e48bSMiquel Raynal nfc->controller.ops = &marvell_nand_controller_ops; 291293db446aSBoris Brezillon INIT_LIST_HEAD(&nfc->chips); 291393db446aSBoris Brezillon 29145dcc9976SMiquel Raynal nfc->regs = devm_platform_ioremap_resource(pdev, 0); 291593db446aSBoris Brezillon if (IS_ERR(nfc->regs)) 291693db446aSBoris Brezillon return PTR_ERR(nfc->regs); 291793db446aSBoris Brezillon 291893db446aSBoris Brezillon irq = platform_get_irq(pdev, 0); 2919aab478caSStephen Boyd if (irq < 0) 292093db446aSBoris Brezillon return irq; 292193db446aSBoris Brezillon 29226b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, "core"); 2923961ba15cSGregory CLEMENT 2924961ba15cSGregory CLEMENT /* Managed the legacy case (when the first clock was not named) */ 29256b6de654SBoris Brezillon if (nfc->core_clk == ERR_PTR(-ENOENT)) 29266b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, NULL); 2927961ba15cSGregory CLEMENT 29286b6de654SBoris Brezillon if (IS_ERR(nfc->core_clk)) 29296b6de654SBoris Brezillon return PTR_ERR(nfc->core_clk); 293093db446aSBoris Brezillon 29316b6de654SBoris Brezillon ret = clk_prepare_enable(nfc->core_clk); 293293db446aSBoris Brezillon if (ret) 293393db446aSBoris Brezillon return ret; 293493db446aSBoris Brezillon 2935961ba15cSGregory CLEMENT nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); 2936f9e64d61SDaniel Mack if (IS_ERR(nfc->reg_clk)) { 2937961ba15cSGregory CLEMENT if (PTR_ERR(nfc->reg_clk) != -ENOENT) { 2938961ba15cSGregory CLEMENT ret = PTR_ERR(nfc->reg_clk); 29396b6de654SBoris Brezillon goto unprepare_core_clk; 2940961ba15cSGregory CLEMENT } 2941f9e64d61SDaniel Mack 2942f9e64d61SDaniel Mack nfc->reg_clk = NULL; 2943961ba15cSGregory CLEMENT } 2944961ba15cSGregory CLEMENT 2945f9e64d61SDaniel Mack ret = clk_prepare_enable(nfc->reg_clk); 2946f9e64d61SDaniel Mack if (ret) 2947f9e64d61SDaniel Mack goto unprepare_core_clk; 2948f9e64d61SDaniel Mack 294993db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_ALL_INT); 295093db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 295193db446aSBoris Brezillon ret = devm_request_irq(dev, irq, marvell_nfc_isr, 295293db446aSBoris Brezillon 0, "marvell-nfc", nfc); 295393db446aSBoris Brezillon if (ret) 2954961ba15cSGregory CLEMENT goto unprepare_reg_clk; 295593db446aSBoris Brezillon 295693db446aSBoris Brezillon /* Get NAND controller capabilities */ 295793db446aSBoris Brezillon if (pdev->id_entry) 295893db446aSBoris Brezillon nfc->caps = (void *)pdev->id_entry->driver_data; 295993db446aSBoris Brezillon else 296093db446aSBoris Brezillon nfc->caps = of_device_get_match_data(&pdev->dev); 296193db446aSBoris Brezillon 296293db446aSBoris Brezillon if (!nfc->caps) { 296393db446aSBoris Brezillon dev_err(dev, "Could not retrieve NFC caps\n"); 296493db446aSBoris Brezillon ret = -EINVAL; 2965961ba15cSGregory CLEMENT goto unprepare_reg_clk; 296693db446aSBoris Brezillon } 296793db446aSBoris Brezillon 296893db446aSBoris Brezillon /* Init the controller and then probe the chips */ 296993db446aSBoris Brezillon ret = marvell_nfc_init(nfc); 297093db446aSBoris Brezillon if (ret) 2971961ba15cSGregory CLEMENT goto unprepare_reg_clk; 297293db446aSBoris Brezillon 297393db446aSBoris Brezillon platform_set_drvdata(pdev, nfc); 297493db446aSBoris Brezillon 297593db446aSBoris Brezillon ret = marvell_nand_chips_init(dev, nfc); 297693db446aSBoris Brezillon if (ret) 2977aafe30baSPeter Ujfalusi goto release_dma; 297893db446aSBoris Brezillon 297993db446aSBoris Brezillon return 0; 298093db446aSBoris Brezillon 2981aafe30baSPeter Ujfalusi release_dma: 2982aafe30baSPeter Ujfalusi if (nfc->use_dma) 2983aafe30baSPeter Ujfalusi dma_release_channel(nfc->dma_chan); 2984961ba15cSGregory CLEMENT unprepare_reg_clk: 2985961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 29866b6de654SBoris Brezillon unprepare_core_clk: 29876b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 298893db446aSBoris Brezillon 298993db446aSBoris Brezillon return ret; 299093db446aSBoris Brezillon } 299193db446aSBoris Brezillon 299293db446aSBoris Brezillon static int marvell_nfc_remove(struct platform_device *pdev) 299393db446aSBoris Brezillon { 299493db446aSBoris Brezillon struct marvell_nfc *nfc = platform_get_drvdata(pdev); 299593db446aSBoris Brezillon 299693db446aSBoris Brezillon marvell_nand_chips_cleanup(nfc); 299793db446aSBoris Brezillon 299893db446aSBoris Brezillon if (nfc->use_dma) { 299993db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 300093db446aSBoris Brezillon dma_release_channel(nfc->dma_chan); 300193db446aSBoris Brezillon } 300293db446aSBoris Brezillon 3003961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 30046b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 300593db446aSBoris Brezillon 300693db446aSBoris Brezillon return 0; 300793db446aSBoris Brezillon } 300893db446aSBoris Brezillon 3009bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_suspend(struct device *dev) 3010bd9c3f9bSDaniel Mack { 3011bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev); 3012bd9c3f9bSDaniel Mack struct marvell_nand_chip *chip; 3013bd9c3f9bSDaniel Mack 3014bd9c3f9bSDaniel Mack list_for_each_entry(chip, &nfc->chips, node) 3015bd9c3f9bSDaniel Mack marvell_nfc_wait_ndrun(&chip->chip); 3016bd9c3f9bSDaniel Mack 3017bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->reg_clk); 3018bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->core_clk); 3019bd9c3f9bSDaniel Mack 3020bd9c3f9bSDaniel Mack return 0; 3021bd9c3f9bSDaniel Mack } 3022bd9c3f9bSDaniel Mack 3023bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_resume(struct device *dev) 3024bd9c3f9bSDaniel Mack { 3025bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev); 3026bd9c3f9bSDaniel Mack int ret; 3027bd9c3f9bSDaniel Mack 3028bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->core_clk); 3029bd9c3f9bSDaniel Mack if (ret < 0) 3030bd9c3f9bSDaniel Mack return ret; 3031bd9c3f9bSDaniel Mack 3032bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->reg_clk); 3033bd9c3f9bSDaniel Mack if (ret < 0) 3034bd9c3f9bSDaniel Mack return ret; 3035bd9c3f9bSDaniel Mack 3036bd9c3f9bSDaniel Mack /* 3037bd9c3f9bSDaniel Mack * Reset nfc->selected_chip so the next command will cause the timing 30382e16dc73SMiquel Raynal * registers to be restored in marvell_nfc_select_target(). 3039bd9c3f9bSDaniel Mack */ 3040bd9c3f9bSDaniel Mack nfc->selected_chip = NULL; 3041bd9c3f9bSDaniel Mack 3042bd9c3f9bSDaniel Mack /* Reset registers that have lost their contents */ 3043bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc); 3044bd9c3f9bSDaniel Mack 3045bd9c3f9bSDaniel Mack return 0; 3046bd9c3f9bSDaniel Mack } 3047bd9c3f9bSDaniel Mack 3048bd9c3f9bSDaniel Mack static const struct dev_pm_ops marvell_nfc_pm_ops = { 3049bd9c3f9bSDaniel Mack SET_SYSTEM_SLEEP_PM_OPS(marvell_nfc_suspend, marvell_nfc_resume) 3050bd9c3f9bSDaniel Mack }; 3051bd9c3f9bSDaniel Mack 305293db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { 305393db446aSBoris Brezillon .max_cs_nb = 4, 305493db446aSBoris Brezillon .max_rb_nb = 2, 305593db446aSBoris Brezillon .need_system_controller = true, 305693db446aSBoris Brezillon .is_nfcv2 = true, 305793db446aSBoris Brezillon }; 305893db446aSBoris Brezillon 305993db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { 306093db446aSBoris Brezillon .max_cs_nb = 4, 306193db446aSBoris Brezillon .max_rb_nb = 2, 306293db446aSBoris Brezillon .is_nfcv2 = true, 306393db446aSBoris Brezillon }; 306493db446aSBoris Brezillon 306593db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = { 306693db446aSBoris Brezillon .max_cs_nb = 2, 306793db446aSBoris Brezillon .max_rb_nb = 1, 306893db446aSBoris Brezillon .use_dma = true, 306993db446aSBoris Brezillon }; 307093db446aSBoris Brezillon 307193db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = { 307293db446aSBoris Brezillon .max_cs_nb = 4, 307393db446aSBoris Brezillon .max_rb_nb = 2, 307493db446aSBoris Brezillon .need_system_controller = true, 307593db446aSBoris Brezillon .legacy_of_bindings = true, 307693db446aSBoris Brezillon .is_nfcv2 = true, 307793db446aSBoris Brezillon }; 307893db446aSBoris Brezillon 307993db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = { 308093db446aSBoris Brezillon .max_cs_nb = 4, 308193db446aSBoris Brezillon .max_rb_nb = 2, 308293db446aSBoris Brezillon .legacy_of_bindings = true, 308393db446aSBoris Brezillon .is_nfcv2 = true, 308493db446aSBoris Brezillon }; 308593db446aSBoris Brezillon 308693db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = { 308793db446aSBoris Brezillon .max_cs_nb = 2, 308893db446aSBoris Brezillon .max_rb_nb = 1, 308993db446aSBoris Brezillon .legacy_of_bindings = true, 309093db446aSBoris Brezillon .use_dma = true, 309193db446aSBoris Brezillon }; 309293db446aSBoris Brezillon 309393db446aSBoris Brezillon static const struct platform_device_id marvell_nfc_platform_ids[] = { 309493db446aSBoris Brezillon { 309593db446aSBoris Brezillon .name = "pxa3xx-nand", 309693db446aSBoris Brezillon .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps, 309793db446aSBoris Brezillon }, 309893db446aSBoris Brezillon { /* sentinel */ }, 309993db446aSBoris Brezillon }; 310093db446aSBoris Brezillon MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids); 310193db446aSBoris Brezillon 310293db446aSBoris Brezillon static const struct of_device_id marvell_nfc_of_ids[] = { 310393db446aSBoris Brezillon { 310493db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand-controller", 310593db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_caps, 310693db446aSBoris Brezillon }, 310793db446aSBoris Brezillon { 310893db446aSBoris Brezillon .compatible = "marvell,armada370-nand-controller", 310993db446aSBoris Brezillon .data = &marvell_armada370_nfc_caps, 311093db446aSBoris Brezillon }, 311193db446aSBoris Brezillon { 311293db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand-controller", 311393db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_caps, 311493db446aSBoris Brezillon }, 311593db446aSBoris Brezillon /* Support for old/deprecated bindings: */ 311693db446aSBoris Brezillon { 311793db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand", 311893db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_legacy_caps, 311993db446aSBoris Brezillon }, 312093db446aSBoris Brezillon { 312193db446aSBoris Brezillon .compatible = "marvell,armada370-nand", 312293db446aSBoris Brezillon .data = &marvell_armada370_nfc_legacy_caps, 312393db446aSBoris Brezillon }, 312493db446aSBoris Brezillon { 312593db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand", 312693db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_legacy_caps, 312793db446aSBoris Brezillon }, 312893db446aSBoris Brezillon { /* sentinel */ }, 312993db446aSBoris Brezillon }; 313093db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids); 313193db446aSBoris Brezillon 313293db446aSBoris Brezillon static struct platform_driver marvell_nfc_driver = { 313393db446aSBoris Brezillon .driver = { 313493db446aSBoris Brezillon .name = "marvell-nfc", 313593db446aSBoris Brezillon .of_match_table = marvell_nfc_of_ids, 3136bd9c3f9bSDaniel Mack .pm = &marvell_nfc_pm_ops, 313793db446aSBoris Brezillon }, 313893db446aSBoris Brezillon .id_table = marvell_nfc_platform_ids, 313993db446aSBoris Brezillon .probe = marvell_nfc_probe, 314093db446aSBoris Brezillon .remove = marvell_nfc_remove, 314193db446aSBoris Brezillon }; 314293db446aSBoris Brezillon module_platform_driver(marvell_nfc_driver); 314393db446aSBoris Brezillon 314493db446aSBoris Brezillon MODULE_LICENSE("GPL"); 314593db446aSBoris Brezillon MODULE_DESCRIPTION("Marvell NAND controller driver"); 3146